Semiconductor device and semiconductor structure with a gate interface

Abstract

Semiconductor device comprising: a first gate structure (250-1) arranged over a first backside dielectric feature (290); a second gate structure (250-2) arranged over a second rear-side dielectric feature (290); a gate cut feature (288) that extends continuously from a point between the first gate structure (250-1) and the second gate structure (250-2) to a point between the first backside dielectric feature (290) and the second backside dielectric feature (290); a lining (284) arranged between the gate cutting feature (288) and the first rear dielectric feature (290) and between the gate cutting feature (288) and the second rear dielectric feature (290); a dielectric self-aligned contact (SAC) layer (256) arranged above the first gate structure (250-1) and the second gate structure (250-2); an etch stop layer (212) over the dielectric SAC layer (256); and a dielectric front-side layer (210) above the etch stop layer (212), wherein the gate cutting feature (288) extends into the dielectric SAC layer (256), the etch stop layer (212) and the dielectric front side layer (210).

Description

BACKGROUND

[0001] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to generations of ICs, each featuring smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected devices per unit area) has generally increased, while geometric size (the smallest component or trace that can be formed by a manufacturing process) has decreased. This miniaturization process generally delivers benefits by increasing production efficiency and reducing manufacturing costs. However, such miniaturization has also increased the complexity of IC processing and manufacturing.

[0002] As integrated circuit (IC) technologies evolve toward smaller technology nodes, ensuring satisfactory mask alignment becomes increasingly challenging. For example, some gate-cut features have an upper and lower portion formed sequentially through lithography and etching processes. If mask alignment is not ideal, the upper portion may not align with the lower portion. Thus, while existing gate-cut features and the processes used to create them have generally been adequate for their intended purposes, they are not entirely satisfactory in every respect.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in DE 10 2018 126 937 A1, DE 10 2018 115 901 A1 and US 2019 / 0 341 297 A1.

[0004] The invention provides for a semiconductor device according to claim 1 and a semiconductor structure according to claim 8. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale and are for illustrative purposes only. The dimensions of the various structural elements may, in fact, be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1 illustrates a flowchart of a method for forming a semiconductor device having a rear contact, according to one or more aspects of the present disclosure. Fig. 2A-11A, 2B-11B, 2C-11C, 2D-11D and 2E-11E illustrate fragmentary cross-sectional views of a workpiece during a manufacturing process according to the method of Fig. 1 according to one or more aspects of the present revelation. Fig. Figures 12-19 illustrate alternative semiconductor structures or intermediate structures that are produced using the method of Fig. 1. manufactured according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0007] Spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify descriptions and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0008] Furthermore, when a number or range of numbers is described using terms like "about," "approximately," and the like, the term should also include numbers that lie within a meaningful range that accounts for variations inherent in any manufacturing process, as understood by the person skilled in the art. For example, the number or range of numbers includes a meaningful range that contains the stated number plus a span of, for example, ±10% of the stated number, based on known manufacturing tolerances associated with the production of a feature that has a property linked to the number. For example, a layer of material that is "about 5 nm" thick may encompass a dimensional range of 4.25 nm to 5.75 nm if the person skilled in the art knows that the manufacturing tolerances associated with the deposition of the layer of material are ±15%.Furthermore, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0009] In semiconductor manufacturing, the cut metal gate (CMG) process refers to a process for forming a dielectric feature to divide a continuous gate structure spanning more than one active region into more than one segment. Such a dielectric feature can be called a gate cut feature or simply a cut feature. In some existing CMG processes, a gate cut feature is formed on a dielectric fin (or hybrid fin). If the gate cut feature is located on the top side and the dielectric fin is on the bottom side, they work synergistically to divide a gate structure into two segments. In some exemplary processes, the gate cut feature is formed from the front side of a substrate (for example, a wafer) using photolithography and etching processes.As semiconductor devices become increasingly miniaturized, limitations regarding overlay and critical dimension uniformity (CDU) make it increasingly difficult to form the gate cutting feature directly on a dielectric fin. In some cases, the gate cutting feature, missing the dielectric fin, can cut into the gate structure or channel region, leading to defects.

[0010] The present disclosure provides CMG processes that, unlike existing technologies, form a cutting feature from the back side of the substrate. Furthermore, according to the present disclosure, the cutting feature extends from the back side of the substrate through the gate structure. That is, the cutting feature of the present disclosure alone—without the aid of a dielectric fin or a hybrid fin—divides the gate structure into segments. In some cases, the cutting feature of the present disclosure can even extend horizontally through more than one gate structure or vertically through one or more dielectric features or layers above the gate structure. The processes of the present disclosure are not only executed from the back side but are also self-aligning to avoid defects associated with misalignment of the mask.Embodiments of the present disclosure can continue to reduce the cell heights while maintaining or increasing the process window.

[0011] The various aspects of the present revelation will now be described in more detail with reference to the figures. In this respect, Fig. Figure 1 is a flowchart illustrating Method 100 for forming a semiconductor device according to embodiments of the present disclosure. Method 100 is merely an example. Additional steps may be performed before, during, and after Method 100, and some of the described steps may be substituted, omitted, or postponed to obtain additional embodiments of the method. For the sake of simplicity, not all steps are described in detail here. Method 100 is subsequently referred to in conjunction with the Fig. Figures 2A-11A, 2B-11B, 2C-11C, 2D-11D and 2E-11E, which are fragmentary cross-sectional views of workpiece 200 at different manufacturing stages, are described according to embodiments of method 100. Among the Fig. Figures 2A-11A, 2B-11B, 2C-11C, 2D-11D, and 2E-11E are perspectives of workpiece 200 ending in A; figures ending in B are fragmentary cross-sectional views along cross-section BB' in the respective perspective view; figures ending in C are fragmentary cross-sectional views along cross-section CC' in the respective perspective view; figures ending in D are fragmentary cross-sectional views along cross-section DD' in the respective perspective view; and figures ending in E are fragmentary cross-sectional views along cross-section EE' in the respective perspective view. Because workpiece 200 has become a semiconductor device 200 after completion of the manufacturing processes, workpiece 200 can be referred to as the semiconductor device 200, depending on the context.Unless otherwise stated, in this application identical reference numbers denote identical characteristics.

[0012] Embodiments of the present disclosure can be implemented in more advanced semiconductor devices, which may include multi-gate devices. A multi-gate device generally refers to a device that has a gate structure, or a portion thereof, arranged over more than one side of a channel region. Fin-type field-effect transistors (FinFETs) and multi-bridge-channel transistors (MBC transistors) are examples of multi-gate devices that have become popular and promising candidates for high-power, low-leakage-current applications. A FinFET has a raised channel that is enclosed on more than one side by a gate (the gate, for example, encloses the top and side walls of a "fin" of semiconductor material extending from a substrate).An MBC transistor has a gate structure that can extend—partially or completely—around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor can also be referred to as a "surrounding-gate transistor" (SGT) or "gate-all-around transistor" (GAA). The channel region of the MBC transistor can be formed from nanowires, nanolayers, other nanostructures, and / or other suitable structures. The shapes of the channel region have also given an MBC transistor alternative names, such as nanolayer transistor or nanowire transistor. Embodiments of the present disclosure are described with reference to an MBC transistor structure that serves only as an illustration.

[0013] As in the Fig. As shown in Figures 1 and 2A-2E, the procedure 100 includes a block 102 in which a workpiece 200 is received. Fig. Figures 2A-2E illustrate a workpiece 200 with its front facing upwards. That is, on the side in the Fig. No backside processes have yet been performed on the workpiece 200 shown in Figures 2A-2E. The workpiece 200 has a substrate 202. In one embodiment, the substrate 202 contains silicon (Si). In other embodiments, the substrate 202 can also contain other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The workpiece 200 has a first base section 202-1 and a second base section 202, each of which is structured from the substrate 202 and can have the same composition as the substrate 20. Although the substrate 202 in the Fig. As shown in 2A-2E, it can be omitted in at least some of the other figures for the sake of simplicity. As in Fig. As shown in Figure 2E, the first base section 202-1 and the second base section 202-2 are separated from each other by an insulation feature 204. In some embodiments, the insulation feature 204 is deposited in trenches that define the substrate 202. The insulation feature 204 may also be referred to as a shallow trench insulation (STI) feature 204. The insulation feature 204 may contain silicon dioxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low k-value dielectric, combinations thereof, and / or other suitable materials.

[0014] As in Fig. As shown in Figure 2E, the workpiece 200 contains several vertically stacked channel elements 208 above the first base section 202-1 and several more vertically stacked channel elements 208 above the second base section 202-2. In the illustrated embodiments, two vertically stacked channel elements 208 are arranged above each of the first base section 202-1 and the second base section 202-2, as shown in Figure 2E. Fig. Figure 2C shows that the channel elements 208 can be formed from a semiconductor material similar to the material of the substrate 202. In one embodiment, the channel elements 208 can contain silicon (Si). A common gate structure 250, extending along the Y-direction, surrounds the channel elements 208 over the first base section 202-1 and the second base section 202-2. Each of the common gate structures 250 can comprise an interface layer 252, a gate dielectric layer 254 over the interface layer 252, and a gate electrode layer over the gate dielectric layer 254. In some embodiments, the interface layer 252 contains silicon dioxide. The gate dielectric layer 254 can also be described as a high k-value dielectric layer because it is formed from a dielectric material with a dielectric constant greater than that of silicon dioxide, which is approximately 3.9.The gate dielectric layer 254 may contain hafnium oxide. Alternatively, the gate dielectric layer 254 can contain other dielectrics with a high k-value, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3)3, zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO). (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable material.

[0015] The gate electrode layer can have a single-layer or, alternatively, a multi-layer structure, such as various combinations of a metal layer with a selected work function to improve device performance (work function metal layer), a lining layer, a wetting layer, a first bonding layer, a metal alloy, or a metal silicide. For example, the gate electrode layer can contain titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials, or a combination thereof.

[0016] As in the Fig. As shown in Figures 2A-2C, the workpiece 200 has a gate spacer 216 arranged along the sidewalls of the common gate structures 250 above the uppermost channel element 208 or above the insulating feature 204. The gate spacer 216 can be a single layer or a multiple layer. In some embodiments, the gate spacer 216 can comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or combinations thereof. Between two adjacent channel elements 208, sidewalls of the gate structures are lined by inner spacer elements 228. The inner spacer features 228 can comprise silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.With respect to each of the first base section 202-1 and the second base section 202-2, each vertical stack of channel elements extends between a source feature 230S and a drain feature 230D. One end face of each of the channel elements 208 is coupled to a source feature 230S, and the other end face of each of the channel elements 208 is coupled to a drain feature 230D. Depending on the conductivity type of the MBC transistor to be formed, the source feature 230S and the drain feature 230D can be of the n-type or the p-type. If they are of the n-type, they may contain silicon (Si), phosphorus-doped silicon (Si:P), arsenic-doped silicon (Si:As), antimony-doped silicon (Si:Sb) or another suitable material and may be doped in situ during the epitaxial process by incorporating an n-doping element such as phosphorus (P), arsenic (As) or antimony (Sb).If they are of the p-type, they can contain germanium (Ge), gallium-doped silicon germanium (SiGe:Ga), boron-doped silicon germanium (SiGe:B) or another suitable material and can be doped in situ during the epitaxial process by incorporating a p-doping agent, such as boron (B) or gallium (Ga).

[0017] We turn to the Fig. 2A, Fig. 2C and Fig. 2D. Each of the source features 230S and drain features 230D has a first epitaxial layer 220 and a second epitaxial layer 222 above the first epitaxial layer 220. In some implementations, the first epitaxial layer 220 and the second epitaxial layer 222 are referred to as such. For example, the doping concentration in the second epitaxial layer 222 is greater than the doping concentration in the first epitaxial layer 220. The increased doping concentration in the second epitaxial layer 222 serves to reduce the contact resistance. The workpiece 200 also includes a contact etch stop layer (CESL) 232, which is arranged above the source feature 230S and the drain feature 230D, and an interlayer dielectric (ILD) layer 234, which is arranged above the CESL 232. CESL 232 may contain silicon nitride, silicon oxynitride and / or other materials known in the prior art.The ILD layer 234 can contain materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass or doped silicon oxide such as boron phosphosilicate glass (BPSG), quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.

[0018] As in the Fig. 2A, Fig. 2C and Fig. As shown in Figure 2D, at least one of the source features 230S is arranged directly above a semiconductor connector 218. The semiconductor connector 218 extends through the substrate 202 and the insulating feature 204. Along the X-direction, the semiconductor connector 218 is located between two base sections. Along the Y-direction, the semiconductor connector 218 is located between two sections of the insulating feature 204. In some embodiments, the semiconductor connector 218 can be made of undoped silicon germanium (SiGe). In some embodiments, the composition of the semiconductor connector 218 and the first epitaxial layer 220 is selected such that the first epitaxial layer 220 can serve as an epitaxial etch stop layer. For example, if an n-MBC transistor is desired, the first epitaxial layer 220 is made of silicon (Si) doped with an n-dotted dopant.An etching process that etches the (silicon germanium) semiconductor connector 218 may be slowed down when etching the first epitaxial layer 220 due to the reduction in germanium content. If a p-MBC transistor is desired, the first epitaxial layer 220 is formed from silicon germanium (Si) doped with boron (B). An etching process that etches the (silicon germanium) semiconductor connector 218 may be slowed down when etching the first epitaxial layer 220 because the boron dopant can decrease the etch rate.

[0019] In some versions, which are in the Fig. 2A, Fig. 2B, Fig. 2C and Fig. The dielectric gate self-aligning contact (SAC) layer 256, shown in Figure 2E, is located above the common gate structure 250 and the gate spacer 216. In some cases, the dielectric gate SAC layer 256 may be arranged above the common gate structure 250 and the gate spacer 216. The dielectric gate SAC layer 256 may be a single layer or a multiple layer and may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or combinations thereof. The workpiece 200 may also include front source contacts 260S via source features 230S and front drain contacts 260D via drain features.The front source contacts 260S or the front drain contacts 260D may contain titanium nitride (TiN), tantalum (Ta), titanium (TiN), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), molybdenum (Mo), titanium silicide (TiSi), tungsten silicide (WSi), platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi) or a combination thereof.

[0020] In block 102, workpiece 200 can be received with its back side facing upwards, as shown in the Fig. 2A-2E shown. In this configuration, with the underside facing upwards, the substrate 202 is located on the underside and the dielectric gate SAC layer 256 is on the top side.

[0021] As in the Fig. As shown in Figures 1 and 3A-3E, the method 100 comprises a block 104 in which the workpiece 200 has been flipped (top side down). To flip the workpiece 200, a support substrate (not explicitly shown) is bonded to a front face of the workpiece 200 facing away from the substrate 202. In some embodiments, the support substrate can be bonded to the workpiece 200 by fusion bonding, by using an adhesive layer, or a combination thereof. In some cases, the support substrate can be formed from semiconductor materials (such as silicon), sapphire, glass, polymeric materials, or other suitable materials. In embodiments using fusion bonding, the support substrate has a bottom oxide layer, and the workpiece 200 has a top oxide layer.After both the lower and upper oxide layers have been treated, they are brought into flush contact for direct bonding at room temperature or at an elevated temperature. Once the substrate has been bonded to the workpiece 200, the workpiece 200 is turned over, as described in the [reference]. Fig. 3A-3E shown. After turning over the workpiece 200, the back of the workpiece 200 is planarized using chemical-mechanical polishing (CMP) until the insulation feature 204, the semiconductor connectors 218, the first base section 202-1 and the second base section 202-2 are exposed on the now upward-facing back of the workpiece 200.

[0022] As in the Fig. As shown in Figures 1 and 4A-4E, method 100 comprises a block 106 in which the rear contacts 270 are formed. The operations in block 106 may include the selective removal of the semiconductor plugs 218 to form rear contact openings and the formation of the rear contacts 270 in the rear openings. In some embodiments, the removal of the semiconductor plug 218 may be self-aligning because the semiconductor plug 218, which is formed of silicon germanium (SiGe), is located between the insulating feature 204 (formed of a dielectric material), the first base section 202-1 (formed of silicon (Si) in at least some embodiments), and the second base section 202-2 (formed of silicon (Si) in at least some embodiments). In these embodiments, the selective removal of the semiconductor plug 218 may be performed using a selective wet etching process.An exemplary selective wet etching process may involve the use of a solution of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). Because the selective etching process in block 106 etches the semiconductor connector 218 faster than the insulating feature 204, the first base section 202-1, and the second base section 202-2, the semiconductor connector 218 can be removed with no or only minor damage. In the embodiments shown, the selective removal of the semiconductor connector 218 can also remove a portion of the first epitaxial layer 220 beneath the semiconductor connector 218. Removing the semiconductor connector 218 and the first epitaxial layer 220 creates backside contact openings to expose the source features 230S.

[0023] The backside contacts 270 are then formed in the backside contact openings. Although not explicitly shown, each of the backside contacts 270 can have a silicide layer between the source feature 230S and a metal filler layer. In an exemplary process, a metal precursor is then deposited over the exposed source features 230S, and an annealing process is carried out to induce silicification between the source feature 230S and the metal precursor to form the silicide layer.In some embodiments, the metal precursor may contain titanium (Ti), chromium (Cr), tantalum (Ta), molybdenum (Mo), zirconium (Zr), nickel (Ni), cobalt (Co), manganese (Mn), tungsten (W), iron (Fe), ruthenium (Ru), or platinum (Pt), and the silicide layer may contain titanium silicide (TiSi), chromium silicide (CrSi), tantalum silicide (TaSi), molybdenum silicide (MoSi), nickel silicide (NiSi), cobalt silicide (CoSi), manganese silicide (MnSi), tungsten silicide (WSi), iron silicide (FeSi), ruthenium silicide (RuSi), or platinum silicide (PtSi). After the formation of the silicide layer, a metal filler material may be injected into the rear contact openings to form the rear contacts 270, as shown in the [reference]. Fig. Figures 4A-4E show the metal filler material to be tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), or aluminum (Al), and to be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, the rear contacts 270 may optionally have a barrier layer arranged at their interface with the insulating feature 204. The optional barrier layer may be titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), nickel nitride (NiN), tungsten nitride (WN), titanium (Ti), or tantalum (Ta). A planarization process, such as a CMP process, may follow the deposition of the metal filler material to remove excess material and obtain a planar top surface. After completion of the operations in block 106, the rear contacts 270 are coupled to the source features 230S.

[0024] As in the Fig. As shown in Figures 1 and 5A-5E, the method 100 comprises a block 108 in which a helmet layer 272 is formed to cover the first base section 202-1 and the second base section 202-2. In some embodiments, the operations in block 108 include selectively recessing the first base section 202-1 and the second base section 202-2 to form recesses and forming the helmet layer 272 in the recesses. As shown in Fig. As shown in Figure 4A, after completion of the operations in block 106, the first base section 202-1 and the second base section 202-2 are surrounded by the insulating feature 204 and the rear contacts 270, which are formed from different materials. In some implementations, the selective recession of the first base section 202-1 and the second base section 202-2 can be performed using a selective wet etching process or a selective dry etching process. An exemplary selective wet etching process may involve the use of ethylenediaminepyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), or a suitable wet etching agent. An example of a selective dry etching process may involve sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), argon or a mixture thereof.After the first base section 202-1 and the second base section 202-2 have been recessed to form cavities, a metal or metal oxide can be deposited in the cavities to form the helmet layer 272. In some embodiments, the helmet layer 272 can contain aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), or tungsten (W). In one embodiment, the helmet layer 272 contains hafnium oxide. Subsequently, a planarization process is performed to obtain a planar back surface. As described in the... Fig. 5A, Fig. 5C, Fig. 5D and Fig. As shown in Figure 5E, the helmet layer 272 can be in contact with one or more rear contacts 270 and the insulating feature 204.

[0025] As in the Fig. As shown in Figures 1, 6A-6E and 7A-7E, the process 100 comprises a block 110 in which the isolation feature 204 is selectively etched to form a pilot opening 282 that exposes the common gate structure 250. The operations in block 110 include the formation of a structured hard mask 280 (in the Fig. 6A-6E shown) and the formation of pilot opening 282 (in the Fig. (7A-7E shown). In an exemplary process, a hard mask layer is deposited over the entire surface of workpiece 200 using CVD. The hard mask layer can be a single layer or a multilayer. If the hard mask layer is a multilayer, it can contain a silicon oxide layer and a silicon nitride layer. After deposition of the hard mask layer, photolithography and etching processes can be performed to pattern the hard mask layer and form the patterned hard mask. In some cases, a photoresist layer is deposited over the hard mask layer. To pattern the photoresist layer, it is exposed to radiation reflected from or transmitted through a photomask, fired in a post-exposure process, and developed in a developer.The structured photoresist layer is then applied as an etching mask to etch the hard mask layer, creating the structured hard mask 280. As shown in the... Fig. As shown in Figures 6A-6E, the structured hard mask 280 includes a mask opening 281 that is substantially aligned with the pilot opening 282 to be formed. According to the present disclosure, the structured hard mask 280 serves to mask sections of the isolation feature 204 that are not to be etched in block 114. It is irrelevant whether a section of the helmet layer 272 is exposed in the mask opening 281. As shown in Fig. As shown in Figure 6E, the mask opening 281 does not need to be congruent with sections of the helmet layer 272 on the first base section 202-1 and the second base section 202-2. This is because the etching process in block 114 is selective for the isolation feature 204 and does not etch the helmet layer 272 significantly. Even if the mask opening 281 is larger than the pilot opening 282 or misaligned, as indicated by the dashed lines in Figure 6E, the mask opening 281 does not need to be congruent with sections of the helmet layer 272 on the first base section 202-1 and the second base section 202-2. Fig. As shown in 6E, the pilot opening 282 can still be successfully formed.

[0026] We now turn to the Fig. 7A and Fig. 7E. With the structured hard mask 280 in place, the insulation feature 204 is selectively and anisotropically etched to form the pilot opening 282. In some embodiments, the insulation feature 204 can be etched using a dry etching process (for example, a reactive ion etching (RIE) process) that uses chlorine (Cl2), oxygen (O2), boron trifluoride (BCl3), carbon tetrafluoride (CF4), or a combination thereof. As shown in Fig. As shown in Figure 7A, the pilot opening 282 can terminate at upward-facing surfaces of the gate dielectric layer 254, the gate spacer 216, and the CESL 232 without extending into the gate electrode layer of the common gate structure 250. Because the mask opening 281 is not congruent with the spacing of the helmet layer 272, the width of the pilot opening 282 between the first base section 202-1 and the second base section 202-2 is smaller than the width of the mask opening 281 along the X-direction. It should be noted that, for better illustration of the pilot opening 282, the structures that intersect the cross-section DD' are shown in Figure 7A. Fig. 7A are omitted. Fig. Figure 7D illustrates the structures along cross-section D-D'.

[0027] As in the Fig. As shown in Figures 1 and 8A-8E, the process 100 comprises a block 112 in which a lining 284 is deposited along sidewalls of the pilot aperture 282. The lining 284 serves to protect the first base section 202-1 and the second base section 202-2 prior to the etching process in block 114. The lining 284 can also be referred to as a cut-metal gate endcap layer. The lining 284 can be a single layer or a multiple layer. In an exemplary process, at least one dielectric material is deposited over the back side of the workpiece 200, and then the deposited dielectric material is anisotropically back-etched to expose the gate dielectric layer 254, as shown in the Fig. 8A, Fig. 8B and Fig. Figure 8E shows that in some cases, the at least one dielectric material for the lining 284 can contain silicon, oxygen, nitrogen, or carbon. For example, the at least one dielectric material can contain silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or silicon oxynitride. After the etching process, the lining 284 can have a thickness between about 6 nm and about 10 nm. It should be noted that, for better illustration of the lining 284, the structures that cut the cross-section DD' are shown in Figure 8E. Fig. 8A are omitted. Fig. Figure 8D illustrates the structures along cross-section D-D'.

[0028] As in the Fig. As shown in Figures 1 and 9A-9E, the method 100 comprises a block 114 in which the pilot opening 282 is extended through the common gate structure 250 to form a gate cut opening 286. An anisotropic etching process is performed in block 114 to extend the pilot opening 282 to form the gate cut opening 286. In some embodiments, the gate cut opening 286 terminates on or within the dielectric gate SAC layer 256. As shown in the Fig. 9A, Fig. 9B and Fig. As shown in Figure 9E, the anisotropic etching process etches the lining 284, the gate spacer 216, and the dielectric gate SAC layer 256 at a slower rate, so that these structures confine the etching process in block 114 and define the boundaries of the gate slit opening 286. In some implementations, the anisotropic etching process in block 114 can be a dry etching process (for example, reactive ion etching (RIE)) using chlorine (Cl₂), oxygen (O₂), boron trifluoride (BCl₃), carbon tetrafluoride (CF₄), or a combination thereof. It should be noted that, for better illustration of the features in the gate slit opening 286, the structures that intersect the cross-section DD' are shown in Figure 9E. Fig. 9A are omitted. Fig. Figure 9D illustrates the structures along cross-section D-D'. As shown in the Fig. 9A and Fig. As shown in Figure 9E, the gate cut opening 286 separates the common gate structure 250 into a first gate segment 250-1 and a second gate segment 250-2.

[0029] As in the Fig. As shown in Figures 1 and 10A-10E, method 100 comprises a block 116 in which a dielectric material is deposited in the gate slit opening 286 to form a gate slit feature 288. In some embodiments, the dielectric material for the gate slit feature 288 can be deposited by plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), or conventional CVD. In some cases, the dielectric material for the gate slit feature 288 can comprise silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or silicon oxynitride. Between the gate cut feature 288 and the helmet layer 284, the gate cut feature 288 is formed from a dielectric material with a low k-value to reduce parasitic capacitance, and the helmet layer 284 is more corrosion-resistant to protect the gate electrode layer, such as the exit working layers located therein.In some alternative embodiments, the gate-cutting feature 288 can be a single layer or a multilayer. If the gate-cutting feature 288 is a multilayer, it can include a dielectric lining in contact with the gate segments and a dielectric filler spaced from the gate segments by the dielectric lining. The dielectric lining and the dielectric filler can be made of different materials. For example, the dielectric lining is oxygen-free, while the dielectric filler contains oxygen. As another example, the dielectric lining can have a higher dielectric constant than the dielectric filler. If the gate-cutting feature 288 is multilayer, the dielectric lining can have a thickness between about 1 nm and about 6 nm.It should be noted that, for better illustration of the features in the gate section 288, the structures that intersect the cross-section DD' are shown in . Fig. 10A are omitted. Fig. Figure 10D illustrates the structures along the cross-section D-D'.

[0030] As in the Fig. As shown in Figures 1 and 11A-11E, the method 100 comprises a block 118 in which the first base section 202-1 and the second base section 202-2 are replaced by a back-side dielectric layer 290. As shown in the Fig. 10A, Fig. 10C, Fig. 10D and Fig. As shown in Figure 10E, after completion of the operations in Block 116, the first base section 202-1 and the second base section 202-2 are surrounded by features formed from different materials, including the insulating feature 204, the lining 284, and the rear contacts 270. This arrangement allows for the selective removal of the first base section 202-1 and the second base section 202-2. In some embodiments, the selective removal of the first base section 202-1 and the second base section 202-2 can be carried out by selective wet etching or selective dry etching. An exemplary selective wet etching process may involve the use of ethylenediaminepyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), or a suitable wet etching agent.An exemplary selective dry etching process can involve sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), argon, or a mixture thereof. Subsequently, a dielectric backside layer 290 is deposited to replace the eroded first base section 202-1 and second base section 202-2. The dielectric backside layer 290 can contain silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonitride, silicon oxynitride, or silicon carbonitride and can be deposited by spin coating, CVD, FCVD, or plasma-enhanced CVD (PECVD). In some implementations, the backside dielectric layer 290 can be formed from a high k-value dielectric material to ensure adequate protection of the gate structure, even though the high k-value dielectric material might slightly increase the parasitic capacitance.In some embodiments, a protective layer can be deposited over the back of the workpiece 200 by CVD, ALD, or a suitable deposition technique prior to the deposition of the back-side dielectric layer 290, if the back-side dielectric layer 290 contains oxygen. The protective layer serves to space the back-side dielectric layer 290 away from adjacent structures and may contain silicon nitride. A planarization process, such as a CMP process, can be performed to remove excess material such that the top surfaces of the back-side dielectric layer 290, the insulating feature 204, the gate-cutting feature 288, the lining 284, and the back contacts 270 are coplanar. It should be noted that, for better illustration of the features in the back-side dielectric layer 290, the structures that intersect the cross-section DD' are shown in . Fig. 11A are omitted. Fig. Figure 11D illustrates the structures along cross-section D-D'.

[0031] As in the Fig. As shown in Figures 1 and 11A-11E, method 100 comprises a block 120 in which rear busbars 292 are formed. The formation of the rear busbars 292 can involve the deposition of an insulating layer 294 (in Fig. 11A not explicitly shown, but in the Fig. (shown in Figures 11B-11E), the structuring of the insulating layer 294 to form busbar grooves, and the formation of the back busbars 292 in the busbar grooves. The insulating layer 294 can have a similar composition to the ILD layer 234. The insulating layer 294 is deposited over the back of the workpiece 200, including the back dielectric layer 290, the back contacts 270, the insulating feature 204, the lining 284, and the gate cut feature 288. Busbar grooves are then structured in the insulating layer 294. The back contacts 270 are exposed in one or more busbar grooves. A metal filler material is then deposited into the busbar grooves to form the back busbars 292, which are electrically coupled to the back contacts 270.In some embodiments, the metal filler material in the rear busbar can contain titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), molybdenum (Mo), or a combination thereof. In some embodiments, a barrier layer can optionally be deposited prior to the deposition of the metal filler material to separate the metal filler material from the insulating layer. The barrier layer can contain titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), nickel nitride (NiN), or tungsten nitride (WN). When the barrier layer is formed, both the barrier layer and the metal filler material can be considered sections of the rear busbars 292. The barrier layer and the metal filler layer can be deposited using PVD, CVD, ALD, or chemical plating.A planarization process, such as a CMP process, can be performed to remove excess material above the insulation layer. Although not explicitly shown, further interconnect structures can be formed above the insulation layer 294 and the rear busbar 292.

[0032] In Fig. Figure 11B comprises the gate cutting feature 288, a lower section arranged between the gate spacers 216 along the X-direction, and an upper section arranged between the liners 284 along the X-direction. Along the X-direction, the lower section has a first width W1, and the upper section has a second width W2. In some cases, the first width W1 can be between approximately 6 nm and approximately 22 nm, and the second width W2 can be between approximately 4 nm and approximately 22 nm. The lower section has a first height H1 along the Z-direction, and the upper section has a second height H2 along the Z-direction. The sum of the first height H1 and the second height H2 can be between approximately 10 nm and approximately 80 nm. As shown in Figure 11B, the lower section has a first height H1 along the Z-direction. The first height H1 and the second height H2 can be between approximately 10 nm and approximately 80 nm. Fig. As shown in Figure 11C, the rear contact 270 can have a third height H3 between approximately 20 nm and approximately 40 nm after completion of the operations in block 120. As shown in Fig. As shown in Figure 10E, the lower section of the gate cut feature is arranged along the Y-direction between the gate electrode sections of the gate segments, and the upper section is arranged between the linings 284. The workpiece 200 in Fig. 11A-11E is upside down (with the top side facing down). If the workpiece is 200 in the Fig. If 11A-11E is rotated back into an upright position, the insulating layer 294 would be on the underside, and the dielectric gate SAC layer 256 would be on the top side.

[0033] Although the Fig. 7A, Fig. 7B and Fig. 7E illustrates that pilot opening 282, as a result of the operations in Block 110, essentially has vertical sidewalls; pilot openings with tapered sidewalls are also considered. We turn to Fig. 12. If the etching process in block 110 is not sufficiently anisotropic and selective, the helmet layer 272, the first base section 202-1, and the second base section 202-2 are also etched in block 110, resulting in a tapered pilot aperture 2820. As in Fig. As shown in Figure 13, the tapered pilot opening 2820 can have a ripple effect on subsequent processes. As shown in Fig. As shown in Figure 13, the lining 284 deposited in the tapered pilot aperture 2820 and the tapered gate cut feature 2880 also adopt the tapered profile. The rear dielectric layer 290, which replaces the now wedge-shaped base sections, can also have a wedge shape when viewed along the X-direction. Fig. Figure 13 also illustrates an alternative embodiment in which the gate cut opening or tapered gate cut feature 2880 extends completely through the dielectric gate SAC layer 256. As shown in Fig. As shown in Figure 13, the tapered gate cut feature 2880 can have a tapered tip section that penetrates the dielectric gate SAC layer 256 into an etch stop layer (ESL) 212 and an upper interlayer dielectric (ILD) layer 210. The ESL 212 and the upper ILD layer 210 can be part of a front-facing interconnect structure. The composition of the ESL 212 can be similar to that of the CESL 232, and the composition of the upper ILD layer 210 can be similar to that of the ILD layer 234. As shown in Fig. As shown in Figure 13, the tapered gate cutting feature 2880 can have an over-etch depth D between about 3 nm and about 100 nm.

[0034] Gate-cut features of the present disclosure may extend over more than one common gate structure. As in Fig. As shown in Figure 14, a first slot pilot opening 2822 can be formed in block 110 of the procedure 100, extending over a first common gate structure 2500 and a second common gate structure 2502. We now turn to Fig. 15. After forming the lining 284, the first slot pilot opening 2822 is extended downwards through the first common gate structure 2500 and the second common gate structure 2502 to form a first slot-gate section opening 2860. The first slot-gate section opening 2860 not only divides the first common gate structure 2500 into two gate segments, but also divides the second common gate structure 2502 into two gate segments. In some implementations that are in Fig. As shown in Figure 15, the etching process for forming the first slot-gate junction 2860 can etch the common gate structures faster than the CESL 232 and the ILD layer 234. As a result, a dielectric island 298 can be formed. Fig. Figure 15 also illustrates that the first slot-gate cut opening 2860 can contain oversized sections 2830 extending through the ESL 212 and the upper ILD layer 210 below the dielectric gate SAC layer 256. In these alternative embodiments, as shown in Fig. As shown in Figure 16, the operations in block 116 can form a first slot-gate cutting feature 2880, which generally follows the shape of the first slot-gate cutting opening 2860. Viewed from the Y direction, the first slot-gate cutting feature 2880 comprises leg sections 300 and extends over the dielectric island 298. The composition of the first slot-gate cutting feature 2880 can be similar to the gate cutting feature 288 described above. The workpiece 200 in Fig. 16 is upside down (with the top side facing down). If the workpiece is 200 in Fig. If 16 is turned back into an upright position, the insulation feature 204 would be on the underside, and the two leg sections 300 would point upwards.

[0035] Gate-cut features of the present disclosure can extend across a slot source / drain contact. As in Fig. As shown in Figure 17, a second slot pilot opening 2824 can be formed, extending over a first common gate structure 2500, a second common gate structure 2502, and a slot source / drain contact 302. We now turn to Fig. 18. After forming the lining 284, the second slot pilot opening 2824 is extended downwards through the first common gate structure 2500 and the second common gate structure 2502 to form a second slot-gate section opening 2862. The second slot-gate section opening 2862 not only divides the first common gate structure 2500 into two gate segments aligned along the Y-direction, but also divides the second common gate structure 2502 into two gate segments aligned along the Y-direction. In some implementations that are described in Fig. As shown in Figure 18, the etching process for forming the second slot-gate junction 2862 can etch the common gate structures faster than the slot-source / drain contact 302. As a result, a metal island 304 can be formed. Fig. Figure 18 also illustrates that the second slot-gate cut opening 2862 can contain oversized sections 2830 extending through the ESL 212 and the upper ILD layer 210 below the dielectric gate SAC layer 256. In these alternative embodiments, as shown in Fig. As shown in Figure 19, the operations in block 116 can form a second slot-gate cutting feature 2882, which generally follows the shape of the second slot-gate cutting opening 2862. Viewed from the Y direction, the second slot-gate cutting feature 2882 comprises leg sections 300 and extends over the metal island 304. The composition of the second slot-gate cutting feature 2882 can resemble the gate cutting feature 288 described above. The workpiece 200 in Fig. 19 is upside down (with the top side facing down). If the workpiece is 200 in Fig. If 19 is turned back into an upright position, the insulation feature 204 would be on the underside, and the two leg sections 300 would point upwards.

[0036] Embodiments of the present disclosure offer advantages. For example, methods of the present disclosure form gate-cut features from the back side of a workpiece. Using structures on the back side of the workpiece and a helmet layer, the formation of the gate-cut opening of the present disclosure is self-adjusting and does not rely on high resolution or high superposition precision of the photolithography process.

[0037] In one exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises: a first gate structure arranged over a first backside dielectric feature, a second gate structure arranged over a second backside dielectric feature, a gate-cutting feature extending continuously from a point between the first gate structure and the second gate structure to a point between the first backside dielectric feature and the second backside dielectric feature, and a lining arranged between the gate-cutting feature and the first backside dielectric feature and between the gate-cutting feature and the second backside dielectric feature.

[0038] In some embodiments, the first gate structure and the second gate structure are arranged above the liner. In some implementations, the semiconductor device may further include a gate spacer extending from a side wall of the first gate structure to a side wall of the second gate structure, with the gate cutting feature in contact with the gate spacer. In some cases, the gate cutting feature is in direct contact with the first and second gate structures. In some cases, the semiconductor device may also include: a self-aligned contact (SAC) layer arranged above the first and second gate structures, an etch stop layer above the SAC layer, and a dielectric layer above the etch stop layer.The gate-cutting feature extends into the dielectric SAC layer, the etch stop layer, and the dielectric layer. In some embodiments, the first back-facing dielectric feature comprises silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonitride, silicon oxynitride, or silicon carbonitride. In some embodiments, the lining comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or silicon oxynitride. In some cases, the gate-cutting feature comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or silicon oxynitride.

[0039] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure comprises a dielectric layer, a contact etch stop layer (CESL) arranged above the dielectric layer, an insulating feature arranged above the CESL, and a gate-cutting feature extending through the insulating feature, the CESL, and the dielectric layer. The gate-cutting feature is arranged between a first gate structure and a second gate structure, as well as between a third gate structure and a fourth gate structure.

[0040] In some embodiments, the first and second gate structures are aligned along one direction, and the third and fourth gate structures are aligned along the other direction. In some implementations, the gate-cutting feature is separated from the isolation feature by a liner. In some cases, the dielectric layer is arranged above an etch stop layer and an upper dielectric layer, and the gate-cutting feature has two leg sections, each extending into the etch stop layer and the upper dielectric layer, respectively. In some embodiments, the semiconductor structure may further include a metal feature positioned between the two leg sections such that the gate-cutting feature extends over the metal feature.In some embodiments, the semiconductor structure may further have a dielectric feature that is arranged between the two leg sections such that the gate cutting feature extends over the dielectric feature.

[0041] In another exemplary aspect, the present disclosure relates to a process.The process comprises: forming multiple first channel elements over a first substrate section of a workpiece and multiple second channel elements over a second substrate section of the workpiece, wherein the first substrate section and the second substrate section are spaced apart by an insulating feature; forming a common gate structure that wraps around each of the multiple first channel elements and each of the multiple second channel elements; turning the workpiece over; after turning it over, forming a pilot opening through the insulating feature; widening the pilot opening through the common gate structure to form a gate-cut opening that separates the common gate structure into a first gate structure and a second gate structure; and after widening, depositing a dielectric material into the gate-cut opening to form a gate-cut feature.

[0042] In some embodiments, the method may further include: recessing, prior to forming the pilot aperture, the first substrate section and the second substrate section, and depositing, after recession, a helmet layer over the first and second substrate sections. In some implementations, forming the pilot aperture includes: depositing a hard mask over the helmet layer and the isolation feature, structuring the hard mask to expose a portion of the isolation feature and a portion of the helmet layer, and etching the isolation feature using the structured hard mask and the helmet layer as an etching mask. In some cases, the helmet layer contains aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), or tungsten (W).In some embodiments, the method may further include depositing a lining over the sidewalls of the pilot opening after its formation. In some cases, the method may further include forming a dielectric self-aligned contact (SAC) layer over the common gate structure before inversion. The expansion also enlarges the pilot opening through the dielectric SAC layer.

Claims

[1] Semiconductor device comprising: a first gate structure (250-1) arranged over a first rear-side dielectric feature (290); a second gate structure (250-2) arranged over a second rear-side dielectric feature (290); a gate cut feature (288) that extends continuously from a point between the first gate structure (250-1) and the second gate structure (250-2) to a point between the first backside dielectric feature (290) and the second backside dielectric feature (290); a lining (284) arranged between the gate cutting feature (288) and the first rear dielectric feature (290) and between the gate cutting feature (288) and the second rear dielectric feature (290); a dielectric self-aligned contact (SAC) layer (256) arranged above the first gate structure (250-1) and the second gate structure (250-2); an etch stop layer (212) over the dielectric SAC layer (256); and a dielectric front-side layer (210) above the etch stop layer (212), wherein the gate cutting feature (288) extends into the dielectric SAC layer (256), the etch stop layer (212) and the dielectric front side layer (210). [2] Semiconductor device according to claim 1, wherein the first gate structure (250-1) and the second gate structure (250-2) are arranged over the lining (284). [3] Semiconductor device according to claim 1 or 2, further comprising: a gate spacer (216) extending from a side wall of the first gate structure (250-1) to a side wall of the second gate structure (250-2), wherein the gate cutting feature (288) is in contact with the gate spacer (216). [4] Semiconductor device according to one of the preceding claims, wherein the gate cutting feature (288) is in direct contact with the first gate structure (250-1) and the second gate structure (250-2). [5] Semiconductor device according to any of the preceding claims, wherein the first rear-side dielectric feature (290) comprises silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonitride, silicon oxynitride or silicon carbonitride. [6] Semiconductor device according to any of the preceding claims, wherein the lining (284) comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide or silicon oxynitride. [7] Semiconductor device according to any of the preceding claims, wherein the gate cutting feature (288) comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide or silicon oxynitride. [8] Semiconductor structure comprising: a dielectric layer (234); a Contact Etch Stop Layer, CESL (232) arranged above the dielectric layer (234); an insulation feature (204) arranged above the CESL (232); and a gate cutting feature (2880) extending through the insulation feature (204), the CESL (232) and the dielectric layer (234), wherein the gate cutting feature (2880) is arranged between a first gate structure (2500) and a second gate structure (2500) and between a third gate structure (2502) and a fourth gate structure (2502), wherein the dielectric layer (234) is arranged above an etch stop layer (212) and a dielectric front side layer (210), wherein the gate cutting feature (2880) comprises two leg sections, each extending into the etch stop layer (212) and the dielectric front side layer (210). [9] Semiconductor structure according to claim 8, wherein the first gate structure (2500) and the second gate structure (2500) are aligned along one direction, wherein the third gate structure (2502) and the fourth gate structure (2502) are aligned along the direction. [10] Semiconductor structure according to claim 8 or 9, wherein the gate cutting feature (2880) is spaced apart from the isolation feature (204) by a lining (284). [11] Semiconductor structure according to any one of claims 8 to 10, further comprising: a metal feature (304) that is positioned between the two leg sections such that the gate cutting feature (2880) extends over the metal feature (304). [12] Semiconductor structure according to any one of claims 8 to 10, further comprising: a dielectric feature (298) which is arranged between the two leg sections such that the gate cutting feature (2880) extends over the dielectric feature (298).

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