PROCESSES FOR SEMICONDUCTOR STRUCTURES

Abstract

Procedure comprising: Providing a structure comprising a substrate (202) and a stack of semiconductor layers (215) over a surface of the substrate (202) which are vertically spaced from each other; Forming an interface layer (280) surrounding each of the semiconductor layers (215); Forming a high-k dielectric layer (282) encasing each of the semiconductor layers (215) over the interface layer (280); Forming a cap layer (284) encasing each of the semiconductor layers (215) over the high-k dielectric layer (282); when the capping layer (284) encloses each of the semiconductor layers (215), performing a thermal treatment of the structure, thereby increasing a thickness of the interface layer (280); and after carrying out the thermal treatment, removing the cover layer (284), wherein the cover layer (284) contains an oxygen-binding oxide or an oxygen-binding nitride and the thermal treatment is carried out with oxygen (O2) from the environment.

Description

BACKGROUND

[0001] The electronics industry is facing increasing demand for ever smaller and faster electronic components that are capable of supporting a greater number of increasingly complex and sophisticated functions. The semiconductor industry, therefore, continues to trend toward producing high-performance, low-cost, and low-power integrated circuits to meet this demand. These goals have so far been achieved primarily by reducing the size of integrated circuits (ICs), thereby improving production efficiency and reducing associated costs. However, such scaling has also led to greater complexity in the semiconductor manufacturing process.Thus, implementing advances in semiconductor devices and their performance requires similar advances in semiconductor manufacturing processes and technology.

[0002] GAA devices are promising candidates for advancing CMOS to the next level of development, featuring improved gate controllability, lower leakage current, and complete compatibility with FinFET device layouts. A GAA device is a device with vertically stacked, horizontally aligned multi-channel transistors, such as nanowire and nanosheet transistors. However, the fabrication of GAA devices is proving increasingly difficult given the continued shrinkage of the vertical gap between channels (or sheets). One challenge in fabricating such small GAA devices is how to incorporate multiple layers of high-k metal gates into the vertical gap between the channels.Accordingly, existing semiconductor devices (particularly multi-gate devices) and processes for their fabrication have been generally adequate for their intended purpose, but have not been entirely satisfactory in all respects.

[0003] A manufacturing method and a semiconductor structure are known from US 10 763 177 B1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] This disclosure will best be understood by considering the following detailed description in conjunction with the accompanying figures. It should be emphasized that, consistent with industry practice, various elements are not drawn to scale and are for illustrative purposes only. Rather, the dimensions of various elements may be increased or decreased as desired for illustrative purposes. Both Fig. 1A and Fig. 1B are flow diagrams for methods of manufacturing a semiconductor device according to various aspects of the present disclosure. Fig. 2A is a schematic top view of portions of a semiconductor device according to various aspects of the present disclosure. Fig. 2B and Fig. 2C are schematic cross-sectional views of parts of the semiconductor device in Fig. 2A according to an embodiment of the present disclosure. Both Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 and Fig. 14 are schematic cross-sectional views of parts of the semiconductor device of Fig. 2A in various stages of production (such as those produced using the process in Fig. 1A and Fig. 1B) according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of implementing various features of the subject matter. Certain example components and arrangements are described below to simplify the present disclosure. In the following description, forming a first element on or at a second element may include, for example, embodiments where the first and second elements are formed in direct contact, as well as embodiments where additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. In addition, throughout the present disclosure, reference numbers and / or reference characters may be repeated throughout the various examples.This repetition is for the purpose of simplification and clarity and does not in itself prescribe any relationship between the various embodiments and / or configurations explained.

[0006] Spatially related terms such as "beneath," "under," "lower," "above," "above," "above," "upper," and the like may also be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially related terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially related descriptors used herein may also be interpreted accordingly.Furthermore, when describing a number or range of numbers with "about," "approximately," and the like, unless otherwise noted, the term includes numbers that fall within certain deviations (such as + / - 10% or other deviations) of the described number, according to the knowledge available in the art in light of the specific technology disclosed herein. Thus, the term "about 5 nm" may apply to the measurement range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, etc.

[0007] The present disclosure relates generally to semiconductor devices such as integrated circuits (ICs), and more particularly to IC devices containing GAA devices (or GAA transistors). A GAA device is a transistor with multiple vertically stacked, horizontally aligned channels, such as a nanowire and a nanosheet transistor. GAA devices are promising candidates for advancing CMOS to the next level in the development roadmap due to their improved gate controllability, lower leakage current, and complete compatibility with FinFET device layouts. However, fabricating GAA devices is proving increasingly difficult given the continued reduction of the vertical spacing between channels (or sheets).One challenge in fabricating such small GAA devices is how to insert various layers of high-k metal gates into the vertical gap between the channels. Such layers include an interface layer, a high-k gate dielectric layer, and a work-function metal layer for adjusting the gate threshold voltage. This issue is more critical for certain devices (such as transistors that perform input / output (I / O) functions, electrostatic discharge functions, or high-voltage functions), where the interface layer is generally thicker than core devices (such as transistors that perform core logic or memory functions), leaving even less room for other layers to fill the gap between channels.

[0008] The present disclosure utilizes an oxygen-scavenging cap layer and a thermal treatment to regrow (or thicken) the interfacial layer in select GAA devices (such as IO-GAA, ESD-GAA, and high-voltage GAA devices). In one embodiment of the present disclosure, after forming a first interfacial gate dielectric layer and a high-k dielectric layer around the channels in a semiconductor structure (such as an IC), a cap layer is formed and patterned. The cap layer is an oxygen-scavenging oxide or, in some embodiments, an oxygen-scavenging nitride. The cap layer is retained in selected regions (such as an IO region of the semiconductor structure) where the interfacial gate dielectric layer needs to be thickened and removed in other regions of the semiconductor structure. A thermal treatment is then performed on the semiconductor structure.The interface gate dielectric layer in the selected regions becomes thicker due to the presence of the cap layer and the thermal treatment. In some embodiments, the interface gate dielectric layer may be about 0.2 nm (2 Å) to about 1 nm (10 Å) thicker. The cap layer is then removed, and a work function metal layer is deposited in the space between the channels. The present disclosure provides the following advantages. First, embodiments of the present disclosure allow the thickness of the interface gate dielectric layers in selected regions to be precisely tuned to achieve small GAA transistors. Second, the present methods prevent the space between channels from being filled in GAA devices with an interface gate dielectric layer and a high-k dielectric layer, leaving enough space for the deposition of one or more work function metal layers.This enables a multiple patterning gate (MPG) process to achieve multiple threshold voltages (Vt) in the same integrated circuit, such as standard, lower, higher Vt, etc. Details of the manufacturing methods and structures of the present disclosure are described with reference to the accompanying figures.

[0009] Both Fig. 1A and Fig. 1B are flow diagrams for a method 100 for manufacturing a semiconductor device according to various aspects of the present disclosure. In some embodiments, the method 100 produces a semiconductor device having GAA transistors. Additional processing is contemplated by the present disclosure. Additional steps may be provided before, during, or after the method 100, and some of the steps described below may be rearranged, replaced, or eliminated for additional embodiments of the method 100. The method 100 is described below in connection with the Fig. 2A to 14. Fig. 2A is a schematic top view of portions of a semiconductor device 200 in a manufacturing stage associated with the method 100 according to various aspects of the present disclosure. Fig. 2B to 14 are schematic cross-sectional views of portions of the device 200 in various manufacturing stages associated with the method 100 according to various aspects of the present disclosure.

[0010] The device 200 of the present embodiments is a multi-gate device (or multi-gate device) that may be included in a microprocessor, memory, and / or other integrated circuit devices. In some embodiments, the device 200 may be a part of an IC chip, a system-on-a-chip (SoC), or a part thereof that includes various passive and active microelectronic components such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally double-diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.In some embodiments, the multi-gate device 200 is included in non-volatile memory such as non-volatile random-access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically erasable programmable read-only memory (EPROM), another suitable memory type, or combinations thereof. Fig. 2A through 14 are simplified for clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to device 200, and some of the features described below may be replaced, altered, or eliminated in other embodiments of device 200. Fabrication of device 200 is described below in connection with embodiments of method 100.

[0011] In the method 100, at step 102 ( Fig. 1A) a first structure of the device 200, a part of which is shown in accordance with an embodiment in the Fig. 2A to 2C, provided or supplied thereto. Fig. In particular, Figure 2A illustrates that device 200 includes two regions 200A and 200B. Region 200A includes an active region 204A and a gate region 206A generally perpendicular to active region 204A. Active region 204A includes two source / drain (S / D) regions and a channel region between the two S / D regions. Gate region 206A abuts the channel region. Region 200A further includes dielectric fins 231 longitudinally extending generally parallel to active region 204A and on either side of active region 204A. The gate region 206A extends in the y-direction between the two dielectric fins 231. The transistor 200B also includes an active region 204B and a gate region 206B that extends generally perpendicular to the active region 204B. The active region 204B includes two S / D regions and a channel region between the two S / D regions. The gate region 206B is adjacent to the channel region.Region 200B further includes dielectric fins 231 extending longitudinally generally parallel to active region 204B and on both sides of active region 204B. Gate region 206B extends in the y-direction between the two dielectric fins 231. In some embodiments, dielectric fins 231 are omitted from region 200A, region 200B, or both regions 200A and 200B.

[0012] Fig. Figure 2B illustrates a cross-sectional view of the device 200 according to an embodiment, which is a cross-sectional view of the regions 200A and 200B along the line A1-A1 and B1-B1, respectively, in Fig. 2A. Fig. Figure 2C illustrates a cross-sectional view of the device 200 according to an embodiment, which is a cross-sectional view of the regions 200A and 200B along the line A2-A2 and B2-B2, respectively, in Fig. 2A. In the case of the Fig. 2B and Fig. The embodiments illustrated in FIG. 2C are nanosheet FETs whose channel layers 215 are in the form of nanosheets. Regions 200A and 200B are illustrated as having the same configuration for clarity and to better understand the inventive concepts of the present disclosure. Regions 200A and 200B may have a different configuration in various embodiments. For example, they may have a different number of channels and / or their channel layers 215 may be of a different shape or size. As another example, one of regions 200A and 200B may be a nanowire FET (i.e., the channel layers 215 are in the form of nanowires or nanorods) or a nanosheet FET.

[0013] The component 200 in Fig. 2B and Fig. 2C includes a substrate (such as a wafer) 202. In the depicted embodiment, the substrate 202 includes silicon. The substrate 202 may alternatively or additionally include another elemental semiconductor such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Alternatively, the substrate 202 is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0014] Each of the regions 200A and 200B further comprises two S / D elements 260. For n-type transistors, the S / D elements 260 are n-type. For p-type transistors, the S / D elements 260 are p-type. The S / D elements 260 may be formed by epitaxially growing semiconductor material(s) (e.g., Si, SiGe) to fill trenches in the device 200, for example, using CVD deposition techniques (e.g., chemical vapor deposition), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S / D elements 260 are doped with suitable n- and / or p-type dopants. For example, for n-type transistors, the S / D elements 260 may include silicon and be doped with carbon, phosphorus, arsenic, another n-type dopant, or combinations thereof, and for p-type transistors, the S / D elements 260 may include silicon germanium or germanium and be doped with boron, another p-type dopant, or combinations thereof.

[0015] Each of the regions 200A and 200B further includes a stack of semiconductor layers 215 that freely hang above the substrate 202 and connect the two S / D elements 260. The stack of semiconductor layers 215 serves as transistor channels for the respective transistors. The semiconductor layers 215 are accordingly also referred to as channel layers 215. The channel layers 215 are exposed in a gate trench 275, which is formed by removing a dummy gate from the corresponding gate region 206A and 206B ( Fig. 2A) is formed therein. The channel layers 215 may comprise single-crystal silicon. Alternatively, the channel layers 215 may comprise germanium, silicon germanium, or one or more other suitable semiconductor materials. The channel layers 215 are first formed as part of a semiconductor layer stack comprising the channel layers 215 and other semiconductor layers made of a different material. The semiconductor layer stack is patterned into a fin protruding above the substrate 202 using one or more photolithography processes, including double and multiple patterning processes. Once the gate trenches 275 are formed, the semiconductor layer stack is selectively etched to remove the other semiconductor layers so that the channel layers 215 hang above the substrate 202 and between the respective S / D elements 260. The channel layers 215 are separated from each other and from the substrate 202 by gaps 277.

[0016] In some embodiments, each channel layer 215 has dimensions on the nanometer scale and thus may be referred to as a nanostructure. For example, in some embodiments, each channel layer 215 may have a length (in the x-direction) of about 10 nm to about 300 nm, a width (in the y-direction) of about 10 nm to about 80 nm, and a height (in the z-direction) of about 4 nm to about 8 nm. The vertical spacing 277 (in the z-direction) between the channel layers 215 may be about 6 nm to about 12 nm in some embodiments. Thus, the channel layer 215 may be referred to as a "nanowire" or "nanosheet," which generally refers to a channel layer that is suspended in such a way that a high-k metal gate can physically wrap around it. In some embodiments, the channel layers 215 may be cylindrical (e.g., nanowire), rectangular (e.g., nanorod), layered (e.g., nanosheet), or have another suitable shape.

[0017] The device 200 further includes one or more isolation elements 230 for isolating various regions, such as the various active regions 204A and 204B. The isolation elements 230 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (such as silicon, oxygen, nitrogen, carbon, or another suitable isolation component), or combinations thereof. The isolation elements 230 may have different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. The isolation elements 230 may comprise multiple layers of isolation material.

[0018] The device 200 further includes gate spacers 247 adjacent to the S / D elements 260. The gate spacers 247 may include silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In some embodiments, the gate spacers 247 include a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. The device 200 further includes internal spacers 255 located vertically between adjacent channel layers 215 and adjacent to the S / D elements 260.The internal spacers 255 may include a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the internal spacers 255 include a low-k dielectric material. The gate spacers 247 and the internal spacers 255 are formed by deposition (e.g., CVD, PVD, ALD, etc.) and etching (e.g., dry etching) processes. The gate trenches 275 are located in the x-direction between opposing gate spacers 247 and internal spacers 255.

[0019] The device 200 further includes a contact etch stop layer (CESL) 268 disposed on the isolation elements 230, the epitaxial S / D elements 260, and the gate spacers 247. The CESL 268 includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. The CESL 268 may be formed by a deposition process such as CVD or other suitable methods. The device 200 may further include an interlayer dielectric (ILD) layer 270 on the CESL 268. The ILD layer 270 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. The ILD layer 270 may be formed by a deposition process such as CVD, flowable CVD (FCVD), or other suitable methods.

[0020] The dielectric fins 231 are arranged on the insulation elements 230. In the Fig. 2C, the dielectric fins 231 include a dielectric liner 232, a dielectric fill layer 233 on the dielectric liner 232, and a dielectric cap 234 on the dielectric layers 232 and 233. In one embodiment, the dielectric liner 232 includes a low-k dielectric material, such as a dielectric material such as Si, O, N, and C. Example low-k dielectric materials include FSG, carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, polyimide, or combinations thereof. Low-k dielectric materials are generally dielectric materials with a low dielectric constant, for example, less than that of silicon oxide (k ≈ 3.9). The dielectric liner 232 may be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof.In one embodiment, the dielectric fill layer 233 includes silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. The dielectric fill layer 233 may be deposited using a flowable CVD (FCVD) process, which may include, for example, depositing a flowable material (such as a liquid) on the device 200 and converting the flowable material into a solid material using a suitable technique, such as annealing and / or ultraviolet radiation treatment. The dielectric fill layer 233 may be deposited using other types of processes. In one embodiment, the dielectric cap 234 includes a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO. x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide alloy (HfO2-Al2O3 alloy), other suitable high-k dielectric material, or combinations thereof. High-k dielectric materials are generally dielectric materials with a high dielectric constant, for example, greater than that of silicon oxide (k ≈ 3.9). The dielectric cap 234 is formed by one of the processes described herein, such as ALD, CVD, PVD, an oxidation-based deposition process, another suitable process, or combinations thereof. The gate trenches 275 are provided in the y-direction between opposing dielectric fins 231.

[0021] In step 104, in the method 100 ( Fig. 1A) an interface gate dielectric layer (or simply interface layer) 280 is formed on the surfaces of the channel layers 215 exposed in the gate trenches 275, as in Fig. 3 is shown. The Fig. 3 to 14 represent cross-sectional views of the area 200A and 200B along the line A2-A2 and the line B2-B2, respectively, in Fig. 2A. In the Fig. 3, the interface layer 280 wraps around each of the channel layers 215 and partially fills the gaps 277. In the present embodiment, the interface layer 280 is disposed on the semiconductor surfaces exposed in the gate trench 275, such as the surfaces of the channel layers 215 and the substrate 202, but not on the dielectric surfaces exposed in the gate trench 275, such as the surfaces of the isolation elements 230, the gate spacers 247, and the dielectric fins 231. The interface layer 280 may be formed, for example, by an oxidation process (such as thermal or chemical oxidation) in which the semiconductor surfaces react with oxygen to form a semiconductor oxide as the interface layer 280. In such an oxidation process, the dielectric surfaces do not react with the oxygen, so that no interface layer 280 is formed thereon.In an alternative embodiment, the interface layer 280 is deposited, for example, using atomic layer deposition (ALD) or other suitable deposition techniques, not only on the channel layers 215 and the substrate 202, but also on the isolation elements 230, the gate spacers 247, and the dielectric fins 231. The interface layer 280 includes a dielectric material such as SiO2, HfSiO, SiON, other silicon-containing dielectric material, other suitable dielectric material, or combinations thereof. In some embodiments, the interface layer 280 has a thickness of about 0.5 nm (5 Å) to about 1.5 nm (15 Å). If the interface layer 280 is too thin (e.g., less than 0.5 nm (5 Å) thick), it may be unstable in some cases.If the interface layer 280 is too thick (e.g., more than 1.5 nm (15 Å) thick), the remaining portion of the gaps 277 may, in some cases, be too small to be filled with a high-k dielectric layer and a work function metal layer.

[0022] In step 106, in the method 100 ( Fig. 1A) a high-k gate dielectric layer (or simply high-k dielectric layer) 282 is formed on the interface layer 280 and other structures exposed in the gate trench 275, as in Fig. 3 is shown. In Fig. 3, the high-k dielectric layer 282 is deposited on the interface layer 280 and encloses each of the channel layers 215. The high-k dielectric layer 282 and the interface layer 280 together partially fill the gaps 277. In the present embodiment, the high-k dielectric layer 282 is also disposed on the isolation elements 230, the gate spacers 247, and the dielectric fins 231. For example, in one embodiment, the high-k dielectric layer 282 is disposed directly on the isolation elements 230, the gate spacers 247, and the dielectric fins 231. The high-k dielectric layer 282 contains a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), hafnium dioxide-alumina alloy (HfO2-Al2O3 alloy), other suitable high-k dielectric material, or combinations thereof. The high-k dielectric layer 282 is formed by one of the processes described herein, such as ALD, CVD, PVD, an oxidation-based deposition process, another suitable process, or combinations thereof. In some embodiments, the high-k dielectric layer 282 has a thickness in the range of about 1 nm to about 2 nm.

[0023] In step 108, the method 100 ( Fig. 1A), as in Fig. 4, according to one embodiment, a cap layer 284 is formed on the high-k dielectric layer 282 in the regions 200A and 200B. In Fig. 4, in both regions 200A and 200B, the cap layer 284 is deposited on the high-k dielectric layer 282 and encloses each of the channel layers 215. The cap layer 284 is also deposited on the isolation elements 230 and the dielectric fins 231. The cap layer 284, the high-k dielectric layer 282, and the interface layer 280 together only partially fill the gaps 277 between adjacent channel layers 215 in the present embodiment. This contributes to a more uniform increase in the thickness of the interface layer 280 during subsequent thermal treatment. In the present embodiment, the cap layer 284 includes one or more oxygen-scavenging materials. In other words, the cap layer 284 includes one or more materials that attract oxygen (O2) from the ambient (oxygen in the ambient of the device 200).The capping layer 284 includes, for example, an oxygen-scavenging oxide, an oxygen-scavenging nitride, or other oxygen-scavenging materials. The one or more oxygen-scavenging materials further exhibit etch selectivity relative to the materials in the high-k dielectric layer 282. In other words, the capping layer 284 may be removed in a subsequent step via an etching process that involves little or no etching of the high-k dielectric layer 282. In one embodiment, the capping layer 284 includes TiN, TiSiN, TiO2, TiON, TaN, TaSiN, TaO2, TaON, or a combination thereof. As will be explained, embodiments of the present disclosure utilize the oxygen-scavenging property of the capping layer 284 to increase the thickness of the interface layer 280 in selected device regions, such as region 200B.By employing such techniques, sufficient spacing can be maintained between the high-k dielectric layer 282 on the adjacent channel layers 215, while achieving a sufficiently thick interface layer 280 for certain transistors such as IO transistors, ESD transistors, and high-voltage transistors. In some embodiments, the capping layer 284 can be deposited using ALD, CVD, a thermal process (such as a furnace process), a PVD process, or other suitable processes, and at a temperature in the range of about 100°C to about 400°C and a pressure in the range of about 133.3 Pa (1 Torr) to 13.3 kPa (100 Torr). In some embodiments, the capping layer 284 has a thickness in the range of about 0.5 nm (5 Å) to 5 nm (50 Å). If the cap layer 284 is too thin (e.g., less than 0.5 nm (5 Å) thick), its uniformity and efficiency as an oxygen scavenger may be poor in some cases.If the capping layer 284 is too thick (e.g., more than 5 nm (50 Å) thick), the capping layer 284 on the dielectric fins 231 may fuse with that on the channel layers 215, causing problems in subsequent steps, such as an uneven increase in the thickness of the interface layer 280.

[0024] In step 110, the method 100 ( Fig. 1A) the cap layer 284 is patterned such that it is retained in regions where the interface layer 280 is thickened and removed in other regions. The cap layer 284 is retained in the region 200B and removed in the region 200A in the present embodiment. This may be done by various processes such as deposition, photolithography, and etching. The cap layer 284 may be patterned using any suitable techniques. Fig. 1B illustrates a flowchart of step 110 according to one embodiment. Other processing is contemplated by the present disclosure. Some of the Fig. 1B may be shifted, replaced, or eliminated for additional embodiments of step 110.

[0025] In step 110 in Fig. 1B is at step 130, as in Fig. 5, according to one embodiment, a hard mask layer (HM layer) 286 (also referred to as sacrificial layer 286) is formed on the cap layer 284. In the Fig. 5, the HM layer 286 partially fills the gate trenches 275 and encloses the channel layers 215 in both device regions 200A and 200B. The HM layer 286 is also deposited on the dielectric fins 231 and the isolation elements 230. The HM layer 286 may be deposited via any of the processes described herein, such as ALD, CVD, PVD, another suitable process, or combinations thereof. A thickness of the HM layer 286 is configured to fill any remaining portion of the gaps 277 between the adjacent channel layers 215 in the device regions 200A and 200B without filling the gate trenches 275. As will be explained, it would be difficult to pattern a later deposited protective layer if the HM layer 286 does not fill the remaining part of the gaps 277 between the adjacent channel layers 215.In some embodiments, the HM layer 286 has a thickness of about 0.5 nm (5 Å) to about 5 nm (50 Å). If the HM layer 286 is too thin (less than 0.5 nm (5 Å) thick), its uniformity and efficiency as a hard mask may be poor in some cases during subsequent steps, or it may not completely fill the remaining portion of the gaps 277 between the adjacent channel layers 215. If the HM layer 286 is too thick (e.g., more than 5 nm (50 Å) thick), the HM layer 286 on the dielectric fins 231 may fuse with that on the channel layers 215, causing problems during subsequent steps (e.g., this may prevent a protective layer from being properly deposited and patterned).

[0026] The HM layer 286 includes a material that achieves high etch selectivity between the HM layer 286 and the cap layer 284 during an etching process. For example, the HM layer 286 may be selectively etched in an etching process, which may be a dry or wet etching process, with minimal (or no) etching of the cap layer 284. In some embodiments, the etch selectivity is at least 100:1. In other words, the HM layer 286 is etched during the etching process at a rate that is at least 100 times the rate at which the cap layer 284 is etched. In some embodiments, the HM layer 286 includes aluminum oxide, silicon nitride, lanthanum oxide, silicon (such as polysilicon), silicon carbonitride, silicon oxycarbonitride, aluminum nitride, aluminum oxynitride, a combination thereof, or other suitable materials.In some embodiments, the HM layer 286 may be deposited using ALD, CVD, a thermal process (such as a furnace process), a PVD process, or other suitable processes and at a temperature in the range of about 100°C to about 400°C and a pressure in the range of about 133.3 Pa (1 Torr) to 13.3 kPa (100 Torr).

[0027] In step 110 ( Fig. 1B) is at step 132, as in Fig. 6, according to one embodiment, the HM layer 286 is etched such that it remains only in the gaps 277 (ie, in the space lying vertically between different parts of the cap layers 284 on the channel layers 215) and is removed everywhere else. In Fig. 6, the HM layer 286 is partially removed, and the remaining portions of the HM layer 286 fill the gap between portions of the cap layer 284 on the channel layers 215 and the substrate 202 in both device regions 200A and 200B. For convenience, the remaining portions of the HM layer 286 are sometimes referred to as sacrificial (HM) plugs 286. In some embodiments, the etching process is a wet or a dry etching process using etchants with high etch selectivity toward the HM layer 286 with respect to the cap layer 284. In some embodiments, the etchants have an etch selectivity (i.e., a ratio of an etch rate of the HM layer 286 to an etch rate of the cap layer 284 in the etching solution) of at least about 100. In some embodiments, a wet etching process employing an NH4OH-based wet etching solution is used in step 132.In some embodiments, step 132 uses a wet etching process employing an SC-1-based wet etching solution, wherein the SC-1 solution contains deionized water, ammonia, and hydrogen peroxide in a suitable ratio to achieve the selectivity discussed above. In some embodiments, step 132 uses a dry etching process employing fluorine-, chlorine-, bromine-based, or other suitable etching gases. For example, NF3, BCl3, HBr, or other suitable etching gases may be used in the dry etching process.Parameters of the etching process (such as etching temperature, etching solution concentration, etching gas flow rate, etching time, other suitable etching parameters, or combinations thereof) are controlled such that the HM layer 286 is removed from the top portion of the cap layer 284, the sidewalls of the channel layers 215, the dielectric fins 231, and the isolation elements 230 with minimal (or no) etching of the cap layer 284.

[0028] In step 110, at step 134 ( Fig. 1B), as in Fig. 7, according to one embodiment, a protection layer 288 may be formed on the device 200, including in regions 200A and 200B. The protection layer 288 may include, for example, a bottom anti-reflective coating (BARC) material that provides a platform for photoresist coating and photoresist patterning. In one embodiment, the protection layer 288 is formed by spin-coating a BARC material onto the device 200 and filling the gate trenches 275 and firing the BARC material (for example, at a temperature in the range of about 100°C to about 200°C) to cause cross-linking in the BARC material. Since the HM elements 286 fill the vertical gap between the channel layers 215 and between the bottommost channel layer 215 and the substrate 202, no protection layer 288 is formed in these gaps.

[0029] In step 110, at step 136 ( Fig. 1B), as in Fig. 8, according to one embodiment, the protective layer 288 is patterned to be removed in region 200A and retained in region 200B. This creates a patterned protective layer 288. In one embodiment, a lithography process is employed in step 110, which includes forming a resist layer (or photoresist layer) on the device 200 by spin coating, performing a pre-exposure firing process, an exposure process, and a post-exposure firing process, and developing the exposed resist layer in a developer solution. After development, the resist layer is a resist pattern corresponding to the photomask, wherein the resist pattern covers the device region 200B and exposes the device region 200A. The exposure process may be implemented using a photomask or a maskless lithography process such as electron beam writing, ion beam writing, or combinations thereof.In step 110, the protective layer 288 is etched and removed from the device region 200A using the resist pattern as an etch mask. In one embodiment, an anisotropic etch process is used when etching the protective layer 288 so that the remaining part of the protective layer 288 on the region 200B is better preserved and the boundary between the regions 200A and 200B can be influenced more precisely. This improves the resolution of step 110. As shown in FIG. Fig. 8, after removing the protective layer 288 in the region 200A, the cover layer 284 and the HM layer 286 are exposed there.

[0030] In step 110, at step 138 ( Fig. 1B) using the structured protective layer 288 and any remaining parts of the resist structure as an etching mask, the cover layer 284 and the HM layer 286 are etched, thereby removing the cover layer 284 and the HM layer 286 in the region 200A. The resulting structure is shown in Fig. 9 according to one embodiment. Region 200B is protected by protection layer 288 prior to the etch process. During the etch process, HM layer 286 and cap layer 284 in region 200A are completely removed, exposing high-k dielectric layer 282 there. The etch process essentially reclaims or re-forms a portion of gaps 277 in region 200A. In one embodiment, two etch processes are employed in step 110, one etch process removing HM layer 286 and another removing cap layer 284. In another embodiment, one etch process removing both HM layer 286 and cap layer 284 is employed in step 110. The etching process(es) in step 138 provide high etch selectivity to the HM layer 286 and the cap layer 284 with respect to the high-k dielectric layer 282.In some embodiments, the etch process(es) has an etch selectivity of about 10 to about 100. In some embodiments, the etch selectivity is at least 100. At step 138, wet etching, dry etching, or a combination thereof may be used. For example, a wet etch process employing an NH4OH or SC-1-based wet etch solution may be used to remove the HM layer 286. The cap layer 284 may be removed, for example, using a wet etch process employing a H2O2-containing wet etch solution, an SC-2 (Standard Clean 2)-based wet etch solution, or an SPM (Sulphuric Peroxide Mix)-based wet etch solution. The cap layer 284 may also be removed using a dry etch process employing NF3, BCl3, HBr, Cl2, CF4, SF6, other gases, or a mixture thereof.Parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) are controlled to ensure complete removal of the HM layer 286 and the cap layer 284 in the region 200A with minimal (or even no) etching of the high-k dielectric layer 282. In some embodiments, the patterned protection layer 288 is partially etched during the etching process.

[0031] In step 110, at step 140 ( Fig. 1B) the structured protective layer 288 is removed, for example, by stripping or burning (ashing). The resulting structure is shown in Fig. 10 according to one embodiment. The cap layer 284 and the HM layer 286 are exposed in the region 200B.

[0032] In step 110, at step 142 ( Fig. 1B) the remaining parts of the HM layer 286 in the region 200B are removed. The resulting structure is shown in Fig. 11 according to one embodiment. In some embodiments, the etching process is a wet etching process or a dry etching using etchants having a high etch selectivity to the HM layer 286 with respect to the cap layer 284 and the high-k dielectric layer 282. In some embodiments, the etchants have an etch selectivity (i.e., a ratio of an etch rate of the HM layer 286 to an etch rate of the cap layer 284 and the high-k dielectric layer 282 in the etching solution) of at least about 100. In some embodiments, a wet etching process employing an NH4OH-based wet etching solution is used in step 142.In some embodiments, step 142 uses a wet etch process employing an SC-1-based wet etch solution, wherein the SC-1 solution contains deionized water, ammonia, and hydrogen peroxide in a suitable ratio to achieve the selectivity discussed above. In some embodiments, step 142 uses a dry etch process employing fluorine-, chlorine-, bromine-based, or other suitable etch gases. For example, the dry etch process may use NF3, BCl3, HBr, or other suitable etch gases. Parameters of the etch process (such as etch temperature, etch solution concentration, etch gas flow rate, etch duration, other suitable etch parameters, or combinations thereof) are controlled to remove the HM layer 286. Using steps 130 to 142, step 110 patterns the cap layer 284 to be removed in region 200A and retained in region 200B. In . Fig. 11, the cap layer 284 is retained on the high-k dielectric layer 282 in region 200B and removed in region 200A.

[0033] In the method 100, at step 112 ( Fig. 1A) a thermal treatment 300 is carried out on the component 200, as in Fig. 12. As will be explained, due to the presence of the cap layer 284, the presence of oxygen (O2) in the environment, and the thermal treatment 300, the interface layer 280 thickens in the region 200B. The thickened interface layer 280 in the region 200B is in Fig. 12 is designated 280b. The interface layer 280 in the region 200A is Fig. 12 to distinguish it from the interface layer 280b. In some embodiments, the interface layer 280a may become slightly thicker than the interface layer 280 (before step 112) depending on the conditions during the thermal treatment 300. In some embodiments, the interface layer 280b is about 0.2 nm (2 Å) to about 1 nm (10 Å) thicker than the interface layer 280 (before step 112). In some embodiments, the interface layer 280b is about 0.2 nm (2 Å) to about 1 nm (10 Å) thicker than the interface layer 280a (after step 112). In some embodiments, the interface layer 280b has a thickness in the range of about 1.0 nm to about 2.0 nm after completion of the thermal treatment 300. Such a thickness is suitable for transistors with IO, ESD or high voltage functions.If the interface layer 280b is too thin (for example, thinner than 1.3 nm), it may not be able to withstand the voltage applied to such transistors in some cases. If the interface layer 280b is too thick (for example, thicker than 1.6 nm), there may not be enough space between the channel layers 215 for the high-k dielectric layer 282 and the subsequently deposited work function metal layer 430 (Fig. Fig. 14).

[0034] In one embodiment, the thermal treatment 300 is a rapid thermal anneal (RTA) or a spike anneal process. An RTA or spike anneal process can be used, for example, to anneal a single wafer (supporting the device 200) by rapidly raising a temperature using a high-pressure lamp, a hot chuck, or a hot plate near the wafer. The temperature can be raised to a range of about 600°C to about 1000°C within seconds or even milliseconds. In another embodiment, the thermal treatment 300 is a soak anneal process. A single wafer (supporting the device 200) can be held at a temperature in the range of about 600°C to about 1000°C for a duration in the range of about a few seconds to a few minutes, for example.In yet another embodiment, the thermal treatment 300 is a furnace process. A plurality of individual wafers (some of which support the device 200) may be maintained in a furnace at a temperature in the range of about 300°C to about 600°C for a duration in the range of about 30 minutes to about 3 hours, for example. In each of the above embodiments, the wafer(s) are annealed with oxygen (O2) in the environment of the wafer(s) (i.e., the wafer(s) are annealed with oxygen (O2) from the environment). In some embodiments, the environment further includes nitrogen (N2) in addition to oxygen (O2). The environment may include, for example, 99% oxygen (O2) and 1% nitrogen (N2), 1% oxygen (O2) and 99% nitrogen (N2), or another mixture of oxygen and nitrogen. In some embodiments, the environment may include one or more noble gases in addition to oxygen (O2).

[0035] As previously explained, capping layer 284 contains an oxygen-scavenging material that attracts oxygen from the surrounding environment. During thermal treatment 300, region 200B attracts oxygen from the surrounding environment, which diffuses through capping layer 284, high-k dielectric layer 282, and interface layer 280 and reacts with the semiconductor material(s) in channel layers 215 (such as silicon) in region 200B. The reaction increases the thickness of interface layer 280. Since no capping layer 284 is present in region 200A, there is little reaction (or a significantly lower reaction than in region 200B) between oxygen from the surrounding environment and the semiconductor material(s) in channel layers 215 in region 200A. As a result of the reaction between semiconductor and oxygen, the thickness of interface layer 280 increases in region 200B.The amount by which the thickness increases can be more precisely tuned by adjusting the amount of oxygen in the environment, the thermal treatment process (such as the annealing temperature and duration), the thickness of the capping layer, and so on. In one embodiment, the thickness of the interfacial layer 280 in region 200B is increased by about 0.2 nm (2 Å) to about 1 nm (10 Å). If the thickness does not increase sufficiently (such as by less than 0.2 nm (2 Å)), there will be insufficient thickening for IO functions (such as input / output and ESD) compared to core functions. If the thickness increases too much (such as by more than 1 nm (10 Å)), then the channel width of the remaining channel layers 215 may not be large enough, as the thickness of the channel layers 215 in region 200B may decrease by about twice the amount of the increase in the thickness of the interfacial layer 280.For example, in various embodiments, the thickness of the channel layers 215 in region 200B may decrease by 0.4 nm (4 Å) to about 2 nm (20 Å) in the z-direction and by about 0.4 nm (4 Å) to about 2 nm (20 Å) in the y-direction. In various embodiments, the high-k dielectric layer 282 remains approximately in the same location in both regions 200A and 200B, such that the distance 277 between the high-k dielectric layer 282 at adjacent channel layers 215 and the substrate 202 remains approximately the same before and after the thermal treatment 300. Furthermore, the horizontal distance between the high-k dielectric layer 282 at the channel layers 215 and the dielectric fins 231 remains approximately the same before and after the thermal treatment 300. Thus, embodiments of the present disclosure provide methods for forming interface layers of different thicknesses in different regions (such as regions 200A and 200B) through the same process.Compared to approaches in which interface layers are formed in different regions by different deposition and patterning processes, the present disclosure simplifies the manufacturing processes.

[0036] In the method 100, at step 114 ( Fig. 1A) the cover layer 284 is removed from the device 200. The resulting structure is shown in Fig. 13 according to one embodiment. In Fig. 13, the device 200 in region 200A includes the channel layers 215, the interface layer 280a surrounding the channel layers 215, and the high-k dielectric layer 282 lying on the interface layer 280a and surrounding the channel layers 215. The high-k dielectric layers 282 on the adjacent channel layers 215 and between the bottommost channel layer 215 and the substrate 202 are separated by the gap 277. The high-k dielectric layer 282 is also disposed directly on the surfaces of the dielectric fins 231. In region 200B, device 200 includes channel layers 215, interface layer 280b surrounding channel layers 215, and high-k dielectric layer 282 lying on interface layer 280b and surrounding channel layers 215. High-k dielectric layers 282 on adjacent channel layers 215 and between the bottommost channel layer 215 and substrate 202 are separated by gap 277.The high-k dielectric layer 282 is also disposed directly on the surfaces of the dielectric fins 231.

[0037] In the method 100, at step 116 ( Fig. 1A), a work function metal layer 430 is formed on the high-k dielectric layer 282 and a bulk metal layer 350 is formed on the work function metal layer 430. The resulting structure is shown in Fig. 14 according to one embodiment. In Fig. 14, in both regions 200A and 200B, the workfunction metal layer 430 is deposited on the high-k dielectric layer 282 and around each of the channel layers 215. The workfunction metal layer 430 is also disposed on the dielectric fins 231 and the isolation elements 230. The portions of the workfunction metal layer 430 lying on the dielectric fins 231 are separated from the portions of the workfunction metal layer 430 lying on the channel layers 215 by a vertical gap filled with the bulk metal layer 350. In some embodiments, the work function metal layer 430 comprises an n-type work function metal for n-type transistors such as Ti, Al, Ag, Mn, Zr, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function material, or combinations thereof.In some embodiments, the work function metal layer 430 comprises a p-type work function metal for p-type transistors such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function material, or combinations thereof. In some embodiments, the work function metal layer 430 has a thickness of about 1 nm to about 4 nm. The work function layer 430 may be deposited using ALD, CVD, PVD, or other suitable processes. Since the gate trenches 275 (. Fig. 13) have sufficient space, at step 116, different work function metal layers 430 may be formed in different regions (such as in regions 200A and 200B) or to provide different threshold voltages (such as standard, lower, higher Vt, etc.) for different transistors. The bulk metal layer 350 may be deposited to fill remaining portions of the gate trenches 275 using ALD, CVD, PVD, plating, or other suitable processes. The bulk metal layer 350 includes a suitable conductive material such as Al, W, and / or Cu. The bulk metal layer 350 may additionally or altogether include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some implementations, optionally (e.g.Using ALD, a barrier layer (not shown) may be formed on the work function layer 430 prior to forming the bulk metal layer 350, so that the bulk metal layer 350 is disposed on the barrier layer. After the bulk metal layer 350 is deposited, a planarization process may then be performed to remove excess gate material from the device 200. For example, a CMP process may be performed until a top surface of the dielectric fins 231 is reached (exposed).

[0038] As in Fig. 14, the channel layers 215 in region 200A have both a vertical thickness T1 and a channel pitch S1 in the z-direction. Thus, the channel layers 215 in region 200A have a vertical pitch (either center-to-center or edge-to-edge pitch) (T1+S1). The channel layers 215 in region 200B have both a vertical thickness T2 and a channel pitch S2 in the z-direction. Thus, the channel layers 215 in region 200B have a vertical pitch (either center-to-center or edge-to-edge pitch) (T2+S2). In some embodiments, the pitch T1+S1 approximately corresponds to the pitch T2+S2. The channel layers 215 are each further spaced laterally from the vertical surface of the dielectric fin 231 in the y-direction by a distance G1 in region 200A and by a distance G2 in region 200B.In some embodiments, the distance S1 ranges from about 6 nm to about 12 nm, and the distance S2 is about 0.4 nm (4 Å) to about 2 nm (20 Å) greater than the distance S1. In some embodiments, the thickness T1 ranges from about 4 nm to about 8 nm, and the thickness T2 is about 0.4 nm (4 Å) to about 2 nm (20 Å) less than the thickness T1. In some embodiments, the distance G1 ranges from about 5 nm to about 30 nm, and the distance G2 is about 0.2 nm (2 Å) to about 1 nm (10 Å) greater than the distance G1.

[0039] In the method 100, at step 118 ( Fig. 1A) further fabrication of the device 200. For example, in the method 100, S / D contacts can be formed that are electrically connected to the S / D elements 260 ( Fig.2B) to form gate vias electrically connected to the bulk metal layer 350 and multilayer interconnects connecting the transistors and other components in the device 200 to form a complete integrated circuit.

[0040] One or more embodiments of the present disclosure provide numerous advantages in a semiconductor device and its formation. For example, embodiments of the present disclosure can be used to precisely tune the thickness of interfacial gate dielectric layers in selected regions or transistors to achieve small GAA devices. In another example, embodiments of the present disclosure can be used to closely maintain channel pitch in GAA devices, leaving sufficient space for depositing one or more work function metal layers. This enables a multiple patterning gate (MPG) process to achieve multiple threshold voltages (Vt) in the same integrated circuit, such as standard, lower, higher Vt, etc.The present embodiments can be easily integrated into existing CMOS manufacturing processes.

[0041] The invention is defined by the main claim and the subordinate claim. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Procedure comprising: Providing a structure comprising a substrate (202) and a stack of semiconductor layers (215) over a surface of the substrate (202) which are vertically spaced from each other; Forming an interface layer (280) surrounding each of the semiconductor layers (215); Forming a high-k dielectric layer (282) encasing each of the semiconductor layers (215) over the interface layer (280); Forming a cap layer (284) encasing each of the semiconductor layers (215) over the high-k dielectric layer (282); when the capping layer (284) encloses each of the semiconductor layers (215), performing a thermal treatment of the structure, thereby increasing a thickness of the interface layer (280); and after carrying out the thermal treatment, removing the cover layer (284), wherein the cover layer (284) contains an oxygen-binding oxide or an oxygen-binding nitride and the thermal treatment is carried out with oxygen (O2) from the environment. [2] The method of claim 1, further comprising, after removing the cover layer (284): Forming a work function metal layer (430) encasing each of the semiconductor layers (215) over the high-k dielectric layer (282). [3] The method of claim 2, further comprising: Forming a bulk metal layer (350) over the work function metal layer (430). [4] Method according to one of the preceding claims, wherein a vertical gap remains between adjacent semiconductor layers (215) when forming the cap layer (284). [5] Method according to one of the preceding claims, wherein the cover layer (284) contains TiN, TiSiN, TiO2, TiON, TaN or TiSiN. [6] A method according to any one of the preceding claims, wherein the thermal treatment is further carried out with nitrogen (N2) from the environment. [7] Method according to one of the preceding claims, wherein the thermal treatment increases the thickness of the interface layer (280) by about 0.2 nm to about 1 nm. [8] A method according to any one of the preceding claims, wherein the thermal treatment is a spike anneal or a soak anneal at a temperature in the range of about 600°C to about 1000°C. [9] A method according to any one of claims 1-7, wherein the thermal treatment is a furnace annealing at a temperature in the range of about 300°C to about 600°C. [10] Procedure comprising: Forming first nanostructures (215) in a first region (200A) over a substrate (202); Forming second nanostructures (215) in a second region (200B) on the substrate (202); Forming an interface layer (280) surrounding the first nanostructures (215) and the second nanostructures (215); Forming a high-k dielectric layer (282) encasing the first nanostructures (215) and the second nanostructures (215) over the interface layer (280); Forming a capping layer (284) enclosing the first nanostructures (215) and the second nanostructures (215) over the high-k dielectric layer (282), wherein forming the capping layer leaves a vertical gap between adjacent first nanostructures (215) and a vertical gap between adjacent second nanostructures (215); Removing the cap layer (284) in the first region (200A) to expose the high-k dielectric layer (282) in the first region (200A) while maintaining the cap layer (284) over the high-k dielectric layer (282) in the second region (200B); Performing a thermal treatment of the first nanostructures (215) and the second nanostructures (215), wherein the interface layer (280) in the second region (200B) is thicker than the interface layer (280) in the first region (200A) after performing the thermal treatment; and after the thermal treatment, removing the cover layer (284) in the second region (200B), wherein during the thermal treatment, the second region (200B) attracts oxygen from the environment, which diffuses through the cover layer (284), the high-k dielectric layer (282) and the interface layer (280) and reacts with the second nanostructure(s) (215) in the second region (200B). [11] The method of claim 10, wherein removing the cover layer (284) in the first region (200A) comprises: Forming a hard mask layer (286) that fills a space between the first nanostructures (215) and a space between the second nanostructures (215); Forming a protective layer (288) over the first region (200A) and the second region (200B); Structuring the protective layer (288) into a structured protective layer (288) exposing the first region (200A) and covering the second region (200B); Removing the hard mask layer (286) and the cap layer (284) from the first region (200A) using the patterned protective layer (288) as an etch mask; Removing the structured protective layer (288); and after removing the patterned protective layer (288), removing the hard mask layer (286) in the second region (200B). [12] The method of claim 11, wherein the hard mask layer (286) comprises aluminum oxide, silicon nitride, lanthanum oxide, silicon, silicon carbonitride, silicon oxycarbonitride, aluminum nitride, or aluminum oxynitride. [13] The method of any one of claims 10 to 12, wherein the first region (200A) is a core region of an integrated circuit and the second region (200B) is an IO region of the integrated circuit. [14] Method according to one of claims 10 to 13, wherein the thermal treatment is carried out with oxygen (O2) from the environment and the cover layer (284) contains an oxygen-binding oxide or an oxygen-binding nitride. [15] The method of any one of claims 10 to 14, wherein the cover layer (284) contains TiN, TiSiN, TiO2, TiON, TaN or TiSiN. [16] A method according to any one of the preceding claims 10 to 15, wherein the thermal treatment is further carried out with nitrogen (N2) from the environment. [17] Method according to one of the preceding claims 10 to 16, wherein the thermal treatment increases the thickness of the interface layer (280) by about 0.2 nm to about 1 nm. [18] A method according to any one of the preceding claims 10 to 17, wherein the thermal treatment is a spike anneal or a soak anneal at a temperature in the range of about 600°C to about 1000°C. [19] A method according to any one of the preceding claims 10 to 17, wherein the thermal treatment is a furnace annealing at a temperature in the range of about 300°C to about 600°C.

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