Bandgap reference circuit with vertically stacked active SOI devices

Abstract

Bandgap reference circuit (500, 600), comprising: first and second vertically stacked structures (200), wherein the first and second vertically stacked structures (200) each comprise: a P-type substrate (202); a P-well region (204) within the P-type substrate (202); an N-type barrier region (206) between the P-type substrate (202) and the P-well region (204), wherein the P-well region (204) and the N-type barrier region (206) form a PN junction; a FET (210, 604A, 604B) above the P-well region (204), which is separated from the P-well region (204) by a buried insulator layer (208), wherein the P-well region (204) forms a substrate gate of the FET (210, 604A, 604B); and a first voltage source coupled to the P-well region (204) and applying a forward bias to a diode formed at the PN junction between the P-well region (204) and the N-type barrier region (206).

Description

BackgroundThe present invention relates to integrated circuits, and more particularly to a band gap reference circuit having vertically stacked active silicon-on-insulator (SOI) devices.In many prior art integrated circuits, an accurate reference voltage is required that is less sensitive to the supply voltage, less sensitive to variable process and model parameters, and has low temperature sensitivity. The band gap voltage of silicon is independent of the supply voltage, almost independent of the temperature and shows almost no dependence on the process. For these reasons, the most accurate voltage references used today are designed so that the output voltage is proportional to the band gap voltage. Such a reference voltage is referred to as a "bandgap reference".Many conventional band gap reference circuits use bipolar transistors in a diode circuit. In implementing a bandgap reference circuit with complementary metal-oxide semiconductor (CMOS) devices, the bipolar transistors are implemented with parasitic vertically stacked PNP (VPNP) devices in a diode-connected embodiment. However, VPNP devices are typically very large compared to the surrounding CMOS devices.US 2014 / 0 015 052 A1 discloses an integrated circuit element which comprises a UTBOX insulation layer under and perpendicular to first and second electronic components and corresponding base plates and oppositely doped wells. DE 10 2008 034 158 A1 mentions an integrated circuit having a semiconductor arrangement in thin-film SOI technology which combines different semiconductor substrate structures of different conductivity types in order to achieve specific electrical properties, in particular in order to reduce disruptive influences caused by parasitic bipolar transistor structures.SummaryA first aspect of the invention is directed to a bandgap reference circuit comprising: first and second vertically stacked structures, the first and second vertically stacked structures each comprising: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) over the P-well region separated from the P-well region by a buried insulator layer, the P-well region forming a substrate gate of the FET; and a first voltage source coupled to the P well region and applying a forward bias voltage to a diode formed at the PN junction between the P well region and the N-type barrier region.A second aspect of the invention is directed to an integrated circuit comprising: a bandgap reference circuit for generating a reference current, the bandgap reference circuit comprising: first and second vertically stacked structures, the first and second vertically stacked structures each comprising: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) over the P-well region separated from the P-well region by a buried insulator layer, the P-well region forming a substrate gate of the FET, the FET in the first vertically stacked structure and the FET in the second vertically stacked structure forming a current mirror; and a first voltage source coupled to the P-well region and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region, the first voltage source simultaneously biasing the substrate gate of the FET.The above and other features of the invention will be apparent from the following more detailed description of the embodiments of the invention. According to the invention, there is provided an apparatus according to claim 1 or 11.Brief Description of Several Views of the DrawingsThe embodiments of this invention are described in detail with reference to the following figures, wherein like numerals designate like elements, Fig. 1 shows a conventional band gap reference circuit. FIG. 2 illustrates a semiconductor structure with vertically stacked active silicon-on-insulator (SOI) devices, according to embodiments. FIG. 3 is an equivalent circuit for the semiconductor structure 200 shown in FIG. 2, according to embodiments. FIG. 4 is an equivalent circuit diagram of the semiconductor structure of FIG. 2 in a diode-connected configuration according to embodiments. FIG. 5 illustrates a band gap reference circuit according to embodiments. FIG. 6 illustrates a band gap reference circuit according to embodiments. FIG. 7 shows an example of area reduction by a bandgap reference circuit according to embodiments. FIG. 8 shows output voltages (measured and simulated) at various temperatures for a conventional bandgap reference circuit and a bandgap reference circuit according to embodiments. FIG. 9 shows output voltages (measured and simulated) at different supply voltages for a conventional bandgap reference circuit and a bandgap reference circuit according to embodiments.It should be noted that the drawings of the invention are not necessarily to scale. The drawings are intended to represent only typical aspects of the invention and should therefore not be considered as limiting the scope of the invention. In the drawings, like reference numerals represent like elements throughout the drawings.Detailed DescriptionIn the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention, and it will be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present invention. The following description is therefore merely illustrative in nature.A bandgap reference circuit implemented with vertically stacked silicon-on-insulator (SOI) active devices according to embodiments is described herein. A very compact bandgap reference circuit is provided by stacking active SOI devices (e.g., field effect transistors (FETs)) via diodes to significantly reduce the area required by the bandgap reference circuit.FIG. 1 illustrates a conventional complementary metal-on-insulator (CMOS) bandgap reference circuit 200. The band gap reference circuit 200 includes the FETs 102, 104, an operational amplifier 106, the resistors R 1, R 2, R 3, and the bipolar transistors (BJTs) 108, 110 (e.g., parasitic VPNP devices) in a diode-connected configuration.The bandgap reference circuit 100 is used to generate a reference voltage (~1.2 V) that remains stable over a wide temperature range. The operational amplifier 106 ensures that the voltage at nodes 'a' and 'b' is at the same voltage. There is a voltage difference between the two BJTs 108, 120 caused by the difference in their device sizes (e.g., 8:1 according to this example). This voltage appears across resistor R1 and is referred to as "proportional to absolute temperature" (PTAT). To obtain a size difference of N between the BJTs 108, 110 in the design of the bandgap reference circuit 100, the BJT 108 is typically copied and placed N times in the design to generate the BJT 110, resulting in a 1:N size ratio between the BJT 108 and the BJT 110.In contrast to the PTAT voltage, the voltage across the BJTs 108, 110 is a "complementary to absolute temperature" (CTAT). The CTAT voltage and the PTAT voltage scaled up with the resistor R 2 are added so that their temperature dependencies cancel each other out. The resulting output voltage V OUT at the node connecting resistors R2 and R3 remains approximately constant over temperature.A semiconductor structure 200 (structure 200) including vertically stacked active silicon-on-insulator (SOI) devices according to embodiments is illustrated in FIG. 2. In FIG. 3, an equivalent circuit 300 for the structure 200 is shown. In FIG. 4, an equivalent circuit 400 is shown with structure 200 in a diode connected configuration. As described in more detail herein, the structure 200 may be incorporated into a bandgap reference circuit to substantially reduce the power requirement and area requirement of the bandgap reference circuit (e.g., on an IC chip / device). The structure 200 includes a PNP junction disposed vertically below and aligned with an FET. The PNP junction may operate as a BJT and may be configured to operate as a diode. In this context, "vertically aligned" or "vertical alignment" refers to the FET being positioned vertically over two PN junctions that together form the PNP junction and at least partially horizontally overlap with respect to a source-drain electrical path over the FET.A PN junction is a device structure in which P-type and N-type semiconductor regions are brought into contact with each other, thereby forming a potential barrier. The size of the potential barrier is determined by the bias voltage applied between the P-type and N-type regions. A PN junction, when formed in a device, may operate as a diode. A diode is a two terminal element that behaves differently between two electrical contact points than conductive or insulating materials. In particular, a diode provides high conductivity from one contact to another in one direction (i.e., the "forward" direction), but little to no conductivity in the opposite direction (i.e., the "reverse" direction). In the case of the PN junction, the alignment of the forward and reverse directions of a diode may depend on the type and magnitude of the bias voltage applied to the material composition of one or both terminals, which affects the size of the potential barrier. In the case of a transition between two semiconductor materials, the potential barrier is formed along the interface between the two semiconductor materials.The structure 200 may be formed from a substrate 202, e.g., comprising one or more semiconductor materials, and may be implanted with P-dopants. The structure 200 may also include a P-well region 204 formed within the substrate 202, e.g., by vertical ion implantation, such that a top surface of the P-well region 204 is aligned with and thus shared with a top surface of the substrate 202. Although the P-well region 204 may have the same doping type as the substrate 202, the P-well region 204 may have a higher or lower doping concentration than the substrate 202. Thus, the P-well region 204 may be differentiated from the substrate 202 based at least in part on the doping concentration, the dopants, etc., even if the P-well region 204 and the substrate 202 are of the same doping type.To form a three terminal PNP junction (e.g., for a BJT) as described herein, the structure 200 may include an N-doped barrier region 206 (barrier region 206) between the substrate 202 and the P-well region 204. The barrier region 206 may be formed within the substrate 202 before the P-well region 204 is formed, and the P-well region 204 may be formed within the barrier region 206 in such cases. In either case, the barrier region 206 may be formed within the substrate 202 to a depth less than the entire thickness of the substrate 202, but may have a top surface coincident with the top surface of the P-well region 204. The barrier region 206 may be formed by implanting N-type dopants into the substrate 202 and / or a precursor semiconductor material by any presently known or later developed technique, e.g., ion implantation. N-type dopants are elements introduced into semiconductor materials to generate free electrons, e.g., by "donating" an electron to the semiconductor. N-type dopants must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) are, for example, phosphorus (P), arsenic (As) and / or antimony (Sb).Transistors (e.g., FET 210 discussed herein) and / or other devices may be formed on P-well region 204 to control various operations of a device, e.g., logic, electrical functions, etc. In the structure 200, the P-well region 204 may serve as a substrate gate region for controlling the electrical characteristics of a transistor formed thereon. A buried insulator layer 208, also known as a "buried oxide" or "BOX" layer, may separate the P-well region 204, as well as optionally the substrate 202 and the barrier layer 206, from overlying portions of a transistor structure, such as the FET 210. Buried insulator layer 208 may be formed of one or more oxide compounds and / or other presently known or later developed electrically insulating substances. Buried insulator layer 208 may be dimensioned as narrow as possible to allow better interaction with P-well region 204. If transistors formed on buried insulator layer 208 also have functional components on a similar thickness scale, structure 200 may be considered a fully depleted semiconductor on insulator (FDSOI) structure. Due to the use of the P-well region 204, the structure 200 may be considered a "flipped-well" device. The use of FDSOI technology offers various advantages, such as adjustable transistor electrical potential by applying a bias voltage to the P-well region 204.A FET 210 may be formed over the buried insulator layer 208 such that the buried insulator layer 208 physically separates the FET 210 from the P-well region 204. The FET 210 may take the form of a three terminal transistor according to one of a plurality of device architectures. The FET 210 is shown as a planar FET for purposes of example, but it is understood that various embodiments of the invention may also include FET(s) 210 in the form of fin-type FETs ("FinFETs"), nanosheet transistors, vertically oriented FET(s) ("VFETs"), and / or any other transistor architecture now known or later developed, and may also include P-type and N-type FETs. The buried insulator layer 208 may separate the P-well region 204 from a source region (S), a drain region (D), and a channel region 214 interposed between the source region S and the drain region D.The source region S and the drain region D and the channel region 214 of the FET 210 may electrically couple a source terminal 216 of the FET 210 to a drain terminal 218 when the FET 210 is in an on state. A gate (G) stack 220 may be disposed over the channel region 214 such that a voltage applied to the gate terminal 222 controls the electrical conductivity between the source and drain terminals 216, 218 via the source region S and drain region D and the channel region 214. The gate stack 220 may include, for example, one or more electrically conductive metals, in addition to a gate dielectric material (characterized by a white space between the bottom of the gate stack 220 and the channel region 214) to separate the conductive metal(s) of the gate stack 220 from at least the channel region 214. In conventional settings, the FET 210 would be the only electrically active component formed over a corresponding portion of the substrate 202. Embodiments of the invention, however, allow a PNP junction and thus a BJT or one or more diodes to be formed in vertical alignment with the FET 210. To form the PNP junction, bias voltages may be applied to the various doped semiconductor materials (i.e., the substrate 202, the P-well region 204, and the barrier region 206) in the structure 200.To apply independent bias voltages to the substrate 202, the P-well region 204, and the barrier region 206, embodiments of the invention may include forming conductive elements in each of the respective regions. To prevent electrical short circuit and / or inadvertent biasing of adjacent elements, the structure 200 may include a group of trench isolation regions 224 to electrically and physically separate the various doped materials of the structure 200. The trench isolation regions 224 may be made of an insulating material such as silicon dioxide (SiO 2) or a high-k dielectric. The trench isolation regions 224 may be formed by selective etching of portions of the structure 200 to create openings and form one or more insulating materials within the openings, e.g., by deposition.As shown, the trench isolation regions 224 may be positioned adjacent to the inner vertical surfaces of the barrier region 206. The trench isolation regions 224 may be formed to separate different contacts from each other and / or from other doped materials of the structure 200. For example, the structure 200 may include a contact 226 to the P-well region 204. Contact 226 (and other contacts described herein) may include one or more conductive materials formed on and / or partially within P-well region 204, e.g., one or more conductive metals and / or conductive silicide regions. The contact 226 may additionally include, for example, refractory metal coatings (not shown) to horizontally separate conductive materials of the contact 226 from the trench isolation regions 224 and / or other horizontally adjacent materials. Such coatings may include materials such as, but not limited to: tantalum nitride (TaN) and tantalum; tantalum nitride, tantalum and cobalt; and magnesium (Mn), or combinations thereof.A voltage source V 1 may be electrically coupled to a contact 228 to apply a corresponding bias voltage to the barrier region 206. Additionally, a voltage source V2 may be electrically coupled to a contact 230 to apply a corresponding bias voltage to the substrate 202. Further, a voltage source V 3 may be electrically coupled to the contact 226 to apply a bias voltage (e.g., "substrate gate bias") to the P-well region 204. In the case of an FDSOI transistor architecture, the voltage source V 3 may affect the initial conductivity between the source region S and the drain region D of the FET 200 via the channel region 214. Applying a voltage V 3 to the contact 226 may induce an electric charge within the P-well region 204 that generates a difference in electric potential between the P-well region 204, the source region S and the drain region D, and the channel region 214 via the buried insulator layer 208. Among other effects, this difference in electrical potential between the P-well region 204, the source region S and the drain regions, and the channel region 214 may affect the threshold voltage V T of the FET 210. The threshold voltage V T of the FET 210 refers to the minimum voltage for inducing the electrical conductivity across the channel region 214 between the source region S and the drain region D. A bias voltage in the P-well region 204 may decrease or increase the threshold voltage V T required for operation of the FET 210. These characteristics of an FDSOI structure may allow, among other things, a smaller width (saving silicon area) compared to conventional applications and transistor structures.Transistors in FDSOI technology included in structure 200 provide the ability to apply a bias voltage to P-well region 204 to manipulate threshold voltage V T( i.e., the minimum voltage for channel formation) of FET 210. As mentioned above, the bias voltage applied to the P-well region 204 may also be electrically coupled to other elements of the structure 200 to provide additional functions and / or elements of the structure 200.Parasitic diodes D 1, D 2, and D 3 may be formed within the structure 200 below the FET 210. The parasitic diodes D 1 and D 2 may be formed at the PN junction between the substrate 202 and the barrier region 206. The parasitic diode D 3 is formed at the PN junction between the P well region 204 and the barrier region 206. According to embodiments, voltage sources V 1 and V 2 may be used to apply a negative bias voltage to substrate 202 and barrier region 206 to reverse bias diodes D 1, D 2, while voltage source V 3 may be used to apply a positive bias voltage to P-well region 204 to forward bias diode D 3. An equivalent circuit 300 for the structure 200 is shown in FIG. 3.An equivalent 'diode' circuit 400 of structure 200 in a diode connected configuration is illustrated in FIG. 4. In the diode-connected configuration, gate G, source S, and drain D of the FET 210 are connected to ground. The voltages V1 and V2 are also connected to ground. A positive bias voltage (V3) is applied to the substrate gate B (e.g., the P-well region 204) of the structure 200.FIG. 5 illustrates a band gap reference circuit 500 according to embodiments. Comparing FIG. 1 with FIG. 5, it can be seen that each of the FETs 102, 104 (FIG. 1 ) has been replaced by the FET 210 in the structure 200. In addition, each of the parasitic VPNP devices (e.g., BJTs 108, 110 in a diode-connected configuration) has been replaced with diode circuit 400 in structure 200 (e.g., structure 200 in a diode-connected configuration). As such, four instances of the structure 200 are required to implement the bandgap reference circuit 500 illustrated in FIG. 5. In the structures 200 including the FETs 210, the voltages V 1, V 2, and V 3 are connected to ground. In the diode circuits 400, the voltages V1, V2 are connected to ground, and the voltage V3 is the voltage at the node 'a' or the node 'b'.According to embodiments of the invention, vertical stacking of active devices in structure 200 may be exploited to provide a bandgap reference circuit 600 that requires significantly less area (e.g., on an IC) without compromising performance. For example, in the band gap reference circuit 600 illustrated in FIG. 6, a combined device 602 (e.g., 602A, 602B) is provided (using structure 200) that combines the functionality of the FET 210 and the diode circuit 400 (as illustrated by arrows X, Y in FIG. 5 ).Similar to the bandgap reference circuit 100 illustrated in FIG. 1, the bandgap reference circuit 600 is configured to generate a reference output voltage V OUT( ~1.2 V) at an output node 'c' that remains stable over a wide temperature range. Each combined device 602A, 602B includes an FET 604A, 604B and a forward biased parasitic diode 606A, 606B. The FETs 604A, 604B form a current mirror.There is a voltage difference between the two FETs 604A, 604B caused by the different size of their devices (e.g., 8:1 in this example). This voltage appears across resistor R1 and is referred to as "proportional to absolute temperature" (PTAT). The size difference N between the FETs 604A, 604B may be obtained in various ways. For example, to obtain a size difference N between the FETs 604A, 604B in the design of the bandgap reference circuit 600, the FET 604A (and other portions of the structure 200 (e.g., P-well region 204, barrier region 206, substrate 202, etc.)) may be copied and placed N times to generate the FET 604B in the design, resulting in a size ratio between the FET 604A and the FET 604B of 1:N.The voltage across the parasitic diodes 606A, 606B is a voltage complementary to 'absolute temperature' (CTAT). The CTAT voltage and the PTAT voltage scaled up with the resistor R 2 are added so that their temperature dependencies cancel each other out. The resulting output voltage VOUTat node 'c' connecting resistors R2 and R3 remains approximately constant over temperature.In the band gap reference circuit 600, the voltages V1, V2 are connected to ground, and the voltage at the two nodes 'a' and 'b' is V3. Diode 606A in combined device 602A is forward biased by applying voltage V3 at node 'a' to substrate gate B of FET 604A. Diode 606B is forward biased by applying voltage V3 at node 'b' to substrate gate B of FET 604B. The source S of each FET 604A, 604B is connected to a supply voltage VDD.The inputs of an operational amplifier 608 are coupled to nodes 'a' and 'b'. The output of the operational amplifier 608 is coupled to the gate G of each of the FETs 604A, 604B. The operational amplifier 608 causes the voltage at nodes 'a' and 'b' to be at the same voltage V3.Resistor R1 is connected between node 'b' and the back gate B of FET 604B in combined package 602B. Resistor R2 is connected between node 'b' and the drain of FET 604B. Resistor R3 is connected between node 'a' and the drain D of FET 604A in combined device 602A.As described, vertical stacking of active devices in structure 200 may be utilized to provide a bandgap reference circuit 600 that requires significantly less area (e.g., on an IC) without suffering performance. Based on simulated and measured silicon (Si) results and similar to conventional bandgap reference circuits, the bandgap reference circuit 600 is capable of generating an output voltage VOUTof ~1.2V, regardless of the supply voltage VDDand over a wide temperature range. Moreover, the bandgap reference circuit 600 requires less supply current (IDD) as compared to conventional bandgap reference circuits and thus has a lower power requirement.An example of area reduction by the bandgap reference circuit 600 is illustrated in FIG. 7. The larger rectangle 700 represents the area required for implementing a conventional bandgap reference circuit with parasitic vertical PNP transistors (e.g., the bandgap reference circuit 100 (FIG. 1 )) designed in silicon (Si) using a particular semiconductor processing technology (e.g., GlobalOund 22FDX). The smaller rectangle 702 represents the area required by a bandgap reference circuit 600 according to embodiments designed in Si using the same semiconductor processing technology. Area and supply current (IDD) measurements for the conventional bandgap reference circuit and bandgap reference circuit 600 are listed below:As such, the bandgap reference circuit 600 provides an area reduction of about 85% and a supply current reduction of about 65%.FIG. 8 shows the output voltages V OUT( measured (Si) and simulated) at different contact temperatures for a conventional bandgap reference circuit (BGR) (e.g., bandgap reference circuit 100) and the bandgap reference circuit 600 according to the embodiments. FIG. 9 shows the output voltages V OUT( measured (Si) and simulated) at different supply voltages V DD for a conventional bandgap reference circuit (e.g. bandgap reference circuit 100) and the bandgap reference circuit 600 according to embodiments. As shown, the performance of the conventional bandgap circuit and the performance of the bandgap reference circuit 600 are comparable. For example, the conventional bandgap reference circuit and bandgap reference circuit 600 according to embodiments generate an output voltage of ~1.2 V over a wide temperature range (FIG. 9 ) that is substantially independent of the supply voltage V DD (FIG. 8 ). However, as described in detail herein, the bandgap reference circuit 600 requires much less area and uses less current than conventional bandgap circuits.Embodiments of the invention may provide several technical and commercial advantages, some of which are discussed by way of example herein. A structure is provided that allows an active device (e.g., an FET) to be vertically stacked over another active device (e.g., a BJT, a diode, etc.) in a single device layer. In conventional IC structures, it is typically necessary to form active devices in horizontally separated regions of a single device layer and / or to form multiple device layers for each of the various components. Moreover, embodiments of the invention allow multiple active devices (e.g., an FET, BJT, diode, etc.) to be combined into a smaller combined structure, thereby reducing the total area occupied by the active devices in one design (e.g., in a band gap reference circuit), thereby further improving device density and reducing the area required to implement different IC designs.The terminology used herein is for describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprises," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optional" means that the event described below or the circumstance described below may or may not occur, and that the description includes cases where the event occurs and cases where it does not occur.Any approximate language as used throughout the specification and claims herein may be used to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "about", "about", and "substantially" is not to be limited to the exact value indicated. At least in some cases, the approximate speech may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range constraints may be combined and / or interchanged, such ranges are identified and include all subareas included therein, unless the context or language indicates otherwise. The "approximate value" applied to a particular value of a range applies to both values and, unless otherwise dependent on the accuracy of the instrument measuring the value, may indicate + / - 10% of the indicated value / values.

Claims

A bandgap reference circuit (500, 600) comprising: first and second vertically stacked structures (200), wherein the first and second vertically stacked structures (200) each comprise: a P-type substrate (202); a P-well region (204) within the P-type substrate (202); an N-type barrier region (206) between the P-type substrate (202) and the P-well region (204), wherein the P-well region (204) and the N-type barrier region (206) form a PN junction; an FET (210, 604A, 604B) over the P-well region (204) separated from the P-well region (204) by a buried insulator layer (208), the P-well region (204) forming a substrate gate of the FET (210, 604A, 604B); and a first voltage source coupled to the P-well region (204) and applying a forward bias voltage to a diode formed at the PN junction between the P-well region (204) and the N-type barrier region (206).The band gap reference circuit (500, 600) of claim 1, further comprising: a second voltage source coupled to the N-type barrier region (206) and applying a reverse bias to a PN junction formed between the P-substrate (202) and the N-type barrier region (206); and a third voltage source coupled to the P-type substrate (202) and applying a reverse bias to the PN junction formed between the P-type substrate (202) and the N-type barrier region (206).The bandgap reference circuit (500, 600) of claim 1, wherein the N-type barrier region (206) and the P-type substrate (202) are connected to ground.The bandgap reference circuit (500, 600) of claim 1, wherein the FET (210, 604A, 604B) in the first vertically stacked structure (200) and the FET (210, 604A, 604B) in the second vertically stacked structure (200) form a current mirror.The bandgap reference circuit (500, 600) of claim 1, wherein the FET (210, 604A, 604B) in each of the first and second vertically stacked structures (200) comprises a source, a drain, and a gate, and wherein the bandgap reference circuit (500, 600) further comprises an operational amplifier (608), the operational amplifier (608) having an output coupled to the gate of the FET (210, 604A, 604B) in each of the first and second vertically stacked structures (200).The bandgap reference circuit (500, 600) of claim 5, wherein the operational amplifier (608) has a first input coupled to a first node and a second input coupled to a second node, the first node being coupled to a substrate gate of the FET (210, 604A, 604B) in the first vertically stacked structure (200).The bandgap reference circuit (500, 600) of claim 6, wherein the bandgap reference circuit (500, 600) further comprises: a first resistor coupled between the second node and the substrate gate of the FET (210, 604A, 604B) in the second vertically stacked structure (200); a second resistor coupled between the second node and the drain of the FET (210, 604A, 604B) in the second vertically stacked structure (200); and a third resistor coupled between the first node and a drain of the FET (210, 604A, 604B) in the first vertically stacked structure (200).The bandgap reference circuit (500, 600) of claim 7, wherein a voltage across the first resistor is proportional to a voltage proportional to the absolute temperature, PTAT, and wherein a voltage across the diode formed at the PN junction between the P-well region (204) and the N-type barrier region (206) in each of the first and second stacked devices is a voltage complementary to the voltage proportional to the absolute temperature, CTAT.The bandgap reference circuit (500, 600) of claim 8, further comprising an output node connected to the second and third resistors, the output node outputting a reference voltage.The bandgap reference circuit (500, 600) of claim 5, wherein the source of the FET (210, 604A, 604B) in each of the first and second vertically stacked structures (200) is coupled to a supply voltage.An integrated circuit comprising: a bandgap reference circuit (500, 600) for generating a reference current, the bandgap reference circuit (500, 600) comprising: first and second vertically stacked structures (200), the first and second vertically stacked structures (200) each comprising: a P-type substrate (202); a P-well region (204) within the P-type substrate (202); an N-type barrier region (206) between the P-type substrate (202) and the P-well region (204), wherein the P-well region (204) and the N-type barrier region (206) form a PN junction; a field effect transistor (FET (210, 604A, 604B)) over the P-well region (204) separated from the P-well region (204) by a buried insulator layer (208), the P-well region (204) forming a substrate gate of the FET (210, 604A, 604B), the FET (210, 604A, 604B) in the first vertically stacked structure (200) and the FET (210, 604A, 604B) in the second vertically stacked structure (200) forming a current mirror; and a first voltage source coupled to the P-well region (204) and applying a forward bias voltage to a diode formed at the PN junction between the P-well region (204) and the N-type barrier region (206), the first voltage source simultaneously biasing the substrate gate of the FET (210, 604A, 604B).The integrated circuit (500, 600) of claim 11, further comprising: a second voltage source coupled to the N-type barrier region (206) and applying a reverse bias to a PN junction formed between the P-type substrate (202) and the N-type barrier region (206); and a third voltage source coupled to the P-type substrate (202) and applying a reverse bias to the PN junction formed between the P-type substrate (202) and the N-type barrier region (206).The integrated circuit (500, 600) of claim 11, wherein the FET (210, 604A, 604B) in each of the first and second vertically stacked structures (200) has a source, a drain, and a gate, and wherein the bandgap reference circuit (500, 600) further comprises an operational amplifier (608), the operational amplifier (608) comprising: an output coupled to the gate of the FET (210, 604A, 604B) in each of the first and second vertically stacked structures (200); and a first input coupled to a first node and a second input coupled to a second node, the first node coupled to a substrate gate of the FET (210, 604A, 604B) in the first vertically stacked structure (200); wherein the bandgap reference circuit (500, 600) further comprises: a first resistor coupled between the second node and the substrate gate of the FET (210, 604A, 604B) in the second vertically stacked structure (200); a second resistor coupled between the second node and the drain of the FET (210, 604A, 604B) in the second vertically stacked structure (200); and a third resistor coupled between the first node and a drain of the FET (210, 604A, 604B) in the first vertically stacked structure (200).The integrated circuit (500, 600) of claim 13, wherein a voltage across the first resistor is proportional to a voltage proportional to absolute temperature, PTAT, and wherein a voltage across the diode formed at the PN junction between the P-well region (204) and the N-type barrier region (206) in each of the first and second stacked devices is a voltage complementary to absolute temperature, CTAT.The integrated circuit (500, 600) of claim 13, further comprising an output node connected to the second and third resistors, the output node outputting a reference voltage.

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