STORAGE MATRIX AND METHOD FOR THE PRODUCTION THEREOF

Abstract

Device with: a semiconductor substrate (50); a first word line (72) over the semiconductor substrate (50), the first word line (72) providing a first gate electrode (204) for a first transistor; a second word line (72) over the first word line (72), the second word line (72) being insulated from the first word line (72) by a first dielectric material (52) and providing a second gate electrode (204) for a second transistor over the first transistor; a source line (108) intersecting the first word line (72) and the second word line (72); a bit line (106) intersecting the first word line (72) and the second word line (72), the bit line (106) being insulated from the source line (108) by a second dielectric material (98); a memory layer (90) between the first word line (72) and the source line (108), the memory layer (90) also being arranged between the first word line (72) and the bit line (106); a first semiconductor material between the storage layer (90) and the source line (108), wherein the first semiconductor material is further disposed between the first word line (72) and the second source line (108); and wherein the first word line (72) is electrically connected to a third word line disposed below the first transistor.

Description

BackgroundSemiconductor memories are used in integrated circuits for electronic devices such as radios, televisions, mobile phones and personal computers. Semiconductor memories are divided into two main categories, namely volatile and nonvolatile memories. Volatile memories are random access memories (RAMs) which in turn can be divided into the two sub-groups of static random access memories (SRAMs) and dynamic random access memories (DRAMs). SRAMs and DRAMs are both volatile because they lose the information they store when not powered.In contrast, non-volatile memories can keep data stored. One type of nonvolatile semiconductor memory is a ferroelectric random access memory (FeRAM or FRAM). Advantages of an FeRAM are its high read / write speed and its small size.US 2019 / 0 148 393 A1 discloses an apparatus comprising a 3D array of cells arranged to perform a product sum operation. US 2018 / 0 350 823 A1 discloses a multilevel semiconductor device. US 2019 / 0 067 327 A1 discloses a staggered memory cell architecture with memory cells on opposite sides of a shared bit line. US 2020 / 0 119 047 A1 discloses a semiconductor device.Brief Description of the DrawingsAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.FIGS. 1A, 1B, and 1C show a perspective view, a circuit diagram, and a top-down view, respectively, of a memory array, in accordance with some embodiments.FIGS. 2, 3A, 3B, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 17A, 17A, 18B, 18B, 19A, 19B, 19B, 19B, 19B, 20, 21, 22, 23A, 23B, 23C, 24A, 25A, 25B, 25C, FIGS. 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, 28C, and 28D show various illustrations in the fabrication of a memory array, in accordance with some embodiments. FIG. 29 illustrates various representations of a memory array, in accordance with some embodiments. FIG. 30 illustrates various representations of a memory array, in accordance with some embodiments.Detailed DescriptionThe invention is defined by claim 1 defining an apparatus, claim 8 defining an apparatus, and claim 15 defining a method. Preferred embodiments of the invention are provided in the dependent claims, the description and the drawings. The following description provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present invention. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein interpreted accordingly.In various embodiments, a 3D memory array is provided having a plurality of vertically stacked memory cells. Each memory cell includes a thin film transistor (TFT) including: a word line region functioning as a gate electrode; a bit line region functioning as a first source / drain electrode; and a source line region functioning as a second source / drain electrode. Each TFT further includes an insulating memory layer (e.g., as a gate dielectric) and an oxide semiconductor (OS) channel region. In some embodiments, word lines may run in a horizontal direction (e.g., parallel to a main surface of a semiconductor substrate), while source lines and bit lines may run in a vertical direction (e.g., perpendicular to the main surface of the semiconductor substrate). The 3D memory array architecture may provide the following advantages, among other things: reduced memory cell size, higher density, reduced memory array footprint (e.g., lower stack height), and ease of manufacture.FIGS. 1A, 1B, and 1C show examples of a memory array, in accordance with some embodiments. FIG. 1A shows an example of a portion of a memory array 200 in a three-dimensional representation, FIG. 1B shows a circuit diagram of the memory array 200, and FIG. 1C shows a top-down view of the memory array 200, in accordance with some embodiments. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. The memory cells 202 may also be vertically stacked to provide a three-dimensional memory array, thereby increasing a device density. The memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array 200 may be disposed in interconnect layers of the semiconductor die, such as over one or more active devices (e.g., transistors) fabricated on a semiconductor substrate.In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a thin film transistor (TFT) 204 with an insulating memory layer 90 as a gate dielectric. In some embodiments, a gate of each TFT 204 is formed by a portion of a respective wordline (e.g., a conductive line 72), a first source / drain region of each TFT 204 is formed by a portion of a respective bitline (e.g., a conductive line 106), and a second source / drain region of each TFT 204 is formed by a portion of a respective source line (e.g., a conductive line 108) that electrically connects the second source / drain region to ground. The memory cells 202 in the same horizontal row of the memory array 200 may use a common word line, while the memory cells 202 in the same vertical column of the memory array 200 may use a common source line and a common bit line.The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines), with dielectric layers 52 disposed between adjacent ones of the conductive lines 72. The conductive lines 72 extend in a direction parallel to a main surface of an underlying substrate (not individually shown in FIGS. 1A and 1B ). The conductive lines 72 may have a staircase configuration such that lower conductive lines 72 are longer than upper conductive lines 72 and extend laterally beyond end points of the upper conductive lines 72. For example, FIG. 1A illustrates multiple stacked layers of conductive lines 72, with uppermost conductive lines 72 being the shortest and lowermost conductive lines 72 being the longest. Respective lengths of the conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each of the conductive lines 72 is accessible from a position above the memory array 200, and conductive contacts may be made with an exposed portion of each of the conductive lines 72.The memory array 200 further includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). The conductive lines 106 and 108 each extend in a direction perpendicular to the conductive lines 72, and a dielectric material 98 is disposed between and isolates adjacent ones of the conductive lines 106 and the conductive lines 108. Pairs of the conductive lines 106 and 108 together with a intersecting conductive line 72 define boundaries of each memory cell 202, and a dielectric material 102 is disposed between and isolates adjacent pairs of the dielectric lines 106 and 108. In some embodiments, the conductive lines 108 are electrically connected to ground. Although FIGS. 1A and 1C show a particular placement of the conductive lines 106 with respect to the conductive lines 108, it should be appreciated that the placement of the conductive lines 106 and 108 may be reversed in other embodiments. In addition, in FIGS. 1A and 1C, conductive lines 106 and 108 in adjacent columns of memory array 200 may be offset from one another for better isolation between memory cells 202. In other embodiments, the conductive lines 106 and 108 may have a different configuration (e.g., may be aligned with each other).As set forth above, the memory array 200 may further include an oxide semiconductor (OS) layer 92. The OS layer 92 may provide channel regions for the TFTs 204 of the memory cells 202. For example, when a corresponding voltage (e.g., higher than a respective threshold voltage V th of a respective TFT 204) is applied across a respective conductive line 72, a current may flow from the conductive lines 106 to the conductive lines 108 (e.g., in a direction indicated by an arrow 206) via a portion of the OS layer 92 intersecting the conductive line 72.Between the conductive lines 72 and the OS layer 92 is disposed a storage layer 90 that can provide gate dielectrics for the TFTs 204. In some embodiments, the memory layer 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Accordingly, the memory array 200 may also be referred to as an FeRAM (ferroelectric random access memory) array. Alternatively, the memory layer 90 may be a multilayer structure including a layer of SiN x between two SiO x- layers (e.g., an ONO structure), another ferroelectric material, another type of memory layer (e.g., which may store a bit), or the like.In embodiments where the memory layer 90 comprises a ferroelectric material, it may be polarized in one of two different directions, wherein the polarization direction may be changed by applying a corresponding voltage difference across the memory layer 90 and generating a corresponding electric field. The polarization may be relatively locally constrained (e.g., generally held between the individual boundaries of the memory cells 202), and a contiguous region of the memory layer 90 may extend across a plurality of memory cells 202. Depending on the polarization direction of a particular region of the storage layer 90, a threshold voltage of a corresponding TFT 204 changes, and a digital value (e.g., 0 or 1) may be stored. For example, if a portion of the memory layer 90 has a first electrical polarization direction, the corresponding TFT 204 may have a relatively low threshold voltage, and if the portion of the memory layer 90 has a second electrical polarization direction, the corresponding TFT 204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage offset. A larger threshold voltage offset makes it easier (e.g., less prone to errors) to read the digital value stored in the corresponding memory cell 202.In these embodiments, to perform a write operation on a memory cell 202, a write voltage is applied across a portion of the memory layer 90 corresponding to the memory cell 202. The write voltage may be applied, for example, by applying corresponding voltages to a corresponding conductive line 72 (e.g., the word line) and the corresponding conductive lines 106 and 108 (e.g., the bit line / source line). By applying the write voltage across the portion of the storage layer 90, the polarization direction of the region of the storage layer 90 can be changed. This also allows the corresponding threshold voltage of the corresponding TFT 204 to be switched from a low threshold voltage value to a high threshold voltage value or vice versa, and a digital value may be stored in the memory cell 202. Since the conductive lines 72 intersect the conductive lines 106 and 108, individual memory cells 202 may be selected for the write operation.In these embodiments, to perform a read operation on the memory cell 202, a read voltage (a voltage between the low and high threshold voltages) is applied to the corresponding conductive line 72 (e.g., the word line). Depending on the polarization direction of the corresponding region of the memory layer 90, the TFT 204 of the memory cell 202 may or may not be turned on. This may or may not discharge the conductive line 106 via the conductive line 108 (e.g., a source line connected to ground), and the digital value stored in the memory cell 202 may be determined. Since the conductive lines 72 intersect the conductive lines 106 and 108, individual memory cells 202 may be selected for the read operation.FIG. 1A also shows reference cross-sections of the memory array 200 used in subsequent figures. A cross-section B - B' runs along a longitudinal axis of the conductive lines 72 and in a direction that is, for example, parallel to the direction of current flow of the TFTs 204. A cross section C - C' is perpendicular to the cross section B - B' and is parallel to a longitudinal axis of the conductive lines 72. A cross-section D-D' is parallel to the cross-section C-C' and passes through the dielectric material 102. In subsequent figures, reference is made to these reference cross sections for clarity.In FIG. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a solid semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-dopant), or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is formed on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and / or Galliumindiumarsenidphosphid; or combinations thereof.FIG. 2 also shows circuits that may be fabricated over the substrate 50. The circuits include active devices (e.g., transistors) on a top surface of the substrate 50. The transistors may include gate dielectric layers 202 over the tops of the substrate 50 and gate electrodes 204 over the gate dielectric layers 202. Source / drain regions 206 are disposed in the substrate 50 on opposite sides of the gate dielectric layers 202 and the gate electrodes 204. Gate spacers 208 are formed along sidewalls of the gate dielectric layers 202 and separate the source / drain regions 206 from the gate electrodes 204 at respective lateral distances. In some embodiments, the transistors may be planar field effect transistors (FETs), fin field effect transistors (FinFETs), nano field effect transistors (nano FETs), or the like.A first ILD 210 (ILD: interlayer dielectric) encloses and isolates the source / drain regions 206, the gate dielectric layers 202, and the gate electrodes 204, and a second ILD 212 is disposed over the first ILD 210. Source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically connected to the source / drain regions 206, and gate contacts 216 extend through the second ILD 212 and are electrically connected to the gate electrodes 204. An interconnect structure 220 comprising one or more stacked dielectric layers 224 and conductive features 222 fabricated in the first or more dielectric layers 224 is disposed over the second ILD 212, the source / drain contacts 214, and the gate contacts 216. Although FIG. 2 shows two dielectric layers 224 stacked on top of each other, it should be appreciated that the interconnect structure 220 may include any number of dielectric layers 224 in which conductive features 222 are disposed. The interconnect structure 220 may be electrically connected to the gate contacts 216 and the source / drain contacts 214 to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure 220 may be logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, or the like, or combinations thereof. Although FIG. 2 shows transistors being fabricated over the substrate 50, other active devices (e.g., diodes or the like) and / or passive devices (e.g., capacitors, resistors, or the like) may also be fabricated as part of the functional circuits.In FIGS. 3A and 3B, a multilayer stack 58 is formed over the structure of FIG. 2. For simplicity and clarity, the substrate 50, transistors, ILDs, and interconnect structure 220 may be omitted from the following drawings. Although the multilayer stack 58 is shown contacting the dielectric layers 224 of the interconnect structure 220, a number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, one or more additional interconnect layers with conductive features may be disposed in insulating layers (e.g., low-k dielectric layers) between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide current, ground, and / or signal lines for the active devices on the substrate 50 and / or the memory array 200 (see FIGS. 1A and 1B ). Alternatively, the multilayer stack 58 may be directly disposed on the substrate 50 without any intervening features. In these embodiments, the substrate 50 may not include active devices.The multilayer stack 58 includes alternating layers of conductive layers 54A- 54D (collectively referred to as conductive layers 54) and dielectric layers 52A- 52C (collectively referred to as conductive layers 52). The conductive layers 54 may be patterned in later steps to define the conductive lines 72 (e.g., word lines). The conductive layers 54 may include a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and the dielectric layers 52 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The conductive layers 54 and the dielectric layers 52 may each be formed by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), or the like. Although FIGS. 3A and 3B show a particular number of conductive layers 54 and dielectric layers 52, in other embodiments, other numbers of conductive layers 54 and / or dielectric layers 52 may be used.FIGS. 4-12B are illustrations of intermediate stages in fabricating a stage structure of the memory array 200, in accordance with some embodiments. Figs. 4 to 11 and 12B are shown along the reference cross section B - B' of Fig. 1, and Fig. 12A is a three-dimensional view.In FIG. 4, a photoresist 56 is formed over the multilayer stack 58. As set forth above, the multilayer stack 58 may include alternating layers of conductive layers 54 (labeled 54A, 54B, 54C, and 54D) and dielectric layers 52 (labeled 52A, 52B, and 52C). The photoresist 56 may be formed by spin coating.In FIG. 5, the photoresist 56 is patterned to expose the multilayer stack 58 in regions 60 while masking remaining portions of the multilayer stack 58. For example, a top layer of the multilayer stack 58 (e.g., the dielectric layer 54D) may be exposed in the regions 60. The photoresist 56 may be patterned using suitable photolithography techniques.In FIG. 6, the exposed portions of the multilayer stack 58 in the regions 60 are etched using the photoresist 56 as a mask. The etch may be performed by any suitable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch may be anisotropic. The etch may remove portions of the conductive layer 54D and the dielectric layer 52C in the regions 60 and may define openings 61. Because the conductive layer 54D and dielectric layer 52C have different material compositions, etchants used to remove exposed portions of these layers may be different. In some embodiments, the dielectric layer 52C functions as an etch stop layer during the etching of the conductive layer 54D, and the conductive layer 54C functions as an etch stop layer during the etching of the dielectric layer 52C. This allows the portions of the conductive layer 54C and the conductive layer 54D to be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be elongated to a desired depth. Alternatively, to complete the etching of the openings 61 after they have reached a desired depth, time-controlled etching processes may be used. In the resulting structure, the conductive layer 54C is exposed in the regions 60.In FIG. 7, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using suitable photolithography techniques. Trimming reduces a width of the photoresist 56, and portions of the multilayer stack 58 in the regions 60 and regions 62 may be exposed. For example, a top surface of the conductive layer 54C may be exposed in the regions 60, and a top surface of the conductive layer 54D may be exposed in the regions 62.In FIG. 8, portions of conductive layer 54D, dielectric layer 52C, conductive layer 54C, and dielectric layer 52B in regions 60 and 62 are removed with suitable etching processes using photoresist 56 as a mask. The etch may be performed by any suitable etching process, such as wet or dry etching, e.g., reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch may be anisotropic. The etching allows the openings 61 to be extended further into the multilayer stack 58. Because the conductive layers 54D / 54C and the dielectric layers 52C / 52B have different material compositions, etchants used to remove exposed portions of these layers may be different. In some embodiments, the dielectric layer 52C functions as an etch stop layer during the etching of the conductive layer 54D; the conductive layer 54C functions as an etch stop layer during the etching of the dielectric layer 52C; the dielectric layer 52B functions as an etch stop layer during the etching of the conductive layer 54C; and the conductive layer 54B functions as an etch stop layer during the etching of the dielectric layer 52B. This allows the portions of the conductive layers 54D / 54C and the dielectric layers 52C / 52B to be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be extended to a desired depth. In addition, during the etching processes, unetched portions of the conductive layers 54 and the dielectric layers 52 function as a mask for underlying layers, and thereby a previous structure of the conductive layer 54D and the dielectric layer 52C (see FIG. 7 ) may be transferred to the underlying conductive layer 54C and the underlying dielectric layer 52B. In the resulting structure, the conductive layer 54B is exposed in the regions 60, and the conductive layer 54C is exposed in the regions 62.In FIG. 9, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using suitable photolithography techniques. Trimming reduces a width of the photoresist 56, and portions of the multilayer stack 58 in regions 60 and 62 and regions 64 may be exposed. For example, a top surface of conductive layer 54B may be exposed in regions 60; a top surface of conductive layer 54C may be exposed in regions 62; and a top surface of conductive layer 54D may be exposed in regions 64.In FIG. 10, portions of the conductive layers 54D, 54C, and 54B in the regions 60, 62, and 64 are removed with suitable etching processes using the photoresist 56 as a mask. The etch may be performed by any suitable etching process, such as by wet or dry etching, e.g., reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch may be anisotropic. The etching allows the openings 61 to be extended further into the multilayer stack 58. In some embodiments, dielectric layer 52C functions as an etch stop layer during the etching of conductive layer 54D; dielectric layer 52B functions as an etch stop layer during the etching of conductive layer 54C; and dielectric layer 52A functions as an etch stop layer during the etching of conductive layer 54B. This allows portions of the conductive layers 54D, 54C, and 54B to be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be elongated to a desired depth. Moreover, during the etching processes, the dielectric layers 52 each function as a mask for underlying layers, and thereby a previous pattern of the dielectric layers 52C / 52B (see FIG. 9 ) may be transferred to the underlying conductive layers 54C / 54B. In the resulting structure, dielectric layer 52A is exposed in regions 60; dielectric layer 52B is exposed in regions 62; and dielectric layer 52C is exposed in regions 64.In FIG. 11, the photoresist 56 may be removed using a suitable stripping or wet stripping process, for example. This creates a staircase structure 68; staircase structure 68 includes a stack of alternating conductive layers 54 and dielectric layers 52. Lower conductive layers 54 are wider than and extend laterally beyond upper conductive layers 54, with a width of each of the conductive layers 54 increasing in a direction toward the substrate 50. For example, conductive layer 54A may be longer than conductive layer 54B; conductive layer 54B may be longer than conductive layer 54C; and conductive layer 54C may be longer than conductive layer 54D. As a result, conductive contacts can be produced in later processing steps from a region above the staircase structure 68 up to each of the conductive layers 54.In FIG. 12, an inter-metal dielectric (IMD) 70 is deposited over the multilayer stack 58. The IMD 70 may be formed of a dielectric material and may be deposited by a suitable method, such as CVD, plasma enhanced CVD (PECVD), or flowable CVD (FCVD). Dielectric materials may be phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials deposited by a suitable method may also be used. The IMD 70 extends along sidewalls of the conductive layers 54 as well as along sidewalls of the dielectric layers 52.As also shown in FIG. 12, a removal process is performed on the IMD 70 to remove excess dielectric material over the multilayer stack 58. In some embodiments, a planarization process may be used, such as a chemical mechanical polishing (CMP) process, an etch back process, a combination thereof, or the like. The planarization process exposes the multilayer stack 58 such that after the planarization process is completed, tops of the multilayer stack 58 and the IMD 70 are level.FIGS. 13-17B are illustrations of intermediate stages in the fabrication of memory array 200, in accordance with some embodiments. In FIGS. 13-17B, trenches are patterned in the multilayer stack 58, thereby defining the conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and may also provide gate electrodes for the resulting TFTs of the memory array 200. FIG. 17A is a three-dimensional view. Figs. 13 to 16 and 17B are shown along the reference cross section C-C' of Fig. 1A.In FIG. 13, a hard mask 80 and a photoresist 82 are deposited over the multilayer stack 58. The hard mask layer 80 may include, for example, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist 82 may be formed by, for example, spin coating.In FIG. 14, the photoresist 82 is patterned to form trenches 86. The photoresist 82 may be patterned using suitable photolithography techniques. For example, the photoresist 82 may be exposed for patterning. After exposure, the photoresist 82 may be developed to remove exposed or unexposed portions of the photoresist 82 depending on whether a negative or a positive resist is used, thereby defining a pattern of the trenches 86 formed.In FIG. 15, the pattern of photoresist 82 is transferred to a hard mask 84 using a suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch may be anisotropic. This creates trenches 86 that extend through the hard mask 84. The photoresist 82 may then be removed using a suitable stripping process, for example.In FIG. 16, a pattern of the hard mask 84 is transferred to the multilayer stack 58 using one or more suitable etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching processes may be anisotropic. This creates trenches 86 that extend through the multilayer stack 58, and the conductive layers 54 form the conductive lines 72 (e.g., word lines). By etching the trenches 86 through the conductive layers 54, adjacent conductive lines 72 may be separated from each other. Subsequently, in FIGS. 17A and 17B, the hard mask 84 may be removed with a suitable process, such as a wet etching process, a dry etching process, a planarization process, combinations thereof, or the like. Due to the staircase shape of the multilayer stack 58 (see, e.g., FIGS. 12A and 12B ), the conductive lines 72 may have different lengths that increase in a direction toward the substrate 50. For example, conductive lines 72A may be longer than conductive lines 72B; conductive lines 72B may be longer than conductive lines 72C; and conductive lines 72C may be longer than conductive lines 72D.FIGS. 18A to 23C show the formation and structuring of channel regions for the TFTs 204 (see FIG. 1A ) in the trenches 86. FIGS. 18A, 19A and 23A show three-dimensional representations. In FIGS. 18B, 19B, 20, 21, 22A, 22B and 23B, sectional views taken along the line C - C' of FIG. 1A are shown. Fig. 23C shows a corresponding top view of the TFT structure.In FIGS. 18A and 18B, a memory layer 90 is conformally deposited in the trenches 86. The storage layer 90 may include a material capable of storing a bit, such as a material capable of switching between two different polarization directions by applying a corresponding voltage difference across the storage layer 90. For example, the polarization of the storage layer 90 may change due to an electric field generated by application of the voltage difference.The storage layer 90 may be, for example, a high-k dielectric material, such as a hafnium (Hf)-based dielectric material, or the like. In some embodiments, the memory layer 90 includes a ferroelectric material (such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like), silicon oxynitride, silicon nitride, or the like. In other embodiments, the memory layer 90 may be a multilayer structure including a layer of SiN x between two SiO x- layers (i.e., an ONO structure) or a layer of SiO x between two SiN x- layers (i.e., a NON structure). In still further embodiments, the memory layer 90 may comprise another ferroelectric material or another type of memory material. The memory layer 90 may be deposited by CVD, PVD, ALD, PECVD, or the like to extend along sidewalls and a bottom of the trenches 86. After the memory layer 90 is deposited, an anneal process (e.g., at a temperature of about 300° C. to about 600° C.) may be performed to achieve a desired crystalline phase, improve layer quality, and reduce layer-related defects / contaminants for the memory layer 90. In some embodiments, the anneal process may also be performed at below 400° C. to meet a BEOL thermal budget and reduce defects that may arise in other structural elements from high temperature anneal processes.In FIGS. 19A and 19B, the OS layer 92 in the trenches 86 is conformally deposited over the memory layer 90. The OS layer 92 includes a material suitable for providing a channel region for a TFT (e.g., the TFTs 204 of FIG. 1A ). In some embodiments, the OS layer 92 includes an indium-containing material, such as In x Ga y Zn z MO, where M may be Ti, Al, Ag, Si, Sn, or the like. X, y and z may each be a value of 0 to 1. In other embodiments, another oxide semiconductor material such as IWO, zinc oxide, or the like may be used for the OS layer 92. In still other embodiments, the OS layer 92 may be replaced with a polysilicon or other semiconductor material. The OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, or the like. The OS layer 92 may extend along the sidewalls and the bottom of the trenches 86 over the storage layer 90. After the OS layer 92 is deposited, an anneal process (e.g., at a temperature of from about 300° C. to about 450° C., or from about 300° C. to about 400° C.) may be performed in an oxygen-based environment to activate charge carriers of the OS layer 92.In FIG. 20, a dielectric material 98A is deposited on the sidewalls and bottom of the trenches 86 and over the OS layer 92. The dielectric material 98A may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, PVD, ALD, PECVD, or the like.In FIG. 21, bottom portions of dielectric material 98A in trenches 86 are removed with a combination of photolithography and etching, for example. The etch may be performed with a suitable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch may be anisotropic.As also shown in FIG. 21, the dielectric material 98A may then be used as an etch mask for etching through a bottom portion of the OS layer 92 in the trenches 86. The etch may be performed with a suitable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch may be anisotropic. By etching the OS layer 92, portions of the memory layer 90 on the bottom of the trenches 86 may be exposed. This may separate portions of the OS layer 92 on the opposing sidewalls of the trenches 86 from each other, thereby improving isolation between the memory cells 202 of the memory array 200 (see FIG. 1A ).In FIGS. 22A and 22B, another dielectric material 98B is deposited to fill the trenches 86. The dielectric material 98B may have the same material composition as the dielectric material 98A and may be manufactured by the same method as this. The dielectric material 98B and the dielectric material 98A may be collectively referred to herein as the dielectric material 98.In FIGS. 23A through 23C, a removal process is then performed on the dielectric material 98, the OS layer 92, and the storage layer 90 to remove excess material over the multilayer stack 58. In some embodiments, a planarization process, such as a CMP process, an etch back process, a combination thereof, or the like, may be used. The planarization process exposes the multilayer stack 58 such that after the planarization process is completed, the top surface of the multilayer stack 58 is planar. Figure 23C shows a corresponding top down view of the structure of Figure 23A.Figures 24A-27C illustrate intermediate stages in the fabrication of the conductive lines 106 and 108 (e.g., source lines and bit lines) in the memory array 200. The conductive lines 106 and 108 may extend along a direction perpendicular to the conductive lines 72 such that individual cells of the memory array 200 may be selected for read and write operations. In Figs. 24A to 27C, figures ending with an "A" show a 3D representation; figures ending with a "B" show a top-down view; and figures ending with a "C" show a corresponding sectional view that is parallel to the line C - C' of Fig. 1A.In FIGS. 24A, 24B, and 24C, trenches 100 are patterned by the OS layer 92 and the dielectric material 98. FIG. 24C is a sectional view taken along a line C - C' of FIG. 24B. The patterning of the trenches 100 may be performed, for example, with a combination of photolithography and etching. The trenches 100 may be disposed between opposing sidewalls of the memory layer 90, and may physically separate adjacent stacks of memory cells in the memory array 200 (see FIG. 1A ). The trenches 100 may be patterned such that trenches 100 in adjacent columns are offset from each other. By arranging the trenches 100 offset, the isolation in the resulting memory array 200 may be improved.In FIGS. 25A, 25B, and 25C, a dielectric material 102 is deposited in the trenches 100 to fill them. FIG. 25C is a sectional view taken along a line C - C' of FIG. 25B. The dielectric material 102 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric material 102 may extend along the sidewalls and the bottom of the trenches 86 over the OS layer 92. After deposition, a planarization process (e.g., a CMP, etch back, or the like) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, tops of the multilayer stack 58, the memory layer 90, the OS layer 92, and the dielectric material 102 may be substantially level (e.g., within process variations). In some embodiments, the dielectric materials 98 and 102 may be selected to be selectively etched with respect to each other. For example, in some embodiments, the dielectric material 98 is an oxide and the dielectric material 102 is a nitride. In some embodiments, the dielectric material 98 is a nitride and the dielectric material 102 is an oxide. Other materials are also possible.In FIGS. 26A, 26B, and 26C, trenches 104 for the conductive lines 106 and 108 are patterned. FIG. 26C is a sectional view taken along a line C - C' of FIG. 26B. The trenches 104 are patterned by patterning the dielectric material 98 (including the dielectric material 98A and the dielectric material 98B), for example, with a combination of photolithography and etching.For example, a photoresist 120 may be deposited over the multilayer stack 58, the dielectric material 98, the dielectric material 102, the OS layer 92, and the memory layer 90. The photoresist 120 may be formed by, for example, spin coating. The photoresist 120 is patterned to define openings 122. The openings 122 may each cover a corresponding portion of the dielectric material 102 and also partially expose two separate portions of the dielectric material 98. For example, each opening 122 may expose a portion of the dielectric material 102, partially expose a first portion of the dielectric material 98, and partially expose a second portion of the dielectric material 98 separated from the first portion of the dielectric material 98 by the portion of the dielectric material 102. In this way, each of the openings 122 may define a structure of a conductive line 106 and an adjacent conductive line 108 separated by the dielectric material 102. The photoresists can be patterned using suitable photolithography techniques. For example, the photoresist 120 may be exposed for patterning. After exposure, the photoresist 120 may be developed to remove exposed or unexposed portions of the photoresist 120 depending on whether a negative or a positive resist is used, thereby defining a pattern of the openings 122 formed.Subsequently, portions of the dielectric material 98 that have been exposed from the openings 122 may be removed, for example, by etching. The etch may be performed by a suitable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch may be anisotropic. An etchant may be used for the etching process that etches the dielectric material 98 without significantly etching the dielectric material 102. As a result, the dielectric material 102 cannot be substantially removed even when exposed by the openings 122. A structure of the trenches 104 may correspond to the conductive lines 106 and 108 (see FIGS. 27A to 27C ). For example, a portion of the dielectric material 98 may remain between each pair of the trenches 104, and the dielectric material 102 may be between adjacent pairs of the trenches 104. After the trenches 104 have been patterned, the photoresist 120 may be removed by, for example, stripping.In FIGS. 27A, 27B, and 27C, the trenches 104 are filled with a conductive material to form the conductive lines 106 and 108. FIG. 27C is a sectional view taken along a line C - C' of FIG. 27B. The conductive lines 106 and 108 may each include a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and may each be formed by, for example, CVD, ALD, PVD, PECVD, or the like. After the conductive lines 106 and 108 are deposited, planarization (e.g., CMP, etch back, or the like) may be performed to remove excess portions of the conductive material to form the conductive lines 106 and 108. In the resulting structure, the tops of the multilayer stack 58, the memory layer 90, the OS layer 92, the conductive lines 106, and the conductive lines 108 are substantially level (e.g., within process variations). The conductive lines 106 may correspond to bit lines in the memory array 200, and the conductive lines 108 may correspond to source lines in the memory array 200. Although FIG. 27C is a sectional view showing only the conductive lines 106, a sectional view with the conductive lines 108 may be similar.In this way, stacked TFTs 204 may be fabricated in the memory array 200. Each TFT 204 includes a gate electrode (e.g., a portion of a corresponding conductive line 72), a gate dielectric (e.g., a portion of a corresponding memory layer 90), a channel region (e.g., a portion of a corresponding OS layer 92), and source and drain electrodes (e.g., portions of corresponding lines 106 and 108). The dielectric material 102 isolates adjacent TFTs 204 in the same column and in the same vertical plane. The TFTs 204 may be arranged in a matrix of rows and columns stacked vertically one on top of the other. The conductive lines 72 extend horizontally (e.g., parallel to a major surface of the underlying substrate 50) and intersect the conductive lines 106 and 108 that extend vertically (e.g., perpendicular to the major surface of the underlying substrate 50).In Figs. 28A to 28D, contacts 110 are made with the conductive lines 72, the conductive lines 106, and the conductive lines 108. Figure 28A is a perspective view of the memory array 200, Figure 28B is a top-down view of the memory array 200, Figure 28C is a sectional view of the device and the underlying substrate 50 taken along line 28C'-28C' of Figure 28A, and Figure 28D is a sectional view of the device taken along line B-B' of Figure 1A. In some embodiments, the staircase shape of the conductive lines 72 may provide a surface on which each of the conductive lines 72 for the conductive contacts 110 may seat. Contacts 110 may be formed, for example, by patterning openings in IMD 70 and dielectric layers 52 to expose portions of conductive layers 54 with a combination of photolithography and etching. In the openings, a film (not shown) such as a diffusion barrier film, an adhesive film or the like and a conductive material are deposited. The coating may include titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the IMD 70. The remaining plating and conductive material form the contacts 110 in the openings.As also shown in the perspective view of FIG. 28A, conductive contacts 112 and 114 may also be made with conductive lines 106 and conductive lines 108, respectively. The conductive contacts 110, 112, and 114 may be electrically connected to conductive lines 116A, 116B, and 116C, respectively, that connect the memory array 200 to a lower or higher level circuit (e.g., a control circuit) and / or to signal, current, and ground lines in the semiconductor die. For example, conductive vias 118 may extend through IMD 70 to electrically connect conductive lines 116C to the underlying circuit of interconnect structure 220 and the active devices on substrate 50, as shown in FIG. 28C. Other conductive vias may be formed through the IMD 70 to electrically connect the conductive lines 116A and 116B to the underlying circuit of the interconnect structure 220. In alternative embodiments, routing and / or power lines to and from the memory array 200 may be provided by an interconnect fabric that is fabricated over the memory array 200 in addition to or in place of the interconnect fabric 220. This enables the memory array 200 to be completed.Although the embodiments of FIGS. 2-28B show a particular structure for the conductive lines 106 and 108, other configurations are possible. For example, in some embodiments, routing lines for the word lines and / or the bit and source lines may be arranged below rather than above the memory array 200.For example, FIG. 29 shows a perspective view of a memory array 250 in which routing lines for the conductive lines 72 (e.g., word lines) are arranged below memory cells of the memory array 250. The memory array 250 may be similar to the memory array 200, wherein like reference numerals designate like elements manufactured with similar processes. As shown, conductive lines 72 are connected to lower conductive lines 116C through contacts 110A, conductive lines 116D, and contacts 110B. Specifically, the conductive lines 72 are electrically connected to higher level conductive lines 116D through the contacts 110A. The conductive lines 116D allow routing and are connected to the lower conductive lines 116C by contacts 110B.As another example, FIG. 30 shows a perspective view of a memory array 300 in which routing lines for the conductive lines 106 and 108 (e.g., bit lines and source lines) are disposed below memory cells of the memory array 300. The memory array 300 may be similar to the memory array 200, wherein like reference numerals designate like elements manufactured with similar processes. As shown, conductive lines 106 and 108 are electrically connected to the lower conductive lines 116A and 116B. In the memory array 300, the routing lines for the conductive lines 72 may be disposed over the memory cells (e.g., as shown in FIGS. 28A-28D ) or under the memory cells (e.g., as shown in FIG. 29).In various embodiments, a 3D memory array is provided having a plurality of vertically stacked memory cells. Each memory cell includes a TFT having a word line region functioning as a gate electrode, a bit line region functioning as a first source / drain electrode, and a source line region functioning as a second source / drain electrode. Each TFT further includes an insulating memory layer (e.g., as a gate dielectric) and an OS channel region. In some embodiments, the word lines may extend in a horizontal direction (e.g., parallel to a main surface of a semiconductor substrate), while the source lines and the bit lines may extend in a vertical direction (e.g., perpendicular to the main surface of the semiconductor substrate). The 3D memory array architecture may provide the following advantages, among other things: reduced memory cell size, higher density, reduced memory array footprint (e.g., lower stack height), and ease of manufacture.In some embodiments, a device includes: a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, the second word line providing a second gate electrode for a second transistor over the first transistor. The device further includes: a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a storage layer between the first word line and the source line; and a first semiconductor material between the storage layer and the source line. Optionally, in some embodiments, the source line provides a first source / drain region for the first transistor and a second source / drain region for the second transistor, and the bit line provides a third source / drain region for the first transistor and a fourth source / drain region for the second transistor. Optionally, in some embodiments, the apparatus further comprises: a second source line intersecting the first word line and the second word line, the second source line providing a fifth source / drain region for a third transistor; and a second bit line intersecting the first word line and the second word line, the second bit line providing a sixth source / drain region for the third transistor and the first word line providing a third gate electrode for the third transistor. Optionally, in some embodiments, the device further comprises a second semiconductor material between the first word line and the second source line, wherein the second semiconductor material is insulated from the first semiconductor material by a third dielectric material. Optionally, in some embodiments, the memory layer is further disposed between the first word line and the second semiconductor material, wherein the memory layer extends continuously from the first semiconductor material to the second semiconductor material. Optionally, in some embodiments, the memory layer is a ferroelectric material. Optionally, in some embodiments, the first word line is longer than the second word line.In some embodiments, a device includes: a semiconductor substrate; and a first memory cell over the semiconductor substrate, the first memory cell including a first thin film transistor, the first thin film transistor including: a gate electrode including a portion of a first word line, the first word line extending in a direction parallel to a top surface of the semiconductor substrate, a first portion of a ferroelectric material, the first portion of the ferroelectric material disposed on a sidewall of the first word line, and a first channel region on a sidewall of the ferroelectric material. The apparatus further comprises: a source line, a first portion of the source line providing a first source / drain electrode for the first thin film transistor, the source line extending in a direction perpendicular to the top surface of the semiconductor substrate; a bit line, a first portion of the bit line providing a second source / drain electrode for the first thin film transistor, the bit line extending in a direction perpendicular to the top surface of the semiconductor substrate; and a second memory cell over the first memory cell. Optionally, in some embodiments, the second memory cell includes a second thin film transistor, wherein a second portion of the source line provides a first source / drain electrode for the second thin film transistor and a second portion of the bit line provides a second source / drain electrode for the second thin film transistor. Optionally, in some embodiments, the device further comprises a second word line over the first word line, wherein a gate electrode of the second thin film transistor comprises a portion of the second word line and the first word line is longer than the second word line. Optionally, in some embodiments, the first word line is electrically connected to a second word line disposed over the second memory cell. Optionally, in some embodiments, the first word line is electrically connected to a second word line disposed below the first memory cell. Optionally, in some embodiments, the source line is electrically connected to a second source line disposed over the second memory cell. Optionally, in some embodiments, the source line is electrically connected to a second source line disposed below the first memory cell.In some embodiments, a method includes the steps of: forming a first conductive line and a second conductive line over a semiconductor substrate, the second conductive line being disposed over the first conductive line and being insulated from the first conductive line and the second conductive line being shorter than the first conductive line; patterning a first trench to extend through the first conductive line and the second conductive line; depositing a memory layer along sidewalls and a bottom surface of the first trench; depositing an oxide semiconductor (OS) layer over the memory layer, the OS layer extending along the sidewalls and the bottom surface of the first trench; depositing a first dielectric material over and in contact with the OS layer; patterning a second trench and a third trench to extend through the first dielectric material; and forming a third conductive line in the second trench and forming a fourth conductive line in the third trench. Optionally, in some embodiments, the method further comprises: prior to patterning the second and third trenches, patterning a fourth trench through the first dielectric material; and filling the fourth trench with a second dielectric material, wherein the patterning the second and third trenches comprises an etching process that selectively etches the first dielectric material with respect to the second dielectric material. Optionally, in some embodiments, the method further comprises forming a wordline over and in electrical communication with the first conductive line. Optionally, in some embodiments, the first conductive line is electrically connected to a wordline below the first conductive line. Optionally, in some embodiments, the method further comprises: forming a source line over and in electrical communication with the third conductive line; and forming a bit line over and in electrical communication with the fourth conductive line. Optionally, in some embodiments, the third conductive line is electrically connected to a source line below the first conductive line, and the fourth conductive line is electrically connected to a bit line below the first conductive line.

Claims

A device comprising: a semiconductor substrate (50); a first word line (72) over the semiconductor substrate (50), the first word line (72) providing a first gate electrode (204) for a first transistor; a second word line (72) over the first word line (72), the second word line (72) being isolated from the first word line (72) by a first dielectric material (52) and providing a second gate electrode (204) for a second transistor over the first transistor; a source line (108) intersecting the first word line (72) and the second word line (72); a bit line (106) intersecting the first word line (72) and the second word line (72), the bit line (106) being isolated from the source line (108) by a second dielectric material (98); a memory layer (90) between the first word line (72) and the source line (108), the memory layer (90) further being disposed between the first word line (72) and the bit line (106); a first semiconductor material between the memory layer (90) and the source line (108), the first semiconductor material further being disposed between the first word line (72) and the second source line (108); and the first word line (72) being electrically connected to a third word line disposed below the first transistor.The device of claim 1, wherein the source line (108) provides a first source / drain region for the first transistor and a second source / drain region for the second transistor, and the bit line (106) provides a third source / drain region for the first transistor and a fourth source / drain region for the second transistor.The device of claim 1 or 2, further comprising: a second source line (108) intersecting the first word line (72) and the second word line (72), the second source line (108) providing a fifth source / drain region for a third transistor; and a second bit line (106) intersecting the first word line (72) and the second word line (72), the second bit line (106) providing a sixth source / drain region for the third transistor and the first word line (72) providing a third gate electrode (204) for the third transistor.The device of claim 3, further comprising a second semiconductor material between the first word line (72) and the second source line (108), the second semiconductor material being insulated from the first semiconductor material by a third dielectric material.The device of claim 4, wherein the memory layer (90) is further disposed between the first word line (72) and the second semiconductor material and continuously extends from the first semiconductor material to the second semiconductor material.The device of any preceding claim, wherein the memory layer (90) is a ferroelectric material.The device of any preceding claim, wherein the first word line (72) is longer than the second word line (72).An apparatus comprising: a semiconductor substrate (50); a first memory cell (202) over the semiconductor substrate (50), the first memory cell (202) comprising a first thin film transistor, the first thin film transistor comprising: a gate electrode having a portion of a first word line (72), the first word line (72) extending in a direction parallel to a top surface of the semiconductor substrate (50), a first portion of a ferroelectric material, the first portion of the ferroelectric material being disposed on a sidewall of the first word line (72), and a first channel region on a sidewall of the ferroelectric material; a source line (108), wherein a first portion of the source line (108) provides a first source / drain electrode for the first thin film transistor and the source line (108) extends in a direction perpendicular to the top surface of the semiconductor substrate (50); a bit line (106), wherein a first portion of the bit line (106) provides a second source / drain electrode for the first thin film transistor and the bit line (106) extends in a direction perpendicular to the top surface of the semiconductor substrate (50); a second memory cell (202) over the first memory cell (202); and wherein the first word line (72) is electrically connected to a second word line disposed under the first memory cell (202).The apparatus of claim 8, wherein the second memory cell (202) comprises a second thin film transistor, a second portion of the source line (108) providing a first source / drain electrode for the second thin film transistor and a second portion of the bit line (106) providing a second source / drain electrode for the second thin film transistor.The device of claim 8 or 9, further comprising a third word line (72) over the first word line (72), wherein a gate electrode (204) of the second thin film transistor comprises a portion of the third word line (72), and the first word line (72) is longer than the third word line (72).The device according to claim 8, wherein the channel region is formed by an oxide semiconductor layer (92).The device of claim 11, wherein the oxide semiconductor layer (92) comprises an indium-containing material.The apparatus of any of claims 8 to 12, wherein the source line (108) is electrically connected to a second source line disposed over the second memory cell (202).The apparatus of any of claims 8 to 12, wherein the source line (108) is electrically connected to a second source line disposed below the first memory cell (202).A method comprising: forming a first conductive line and a second conductive line over a semiconductor substrate (50), the second conductive line being disposed over the first conductive line and being insulated from the first conductive line and the second conductive line being shorter than the first conductive line, the first conductive line being electrically connected to a word line below the first conductive line; patterning a first trench (86) to extend through the first conductive line and the second conductive line; depositing a memory layer (90) along sidewalls and a bottom surface of the first trench (86); depositing an oxide semiconductor, OS, layer (92) over the memory layer (90), the OS layer (92) extending along the sidewalls and the bottom surface of the first trench (86); depositing a first dielectric material (98A) over and in contact with the OS layer (92); patterning a second trench (104) and a third trench (104) to extend through the first dielectric material (98A); and forming a third conductive line (106) in the second trench (104) and forming a fourth conductive line (106) in the third trench (104).The method of claim 15, further comprising: prior to patterning the second and third trenches (104), patterning a fourth trench (100) through the first dielectric material (98A); and filling the fourth trench (100) with a second dielectric material (102), wherein patterning the second and third trenches (104) comprises an etching process that selectively etches the first dielectric material with respect to the second dielectric material.The method of claim 15 or 16, wherein the storage layer is a ferroelectric material.The method of any of claims 15 to 17, wherein the oxide semiconductor layer (92) comprises an indium-containing material.The method of any of claims 15 to 18, further comprising: forming a source line over and in electrical communication with the third conductive line; and forming a bit line over and in electrical communication with the fourth conductive line.The method of any one of claims 15 to 19, wherein the third conductive line is electrically connected to a source line under the first conductive line, and the fourth conductive line is electrically connected to a bit line under the first conductive line.

Images