INTEGRATED CIRCUIT AND METHOD FOR MAKING AN INTEGRATED CIRCUIT

Abstract

Featuring an integrated circuit: a set of busbars (404, 504, 604) on a rear side of a substrate extending in a first direction, each busbar being separated from an adjacent busbar in a second direction different from the first direction; comprising a first flip-flop (102, 202) comprising a first set of conductive structures (520) extending in the first direction and arranged on a first metal layer; a second flip-flop (104, 204) adjacent to the first flip-flop (102, 202) at a first boundary (501a), wherein the second flip-flop (104, 204) has a second set of conductive structures (530) extending in the first direction and arranged on the first metal layer, wherein the second set of conductive structures is separate in the second direction from the first set of conductive structures; and a third flip-flop (106, 206) adjacent to the second flip-flop (104, 204) at a second boundary (501b), wherein the third flip-flop (106, 206) has a third set of conductive structures (532) extending in the first direction, arranged on the first metal layer and separated in the second direction from the first set of conductive structures and the second set of conductive structures, wherein the first flip-flop (102, 202), the second flip-flop (104, 204) and the third flip-flop (106, 206) are located on a front side of the substrate that is opposite the back side, where the second set of conductive structures is offset in the second direction from the first boundary and the second boundary.

Description

BACKGROUND

[0001] The recent trend of miniaturizing integrated circuits (ICs) has resulted in ever smaller components that consume less power yet offer more functionality at higher speeds.

[0002] However, the miniaturization process also resulted in stricter design and manufacturing specifications, as well as reliability challenges. Various EDA (Electronic Design Automation) tools generate, optimize, and verify standard cell layout designs for integrated circuits, ensuring compliance with the design and manufacturing specifications for these layouts.

[0003] The invention is defined in the claims.

[0004] US 2017 / 0077910A1 discloses an integrated semiconductor circuit comprising a scan-enable inverter (SE inverter) and a clock inverter (CK inverter) on a substrate, a first multiplexed section, and a second multiplexed section. The SE inverter and the CK inverter are aligned in a first direction relative to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced as appropriate for the sake of clarity. Fig. Figure 1 is a schematic diagram of an MBFF (multi-bit flip-flop) according to some embodiments. Fig. Figure 2 is a circuit diagram of a circuit according to some embodiments. Fig. 3A is a circuit diagram of an integrated circuit according to some embodiments. Fig. 3B is a circuit diagram of an integrated circuit according to some embodiments. Fig. Figures 4A-4E are diagrams of a layout design of an integrated circuit according to some embodiments. Fig. Figures 5A-5E are diagrams of an integrated circuit according to some embodiments. Fig. Figure 6A is a diagram of a layout design of an integrated circuit according to some embodiments. Fig. Figure 6B is a schematic view of a diagram of an integrated circuit according to some embodiments. Fig. Figure 6C is a top view of an integrated circuit according to some embodiments. Fig. Figure 7A is a diagram of a layout design of an integrated circuit according to some embodiments. Fig. Figure 7B is a top view of an integrated circuit according to some embodiments. Fig. Figure 8 is a flowchart of a process for forming or manufacturing an integrated circuit according to some embodiments. Fig. Figure 9 is a flowchart of a method for generating a layout design of an integrated circuit according to some embodiments. Fig. Figure 10 is a functional flowchart of a method for manufacturing an IC device according to some embodiments. Fig. Figure 11 is a schematic view of a system for designing an IC layout and for manufacturing an IC circuit according to some embodiments. Fig. Figure 12 is a block diagram of an IC manufacturing system and an associated IC manufacturing flow according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0006] In some embodiments, an integrated circuit comprises a set of bus bars extending in a first direction. In some embodiments, the IC further comprises a first flip-flop having a first set of conductive structures extending in the first direction. In some embodiments, the IC further comprises a second flip-flop adjacent to the first flip-flop at a first boundary. In some embodiments, the second flip-flop comprises a second set of conductive structures extending in the first direction. In some embodiments, the IC further comprises a third flip-flop adjacent to the second flip-flop at a second boundary. In some embodiments, the third flip-flop comprises a third set of conductive structures extending in the first direction.

[0007] In some embodiments, the set of busbars is located on the back side of a substrate. In some embodiments, the first, second, and third flip-flops are located on the front side of the substrate, opposite the back side.

[0008] In some embodiments, the second set of conductive structures is offset in the second direction from both the first and second boundaries. In some embodiments, arranging the second set of conductive structures so that they are offset from the second boundary causes them to be displaced in the second direction from both the second boundary and the third set of conductive structures, thereby increasing the distance between them. In some embodiments, this increased distance results in a lower coupling capacity between the second and third sets of conductive structures compared to other approaches.In some embodiments, reducing the coupling capacitance between the second set of conductive structures and the third set of conductive structures results in the integrated circuit consuming less energy than with other approaches.

[0009] Fig. Figure 1 is a schematic diagram of an MBFF (Multi-Bit Flip-Flop) 100 according to some embodiments.

[0010] The MBFF 100 comprises a flip-flop 102, a flip-flop 104, a flip-flop 106, an inverter 120, an inverter 122, and a clock input pin 130. The MBFF 100 is a three-bit flip-flop. In other words, the MBFF comprises three flip-flops (for example, flip-flops 102, 104, and 106). Other numbers of bits or corresponding flip-flops in the MBFF 100 are within the scope of this disclosure. In some embodiments, the MBFF 100 is part of an integrated circuit (not shown) that includes other MBFFs similar to the MBFF 100 or one or more other flip-flops.

[0011] The MBFF 100 is configured to receive input signals D1, D2, and D3 and to receive the clock signal CP at clock input pin 130. The MBFF 100 is configured to generate output signals Q1, Q2, and Q3.

[0012] Flip-flops 102, 104, and 106 are configured to receive input signals D1, D2, and D3, respectively, at their respective input terminals (not labeled). Flip-flops 102, 104, and 106 are configured to generate output signals Q1, Q2, and Q3, respectively, and to output these signals at their respective output terminals (not labeled).

[0013] Each of the flip-flops 102, 104, and 106 is further configured (not shown) to receive the clock signal CP and the clock signal CPB. Each of the flip-flops 102, 104, and 106 is coupled to the inverters 120 and 122. In some embodiments, each of the flip-flops 102, 104, and 106 is configured (not shown) to share the input pin 130. Each of the flip-flops 102, 104, and 106 is further configured to receive the clock signal CP from the input pin 130 and is configured to receive the clock signal CPB from the inverter 120. In some embodiments, each of the flip-flops 102, 104, and 106 is configured to receive the clock signal CPBB from the inverter 122. In some embodiments, the clock signal CPBB is a buffered version of the clock signal CP. In some embodiments, the clock signal CPBB is inverted from the clock signal CP.

[0014] In some embodiments, one or more of the flip-flops 102, 104, and 106 are edge-triggered flip-flops. In some embodiments, one or more of the flip-flops 102, 104, and 106 are a DQ flip-flop, an SR flip-flop, a T flip-flop, a JK flip-flop, or the like. Other types of flip-flops or configurations, at least for flip-flops 102, 104, 106, or 108, are within the scope of this disclosure.

[0015] One input terminal of inverter 120 is connected to the clock input pin 130 and configured to receive the clock signal CP. One output terminal of inverter 120 is connected to an input terminal of inverter 122 and configured to output the clock signal CPB.

[0016] An input terminal of inverter 122 is configured to receive the clock signal CPB. An output terminal of inverter 120 is configured to output the clock signal CPBB. Other configurations, at least for inverter 120 or 122, are within the scope of this disclosure.

[0017] Flip-flop 102, flip-flop 104, and flip-flop 106 (collectively referred to as a set of flip-flops 110) are each configured to have the same drive current capability. In some embodiments, the drive current capability is equal to the drive current conducted by at least flip-flop 102, flip-flop 104, or flip-flop 106. In some embodiments, at least flip-flop 102, flip-flop 104, or flip-flop 106 is configured to have a drive current capability that differs from the drive current capability of at least flip-flop 102, flip-flop 104, or flip-flop 106. For example, in some embodiments, MBFF 100 is configured as a mixed-drive multi-bit flip-flop. In some embodiments, MBFF 100 comprises flip-flops configured with at least two different drive current capabilities.In some embodiments, each of the flip-flops included in the MBFF 100 is configured to have a different driver current capability. Other numbers of different driver current capabilities for the MBFF 100 are within the scope of this disclosure. In some embodiments, for example, the MBFF 100 comprises three different flip-flops, each of the three different flip-flops being configured with a driver current capability different from the others.

[0018] In some embodiments, the driver current capability of at least flip-flop 102, flip-flop 104, or flip-flop 106 is based on the number of fins in one or more transistors within flip-flop 102, flip-flop 104, or flip-flop 106. In some embodiments, the number of fins and the driver current capability are directly related. For example, in some embodiments, increasing the number of fins in one or more transistors within flip-flop 102, flip-flop 104, or flip-flop 106 also increases the respective driver current capability, and vice versa.

[0019] In some embodiments, configuring the MBFF 100 as a multi-bit flip-flop reduces the number of dual inverters in its clock path. This results in fewer input pins for the MBFF 100's associated clock signal, which in turn leads to lower overall dynamic clock power consumption and a smaller footprint compared to other approaches. Furthermore, configuring the MBFF 100 as a multi-bit flip-flop optimizes the power consumption of each flip-flop within the MBFF 100 compared to other approaches.

[0020] Fig. Figure 2 is a circuit diagram of a circuit 200 according to some embodiments.

[0021] Circuit 200 is an embodiment of the MBFF 100 from Fig. 1 and thus a similarly detailed description is unnecessary. In some embodiments, circuit 200 is an MBFF circuit. In some embodiments, circuit 200 is part of an integrated circuit with components other than those described in Fig. 2 shown.

[0022] Components that are in Fig. Components 2-12 that are identical or similar are designated with the same reference symbols, so that a detailed description of these components is unnecessary.

[0023] The circuit 200 includes a flip-flop 202, a flip-flop 204, a flip-flop 206, a clock input pin 230 and a sample enable pin 232.

[0024] Flip-flops 202, 204 and 206 are embodiments of flip-flops 102, 104 and 106 of Fig. 1 and a similar detailed description are omitted. The clock input pin 230 is an embodiment of the clock input pin 130 of Fig. 1 and a similar detailed description are omitted.

[0025] Circuit 200 is a three-bit flip-flop, and each bit is assigned to a specific flip-flop (for example, flip-flops 202, 204, and 206). In other words, circuit 200 comprises three flip-flops (for example, flip-flops 202, 204, and 206). Other numbers of bits or other numbers of flip-flops in circuit 200 are within the scope of this disclosure. In some embodiments, circuit 200 is part of an integrated circuit (not shown) that includes other MBFFs similar to MBFF 100 or one or more other flip-flops.

[0026] Each of the flip-flops 202, 204, and 206 is a DQ flip-flop. In some embodiments, one or more of the flip-flops 202, 204, or 206 are an SR flip-flop, a T flip-flop, a JK flip-flop, or the like. Other types of flip-flops or configurations, at least for flip-flop 202, 204, or 206, are within the scope of this disclosure.

[0027] Each of the flip-flops 202, 204, and 206 has a respective clock input pin CK, which is configured to receive the clock signal CP. In some embodiments, each of the flip-flops 202, 204, and 206 is configured to share the clock input pin 230. In some embodiments, the clock input pins of the flip-flops 202, 204, and 206 are coupled together and configured to receive the clock signal CP from the clock input pin 230.

[0028] Each of the flip-flops 202, 204, and 206 has a respective scan enable pin SE configured to receive scan enable signals SE1, SE2, and SE3. In some embodiments, each of the flip-flops 202, 204, and 206 is configured to share the scan enable pin 232. In some embodiments, the scan enable pins of flip-flops 202, 204, and 206 are coupled together and configured to receive the scan enable signal SE_SE from scan enable pin 232. In these embodiments, the scan enable signal SE_SE is equal to each of the scan enable signals SE1, SE2, and SE3.

[0029] Each of the flip-flops 202, 204, and 206 has a corresponding data terminal D, configured to receive the respective data signal D1, D2, and D3. Each of the flip-flops 202, 204, and 206 includes a corresponding scan terminal SI, configured to receive the associated scan signal SI1, SI2, and SI3. Each of the flip-flops 202, 204, and 206 has a corresponding output terminal Q, configured to output the corresponding output signal Q1, Q2, and Q3.

[0030] In some embodiments, each of the flip-flops 202, 204 and 206 comprises a respective multiplexer (in Fig. 2 not shown, but in Fig. 3A-3B shown), which is set up to multiplex one or more of the following signals: Scan enable signal SE_SE, Scan in signal SI1, SI2 or SI3, or Data signal D1, D2 or D3.

[0031] Fig. 3A is a circuit diagram of an integrated circuit 300A according to some embodiments.

[0032] The integrated circuit 300A is an embodiment of one or more of the flip-flops 102, 104 or 106 from Fig. 1 or one or more of the flip-flops 202, 204 or 206 from Fig. 2 and therefore a similarly detailed description is unnecessary.

[0033] The integrated circuit 300A is a flip-flop circuit. The integrated circuit 300A is configured to receive at least one data signal D or one scan signal SI and to output a signal Q. In some embodiments, the data signal D is a data input signal. In some embodiments, the scan signal SI is a scan input signal. In some embodiments, the output signal Q is a stored state of at least the data signal D or the scan signal SI. A flip-flop circuit is used for illustration purposes, but other types of circuits are within the scope of this disclosure.

[0034] The integrated circuit 300A includes a multiplexer 302, a latch 304, a latch 306, an output circuit 308, an inverter 310, an inverter 312 and an inverter 314.

[0035] The multiplexer 302 comprises a first input port configured to receive the data signal D, a second input port configured to receive the scan signal SI, and a third input port configured to receive a scan enable signal SE or an inverted scan enable signal SEB. In some embodiments, the scan enable signal SE is a select signal of the multiplexer 302, and an inverted scan enable signal SEB is an inverted select signal of the multiplexer 302. An output port of the multiplexer 302 is coupled at node mx1 to an input port of the latch 304. The multiplexer 302 is configured to output a multiplexed signal S1 at the latch 304. In some embodiments, the multiplexed signal S1 corresponds to the data signal D or the scan signal SI in response to the scan enable signal SE or the inverted scan enable signal SEB.In some embodiments, the third input terminal of the multiplexer 304 is coupled to the inverter 314 to receive at least the sample release signal SE or the inverted sample release signal SEB.

[0036] Latch 304 is coupled to multiplexer 302 and latch 306. The input terminal of latch 304 is configured to receive the multiplexed signal S1 from multiplexer 302. An output terminal of latch 304 is coupled to an input terminal of latch 306 at node mx2. Latch 304 is configured to output a signal Mq_x to latch 306 via its output terminal. In some embodiments, the signal Mq_x is a latched version of signal S1. In some embodiments, latch 304 is coupled to inverter 310 and configured to receive the clock signal CPB. In some embodiments, the buffer 304 is coupled to inverter 312 and configured to receive the clock signal CPBB.

[0037] Latch 306 is coupled to latch 304 and output circuit 308. The input terminal of latch 306 is configured to receive the signal Mq_x from latch 304. An output terminal of latch 306 is coupled at node mx4 to an input terminal of output circuit 308. Latch 306 is configured to output a signal QF to output circuit 308 via its output terminal. In some embodiments, the signal QF is a latched version of signal S1 or Mq_x. In some embodiments, latch 306 is coupled to inverter 310 and configured to receive the clock signal CPB. In some embodiments, latch 306 is coupled to inverter 312 and configured to receive the clock signal CPBB.

[0038] Output circuit 308 is coupled to latch 306. The input terminal of output circuit 308 is configured to receive the signal QF from latch 306. An output terminal of output circuit 308 is configured to output the signal Q. In some embodiments, the signal QF is a latched version of signal S1 or Mq_x.

[0039] The Latch 304 includes a transmission gate TG1, NMOS transistors N2 and N3 and PMOS transistors P2 and P3.

[0040] The transmission gate TG1 is coupled between nodes mx1 and mx2. Transmission gate TG1 is configured to receive the signal S1, the clock signal CPB, and the clock signal CPBB. Transmission gate TG1 is configured to output the signal Mq_x to inverter I1, PMOS transistor P3, and NMOS transistor N3. Transmission gate TG1 comprises an NMOS transistor N1 and a PMOS transistor P1, which are coupled together.

[0041] One gate terminal of the PMOS transistor P1 is configured to receive the clock signal CPBB. One gate terminal of the NMOS transistor N1 is configured to receive the clock signal CPB.

[0042] A source terminal of the PMOS transistor P1, a source terminal of the NMOS transistor N1, node mx1, and the output terminal of the multiplexer 302 are coupled together. In some embodiments, a drain terminal of the PMOS transistor P1 and a drain terminal of the NMOS transistor N1 are coupled to node mx1 and the output terminal of the multiplexer 302.

[0043] The drain terminal of PMOS transistor P1, the drain terminal of NMOS transistor N1, node mx2, a drain terminal of NMOS transistor N3, and a drain terminal of PMOS transistor P3 are coupled together. In some embodiments, the source terminal of PMOS transistor P1 and the source terminal of NMOS transistor N1 are coupled to node mx2, the drain terminal of NMOS transistor N3, and the drain terminal of PMOS transistor P3.

[0044] A gate terminal of the PMOS transistor P2 and a gate terminal of the NMOS transistor N2 are coupled together and are further coupled at least to the node mx3.

[0045] A source terminal of PMOS transistor P2 is connected to the voltage supply VDD. A drain terminal of PMOS transistor P2 is connected to a source terminal of PMOS transistor P3.

[0046] A gate terminal of the PMOS transistor P3 is configured to receive the clock signal CPB. In some embodiments, the gate terminal of the PMOS transistor P3 is coupled to at least one output terminal of the inverter 310. A drain terminal of the PMOS transistor P3 and a drain terminal of the NMOS transistor N3 are each coupled to each other and further coupled to at least node mx2.

[0047] One gate terminal of the NMOS transistor N3 is configured to receive the clock signal CPBB. In some embodiments, the gate terminal of the NMOS transistor N3 is coupled to at least one output terminal of the inverter 312.

[0048] A source terminal of the NMOS transistor N3 is coupled to a drain terminal of the NMOS transistor N2. A source terminal of transistor N2 is coupled to the reference voltage supply VSS.

[0049] The Latch 306 includes an inverter I1, a transfer gate TG2, NMOS transistors N5 and N6 and PMOS transistors P5 and P6.

[0050] An input terminal of inverter I1 is coupled to at least node mx2 and transmission gate TG1 and is configured to receive the signal Mq_x. An output terminal of inverter I1 is coupled to at least node mx3 and is configured to output a signal Mq to the gate of PMOS transistor P2, the gate of NMOS transistor N2, and transmission gate TG2.

[0051] The transmission gate TG2 is coupled between nodes mx3 and mx4. Transmission gate TG2 is configured to receive the signal Mq, the clock signal CPB, and the clock signal CPBB. Transmission gate TG2 is configured to output the signal QF to inverter I2, the PMOS transistor P5, and the NMOS transistor N5. Transmission gate TG2 includes an NMOS transistor N4 and a PMOS transistor P4, which are coupled together.

[0052] One gate terminal of the PMOS transistor P4 is configured to receive the clock signal CPB. One gate terminal of the NMOS transistor N4 is configured to receive the clock signal CPBB.

[0053] A source terminal of the PMOS transistor P4, a source terminal of the NMOS transistor N4, node mx3, the output terminal of inverter I1, the gate terminal of the PMOS transistor P2, and the gate terminal of the NMOS transistor N2 are coupled together. In some embodiments, a drain terminal of the PMOS transistor P4 and a drain terminal of the NMOS transistor N4 are coupled to node mx3, the output terminal of inverter I1, the gate terminal of the PMOS transistor P2, and the gate terminal of the NMOS transistor N2.

[0054] The drain terminal of PMOS transistor P4, the drain terminal of NMOS transistor N4, node mx,4, an input terminal of inverter I2, a drain terminal of NMOS transistor N5, and a drain terminal of PMOS transistor P5 are coupled together. In some embodiments, the source terminal of PMOS transistor P4 and the source terminal of NMOS transistor N4 are coupled to node mx,4, an input terminal of inverter I2, a drain terminal of NMOS transistor N5, and a drain terminal of PMOS transistor P5.

[0055] A gate terminal of the PMOS transistor P6 and a gate terminal of the NMOS transistor N6 are coupled together and are further coupled at least to the node mx5.

[0056] A source terminal of PMOS transistor P6 is connected to the voltage supply VDD. A drain terminal of PMOS transistor P6 is connected to a source terminal of PMOS transistor P5.

[0057] A gate terminal of the PMOS transistor P5 is configured to receive the clock signal CPBB. In some embodiments, the gate terminal of the PMOS transistor P5 is coupled to at least one output terminal of the inverter 312. A drain terminal of the PMOS transistor P5 and a drain terminal of the NMOS transistor N5 are coupled to each other and furthermore connected to at least node mx4.

[0058] One gate terminal of the NMOS transistor N5 is configured to receive the clock signal CPB. In some embodiments, the gate terminal of the NMOS transistor N5 is coupled to at least one output terminal of the inverter 310.

[0059] A source terminal of the NMOS transistor N5 is coupled to a drain terminal of the NMOS transistor N6. A source terminal of transistor N6 is coupled to the reference voltage supply VSS.

[0060] The output circuit 308 includes an inverter I2 coupled to an inverter I3.

[0061] An input terminal of inverter I2 is coupled to at least node mx4 and configured to receive the signal QF. An output terminal of inverter I2 is coupled to at least one input terminal of inverter I3, the gate of PMOS transistor P6, the gate of NMOS transistor N6, or node mx5 and configured to output a signal QF_x.

[0062] One input terminal of inverter I3 is coupled to at least node mx5 and configured to receive the signal QF_x from inverter I2. One output terminal of inverter I3 is configured to output the signal Q.

[0063] An input terminal of inverter 310 is configured to receive the clock signal CP. An output terminal of inverter 310 is configured to output the clock signal CPB to at least one input terminal of inverter 312. In some embodiments, the output terminal of inverter 310 is coupled to at least the gate terminal of PMOS transistor P3, the gate terminal of NMOS transistor N5, the gate terminal of PMOS transistor P4, or the gate terminal of NMOS transistor N1.

[0064] An input terminal of inverter 312 is coupled to at least the output terminal of inverter 310 and configured to receive the clock signal CPB. An output terminal of inverter 312 is configured to output the clock signal CPBB. In some embodiments, the output terminal of inverter 312 is coupled to at least the gate terminal of PMOS transistor P5, the gate terminal of NMOS transistor N3, the gate terminal of PMOS transistor P1, or the gate terminal of NMOS transistor N4 and outputs the clock signal CPBB to these transistors.

[0065] An input port of inverter 314 is configured to receive the scan enable signal SE. In some embodiments, the input port of inverter 314 is coupled to the third input port of multiplexer 302. An output port of inverter 314 is configured to output the inverted scan enable signal SEB. In some embodiments, the output port of inverter 314 is coupled to the third input port of multiplexer 302.

[0066] Fig. 3B is a circuit diagram of an integrated circuit 300B according to some embodiments.

[0067] The integrated circuit 300B is an embodiment of the integrated circuit 300A, and therefore a similarly detailed description is unnecessary. The integrated circuit 300B is an embodiment of one or more of the flip-flops 102, 104, or 106 of Fig. 1 or one or more of the flip-flops 202, 204 or 206 from Fig. 2 and therefore a similarly detailed description is unnecessary.

[0068] The 300B integrated circuit includes the 302 multiplexer and the 304 latch (in Fig. 3B not marked with a reference), the Latch 306 (in Fig. 3B not marked with reference numerals), the output circuit 308, the inverter 310, the inverter 312 and the inverter 314.

[0069] The multiplexer 302 contains NMOS transistors N7, N8, N9 and N10 as well as PMOS transistors P7, P8, P9 and P10.

[0070] One gate terminal of the PMOS transistor P7 is configured to receive the scan signal SI. One gate terminal of the NMOS transistor N7 is configured to receive the scan signal SI. In some embodiments, the gate terminal of the PMOS transistor P7 is coupled to the gate terminal of the NMOS transistor N7. In some embodiments, the gate terminals of the PMOS transistor P7 and the NMOS transistor N7 correspond to the second input terminal of the multiplexer 302 in Fig. 3A. A source terminal of PMOS transistor P7 is connected to the voltage supply VDD. A drain terminal of PMOS transistor P7 is connected to a source terminal of PMOS transistor P8.

[0071] A gate terminal of PMOS transistor P8 is configured to receive the inverted scan enable signal SEB. A drain terminal of PMOS transistor P8, a drain terminal of PMOS transistor P10, a drain terminal of NMOS transistor N8, a drain terminal of NMOS transistor N10, the drain or source terminal of PMOS transistor P1, and the drain or source terminal of NMOS transistor N1 are coupled together.

[0072] A gate terminal of PMOS transistor P9 is configured to receive the scan enable signal SE. A source terminal of PMOS transistor P9 is connected to the voltage supply VDD. A drain terminal of PMOS transistor P9 is connected to a source terminal of PMOS transistor P10.

[0073] One gate terminal of the PMOS transistor P10 is configured to receive the data signal D. One gate terminal of the NMOS transistor N10 is configured to receive the data signal D. In some embodiments, the gate terminal of the PMOS transistor P10 is coupled to the gate terminal of the NMOS transistor N10. In some embodiments, the gate terminals of the PMOS transistor P10 and the NMOS transistor N10 correspond to the first input terminal of the multiplexer 302 in Fig. 3A.

[0074] One source terminal of the NMOS transistor N7 is coupled to the reference voltage supply VSS. One drain terminal of the NMOS transistor N7 is coupled to a source terminal of the NMOS transistor N8.

[0075] One gate terminal of the NMOS transistor N8 is configured to receive the scan enable signal SE. In some embodiments, the gate terminal of the NMOS transistor N8 is coupled to the gate terminal of the PMOS transistor P9.

[0076] A source terminal of the NMOS transistor N9 is coupled to the reference voltage supply VSS. A gate terminal of the NMOS transistor N9 is configured to receive the inverted scan enable signal SEB. In some embodiments, the gate terminal of the NMOS transistor N9 is coupled to the gate terminal of the PMOS transistor P8. A drain terminal of the NMOS transistor N9 is coupled to a source terminal of the NMOS transistor N10.

[0077] In some embodiments, at least the gate terminals of the PMOS transistor P8 and the NMOS transistor N9 or the gate terminals of the PMOS transistor P9 and the NMOS transistor N8 correspond to the third input terminal of the multiplexer 302 in Fig. 3A.

[0078] Inverter I1 contains the NMOS transistor N11 and the PMOS transistor P11.

[0079] A gate terminal of the PMOS transistor P11 is configured to receive the signal Mq_x. A gate terminal of the NMOS transistor N11 is configured to receive the signal Mq_x. The gate terminal of the PMOS transistor P11 is coupled to the gate terminal of the NMOS transistor N11. A source terminal of the PMOS transistor P11 is coupled to the voltage supply VDD. A drain terminal of the PMOS transistor P11 is coupled to a drain terminal of the NMOS transistor N11. A source terminal of the NMOS transistor N11 is coupled to the reference voltage supply VSS.

[0080] Inverter I2 contains the NMOS transistor N12 and the PMOS transistor P12.

[0081] A gate terminal of the PMOS transistor P12 is configured to receive the QF signal. A gate terminal of the NMOS transistor N12 is configured to receive the QF signal. The gate terminal of the PMOS transistor P12 is coupled to the gate terminal of the NMOS transistor N12. A source terminal of the PMOS transistor P12 is coupled to the voltage supply VDD. A drain terminal of the PMOS transistor P12 is coupled to a drain terminal of the NMOS transistor N12. A source terminal of the NMOS transistor N12 is coupled to the reference voltage supply VSS.

[0082] Inverter I3 contains the NMOS transistor N13 and the PMOS transistor P13.

[0083] A gate terminal of the PMOS transistor P13 is configured to receive the signal QF_x. A gate terminal of the NMOS transistor N13 is configured to receive the signal QF_x. The gate terminal of the PMOS transistor P13 is coupled to the gate terminal of the NMOS transistor N13. A source terminal of the PMOS transistor P13 is coupled to the voltage supply VDD. A drain terminal of the PMOS transistor P13 is coupled to a drain terminal of the NMOS transistor N13. A source terminal of the NMOS transistor N13 is coupled to the reference voltage supply VSS.

[0084] The inverter 310 contains the NMOS transistor N14 and the PMOS transistor P14.

[0085] One gate terminal of the PMOS transistor P14 is configured to receive the clock signal CP. One gate terminal of the NMOS transistor N14 is configured to receive the clock signal CP. The gate terminal of the PMOS transistor P14 is coupled to the gate terminal of the NMOS transistor N14. One source terminal of the PMOS transistor P14 is coupled to the voltage supply VDD. One drain terminal of the PMOS transistor P14 is coupled to a drain terminal of the NMOS transistor N14. One source terminal of the NMOS transistor N14 is coupled to the reference voltage supply VSS.

[0086] The inverter 312 contains the NMOS transistor N15 and the PMOS transistor P15.

[0087] One gate terminal of the PMOS transistor P15 is configured to receive the clock signal CPB. One gate terminal of the NMOS transistor N15 is configured to receive the clock signal CPB. The gate terminal of the PMOS transistor P15 is coupled to the gate terminal of the NMOS transistor N15. One source terminal of the PMOS transistor P15 is coupled to the voltage supply VDD. One drain terminal of the PMOS transistor P15 is coupled to a drain terminal of the NMOS transistor N15. One source terminal of the NMOS transistor N15 is coupled to the reference voltage supply VSS.

[0088] The inverter 314 contains the NMOS transistor N16 and the PMOS transistor P16.

[0089] A gate terminal of the PMOS transistor P16 is configured to receive the scan enable signal SE. A gate terminal of the NMOS transistor N16 is configured to receive the scan enable signal SE. The gate terminal of the PMOS transistor P16 is coupled to the gate terminal of the NMOS transistor N16. A source terminal of the PMOS transistor P16 is coupled to the voltage supply VDD. A drain terminal of the PMOS transistor P16 is coupled to a drain terminal of the NMOS transistor N16. A source terminal of the NMOS transistor N16 is coupled to the reference voltage supply VSS.

[0090] Fig. 4A-4E are diagrams of a layout design 400 of an integrated circuit according to some embodiments. The layout design 400 is a layout diagram of the integrated circuit 300A of Fig. 3A or the integrated circuit 300B from Fig. 3B.

[0091] Layout design 400 is a layout diagram of at least the flip-flop 102, 104 or 106 of Fig. 1 or at least of the flip-flop 102, 104 or 106 of Fig. 3A or Fig. 3B.

[0092] Fig. 4A is a diagram of a 400 layout design. For clarity, some of the elements shown in Fig. 4A are marked with reference numbers, in Fig. 4B-4E are not provided with reference numerals. In some embodiments, the Fig. 4A-4E additional elements that are in Fig. 4A-4E are not shown.

[0093] Fig. 4A-4E are diagrams of a respective section 400A-400E of layout design 400 of Fig. 4A, simplified for clarity. Section 400A contains one or more features of layout design 400 of Fig. Section 4A of the oxide diffusion / epitaxy level (OD / EPI level), POLY level, cut poly level (CPO level), metal diffusion level (MD level), VD level (via over diffusion), BG level (via over gate), Mo level (metal 0), Vo level, CMo level (cut metal 0), and M1 level (metal 1) of layout design 400. Section 400B contains one or more features of layout design 400 of Fig. 4A of the BPR (Buried Power Rail) level and the OD (Oxide Diffusion) level of the 400 layout design.

[0094] Section 400C contains one or more features of Layout Design 400 of Fig. 4A of the BPR level, VB level, OD / EPI level, POLY level, CPO level, MD level, VD level, VG level, Mo level, Vo level, CMo level, and M1 level of layout design 400. Section 400C corresponds to an enlarged area (designated as area 403) of layout design 400. Fig. 4A, Fig. 4B and Fig. 4E, so for the sake of brevity a similarly detailed description is omitted. Area 403 of layout design 400 is in Fig. 4A and Fig. 4E marked with reference number.

[0095] Section 400D contains one or more features of the Layout Design 400 of Fig. 4A of the Mo level (Metal 0), a CMoA level (Cut Metal 0 Color A), a CMoB level (Cut Metal 0 color B), a V0 level (Via 0) and an M1 level (Metal 1) of the layout design 400.

[0096] Section 400E contains one or more features of layout design 400 from Fig. 4A of the OD / EPI level, the POLY level, the CPO level, the MD level, the VD level, the VG level, the Mo level, the Vo level, the CMo level and the M1 level of layout design 400. Section 400E of Fig. 4E corresponds to section 400A of Fig. Section 4A, but Sections 400A and 400E contain different designations for clarity. For example, Section 400A identifies each of the positions of the PMOS and NMOS transistors from the 300B integrated circuit, and a similar detailed description is omitted. Section 400E, for example, does not identify the positions of the PMOS and NMOS transistors of the 300B integrated circuit to simplify presentation, but Section 400E includes reference symbols for each set of gate layout structures 450 and each set of cut-gate layout structures 452, and a similar detailed description is omitted.

[0097] The layout design 400 is for the production of the integrated circuit 300A from Fig. 3A or the integrated circuit 300B from Fig. 3B usable. Layout design 400 is suitable for the production of at least the flip-flop 102, 104 or 106 from Fig. 1 or at least of the flip-flop 102, 104 or 106 of Fig. 3A or Fig. 3B usable.

[0098] Layout design 400 comprises a cell boundary 401a and a cell boundary 401b extending in a first direction X, a cell boundary 401c and 401d extending in a second direction Y, and a center point 401e extending in the first direction X. Layout design 400 has a height (not referenced) in a second direction Y from cell boundary 401b to cell boundary 401a. In some embodiments, the second direction Y is different from the first direction X. In some embodiments, layout design 400 abuts other cell layout designs along cell boundaries 401a and 401b (shown in Fig. 6A and Fig. 7A).

[0099] The layout design 400 comprises active area layout structures 402a, 402b, 402c, and 402d (collectively referred to as the set of active area layout structures 402) that extend in the first direction X. The layout structures 402a, 402b, 402c, and 402d of the set of active area layout structures 402 are separated from each other in the second direction Y. The set of active area layout structures 402 is used to create a corresponding set of active areas 502 ( Fig. 5) of the integrated circuit 500. In some embodiments, the set of active areas 502 is located on a front face of the integrated circuit 500. In some embodiments, the set of active areas 502 is also referred to as a set of epitaxial areas 502. In some embodiments, the layout structures 402a, 402b, 402c, 402d of the set of active area layout structures 402 can be used to define corresponding active areas 502a, 502b, 502c, 502d of the set of active areas 502 ( Fig. 5A-5E) of the integrated circuit 500.

[0100] In some embodiments, the set of active area layout structures 402 is referred to as an oxide diffusion area (OD) that defines the source or drain diffusion areas of at least the integrated circuit 300A, 300B or 500.

[0101] In some embodiments, at least the layout structure 402a or 402d of the set of active area layout structures 402 can be used to produce source and drain regions of NMOS transistors of the integrated circuits 300A-300B, and at least the layout structure 402b or 402c of the set of active area layout structures 402 can be used to produce source and drain regions of PMOS transistors of the integrated circuits 300A-300B.For example, in these embodiments, at least the active-area layout structure 402a or 402d of the set of active-area layout structures 402 can be used to fabricate source and drain regions of one or more NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15 or N16, and at least the active-area layout structure 402b or 402c of the set of active-area layout structures 402 can be used to fabricate source and drain regions of PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15 or P16.In some embodiments, at least the layout structure 402a or 402d of the set of active area layout structures 402 can be used to produce source and drain regions of PMOS transistors of the integrated circuits 300A-300B, and at least the layout structure 402b or 402c of the set of active area layout structures 402 can be used to produce source and drain regions of NMOS transistors of the integrated circuits 300A-300B.For example, in these embodiments, at least the active-area layout structure 402a or 402d of the set of active-area layout structures 402 can be used to fabricate source and drain regions of one or more PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15 or P16, and at least the active-area layout structure 402b or 402c of the set of active-area layout structures 402 can be used to fabricate source and drain regions of NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15 or N16.

[0102] In some embodiments, the set of active area layout structures 402 lies on a first layout level. In some embodiments, the first layout level corresponds to an active level or an OD level of one or more of the layout structures 400, 600A, or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the OD plane is also referred to as an EPI plane.

[0103] Other configurations, arrangements on other layout levels, or sets of structures in the set of active area layout structures 402 fall within the scope of this disclosure.

[0104] Layout design 400 further comprises one or more busbar layout structures 404a, 404b, or 404c (collectively referred to as a set of busbar layout structures 404) extending in the first direction X and lying on a second layout plane. In some embodiments, the second layout plane is different from the first layout plane. In some embodiments, the second layout plane corresponds to a buried power rail (BPR) plane of one or more of layout designs 400, 600A, or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the BPR plane lies below the OD plane.

[0105] The set of busbar layout structures 404 can be used to manufacture a corresponding set of busbars 504 of the integrated circuit 500 ( Fig. 5) In some embodiments, the set of busbars 504 is located on a rear side of the integrated circuit 500. In some embodiments, the busbar layout structures 404a, 404b, 404c of the set of busbar layout structures 404 can be used to connect corresponding busbars 504a, 504b, 504c of the set of busbars 504 ( Fig. 5) to manufacture the integrated circuit 500.

[0106] In some embodiments, the set of busbars 504 is arranged to supply a first supply voltage of a voltage supply VDD or a second supply voltage of a reference voltage supply VSS to the integrated circuit, such as the integrated circuit 500.

[0107] In some embodiments, busbars 504a and 504c are configured to provide the first supply voltage to the voltage supply VDD, and busbar 504b is configured to provide the second supply voltage to the reference voltage supply VSS. In some embodiments, busbars 504a and 504c are configured to provide the second supply voltage to the reference voltage supply VSS, and busbar 504b is configured to provide the first supply voltage to the voltage supply VDD.

[0108] In some embodiments, the busbar layout structures 504a and 504c of the set of busbar layout structures 404 are located along the respective cell boundaries 401a and 401b of the layout design 400. In some embodiments, the busbar layout structure 504b of the set of busbar layout structures 404 is located along a center point 401e of the layout design 400 in the first direction X.

[0109] Other configurations, arrangements on other layout levels or sets of structures in the set of busbar layout structures 404 fall within the scope of this disclosure.

[0110] Layout design 400 further comprises one or more via layout structures 406a (not referenced), 406b, 406c, ..., 406z (collectively referred to as a set of via layout structures 406), where z is an integer corresponding to the number of via layout structures in the set of via layout structures 406. For clarity, one or more via layout structures of the set of via layout structures 406 are not referenced. The set of via layout structures 406 lies on a VB (via buried power) layer of one or more of the layout designs 400, 600A, or 700A. Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the VB layer lies between the OD layer and the BPR layer. In some embodiments, the VBP layer lies between the BP layer and at least the OD layer or the MD layer. In some embodiments, the VBP layer lies between the first layout layer and at least the second layout layer. Other layout layers fall within the scope of this disclosure.

[0111] The via layout structure 406b is located between the busbar layout structure 404b and the active area layout structure 402c. In some embodiments, the via layout structure 406b is located between the busbar layout structure 404b and the contact layout structure 408b. The via layout structure 406c is located between the busbar layout structure 404c and the active area layout structure 402d. In some embodiments, the via layout structure 406c is located between the busbar layout structure 404c and the contact layout structure 408c. In some embodiments, at least one via layout structure from the set of via structures 406 is not included in the layout design 100.

[0112] Other configurations, arrangements on other layout levels, or sets of structures in the set of via structures 406 fall within the scope of this disclosure.

[0113] The layout design 400 further comprises one or more contact layout structures 408a, 408b, 408c, ..., 408o (collectively referred to as a set of contact layout structures 408) and one or more contact layout structures 409a, 409b, 409c, ..., 409u (collectively referred to as a set of contact layout structures 409) extending in the second direction Y. Each contact layout structure of the set of contact layout structures 408 is separated in the first direction X from an adjacent contact layout structure of the set of contact layout structures 408. Each contact layout structure of the set of contact layout structures 409 is separated in the first direction X from an adjacent contact layout structure of the set of contact layout structures 409. For the sake of clarity, one or more contact layout structures of the set of contact layout structures 408 or of the set of contact layout structures 409 are not provided with reference marks.

[0114] The set of contact layout structures 408 corresponds to the contact layout structures between the cell boundary 401b and the center point 401e. The set of contact layout structures 409 corresponds to the contact layout structures between the cell boundary 401a and the center point 401e.

[0115] The set of contact layout structures 408 can be used to produce a corresponding set of contacts 508 ( Fig. 5A-5E) of the integrated circuit 500. The set of contact layout structures 409 can be used to manufacture a corresponding set of contacts 509 ( Fig. 5A-5E) of the integrated circuit 500 can be used.

[0116] In some embodiments, contact layout structure 408a, 408b, 408c, ..., 408o of the set of contact layout structures 408 can be used to produce the corresponding contact 508a, 508b, 508c, ..., 508o of the set of contact layout structures 508. In some embodiments, contact layout structure 409a, 409b, 409c, ..., 409u of the set of contact layout structures 409 can be used to produce the corresponding contact 509a, 509b, 509c, ..., 509u of the set of contact layout structures 509. In some embodiments, the set of contact layout structures 408 or 409 is also referred to as a set of metal-over-diffusion (MD) layout structures.

[0117] In some embodiments, at least one of the contact layout structures 408a, 408b, 408c, ..., 408o of the set of contact layout structures 408 can be used to create source or drain terminals of one of the NMOS or PMOS transistors of the integrated circuit 500, and at least one of the contact layout structures 409a, 409b, 409c, ..., 409u of the set of contact layout structures 409 can be used to create source or drain terminals of one of the NMOS or PMOS transistors of the integrated circuit 500.

[0118] In some embodiments, the set of contact layout structures 408 overlaps the set of active area structures 402. The set of contact layout structures lies on a fifth layout level. In some embodiments, the fifth layout level is different from the first, second, third, and fourth layout levels. In some embodiments, the fifth layout level lies above the first and second layout levels.

[0119] In some embodiments, the fifth layout level corresponds to the contact level or an MD level of one or more of the layout designs 400, 600A or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B).

[0120] Other configurations, arrangements on other layout levels, or sets of structures in the set of contact layout structures 408 fall within the scope of this disclosure.

[0121] Layout design 400 further comprises one or more line feature layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, or 420h (collectively referred to as a set of line feature layout structures 420) extending in the first direction X and arranged on a third layout plane. In some embodiments, the third layout plane is different from the first and second layout planes. In some embodiments, the third layout plane corresponds to a Mo plane (Metal 0) of one or more of layout designs 400, 600A, or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the Mo plane lies above the OD plane and the BPR plane.

[0122] The set of conductor feature layout structures 420 can be used to produce a corresponding set of conductive structures 520 ( Fig. 5C) of the integrated circuit 500. The conduction feature layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, 420h can be used to fabricate the corresponding conductive structures 520a, 520b, 520c, 520d, 520e, 520f, 520g, 520h ( Fig. 5C).

[0123] The set of conductor feature layout structures 420 overlaps at least one busbar layout structure of the set of busbar layout structures 404.

[0124] In some embodiments, the set of line feature layout structures 420 overlaps other underlying layout structures (not shown) of other layout levels (for example, Active, MD, POLY or the like) of the layout design 400.

[0125] In some embodiments, each of the layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, 420h of the set of line feature layout structures 420 overlaps a corresponding grid line 422a, 422b, 422c, 422d, 422e, 422f, 422g, 422h of a set of grid lines 422. In some embodiments, a center of each of the layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, 420h of the set of line feature layout structures 420 in the first direction X is overlapped with a respective grid line 422a, 422b, 422c, 422d, 422e, 422f, 422g, 422h of a set of grid lines 422 aligned (aligned).

[0126] At least layout structure 420b, 420c, 420f, or 420g of the set of feature layout structures 420 has a width W1 in the second direction Y. At least layout structure 420a, 420d, 420e, or 420h of the set of feature layout structures 420 has a width W2 in the second direction Y. The width W2 is different from the width W1. In some embodiments, the width W2 is equal to the width W1.

[0127] Other widths for the set of line feature layout structures 420 are within the scope of this disclosure. In some embodiments, at least line feature layout structure 420b, 420c, 420f, or 420g of the set of line feature layout structures 420 has a width W2 in the second direction Y. In some embodiments, at least line feature layout structure 420a, 420d, 420e, or 420h of the set of line feature layout structures 420 has a width W1 in the second direction Y.

[0128] In some embodiments, the feature layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, 420h of the set of feature layout structures 420 correspond to the 8 M0 routing lanes in the layout design 400. Other numbers of M0 routing lanes are within the scope of this disclosure. When the number of M0 lanes is increased, in some embodiments the number of feature layout structures of the set of feature layout structures 420 with width W2 is reduced to maintain sufficient spacing between adjacent feature layout structures of the set of feature layout structures 420 to meet minimum spacing requirements that ensure sufficient production yield to overcome manufacturing variations.When the number of Mo paths is reduced, in some embodiments the number of line feature layout structures of the set of line feature layout structures 420 with width W2 is increased, while maintaining a sufficient distance between adjacent line feature layout structures of the set of line feature layout structures 420 to meet the minimum spacing requirements that ensure a sufficient production yield that overcomes manufacturing variations.

[0129] In some embodiments, the layout design 400 further includes one or more line feature layout structures 430a or 430b (collectively referred to as a set of line feature layout structures 430) or one or more line feature layout structures 432a or 432b (collectively referred to as a set of line feature layout structures 432) extending in the first direction X and located on the third layout plane. In some embodiments, the set of line feature layout structures 430 and 432 is similar to the set of line feature layout structures 420, and thus a similar detailed description is unnecessary.

[0130] In some embodiments, the sets of line feature layout structures 430 and 432 are part of associated layout designs (similar to layout design 400) that adjoin layout design 400 along corresponding cell boundaries 401a and 401b.

[0131] In some embodiments, the conductor feature layout structures 420a and 430a are offset in the second direction Y from the cell boundary 401a and are referred to as the "Sharing Space". In some embodiments, the conductor feature layout structures 420h and 432a are offset in the second direction Y from the cell boundary 401a and are referred to as the Sharing Space.

[0132] In some embodiments, the arrangement of feature layout structures 420a and 420h of the set of feature layout structures 420 such that they are offset from the cell boundaries 401a and 401b causes the feature layout structures 420b, 420c, 420d, 420e, 420f and 420g of the set of feature layout structures 420, in contrast to other approaches, to be shifted in the second direction Y from the cell boundary 401b, thereby creating additional space between similar, corresponding feature layout structures of adjacent layout designs (as, for example, in Fig. 6A and Fig. 7A shown), which results in a lower coupling capacity than with other approaches.

[0133] Other configurations, arrangements on other layout levels, or sets of structures in the set of feature layout structures 420 fall within the scope of this disclosure.

[0134] Layout design 400 further includes one or more via layout structures 456a (not referenced), 456b, 456c, ..., 4560 (collectively referred to as a set of via layout structures 456). For clarity, one or more via layout structures of the set of via layout structures 456 are not referenced. The set of via layout structures 456 is located at a VD (via over diffusion) layer of one or more of the layout designs 400, 600A, or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the VD layer is located between the MD layer and the Mo layer. In some embodiments, the VD layer is located between the fifth layout layer and at least the third layout layer. In some embodiments, at least one via layout structure of the set of via structures 456 is not included in the layout design 400. Other layout layers are within the scope of this disclosure.

[0135] Other configurations, arrangements on other layout levels, or sets of structures in the set of via structures 456 fall within the scope of this disclosure.

[0136] Layout design 400 further comprises one or more line feature layout structures 424a, 424b, 424c, 424d, 424e, 424f, 424g, 424h, 424i, 424j, or 424k (collectively referred to as a set of line feature layout structures 424) extending in the second direction Y and arranged on a fourth layout plane. In some embodiments, the fourth layout plane is different from the first, second, and third layout planes. In some embodiments, the fourth layout plane corresponds to an M1 (Metal 1) plane of one or more of layout designs 400, 600A, or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the M1 plane lies above the OD plane, the BPR plane and the Mo plane.

[0137] In some embodiments, each line feature layout structure of the set of line feature layout structures 424 is separated in the first direction X from an adjacent line feature layout structure.

[0138] The set of conductor feature layout structures 424 can be used to produce a corresponding set of conductive structures 524 ( Fig. 5) of the integrated circuit 500. The conduction feature layout structures 424a, 424b, 424c, 424d, 424e, 424f, 424g, 424h, 424i, 424j, 424k can be used to fabricate the corresponding conductive structures 524a, 524b, 524c, 524d, 524e, 524f, 524g, 524h, 524i, 524j, 524k ( Fig. 5) can be used.

[0139] The set of line feature layout structures 424 overlaps the set of line feature layout structures 420. In some embodiments, layout structures 424a, 424f, 424g, and 424k overlap at least line feature layout structures 420b, 420c, 420d, 420e, 420f, or 420h. In some embodiments, layout structures 424b and 424d overlap at least line feature layout structures 420a, 420b, 420c, or 420d. In some embodiments, layout structures 424c, 424e, and 424j overlap at least line feature layout structures 420e, 420f, 420g, or 420h. In some embodiments, the layout structure 424h overlaps at least the line feature layout structure 420d, 420e or 420f. In some embodiments, the layout structure 424i overlaps at least the line feature layout structure 420c, 420d or 420e.

[0140] In some embodiments, the set of line feature layout structures 424 overlaps the set of grid lines 422. In some embodiments, the set of line feature layout structures 424 overlaps other underlying layout structures (not shown) of other layout levels (for example, BPR, Active, MD, Mo, Vo, or the like) of the layout design 400.

[0141] Other configurations, arrangements on other layout levels, or sets of structures in the set of line feature layout structures 424 fall within the scope of this disclosure.

[0142] The layout design 400 further includes one or more via layout structures 426a, 426b, ..., 426r or 426s (collectively referred to as a set of via layout structures 426).

[0143] The set of via layout structures 426 can be used to produce a corresponding set of vias 526 ( Fig. 5D). In some embodiments, the via layout structures 426a, 426b, ..., 426r or 426s of the set of via layout structures 426 can be used to create corresponding vias 526a, 526b, ..., 526r or 526s of the set of vias 526 ( Fig. 5D) of the integrated circuit 500. In some embodiments, the set of via layout structures 426 is located between the set of conductor feature layout structures 420 and the set of conductor feature layout structures 424.

[0144] The set of via layout structures 426 is placed on a Vo level (Via 0) of one or more layout designs 400, 600A or 700A ( Fig. 4A-4D, 6A or 7A) or an integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the Vo plane is located between the M0 plane and the M1 plane. In some embodiments, the Vo plane is located between the fourth layout plane and the third layout plane. Other layout planes fall within the scope of this disclosure.

[0145] The via layout structures 426a and 426b are located between the conductor layout structure 424a and the corresponding conductor layout structures 420b and 420h. The via layout structure 426c is located between conductor layout structures 424b and 420d. The via layout structure 426d is located between conductor layout structures 424c and 420f. The via layout structure 426e is located between conductor layout structures 424d and 420c. The via layout structure 426f is located between conductor layout structures 424e and 420f. The via layout structures 426g, 426h, and 426i lie between the conductor feature layout structure 424f and the conductor feature layout structures 420a, 420f, and 420h. The via layout structures 426j, 426k, and 426l lie between the conductor feature layout structure 424g and the conductor feature layout structures 420a, 420e, and 420h.The via layout structures 426m and 426n are located between the conductor layout structure 424h and the conductor layout structures 420d and 420f. The via layout structures 426o and 426p are located between the conductor layout structure 424i and the conductor layout structures 420c and 420e. The via layout structure 426q is located between the conductor layout structures 424j and 420h. The via layout structures 426r and 426s are located between the conductor layout structure 424k and the conductor layout structures 420b and 420g. In some embodiments, at least one via layout structure of the set of via layout structures 426 is not included in the layout design 400.

[0146] Other configurations, arrangements on other layout levels, or sets of structures in the set of through-hole layout structures 426 fall within the scope of this disclosure.

[0147] The layout design 400 further comprises one or more cut feature layout patterns 440a, 440b, ..., 440g or 440h (collectively referred to as a set of cut feature layout patterns 440) or one or more cut feature layout patterns 442a, 442b, ..., 442i or 442j (collectively referred to as a set of cut feature layout patterns 442). The set of cutting feature layout structures 440 and 442 extends in the second direction Y. In some embodiments, each cutting feature layout structure 440a, 440b, ..., 440g or 440h of the set of cutting feature layout structures 440 or each cutting feature layout structure 442a, 442b, ..., 442i or 442j of the set of cutting feature layout structures 442 is separated from an adjacent cutting feature layout structure at least in the first direction X or the second direction Y. The set of cutting feature layout structures 440 and 442 lies in the third layout plane.

[0148] In some embodiments, the set of interface feature layout structures 440 and 442 overlaps at least one section of a layout structure of the set of line feature layout structures 420. In some embodiments, the set of interface feature layout structures 440 and 442 overlaps other underlying layout structures (not shown) of other layout levels (for example, BPR, Active, MD, or the like) of the layout design 400.

[0149] In some embodiments, the section feature layout structures 440a, 440b, ..., 440g or 440h and the section feature layout structures 442a, 442b, ..., 442i or 442j identify the respective locations of the corresponding sections (not referenced) of the set of conductive structures 520 that are used in step 806 of process 800 ( Fig. 8) be removed.

[0150] In some embodiments, the set of cut feature layout structures 440 has a first color (for example, color B) and the set of cut feature layout structures 442 has a second color (for example, color A). The color (for example, color A and color B) indicates that features with the same color are to be created on the same mask of a multi-mask set, and features with a different color are to be created on a different mask of the multi-mask set. Fig. The 4D diagram shows two colors as an example. In some embodiments, more or fewer than two colors are provided in the layout design 400.

[0151] Other configurations, arrangements on other layout levels, or sets of structures in the set of intersection feature layout structures 440 are within the scope of this disclosure. In some embodiments, at least one intersection feature layout structure of the set of intersection feature layout structures 440 or 442 is not included in the layout design 400.

[0152] The layout design 400 further comprises one or more gate layout structures 450a, 450b, 450c, ..., 450l (collectively referred to as a set of gate layout structures 450) extending in the second direction Y. Each of the gate layout structures of the set of gate layout structures 450 is separated from an adjacent gate layout structure of the set of gate layout structures 450 by a first distance (not shown) in the first direction X.

[0153] The set of gate layout structures 450 can be used to produce a corresponding set of gates 550 ( Fig. 5A-5E) of the integrated circuit 500 can be used. In some embodiments, the gate layout structures 450a, 450b, 450c, ..., 4501 of the set of gate layout structures 450 can be used to fabricate corresponding gates 550a, 550b, 550c, ..., 550l of the set of gates 550 ( Fig. 5A-5E) of the integrated circuit 500 can be used.

[0154] In some embodiments, at least a part of the gate layout structure 450a, 450b, 450c, ..., 450l of the set of gate layout structures 450 is usable for the manufacture of gates of NMOS transistors of the integrated circuit 300B, 500, 600B or 700B ( Fig. 3B, Fig. 5, Fig. 6B or Fig. 7B) and at least a part of the gate layout structure 450a, 450b, 450c, ..., 450l of the set of gate layout structures 450 is for the manufacture of gates of PMOS transistors of the integrated circuit 300B, 500, 600B or 700B ( Fig. 3B, Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the gate layout structures correspond to other transistors in the 300B integrated circuit.

[0155] The set of gate layout structures 450 is located above the set of active area layout structures 402, the set of busbar layout structures 404, and the set of via layout structures 406. The set of gate layout structures 450 is arranged on a sixth layout level (POLY) that is different from the first, second, third, and fourth layout levels. In some embodiments, the fifth layout level is located above the first and second layout levels. In some embodiments, the sixth layout level is the same as the fifth layout level. In some embodiments, the sixth layout level is different from the fifth layout level.

[0156] In some embodiments, the sixth layout level corresponds to the POLY level of one or more of the layout designs 400, 600A or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B).

[0157] Other configurations, arrangements on other layout levels, or sets of structures in the set of gate layout structure 450 fall within the scope of this disclosure.

[0158] Layout design 400 further includes one or more via layout structures 454a (not referenced), 454b, 454c, ..., 454q (collectively referred to as a set of via layout structures 454). For clarity, one or more via layout structures of the set of via layout structures 454 are not referenced. The set of via layout structures 454 is located at a VG (Via over Gate) level of one or more of the layout designs 400, 600A, or 700A ( Fig. 4A-4D, 6A or 7A) or the integrated circuit 500, 600B or 700B ( Fig. 5, Fig. 6B or Fig. 7B). In some embodiments, the VG plane is located between the POLY plane and the Mo plane. In some embodiments, the VG plane is located between the sixth layout plane and at least the third layout plane. In some embodiments, at least one via layout structure of the set of via structures 454 is not included in the layout design 400. Other layout planes fall within the scope of this disclosure.

[0159] Other configurations, arrangements on other layout levels, or sets of structures in the set of via structures 454 fall within the scope of this disclosure.

[0160] The layout design 400 further includes one or more cut feature layout patterns 452a, 452b, ..., 452g, or 452k (collectively referred to as a set of cut feature layout patterns 452). The set of cut feature layout patterns 452 extends in the first direction X. In some embodiments, each cut feature layout pattern 452a, 452b, ..., 452g, or 452k of the set of cut feature layout patterns 452 is separated from an adjacent cut feature layout pattern at least in the first direction X or the second direction Y. The set of cut feature layout patterns 452 lies on the sixth layout layer.

[0161] In some embodiments, the set of interface feature layout structures 452 overlaps at least part of a layout structure of the set of gate layout structures 450. In some embodiments, the set of interface feature layout structures 452 overlaps other underlying layout structures (not shown) of other layout levels (for example, BPR, Active, MD, or the like) of the layout design 400.

[0162] In some embodiments, the cut feature layout structures 452a, 452b, ..., 452g or 452k identify the respective positions of the corresponding sections (not referenced) of the set of gates 550 in the integrated circuit 500 that are removed by a cut-poly process. In some embodiments, the cut-poly process is the same as the cut-metal process in operation 806 of method 800 ( Fig. 8) similar and a similar detailed description is omitted.

[0163] Other configurations, arrangements on other layout levels, or sets of structures in the set of intersection feature layout structures 452 are within the scope of this disclosure. In some embodiments, at least one intersection feature layout structure of the set of intersection feature layout structures 452 is not included in the layout design 400.

[0164] Other configurations, arrangements on other layout levels, or sets of structures in the layout design 400 fall within the scope of this disclosure.

[0165] Fig. Figures 5A-5E are diagrams of an integrated circuit 500 according to some embodiments.

[0166] The integrated circuit 500 is manufactured using the layout design 400. The integrated circuit 500 is an embodiment of the integrated circuit 300A. Fig. 3A or the integrated circuit 300B from Fig. 3B.

[0167] Structural relationships, including orientation, lengths and widths, as well as configurations and layering of the integrated circuit 500, correspond to the structural relationships, configurations and layering of the layout design 400. Fig. 4A-4D are similar, and for the sake of brevity, a similarly detailed description with reference to them is omitted. Fig. 5A-5E, 6B-6C and 7B.

[0168] Fig. Figures 5A-5B and 5D-5E are top views of the integrated circuit 500 according to some embodiments. Fig. Figure 5C is a cross-sectional view of the integrated circuit 500 according to some embodiments. Fig. Figure 5C is a cross-sectional view of the integrated circuit 500 taken from plane AA', according to some embodiments. In some embodiments, Fig. 5C a cross-sectional view of the integrated circuit 500, which corresponds to the layout design 400 and is taken from plane AA', according to some embodiments. Fig. 5A-5E are diagrams of respective sections 500A-500E of the integrated circuit 500 of Fig. 5A, simplified for clarity.

[0169] Section 500A contains one or more features of the 500 integrated circuit. Fig. Section 5A describes the OD / EPI level, the POLY level, the MD level, the VD level, the VG level, the Mo level, the Vo level, and the M1 level of the 500 integrated circuit. Section 500B contains one or more features of the 500 integrated circuit. Fig. 5A of the BPR level and the OD / BPR level of the 500 integrated circuit.

[0170] Section 500C contains one or more features of the 500 integrated circuit. Fig. Section 5A describes the BPR, VB, OD, POLY, MD, and Mo levels of the 500 integrated circuit. Section 500D describes one or more features of the 500 integrated circuit. Fig. Section 5A of the Mo level, the CMoA level, the CMoB level, the Vo level and the M1 level of the 500 integrated circuit. Section 500E contains one or more features of the 500 integrated circuit. Fig. 5A of the OD / EPI level, the POLY level, the MD level, the VD level, the VG level, the Mo level, the Vo level and the M1 level of the 500 integrated circuit. The 500E section of Fig. 5E corresponds to section 500A of Fig. Section 5A, but sections 500A and 500E are provided with different reference symbols for clarity. For example, section 500A identifies each of the positions of the PMOS and NMOS transistors of the 300B integrated circuit, and a similar detailed description is omitted. Similarly, section 500E does not specify the positions of the PMOS and NMOS transistors of the 300B integrated circuit, but section 400E includes reference symbols for each set of 550 gates, and a similar detailed description is omitted.

[0171] The integrated circuit 500 comprises at least the set of active areas 502, the set of bus bars 504, the set of via layout structures 506, the set of contacts 508, the set of contacts 509, the set of conductive structures 520, the set of conductive structures 524 or the set of vias 526, the set of gate layout structures 550, the set of vias 554 and the set of vias 556.

[0172] In some embodiments, at least the active region 502a or 502d of the set of active regions corresponds to the source and drain regions of NMOS transistors of the integrated circuits 300A-300B, and at least the active region 502b or 502c of the set of active regions 502 corresponds to the source and drain regions of PMOS transistors of the integrated circuits 300A-300B. For example, at least the active region 502a or 502d of the set of active regions 502 in these embodiments corresponds to the source and drain regions of one or more NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15 or N16, and at least the active region 502b or 502c of the set of active regions 502 corresponds to the source and drain regions of the PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15 or P16.

[0173] In some embodiments, at least the active region 502a or 502d of the set of active regions 502 corresponds to the source and drain regions of PMOS transistors of the integrated circuits 300A-300B and at least the active region 502b or 502c of the set of active regions 502 corresponds to the source and drain regions of NMOS transistors of the integrated circuits 300A-300B. For example, at least the active region 502a or 502d of the set of active regions 502 in these embodiments corresponds to the source and drain regions of one or more PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15 or P16, and at least one active region 502b or 502c of the set of active regions 502 corresponds to the source and drain regions of NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15 or N16.The set of active regions 502 is electrically isolated from one another by a set of insulating structures 503. Each of the active regions 502c and the active region 502d are electrically isolated from one another by the insulating structure 503b. In some embodiments, the set of insulating structures 503 is an epitaxial structure. In some embodiments, the set of insulating structures 503 includes an oxide or a nitride of a high-k dielectric. Other configurations, arrangements on other layout planes, or sets of structures in the set of active regions 502 are within the scope of this disclosure.

[0174] In some embodiments, the set of active areas 502 is located on a front side of the integrated circuit 500. In some embodiments, the set of busbars 504 is located on a back side of the integrated circuit 500. The front side of the integrated circuit 500 faces the back side of the integrated circuit 500 in the second direction Y. In some embodiments, the arrangement of the busbar set 504 on the back side of the integrated circuit 500 results in the integrated circuit 500 occupying less area than in other approaches.

[0175] Other configurations, arrangements on other layout levels or sets of structures in the set of busbars 504 fall within the scope of this disclosure.

[0176] The busbar 504b is configured to supply a supply voltage VDD, and the busbars 504a and 504c are configured to supply a reference supply voltage VSS. The set of vias 506 is configured to electrically couple the set of busbars 504 to the set of active areas 502. The via 506b is located between the busbar 504b and the active area 502c. In some embodiments, the via 506b is located between the busbar 504b and the contact 508b. The via 506c is located between the busbar 504c and the active area 502d. In some embodiments, the via 506c is located between the busbar 504c and the contact 508c. Other configurations, arrangements on other planes, or quantities in the set of vias 506 are within the scope of this disclosure.

[0177] The set of contacts 508 and 509 correspond to the contacts of the PMOS and NMOS transistors in the 300B integrated circuit. Fig. 3B. For the sake of clarity, one or more contacts of the set of contacts 508 or 509 are not provided with reference marks.

[0178] In some embodiments, at least one contact 508a, 508b, 508c, ..., 508o of the set of contacts 508 corresponds to the source or drain terminals of one of the NMOS or PMOS transistors of the integrated circuit 300B, and at least one contact 509a, 509b, 509c, ..., 509u of the set of contacts 509 corresponds to the source or drain terminals of one of the NMOS or PMOS transistors of the integrated circuit 300B. Other configurations, arrangements at other levels, or sets of structures in the set of contacts 508 are within the scope of this disclosure.

[0179] The set of vias 556 is configured to electrically couple the set of active areas 502 with the set of contacts 508 and 509. For clarity, one or more vias of the set of vias 556 are not labelled. Other configurations, arrangements on other levels, or quantities in the set of vias 556 are within the scope of this disclosure.

[0180] The set of conductive structures 520 comprises one or more of the conductive structures 520a, 520b, 520c, 520d, 520e, 520f, 520g or 520h. The set of conductive structures 520 overlaps at least one busbar of the set of busbars 504.

[0181] In some embodiments, the set of conductive structures 520 overlaps other underlying structures (not shown) of other levels (for example, Active, MD, POLY or the like) of the integrated circuit 500.

[0182] At least the conductive structure 520b, 520c, 520f, or 520g of the set of conductive structures 520 has a width W1' in the second direction Y. At least the conductive structure 520a, 520d, 520e, or 520h of the set of conductive structures 520 has a width W2' in the second direction Y. The width W2' is different from the width W1'. In some embodiments, the width W2' is equal to the width W1'.

[0183] Other widths for the set of conductive structures 520 are within the scope of this disclosure. In some embodiments, at least the conductive structure 520b, 520c, 520f, or 520g of the set of conductive structures 520 has a width W2' in the second direction Y. In some embodiments, at least the conductive structure 520a, 520d, 520e, or 520h of the set of conductive structures 520 has a width W1' in the second direction Y.

[0184] In some embodiments, the conductive structures 520a, 520b, 520c, 520d, 520e, 520f, 520g, 520h of the set of conductive structures 520 correspond to 8 Mo routing paths in the integrated circuit 500. Other numbers of Mo routing paths are within the scope of this disclosure. When the number of Mo paths is increased, in some embodiments the number of conductive structures of the set of conductive structures 520 with width W2' is reduced to maintain sufficient spacing between adjacent conductive structures of the set of conductive structures 520 to meet minimum spacing requirements that ensure a sufficient production yield to overcome manufacturing variations.When the number of Mo tracks is reduced, in some embodiments the number of conductive structures of the set of conductive structures 520 with width W2' is increased, while maintaining a sufficient distance between adjacent conductive structures of the set of conductive structures 520 to meet the minimum spacing requirements that ensure a sufficient production yield which overcomes manufacturing variations.

[0185] In some embodiments, the integrated circuit 500 further comprises at least one set of conductive structures 530 or one set of conductive structures 532. The set of conductive structures 530 comprises one or more conductive structures 530a or 530b. The set of conductive structures 532 comprises one or more conductive structures 532a or 532b. In some embodiments, the set of conductive structures 530 and 532 is similar to the set of conductive structures 520, and thus a similar detailed description is unnecessary.

[0186] In some embodiments, at least one conductive structure of the set of conductive structures 520, 524, 530 or 532, or at least one busbar of the set of busbars 504, comprises one or more layers of a conductive material. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or the like, or combinations thereof.

[0187] In some embodiments, the set of conductive structures 530 and 532 is part of corresponding integrated circuits (similar to the integrated circuit 500) that adjoin the integrated circuit 500 along respective cell boundaries 501a and 501b. In some embodiments, the conductive structures 520a and 530a are offset in the second direction Y from the cell boundary 501a and are referred to as the sharing space. In some embodiments, the conductive structures 520h and 532a are offset in the second direction Y from the cell boundary 501a and are referred to as the sharing space.

[0188] In some embodiments, increasing the width W1' or W2' decreases the resistance of the respective conductive structure of the set of conductive structures 520, and vice versa. However, in some embodiments, the coupling capacitance between the corresponding conductive structures of the set of conductive structures 520 also increases with increasing width W1' or W2'. The arrangement of conductive structures 520a and 520h of the set of conductive structures 520 such that they are offset from the cell boundaries 501a and 501b causes, in some embodiments, conductive structures 520b, 520c, 520d, 520e, 520f, and 520g of the set of conductive structures 520 to be displaced in the second direction Y from the cell boundary 501b, in contrast to other approaches. This creates an additional distance between similar conductive structures of adjacent integrated circuits (as, for example, in Fig. (6B-6C and 7B shown), resulting in a lower coupling capacitance between the set of conductive structures 520 than in other approaches. In some embodiments, the reduction in the coupling capacitance of the set of conductive structures 520 results in the integrated circuit 500 consuming less energy than in other approaches.

[0189] The set of 550 gates corresponds to the gates of the PMOS transistors and NMOS transistors of the 300B integrated circuit. Fig. 3B.

[0190] Gate 550b corresponds to the gates of each of the PMOS transistors P7 and P13 and the NMOS transistors N7 and N13. Part of gate 550b corresponds to the gate of PMOS transistor P7 and NMOS transistor N7, and another part of gate 550b corresponds to the gate of PMOS transistor P13 and NMOS transistor N13.

[0191] Gate 550c corresponds to the gates of each of the PMOS transistors P8 and P12 and the NMOS transistors N8 and N12. Part of gate 550c corresponds to the gate of PMOS transistor P8 and NMOS transistor N8, and another part of gate 550c corresponds to the gate of PMOS transistor P12 and NMOS transistor N12.

[0192] The 550d gate corresponds to the gates of PMOS transistor P10 and NMOS transistor N10.

[0193] Gate 550e corresponds to the gates of each of the PMOS transistors P9 and P16 and the NMOS transistors N9 and N16. Part of gate 550e corresponds to the gate of PMOS transistor P9 and NMOS transistor N9, and another part of gate 550e corresponds to the gate of PMOS transistor P16 and NMOS transistor N16.

[0194] Gate 550f corresponds to the gates of PMOS transistor P6 and NMOS transistor N6.

[0195] Gate 550g corresponds to the gates of each of the PMOS transistors P1 and P5 and the NMOS transistors N1 and N5. One part of Gate 550g corresponds to the gate of PMOS transistors P1 and P5, another part of Gate 550g corresponds to the gate of NMOS transistor N1, and another part of Gate 550g corresponds to the gate of NMOS transistor N5.

[0196] Gate 550h corresponds to the gates of each of the PMOS transistors P3 and P4 and the NMOS transistors N3 and N4. Part of gate 550h corresponds to the gate of PMOS transistors P3 and P4, another part of gate 550h corresponds to the gate of NMOS transistor N3, and another part of gate 550h corresponds to the gate of NMOS transistor N4.

[0197] The 550i gate corresponds to the gates of PMOS transistor P2 and NMOS transistor N2.

[0198] Gate 550j corresponds to the gates of PMOS transistor P11 and NMOS transistor N11.

[0199] The 550k gate corresponds to the gates of each of the PMOS transistors P14 and P15 and the NMOS transistors N14 and N15. Part of the 550k gate corresponds to the gate of PMOS transistor P14 and NMOS transistor N14, and another part of the 550k gate corresponds to the gate of PMOS transistor P15 and NMOS transistor N15.

[0200] Other configurations, arrangements at other levels, or sets in the Gates 550 set are within the scope of this disclosure.

[0201] The set of vias 554 electrically couples the set of gates 550 and the set of conductive structures 520. For clarity, one or more vias of the set of vias 554 are not labelled. Other configurations, arrangements on other levels, or quantities in the set of vias 554 are within the scope of this disclosure.

[0202] Other configurations, arrangements on other layout levels, or sets of structures in the integrated circuit 500 fall within the scope of this disclosure.

[0203] Fig. 6A is a diagram of a layout design 600A of an integrated circuit according to some embodiments. The layout design 600A is a layout diagram of the integrated circuit 100 of Fig. 1 or the integrated circuit 200 of Fig. 2. For the sake of clarity, some of the elements that are in Fig. 6A are marked with reference numbers, in Fig. 6A not labelled with a reference mark.

[0204] Layout design 600A includes layout designs 602, 604, and 606. In some embodiments, layout design 600A contains additional elements that are described in Fig. 6A are not shown.

[0205] In some embodiments, each of the layout designs 602, 604, and 606 corresponds to layout design 400, thus rendering a similarly detailed description unnecessary. In some embodiments, layout design 602 is a layout design of flip-flop 102. Fig. 1. Layout design 604 is a layout design of flip-flop 104, and layout design 604 is a layout design of flip-flop 106, thus rendering a similarly detailed description unnecessary. In some embodiments, layout design 602 is a layout design of flip-flop 202. Fig. 2. Layout design 604 is a layout design of flip-flop 204, and layout design 604 is a layout design of flip-flop 206, and thus a similar detailed description is unnecessary.

[0206] Each of the layout designs 602, 604, and 606 extends at least in the first direction X. Each of the layout designs 602, 604, and 606 is separated from another of the layout designs 602, 604, and 606 in the second direction Y.

[0207] Layout design 602 has cell boundaries 601a and 601b extending in the first direction X. In some embodiments, layout design 602 borders other layout designs in the first direction along cell boundary 601a (not shown for clarity).

[0208] Layout design 602 borders layout design 604 in the first direction X along cell boundary 601b. Layout design 604 borders layout design 606 in the first direction X along cell boundary 601c. Layout design 606 borders other layout designs in the first direction X along cell boundary 601d (not shown for illustrative purposes).

[0209] In some embodiments, the layout designs 602, 604, or 606 are different from each other. Each of the layout designs 602, 604, and 606 has a height H1 in the second direction Y. In some embodiments, the layout designs 602 and 604 are mirror images of each other with respect to cell boundary 601b. In some embodiments, the layout designs 604 and 606 are mirror images of each other with respect to cell boundary 601c.

[0210] In some embodiments, each of the layout designs 602, 604 and 606 corresponds to layout design 400, thus making a similar detailed description unnecessary.

[0211] In contrast to layout design 400, the feature layout structures 620a, 620b, 620c, 620d, 620e, 620f, 620g, 620h of the set of feature layout structures 620 of layout design 604 replace the corresponding feature layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, 420h of the set of feature layout structures 420 in some embodiments, thus making a similar detailed description unnecessary.

[0212] In some embodiments, layout design 602 is a mirror image of layout design 400 with respect to the first direction X. In contrast to layout design 400, the feature layout structures 610a, 610b, 610c, 610d, 610e, 610f, 610g, 610h of the set of feature layout structures 610 of layout design 602 replace, in some embodiments, the corresponding feature layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, 420h of the set of feature layout structures 420, thus rendering a similarly detailed description unnecessary.

[0213] In some embodiments, layout design 606 is a mirror image of layout design 400 with respect to the first direction X. In contrast to layout design 400, the feature layout structures 630a, 630b, 630c, 630d, 630e, 630f, 630g, 630h of the set of feature layout structures 630 of layout design 606 replace, in some embodiments, the corresponding feature layout structures 420a, 420b, 420c, 420d, 420e, 420f, 420g, 420h of the set of feature layout structures 420, thus rendering a similarly detailed description unnecessary.

[0214] In some embodiments, at least the line feature layout structure 610b, 620g or 630b is a layout structure of the input pin of inverter 310. Fig. 3B. In some embodiments, at least the line feature layout structure 61oh, 620a or 630h is a layout structure of the output pin of inverter 312 of Fig. 3B.

[0215] In some embodiments, at least the line feature layout structure 610b, 620g or 630b is a layout structure of the respective input pin of the inverter 650a, 650b and 650c of Fig. 6B. In some embodiments, at least the line feature layout structure 61oh, 620a or 630h is a layout structure of the corresponding output pin of the inverter 652a, 652b and 652c of Fig. 6B

[0216] In some embodiments, arranging the conductive feature layout structures 620h and 630a such that they are offset from the cell boundary 601c results in an increased distance between the conductive feature layout structures 620h and 630a in the second direction Y compared to other approaches. In some embodiments, the increased distance between the conductive feature layout structures 620h and 630a in the second direction Y leads to a lower coupling capacitance between the conductive structures 620h' ( Fig. 6C) and 630a', which are produced by associated conductor feature layout structures 620h and 630a, than in other approaches.

[0217] In some embodiments, arranging the conductive feature layout structures 610h and 620a such that they are offset from the cell boundary 601b results in an increased distance between the conductive feature layout structures 610h and 620a in the second direction Y compared to other approaches. In some embodiments, the increased distance between the conductive feature layout structures 610h and 620a in the second direction Y leads to a lower coupling capacitance between the conductive structures 610h' ( Fig. 6C) and 620a', which are produced by corresponding conductor feature layout structures 610h and 620a, than in other approaches.

[0218] Other configurations or sets of layout designs 602, 604, and 606 fall within the scope of this disclosure. For example, layout design 600A of Fig. 6A one column (column 1) and three rows (rows 1-3) of cells (for example, layout designs 602, 604, and 606). Other numbers of rows and / or columns in layout design 600A are within the scope of this disclosure.

[0219] In some embodiments, layout design 600A includes, for example, at least one additional column of cells similar to column 1 and adjacent to column 1. In some embodiments, layout design 600A includes, for example, at least one additional row of cells similar to row 2 and adjacent to row 1 along cell boundary 601a. ​​In some embodiments, layout design 600A includes, for example, at least one additional row of cells similar to row 2, adjacent to row 3 along the associated cell boundary 601d. In some embodiments, layout design 602 or 606 alternates with the standard cell layout design 604 in the second direction Y.

[0220] Fig. Figure 6B is a schematic view of a diagram of an integrated circuit 600B according to some embodiments.

[0221] The 600B integrated circuit comprises sections 602', 604', and 606'. In some embodiments, each section 602', 604', and 606' corresponds to the 300B integrated circuit. Fig. 3B and therefore a similar detailed description is unnecessary.

[0222] In some embodiments, the integrated circuit 600B is manufactured using the layout design 600A, thus rendering a similarly detailed description unnecessary. In some embodiments, the sections 602', 604', and 606' are manufactured using the layout designs 602, 604, and 606 of Fig. 6A manufactured, therefore a similar detailed description is unnecessary.

[0223] In some embodiments, boundaries 601a', 601b', 601c' and 601d' correspond to cell boundaries 601a, 601b, 601c and 601d of layout design 600A, thus a similar detailed description is unnecessary.

[0224] Each section 602', 604', and 606' contains one inverter 650a, 650b, and 650c, respectively, and one inverter 652a, 652b, and 652c, respectively. Each of the inverters 650a, 650b, and 650c is connected to inverter 310. Fig. 3B similar and each of the inverters 652a, 652b and 652c is similar to the inverter 310 from Fig. 3B is similar, and therefore a similarly detailed description is unnecessary.

[0225] In some embodiments, the output pins of inverters 652a, 652b, and 652c are coupled together. In some embodiments, the output pin of inverter 652a and the output pin of inverter 652b have a coupling capacitance C1.

[0226] In some embodiments, the input pins of inverters 650a, 650b, and 650c are coupled together. In some embodiments, the input pin of inverter 650b and the input pin of inverter 650c have a coupling capacitance C2.

[0227] Fig. Figure 6C is a top view of an integrated circuit 600B according to some embodiments.

[0228] The 600B integrated circuit is manufactured using the 600A layout design.

[0229] The 600B integrated circuit is an embodiment of the 100 integrated circuit. Fig. 1 or the integrated circuit 200 of Fig. 2.

[0230] In some embodiments, each section 602', 604', and 606' corresponds to the integrated circuit 500, thus rendering a similarly detailed description unnecessary. In some embodiments, section 602' is an embodiment of the flip-flop 102 of Fig. 1. Area 604' is an embodiment of flip-flop 104 and area 604' is an embodiment of flip-flop 106, and thus a similarly detailed description is unnecessary. In some embodiments, area 602' is an embodiment of flip-flop 202 of Fig. 2, area 604 is an embodiment of the flip-flop 204 and area 604' is an embodiment of the flip-flop 206, and thus a similar detailed description is unnecessary.

[0231] In contrast to the integrated circuit 500, the conductive structures 620a', 620b', 620c', 620d', 620e', 620f, 620g', 620h' of the set of conductive structures 620' of the area 604' replace, in some embodiments, the corresponding conductive structures 520a, 520b, 520c, 520d, 520e, 520f, 520g, 520h of the set of conductive structures 520, thus making a similar detailed description unnecessary.

[0232] In some embodiments, the region 602' is a mirror image of the integrated circuit 500 with respect to the first direction X. In contrast to the integrated circuit 500, the conductive structures 610a', 610b', 610c', 610d', 610e', 610f, 610g', 610h' of the set of conductive structures 610' of region 602' replace, in some embodiments, the corresponding conductive structures 520a, 520b, 520c, 520d, 520e, 520f, 520g, 520h of the set of conductive structures 520, thus rendering a similarly detailed description unnecessary.

[0233] In some embodiments, the region 606' is a mirror image of the integrated circuit 500 with respect to the first direction X. In contrast to the integrated circuit 500, the conductive structures 630a', 630b', 630c', 630d', 630e', 630f, 630g', 630h' of the set of conductive structures 630' of region 606' replace, in some embodiments, the corresponding conductive structures 520a, 520b, 520c, 520d, 520e, 520f, 520g, 520h of the set of conductive structures 520, thus rendering a similarly detailed description unnecessary.

[0234] In some embodiments, at least the conductive structure 610b', 620g' or 630b' is the respective input pin of the inverter 650a, 650b and 650c of Fig. 6B. In some embodiments, at least the conductive structure 610h', 620a' or 630h' is the respective output pin of the inverter 652a, 652b and 652c of Fig. 6B.

[0235] In some embodiments, the output pin of inverter 652a and the output pin of inverter 650b have a coupling capacitance C1.

[0236] In some embodiments, the input pin of inverter 650b and the input pin of inverter 650c have a coupling capacitance C2.

[0237] In some embodiments, arranging the conductive structures 620h' and 630a' such that they are offset from the boundary 601c' results in an increased distance between the conductive structures 620h' and 630a' in the second direction Y compared to other approaches. In some embodiments, this increased distance between the conductive structures 620h' and 630a' in the second direction Y leads to a lower coupling capacitance C2 between the conductive structures 620h' and 630a' than in other approaches for the same clock rate.

[0238] In some embodiments, arranging the conductive structures 610h' and 620a' such that they are offset from the boundary 601b' results in an increased distance between the conductive structures 610h' and 620a' in the second direction Y compared to other approaches. In some embodiments, this increased distance between the conductive structures 610h' and 620a' in the second direction Y leads to a lower coupling capacitance C1 between the conductive structures 610h' and 620a' than in other approaches for the same clock rate. In some embodiments, the reduction of the coupling capacitances C1 and C2 results in the integrated circuit 600B consuming less energy than in other approaches.

[0239] In some embodiments, reducing the coupling capacitance C1 and C2 results in the integrated circuit 600B consuming less energy than with other approaches.

[0240] Other configurations or quantities of areas 602', 604', and 606' fall within the scope of this disclosure. For example, the integrated circuit 600B comprises Fig. 6C has one column (column 1) and three rows (rows 1-3) of cells (for example, the ranges 602', 604' and 606'). Other numbers of rows and / or columns in the integrated circuit 600B are within the scope of this disclosure.

[0241] Fig. 7A is a diagram of a layout design 700A of an integrated circuit according to some embodiments. The layout design 700A is a layout diagram of the integrated circuit 100 of Fig. 1 or the integrated circuit 200 of Fig. 2. For the sake of clarity, some of the elements that are in Fig. 6A are marked with reference numbers, in Fig. 6A not labelled with a reference mark.

[0242] Layout design 700A is a variation of layout design 600A, and therefore a similarly detailed description is unnecessary. For example, layout design 700A illustrates an example where a set of feature layout structures 710, 720, 730 replaces the corresponding set of feature layout structures 610, 620, 630. Fig. 6A is replaced, resulting in layout design 700A having more Mo routing lanes than layout design 600A.

[0243] In contrast to the layout design 600A, the line feature layout structures 710a, 710d, 710e, 710h, 720a, 720d, 720e, 720h, 730a, 730d, 730e, 730h replace the corresponding line feature layout structures 610a, 610d, 610e, 610h, 620a, 620d, 620e, 620h, 630a, 630d, 630e, 630h, thus rendering a similar detailed description unnecessary.

[0244] The set of feature layout structures 720 includes one or more of the feature layout structures 720a, 620b, 620c, 720d, 720e, 620f, 620g, 720h or 720i.

[0245] The set of feature layout structures 710 includes one or more of the feature layout structures 710a, 610b, 610c, 710d, 710e, 610f, 610g, 710h or 710i.

[0246] The set of feature layout structures 730 includes one or more of the feature layout structures 730a, 710b, 710c, 730d, 730e, 710f, 710g, 730h or 730i.

[0247] In contrast to the layout design 600A, each of the line feature layout structures 710a, 710d, 710e, 710h, 720a, 720d, 720e, 720h, 730a, 730d, 730e, 730h has the width W1 instead of the width W2, thus making a similar detailed description unnecessary.

[0248] The feature layout structure 720i is located between feature layout structures 720d and 720e. The feature layout structure 710i is located between feature layout structures 710d and 710e. The feature layout structure 730i is located between feature layout structures 730d and 730e.

[0249] By changing the widths of each of the line feature layout structures 720a, 720d, 720e, 720h, the set of line feature layout structures 720 has 9 Mo routing paths in some embodiments, in contrast to the 8 Mo routing paths in Fig. 6A.

[0250] By changing the widths of each of the line feature layout structures 710a, 710d, 71oe, 710h, the set of line feature layout structures 710 has 9 Mo routing paths in some embodiments, in contrast to the 8 Mo routing paths in Fig. 6A.

[0251] By changing the widths of each of the conductor feature layout structures 730a, 730d, 730e, 730h, the set of conductor feature layout structures 730 has 9 Mo conductor tracks in some embodiments, in contrast to the 8 Mo conductor tracks in Fig. 6A.

[0252] Other configurations, arrangements on other layout levels, or sets of structures in the set of feature layout structures 710, 720, or 730 are within the scope of this disclosure. Other configurations or sets of layout structures in layout design 700A are within the scope of this disclosure.

[0253] In some embodiments, arranging the conductive feature layout structures 720h and 730a such that they are offset from the cell boundary 601c results in an increased distance between the conductive feature layout structures 720h and 730a in the second direction Y compared to other approaches. In some embodiments, the increased distance between the conductive feature layout structures 720h and 730a in the second direction Y leads to a lower coupling capacitance between the conductive structures 720h' ( Fig. 7B) and 730a', which are produced using corresponding line feature layout structures 720h and 730a, than in other approaches.

[0254] In some embodiments, arranging the conductive feature layout structures 710h and 720a such that they are offset from the cell boundary 601b results in an increased distance between the conductive feature layout structures 710h and 720a in the second direction Y compared to other approaches. In some embodiments, the increased distance between the conductive feature layout structures 710h and 720a in the second direction Y leads to a lower coupling capacitance between the conductive structures 710h' ( Fig. 7B) and 720a', which are produced using corresponding line feature layout structures 710h and 720a, than in other approaches.

[0255] Fig. Figure 7B is a top view of an integrated circuit 700B according to some embodiments.

[0256] The 700B integrated circuit is manufactured using the 700A layout design.

[0257] The 700B integrated circuit is an embodiment of the 100 integrated circuit. Fig. 1 or the integrated circuit 200 of Fig. 2.

[0258] The 700B integrated circuit is a variant of the 600C integrated circuit, and a similarly detailed description is omitted. For example, the 700B integrated circuit illustrates an example where a set of conductive structures 710', 720', 730' represents the corresponding set of conductive structures 610', 620', 630' of the 600C. Fig. 6C replaced, resulting in the 700B integrated circuit having more Mo routing traces than the 600B integrated circuit.

[0259] In contrast to the integrated circuit 700B, the conductive structures 710a', 710d', 710e', 710h', 720a', 720d', 720e', 720h', 730a', 730d', 730e', 730h' replace corresponding conductive structures 610a', 610d', 610e', 610h', 620a', 620d', 620e', 620h', 630a', 630d', 630e', 630h' and thus a similar detailed description is unnecessary.

[0260] The set of conductive structures 720' includes one or more of the conductive structures 720a', 620b', 620c', 720d', 720e', 620f, 620g', 720h' or 720i'.

[0261] The set of conductive structures 710' includes one or more of the conductive structures 710a', 610b', 610c', 710d', 710e', 610f, 610g', 710h' or 710i'.

[0262] The set of conductive structures 730' includes one or more of the conductive structures 730a', 710b', 710c', 730d', 730e', 710f, 710g', 730h' or 730i'.

[0263] In contrast to the 700B integrated circuit, each of the conductive structures 710a, 710d, 710e, 710h, 720a, 720d, 720e, 720h, 730a, 730d, 730e, 730h has a width W1' instead of a width W2', so that a similar detailed description is not necessary.

[0264] The conductive structure 720i' lies between the conductive structures 720d' and 720e'. The conductive structure 710i' is located between the conductive structures 71od' and 710e'. The conductive structure 730i' is located between the conductive structures 730d' and 730e'.

[0265] By changing the widths of the conductor structures 720a', 720d', 720e', 720h', the set of conductor structures 720' has 9 Mo routing paths in some embodiments, compared to the 8 Mo routing paths in Fig. 6C.

[0266] By changing the widths of the conductor structures 710a', 710d', 71oe', 710h', the set of conductor structures 710' has 9 Mo routing paths in some embodiments, compared to the 8 Mo routing paths in Fig. 6C.

[0267] By changing the widths of the conductor structures 730a', 730d', 730e', 730h', the set of conductor structures 730' has 9 Mo routing paths in some embodiments, compared to the 8 Mo routing paths in Fig. 6C.

[0268] Other configurations, arrangements on other layout levels, or sets of structures in the set of conductive structures 710', 720', or 730' are within the scope of this disclosure. Other configurations or sets of structures in the integrated circuit 700B are within the scope of this disclosure.

[0269] In some embodiments, arranging the conductive structures 720h' and 730a' such that they are offset from the boundary 601c' results in an increased distance between the conductive structures 720h' and 730a' in the second direction Y compared to other approaches. In some embodiments, this increased distance between the conductive structures 720h' and 730a' in the second direction Y leads to a lower coupling capacitance C2 between the conductive structures 720h' and 730a' than in other approaches for the same clock rate.

[0270] In some embodiments, arranging the conductive structures 710h' and 720a' such that they are offset from the boundary 601b' results in an increased distance between the conductive structures 710h' and 720a' in the second direction Y compared to other approaches. In some embodiments, this increased distance between the conductive structures 710h' and 720a' in the second direction Y leads to a lower coupling capacitance C1 between the conductive structures 710h' and 720a' than in other approaches for the same clock rate. In some embodiments, the reduction of the coupling capacitances C1 and C2 results in the integrated circuit 700B consuming less energy than in other approaches.

[0271] In some embodiments, reducing the coupling capacitance C1 and C2 results in the integrated circuit 700B consuming less energy than with other approaches.

[0272] Fig. Figure 8 is a flowchart of a process 800 for forming or manufacturing an integrated circuit according to some embodiments. It is understood that additional operations may occur before, during, and / or after the process described in the diagram. Fig. The processes described in Figure 8 can be carried out using Method 800, and some other processes are only briefly outlined herein. In some embodiments, Method 800 can be used to fabricate integrated circuits such as 100, 200, 300A-300B, 400A-400B, 500, 600B, or 700B. In some embodiments, Method 800 can be used to form integrated circuits that have similar structural relationships to one or more of the layout designs 400, 600A, or 700A.

[0273] In step 802 of procedure 800, a layout design of an integrated circuit is generated. Step 802 is performed by a processor unit (for example, a processor 1102 ( Fig. 11)) executed, which is configured to execute instructions for generating a layout design. In some embodiments, the layout design of method 800 includes one or more structures of at least layout design 400, 600A, or 700A. In some embodiments, the layout design of the present application is in a file format for a graphic database system (GDSII).

[0274] In step 804 of method 800, the integrated circuit is fabricated based on the layout design. In some embodiments, step 804 of method 800 comprises fabricating at least one mask based on the layout design and fabricating the integrated circuit based on the at least one mask.

[0275] In operation 806, one or more parts of the conductive structures of the set of conductive structures are removed. In some embodiments, operation 806 comprises forming the set of conductive structures 520 of the integrated circuit 100, 200, 300A-300B, 400A-400B, 500, 600B, or 700B. In some embodiments, the cut feature layout structures 440a, 440b, ..., 440g, or 440h and the cut feature layout structures 442a, 442b, ..., 442i, or 442j identify the respective locations of the corresponding sections (not referenced) of the set of conductive structures 520 to be removed.

[0276] In some embodiments, the removed portions of the set of conductive structures 520 correspond to a cut region. In some embodiments, process 806 is referred to as a CMo (Cut-Metal 0) process. In some embodiments, process 806 is performed by a removal process. In some embodiments, the removal process comprises one or more etching processes suitable for removing a portion of the set of conductive structures 520. In some embodiments, the etching process of process 806 comprises identifying portions of the set of conductive structures 520 to be removed and etching the portions of the set of conductive structures 520 to be removed. In some embodiments, a mask is used to specify portions of the set of conductive structures 520 to be cut or removed. In some embodiments, the mask is a hard mask.In some embodiments, the mask is a soft mask. In some embodiments, the etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable methods, any combination thereof, or the like.

[0277] Fig. Figure 9 is a flowchart of a method 900 for generating a layout design of an integrated circuit according to some embodiments. It is understood that additional operations may occur before, during, and / or after the process described in Figure 900. Fig. The processes described in Figure 900 can be carried out, and some other processes are only briefly outlined herein. Other sequences of operations for Process 900 fall within the scope of this disclosure. In some embodiments, Process 900 is an embodiment of Operation 802 of Process 800. In some embodiments, Process 900 can be used to generate one or more layout structures of at least Layout Design 400, 600A, or 700A of an integrated circuit, such as the integrated circuit 100, 200, 300A-300B, 400A-400B, 500, 600B, or 700B.

[0278] In step 902 of method 900, a set of active area layout structures is created or arranged on a layout design. In some embodiments, the set of active area layout structures of method 900 contains at least parts of one or more layout structures of the set of active area layout structures 402. In some embodiments, the layout design of method 900 contains one or more layout structures of at least layout design 400, 600A, or 700A.

[0279] In step 904 of method 900, a set of busbar layout structures is generated or arranged on the layout design. In some embodiments, the set of busbar layout structures of method 900 includes at least parts of one or more layout structures of the set of busbar layout structures 404.

[0280] In step 906 of method 900, a first set of feature layout structures is generated or arranged on the layout design. In some embodiments, the first set of feature layout structures of method 900 includes at least parts of one or more layout structures from the set of feature layout structures 420, 430, 432, 610, 620, 630, 710, 720, or 730.

[0281] In step 908 of method 900, a second set of feature layout structures is generated or arranged on the layout design. In some embodiments, the second set of feature layout structures of method 900 includes at least parts of one or more layout structures of the set of feature layout structures 424.

[0282] In step 910 of method 900, a set of via layout structures is generated or arranged on the layout design. In some embodiments, the set of via layout structures of method 900 includes at least parts of one or more layout structures of the set of via layout structures 426.

[0283] In step 912 of method 900, a set of section feature layout structures is generated or arranged on the layout design. In some embodiments, the set of section feature layout structures of method 900 includes at least parts of one or more layout structures of the set of section feature layout structures 440 or 442.

[0284] Fig. Figure 10 is a functional flowchart of a process for manufacturing an IC device according to some embodiments. It should be understood that additional operations may occur before, during, and / or after the process described in the diagram. Fig. The processes described in section 10 can be carried out using process 1000, and some other processes are only briefly outlined here. Other sequences of operations for process 1000 fall within the scope of this disclosure.

[0285] In some embodiments, method 1000 is an embodiment of process 804 of method 800. In some embodiments, method 1000 can be used to manufacture or fabricate at least the integrated circuit 100, 200, 300A-300B, 400A-400B, 500, 600B or 700B or an integrated circuit with similar features to at least the layout design 400, 600A or 700A.

[0286] In step 1002 of process 1000, a first set of transistors is fabricated on a substrate or semiconductor wafer. In some embodiments, the first set of transistors of process 1000 comprises one or more NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, or N16, or one or more PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, or P16.

[0287] In some embodiments, the process comprises fabricating source and drain regions of the first set of transistors in a first well. In some embodiments, the first well contains p-type dopants. In some embodiments, the p-type dopants contain boron, aluminum, or other suitable p-type dopants. In some embodiments, the first well comprises an epilayer grown over a substrate. In some embodiments, the epilayer is doped by adding dopants during the epitaxy process. After the formation of the epilayer, in some embodiments, the epilayer is doped by ion implantation. In some embodiments, the first well is formed by doping the substrate. In some embodiments, the doping is performed by ion implantation. In some embodiments, the first well has a dopant concentration of 1 × 10⁻⁶ 12 atoms / cm² 3 up to 1 × 10 14atoms / cm² 3 .

[0288] In some embodiments, the first well comprises n-doping agents. In some embodiments, the n-doping agents contain phosphorus, arsenic, or other suitable n-doping agents. In some embodiments, the n-doping concentration is approximately 1 × 10 12 atoms / cm² 2 up to about 1 × 10 14 atoms / cm² 2 .

[0289] In some embodiments, the formation of the source / drain features involves removing a portion of the substrate to create recesses at the edge of spacers and performing a filling process by filling the recesses in the substrate. In some embodiments, the recesses are etched, for example, by wet etching or dry etching after a pad oxide layer or sacrificial oxide layer has been removed. In some embodiments, the etching process is performed to remove an upper surface portion of the active area adjacent to an isolation area, such as an STI area. In some embodiments, the filling process is performed by an epitaxial process (epi-process).In some embodiments, the recesses are filled by a growth process that occurs simultaneously with an etching process, where the growth rate of the growth process is greater than the etching rate. In other embodiments, the recesses are filled by a combination of growth and etching processes. For example, a layer of material is grown in the recess, and then the grown material is subjected to an etching process to remove some of the material. A subsequent growth process is then carried out on the etched material until a desired thickness of material is achieved in the recess. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate.In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first recess is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching any gate structure or spacers. In some embodiments, the etching process is performed by reactive ion etching (RIE), wet etching, or other suitable techniques. In some embodiments, a semiconductor material is deposited in the recesses to form the source / drain features. In some embodiments, an epi-process is performed to deposit the semiconductor material in the recesses.In some embodiments, the epi-process comprises a selective epitaxial growth (SEG) process, a continuous vapor deposition (CVD) process, molecular beam epitaxy (MBE), other suitable processes, and / or a combination thereof. The epi-process utilizes gaseous and / or liquid precursors that interact with a substrate composition. In some embodiments, the source / drain features comprise epitaxially grown silicon (epiSi), silicon carbide, or silicon germanium. Source / drain features of the IC device, which are associated with the gate structure, are in some cases doped or undoped in situ during the epi-process. If the source / drain features are undoped during the epi-process, they are, in some cases, doped during a subsequent process.The subsequent doping process is carried out by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, the source / drain features are subjected to further tempering processes after their formation and / or after the subsequent doping process.

[0290] In some embodiments, process 1002 further comprises forming a gate region of the first set of transistors. In some embodiments, the gate region is located between the drain region and the source region. In some embodiments, the gate region is located above the first well and the substrate. In some embodiments, the fabrication of the gate regions in process 1002 comprises performing one or more deposition processes to form one or more layers of dielectric material. In some embodiments, a deposition process comprises chemical vapor deposition (CVD), plasma-enhanced electrochemical vapor deposition (PECVD), atomic layer deposition (ALD), or another process suitable for depositing one or more layers of material. In some embodiments, the fabrication of the gate regions comprises performing one or more deposition processes to form one or more conductive layers of material.In some embodiments, the fabrication of the gate regions includes forming gate electrodes or dummy gate electrodes. In some embodiments, the fabrication of the gate regions includes depositing or growing at least one dielectric layer, for example, a gate dielectric. In some embodiments, the gate regions are formed using doped or undoped polycrystalline silicon (or polysilicon). In some embodiments, the gate regions contain a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0291] In step 1004 of process 1000, the wafer is thinned on the back side of the substrate. In some embodiments, step 1004 includes a thinning process performed on the back side of the semiconductor wafer or substrate. In some embodiments, the thinning process includes a grinding and polishing process (such as chemical-mechanical polishing (CMP)) or other suitable processes. In some embodiments, a wet etching process is performed after the thinning process to remove defects that have formed on the back side of the semiconductor wafer or substrate.

[0292] In step 1006 of method 1000, a set of busbars is deposited on the back side of the substrate, thereby forming the busbar set. In some embodiments, step 1006 comprises at least depositing a set of conductive areas on the back side of the integrated circuit, thereby forming a back-side busbar set. In some embodiments, the busbar set of method 1000 comprises at least parts of one or more of the busbar set 504.

[0293] In step 1008 of method 1000, a first set of conductive structures is deposited over the first set of transistors. In some embodiments, the first set of conductive structures of method 1000 comprises at least parts of one or more of the set of conductive structures 520, 530, 532, 610', 620', 630', 710', 720' or 730'.

[0294] In step 1010 of method 1000, a set of vias is produced. In some embodiments, step 1010 further comprises depositing the set of vias at least over the first set of conductive structures. In some embodiments, the set of vias of method 1000 comprises at least parts of one or more of the set of vias 526.

[0295] In step 1012 of method 1000, a second set of conductive structures is deposited at least above the first set of conductive structures or the set of vias. In some embodiments, the second set of conductive structures of method 1000 contains at least parts of one or more from the set of conductive structures 524.

[0296] In some embodiments, one or more of steps 1006, 1008, 1010, or 1012 of method 1000 comprise the use of a combination of photolithography and material removal processes to form openings in an insulating layer (not shown) over the substrate. In some embodiments, the photolithography process comprises structuring a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithography process comprises forming a hard mask, an antireflection structure, or another suitable photolithography structure. In some embodiments, the material removal process comprises a wet etching process, a dry etching process, an RIE process, laser drilling, or another suitable etching process. The openings are then filled with conductive material, such as copper, aluminum, titanium, nickel, tungsten, or another suitable conductive material.In some embodiments, the openings are filled by CVD, PVD, sputtering, ALD or another suitable forming process.

[0297] In some embodiments, at least one or more processes of method 1000 are performed by system 1200. Fig. 12. In some embodiments, at least one process, such as the process 1000 described above, is carried out wholly or partly by at least one manufacturing system, including the system 1200. One or more of the operations of process 1000 are carried out by the IC factory 1240 ( Fig. 12) is carried out to manufacture the IC device 1260. In some embodiments, one or more of the operations of the method 1000 are carried out by the manufacturing tools 1252 to manufacture the wafer 1242.

[0298] In some embodiments, one or more of the operations of method 800, 900, or 1000 are not performed. One or more of the operations of methods 800-900 are performed by a processor unit configured to execute instructions for fabricating an integrated circuit such as integrated circuit 100, 200, 300A-300B, 400A-400B, 500, 600B, or 700B. In some embodiments, one or more of the operations of methods 800-900 are performed using the same processor unit as is used in one or more other operations of methods 800-900. In some embodiments, one or more of the operations of methods 800-900 are performed using a different processor unit than the one used to perform one or more other operations of methods 800-900.

[0299] Fig. Figure 11 is a schematic view of a system 1100 for designing an IC layout and fabricating an IC circuit according to some embodiments. In some embodiments, the system 1100 creates or places one or more IC layout designs described herein. The system 1100 comprises a hardware processor 1102 and a non-volatile, computer-readable storage medium 1104 (for example, a memory 1104) encoded with, i.e., storing, the computer program code 1106, i.e., a set of executable instructions 1106. The computer-readable storage medium 1104 is configured for connection to fabrication machines for manufacturing the integrated circuit. The processor 1102 is electrically coupled to the computer-readable storage medium 1104 via a bus 1108. The processor 1102 is also electrically coupled to an I / O interface 1110 via a bus 1108.A network interface 1112 is also electrically connected to the processor 1102 via the bus 1108. The network interface 1112 is connected to a network 1114, so that the processor 1102 and the computer-readable storage medium 1104 are able to connect to external elements via the network 1114. The processor 1102 is configured to execute the computer program code 1106, which is encoded in the computer-readable storage medium 1104, in order to enable the system 1100 to perform some or all of the operations as described with reference to procedure 900.

[0300] In some embodiments, the 1102 processor is a central processing unit (CPU), a multiprocessor, a distributed processor system, an application-specific integrated circuit (ASIC) and / or a suitable processor unit.

[0301] In some embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1104 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 1104 comprises a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disc (DVD).

[0302] In some embodiments, the storage medium 1104 stores the computer program code 1106, which is configured to cause the system 1100 to execute the method 900. In some embodiments, the storage medium 1104 further stores information required for the execution of the method 900, as well as information generated during the execution of the method 900, such as the layout design 1116, the user interface 1118, and the manufacturing unit 1120, and / or a set of executable instructions for carrying out the operations of the method 900. In some embodiments, the layout design 1116 comprises one or more layout structures of at least layout design 400, 600A, or 700A.

[0303] In some embodiments, the storage medium 1104 stores instructions (for example, the computer program code 1106) for connecting to manufacturing machines. The instructions (for example, the computer program code 1106) enable the processor 1102 to generate manufacturing instructions that can be read by the manufacturing machines to effectively implement the method 900 during a manufacturing process.

[0304] The System 1100 includes an I / O interface 1110. The I / O interface 1110 is connected to an external circuit. In some embodiments, the I / O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to the processor 1102.

[0305] System 1100 further includes a network interface 1112, which is connected to the processor 1102. The network interface 1112 enables System 1100 to communicate with the network 1114, to which one or more other computer systems are connected. The network interface 1112 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-1194. In some embodiments, Method 900 is implemented in two or more Systems 1100, and information such as layout designs and user interfaces is exchanged between different Systems 1100 via the network 1114.

[0306] The System 1100 is configured to receive layout design information via the I / O interface 1110 or the network interface 1112. This information is transmitted via the bus 1108 to the processor 1102 to determine a layout design for the manufacture of the integrated circuit 100, 200, 300A-300B, 400A-400B, 500, 600B, or 700B. The layout design is then stored as layout design 1116 on the computer-readable medium 1104. The System 1100 is also configured to receive user interface information via the I / O interface 1110 or the network interface 1112. This information is stored as user interface 1118 on the computer-readable medium 1104. System 1100 is configured to receive information regarding a manufacturing unit via the I / O interface 1110 or the network interface 1112.The information is stored as manufacturing unit 1120 in the computer-readable medium 1104. In some embodiments, manufacturing unit 1120 contains manufacturing information that is used by system 1100. In some embodiments, manufacturing unit 1120 corresponds to mask manufacturing 1234. Fig. 12.

[0307] In some embodiments, Method 900 is implemented as a standalone software application for execution by a processor. In some embodiments, Method 900 is implemented as a software application that is part of another software application. In some embodiments, Method 900 is implemented as a plug-in for a software application. In some embodiments, Method 900 is implemented as a software application that is part of an EDA tool. In some embodiments, Method 900 is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit. In some embodiments, the layout is stored on a non-volatile, computer-readable medium. In some embodiments, the layout is generated using a tool such as VIRTUOSO® from CADENCE DESIGN SYSTEMS, Inc.or another suitable layout generation tool. In some embodiments, the layout is generated based on a netlist created based on the schematic design. In some embodiments, the method 900 is implemented by a manufacturing apparatus to produce an integrated circuit using a set of masks produced based on one or more layout designs generated by the system 1100. In some embodiments, the system 1100 is a manufacturing apparatus configured to produce an integrated circuit using a set of masks produced based on one or more layout designs of the present disclosure. In some embodiments, the system 1100 generates from . Fig. Eleven layout designs of an integrated circuit that are smaller than other approaches. In some embodiments, the system generates 1100 of Fig. 11 layout designs of an integrated circuit structure that take up less space and provide better routing resources than other approaches.

[0308] Fig. Figure 12 is a block diagram of an IC manufacturing system 1200 and an associated IC manufacturing process according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an integrated semiconductor circuit is manufactured using the manufacturing system 1200.

[0309] In Fig. 12 The IC manufacturing system 1200 (hereinafter referred to as "the system 1200") comprises units, such as a design house 1220, a mask house 1230, and an IC manufacturer / factory (fab) 1240, which interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1260. The units in the system 1200 are interconnected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is several different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each unit interacts with one or more of the other units, providing and / or receiving services to one or more of the other units.In some embodiments, one or more of the units—Design House 1220, Mask House 1230, and IC Fab 1240—are owned by a single larger company. In other embodiments, one or more of the components of Design House 1220, Mask House 1230, and IC Fab 1240 exist in a common facility and share resources.

[0310] The design house (or design team) 1220 creates an IC design layout 1222. The IC design layout 1222 contains various geometric structures designed for an IC device 1260. The geometric structures correspond to the structures of the metal, oxide, or semiconductor layers from which various components of the IC device 1260 to be manufactured are formed. The various layers combine to form various IC features. For example, part of the IC design layout 1222 includes various IC features, such as an active area, a gate electrode, a source electrode, and a drain electrode, metal traces or vias of an interconnect connection, and openings for bonding pads, to be formed in a semiconductor substrate (for example, a silicon wafer) and various material layers arranged on the semiconductor substrate.Design House 1220 implements a suitable design procedure to create the IC design layout 1222. The design procedure includes one or more of the logic design, physical design, or place-and-route methods. The IC design layout 1222 is represented in one or more files containing information about the geometric structures. For example, the IC design layout 1222 can be represented in a GDSII or DFII file format.

[0311] The mask house 1230 comprises a data preparation unit 1232 and a mask manufacturing unit 1234. The mask house 1230 uses the IC design layout 1222 to produce one or more masks 1245, which are used to manufacture the various layers of the IC device 1260 according to the IC design layout 1222. The mask house 1230 performs a mask data preparation unit 1232, in which the IC design layout 1222 is translated into a Representative Data File (RDF). The mask data preparation unit 1232 delivers the RDF to the mask manufacturing unit 1234. The mask manufacturing unit 1234 includes a mask writer. The mask writer converts the RDF into an image on a substrate, for example a mask (a reticle) 1245 or a semiconductor wafer 1242. The design layout 1222 is modified by the mask data preparation 1232 to meet certain properties of the mask writer and / or requirements of IC manufacturing 1240. Fig. Figure 12 shows the mask data preparation 1232 and the mask production 1234 as separate elements. In some embodiments, the mask data preparation 1232 and the mask production 1234 can be referred to together as a mask data preparation.

[0312] In some embodiments, the mask data preparation 1232 includes OPC (Optical Proximity Correction), which uses lithographic enhancement techniques to compensate for imaging errors that may arise, for example, from diffraction, interference, other process effects, and the like. The OPC adapts the IC design layout 1222. In some embodiments, the mask data preparation 1232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shifted masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technique (ILT) is also used, in which the OPC is treated as an inverse imaging problem.

[0313] In some embodiments, the mask data preparation 1232 includes a Mask Rule Checker (MRC) that checks the IC design layout, which has undergone processes in the OPC, against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient leeway to accommodate variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 1234, thereby reversing some of the modifications made by the OPC to satisfy the mask creation rules.

[0314] In some embodiments, the mask data preparation 1232 includes lithography process checking (LPC), which simulates the processing performed by the IC fab 1240 to manufacture the IC fixture 1260. The LPC simulates this processing based on the IC design layout 1222 to generate a simulated manufactured fixture, such as the IC fixture 1260. The processing parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters associated with the tooling used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated, fabricated device has been created by the LPC, the OPC and / or the MRC are repeated to further refine the IC design layout 1222 if the simulated device is not close enough to the design rules.

[0315] It should be understood that the above description of mask data preparation 1232 is simplified for the sake of clarity. In some embodiments, data preparation 1232 includes additional functions, such as a logical operation (LOP), to modify the IC design layout according to the manufacturing rules. Furthermore, the processes applied to the IC design layout 1222 during data preparation 1232 can be executed in various other sequences.

[0316] Following mask data preparation 1232 and during mask fabrication 1234, a mask 1245 or a group of masks 1245 is produced based on the modified IC design layout 1222. In some embodiments, mask fabrication 1234 includes performing one or more lithographic exposures based on the IC design 1222. In some embodiments, an electron beam (E-beam) or a mechanism with multiple E-beams is used to form a structure on a mask (photomask or reticulum) 1245 based on the modified IC design layout 1222. The mask 1245 can be formed by various technologies. In some embodiments, the mask 1245 is formed by binary technology. In some embodiments, a mask structure comprises opaque and transparent regions.A beam of radiation, such as an ultraviolet (UV) beam, used to illuminate the image-sensitive material layer (e.g., a photoresist) deposited on a wafer, is blocked by the opaque region and penetrates the transparent regions. In one example, a binary version of the Mask 1245 contains a transparent substrate (e.g., molten quartz) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, the Mask 1245 is formed using a phase-shifting technology. In the Phase-Shift Mask (PSM) version of the Mask 1245, various features in the structure formed on the mask are designed to exhibit a suitable phase difference to improve resolution and image quality.In various examples, the phase-shift mask can be a weakened PSM or an alternating PSM. The mask(s) produced by mask fabrication 1234 are used in various processes. For example, such a mask is used in an ion implantation process to create different doped regions in the semiconductor wafer, in an etching process to create different etched regions in the semiconductor wafer, and / or in other suitable processes.

[0317] The IC-Fab 1240 is an IC manufacturing unit comprising one or more manufacturing facilities for the production of various IC products. In some embodiments, the IC-Fab 1240 is a semiconductor foundry. For example, one manufacturing facility may be provided for the front-end manufacturing of various IC products (front-end-of-line manufacturing (FEOL)), while a second manufacturing facility provides the back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line manufacturing (BEOL)), and a third manufacturing facility provides other services for the foundry unit.

[0318] The IC-Fab 1240 comprises wafer fabrication tools 1252 (hereinafter referred to as fabrication tools 1252) configured to perform various fabrication operations on the semiconductor wafer 1242, such that the IC device 1260 is fabricated according to the mask(s), for example, the mask 1245. In various embodiments, the fabrication tools 1252 comprise one or more wafer steppers, an ion implanter, a photoresist coater, a process chamber, for example, a CVD chamber or an LPCVD furnace, a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as described herein.

[0319] IC Factory 1240 uses the mask(s) 1245 produced by Mask Factory 1230 to manufacture IC Device 1260. Thus, IC Factory 1240 uses, at least indirectly, the IC Design Layout 1222 to manufacture IC Device 1260. In some embodiments, IC Factory 1240 produces a semiconductor wafer 1242 using mask(s) 1245 to form IC Device 1260. In some embodiments, IC manufacturing includes performing one or more lithographic exposures based, at least indirectly, on IC Design 1222. The semiconductor wafer 1242 comprises a silicon substrate or other suitable substrate with material layers formed on it. The semiconductor wafer 1242 further comprises one or more different doped regions, dielectric features, multilevel interconnects and the like (which are formed in subsequent manufacturing steps).

[0320] System 1200 is depicted as showing the Design House 1220, the Mask House 1230, or the IC Fab 1240 as separate components or units. However, it should be understood that one or more of the components of the Design House 1220, the Mask House 1230, or the IC Fab 1240 are part of the same component or unit.

[0321] Details of an IC manufacturing system (for example, the System 1200 in Fig. 12) and an associated IC manufacturing process can be found, for example, in US Patent 9,256,709, issued on February 9, 2016, US Disclosure 2015 O 278,429, published on October 1, 2015, US Disclosure 2010 O 040,838, published on February 6, 2014, and US Disclosure 7,260,442, issued on August 21, 2007.

[0322] One aspect of this description concerns an integrated circuit (IC). In some embodiments, the IC comprises: a set of busbars on the back side of a substrate, extending in a first direction. In some embodiments, each busbar is separated from an adjacent busbar in a second direction, different from the first direction. In some embodiments, the IC further comprises: a first flip-flop, which has a first set of conductive structures extending in the first direction and arranged on a first metal layer. In some embodiments, the IC further comprises a second flip-flop, which is adjacent to the first flip-flop at a first boundary.In some embodiments, the second flip-flop has a second set of conductive structures extending in the first direction and arranged on the first metal layer, the second set of conductive structures being separated from the first set of conductive structures in the second direction. In some embodiments, the IC further has a third flip-flop adjacent to the second flip-flop at a second boundary. In some embodiments, the third flip-flop has a third set of conductive structures extending in the first direction, arranged on the first metal layer, and separated from the first and second sets of conductive structures in the second direction. In some embodiments, the first, second, and third flip-flops are located on a front side of the substrate that is opposite the back side.In some embodiments, the second set of conductive structures is offset in the second direction from the first boundary and the second boundary.

[0323] Another aspect of this description concerns an integrated circuit (IC). In some embodiments, the IC comprises: a set of busbars on the back side of a substrate, extending in a first direction. In some embodiments, each busbar is separated from an adjacent busbar in a second direction, different from the first direction. In some embodiments, the IC further comprises: a first flip-flop having a first region. In some embodiments, the first region has a first set of conductive structures extending in the first direction and lying on a first plane. In some embodiments, the IC further comprises: a second flip-flop having a second region, the second region being adjacent to the first region at a first boundary.In some embodiments, the second flip-flop has a second set of conductive structures extending in the first direction and lying on the first plane. In some embodiments, the second set of conductive structures is separated from the first set of conductive structures in the second direction. In some embodiments, the IC further has a third flip-flop having a third region, wherein the third region is adjacent to the second region along a second boundary. In some embodiments, the third flip-flop has a third set of conductive structures extending in the first direction, lying on the first plane, and separated from the first and second sets of conductive structures in the second direction.In some embodiments, the first, second, and third flip-flops are located on a front side of the substrate that is opposite the back side. In some embodiments, the first set of conductive structures and the second set of conductive structures are offset in the second direction from the first boundary.

[0324] Another aspect of this description concerns a method for fabricating an IC. In some embodiments, the method comprises: depositing a set of busbars on the back side of a substrate, wherein the set of busbars extends in a first direction and each busbar is separated from an adjacent busbar in a second direction, which is different from the first direction. In some embodiments, the method further comprises: forming a first flip-flop comprising a first set of transistors in a first region. In some embodiments, forming the first flip-flop comprises depositing a first set of conductive structures over the first set of transistors, wherein the first set of conductive structures extends in the first direction and lies on a first plane.In some embodiments, the method further comprises: forming a second flip-flop comprising a second set of transistors in a second region, wherein the second region adjoins the first region at a first boundary. In some embodiments, forming the second flip-flop comprises depositing a second set of conductive structures over the second set of transistors, wherein the second set of conductive structures extends in the first direction, is arranged on the first plane, and is separated from the first set of conductive structures in the second direction. In some embodiments, the method further comprises forming a third flip-flop comprising a third set of transistors in a third region, wherein the third region adjoins the second region at a second boundary.In some embodiments, forming the third flip-flop involves depositing a third set of conductive structures over the third set of transistors, wherein the third set of conductive structures extends in the first direction, is arranged on the first plane, and is separated in the second direction from the first and second sets of conductive structures. In some embodiments, the first, second, and third flip-flops are located on a front side of the substrate that is opposite the back side. In some embodiments, the first and second sets of conductive structures are offset in the second direction from the first boundary.

Claims

[1] Including an integrated circuit: a set of busbars (404, 504, 604) on a rear side of a substrate extending in a first direction, each busbar being separated from an adjacent busbar in a second direction different from the first direction; comprising a first flip-flop (102, 202) comprising a first set of conductive structures (520) extending in the first direction and arranged on a first metal layer; a second flip-flop (104, 204) adjacent to the first flip-flop (102, 202) at a first boundary (501a), wherein the second flip-flop (104, 204) has a second set of conductive structures (530) extending in the first direction and arranged on the first metal layer, wherein the second set of conductive structures is separate in the second direction from the first set of conductive structures; and a third flip-flop (106, 206) adjacent to the second flip-flop (104, 204) at a second boundary (501b), wherein the third flip-flop (106, 206) has a third set of conductive structures (532) extending in the first direction, arranged on the first metal layer and separated in the second direction from the first set of conductive structures and the second set of conductive structures, wherein the first flip-flop (102, 202), the second flip-flop (104, 204) and the third flip-flop (106, 206) are located on a front side of the substrate that is opposite the back side, where the second set of conductive structures is offset in the second direction from the first boundary and the second boundary. [2] Integrated circuit according to claim 1, wherein the first flip-flop (102, 202) further comprises a first inverter (310) having a first input pin, wherein at least one first conductive structure of the first set of conductive structures corresponds to the first input pin of the first inverter (310), wherein the second flip-flop (104, 204) further comprises a second inverter (312) which has a second input pin (130, 230), wherein at least one second conductive structure of the second set of conductive structures corresponds to the second input pin of the second inverter, wherein the third flip-flop (106, 206) further comprises a third inverter (314) which has a third input pin, wherein at least one third conductive structure of the third set of conductive structures corresponds to the third input pin of the third inverter (314). [3] Integrated circuit according to claim 2, further comprising: a fourth conductive structure on a second metal layer above the first metal layer, extending in the second direction, overlapping the first boundary and the second boundary, and electrically coupling the first input pin, the second input pin, and the third input pin, wherein the fourth conductive structure is configured to receive a first clock signal. [4] Integrated circuit according to claim 2, wherein the first flip-flop (102, 202) further comprises a fourth inverter having a first output pin, wherein at least one fourth conductive structure of the first set of conductive structures corresponds to the first output pin of the fourth inverter, wherein the second flip-flop (104, 204) further comprises a fifth inverter having a second output pin, wherein at least one fifth conductive structure of the second set of conductive structures corresponds to the second output pin of the fifth inverter; and wherein the third flip-flop (106, 206) further comprises a sixth inverter having a third output pin, wherein at least a sixth conductive structure of the third set of conductive structures corresponds to the third output pin of the sixth inverter. [5] Integrated circuit according to claim 4, further comprising: a seventh conductive structure on a second metal layer above the first metal layer, extending in the second direction, overlapping the first boundary and the second boundary, and electrically coupling the first output pin, the second output pin, and the third output pin, wherein the fourth inverter, the fifth inverter, and the sixth inverter are each configured to output a clock signal on the seventh conductive structure. [6] Integrated circuit according to any one of claims 2 to 5, where the first inverter (310) is coupled to the fourth inverter, where the second inverter (312) is coupled to the fifth inverter, where the third inverter (314) is coupled with the sixth inverter. [7] Integrated circuit according to any one of the preceding claims, where the first set of conductive structures is offset in the second direction from the first boundary, where the third set of conductive structures is offset from the second boundary in the second direction. [8] Integrated circuit according to claim 1, wherein the first flip-flop (102, 202) further comprises a fourth set of conductive structures extending in the second direction, overlapping the first set of conductive structures and arranged on a second metal layer that is different from the first metal layer, wherein the second flip-flop (104, 204) further comprises a fifth set of conductive structures extending in the second direction, overlapping the second set of conductive structures and arranged on the second metal layer, wherein the third flip-flop (106, 206) further comprises a sixth set of conductive structures extending in the second direction, overlapping the third set of conductive structures and arranged on the second metal layer. [9] Integrated circuit according to claim 8, wherein the first flip-flop (102, 202) further features a first set of vias between the first set of conductive structures and the fourth set of conductive structures, wherein the second flip-flop (104, 204) further features a second set of vias between the second set of conductive structures and the fifth set of conductive structures, wherein the third flip-flop (106, 206) further features a third set of vias between the third set of conductive structures and the sixth set of conductive structures. [10] Including an integrated circuit: a first busbar on the back side of a substrate, extending in a first direction; a first flip-flop (102, 202) that is coupled to at least the first power rail and has a first region, wherein the first region has: - a first inverter (310) coupled to the first busbar; and - a first input pin (130, 230) that is coupled to the first inverter (310); a second flip-flop (104, 204) that is coupled at least to the first power rail and has a second area, wherein the second area is adjacent to the first area at a first boundary and has: - a second inverter (312) coupled to the first busbar; and - a second input pin (130, 230) that is coupled to the second inverter, wherein the first flip-flop (102, 202) and the second flip-flop (104, 204) are located on a front side of the substrate that is opposite the back side, wherein the first input pin (130, 230) and the second input pin (130, 230) are offset from the first boundary in a second direction which is different from the first direction. [11] Integrated circuit according to claim 10, wherein the first inverter (310) comprises: comprising a first transistor and a first gate, wherein the first gate extends in the second direction; comprising a second transistor and a second gate, wherein the second gate extends in the second direction and is coupled to the first gate; and a first through-connection between the first input pin and the first gate or the second gate, where the first input pin is electrically coupled to the first gate or the second gate via the first via. [12] Integrated circuit according to claim 11, wherein the second inverter comprises: comprising a third transistor and a third gate, the third gate extending in the second direction; comprising a fourth transistor and a fourth gate, wherein the fourth gate extends in the second direction and is coupled to the third gate; and a second via between the second input pin and the third gate or the fourth gate, the second input pin is electrically coupled to the third gate or the fourth gate via the second via. [13] Integrated circuit according to claim 12, further comprising: a set of active regions in the substrate extending in the first direction and lying on a first plane and above the first busbar, wherein each active region is separated in the second direction from an adjacent active region in the set of active regions. [14] Integrated circuit according to claim 13, further comprising: a first via between the set of active areas and the first busbar, wherein the first via electrically couples the first busbar and the set of active areas. [15] Integrated circuit according to any one of claims 10 to 14, wherein the first area further comprises a first conductive structure extending in the second direction and lying on a first plane, wherein the first inverter (310) has a first transistor, wherein the first transistor has a first drain region, wherein the second inverter (312) has a second transistor, wherein the second transistor has a second drain region; wherein the first conductive structure electrically couples the first drain area and the second drain area. [16] Integrated circuit according to claim 14, wherein the first region further comprises a first set of conductive structures extending in the first direction, overlapping the first conductive structure and lying on a second plane that is different from the first plane, wherein the second area further comprises a second set of conductive structures extending in the first direction, lying on the second plane and separated in the second direction from the first set of conductive structures; where the first set of conductive structures and the second set of conductive structures are offset in the second direction from the first boundary. [17] Integrated circuit according to claim 16, wherein the first region further comprises a third set of conductive structures extending in the second direction, overlapping the first set of conductive structures and lying on a third plane that is different from the first plane and the second plane, wherein the second area further includes a fourth set of conductive structures that extends in the second direction, overlaps the second set of conductive structures and lies on the third level. [18] Integrated circuit according to claim 17, wherein the first area further features a first set of vias between the first set of conductive structures and the third set of conductive structures, the second area further features a second set of vias between the second set of conductive structures and the fourth set of conductive structures. [19] Integrated circuit according to claim 16, wherein the first input pin has a first width in the second direction, wherein the second input pin has the first width in the second direction; wherein at least one first conductive structure of the first set of conductive structures has a second width in the second direction that is different from the first width, wherein at least one first conductive structure of the second set of conductive structures has a third width in the second direction that is different from the first width. [20] Method for manufacturing an integrated circuit, comprising: Fabricating a first set of transistors in a front face of a wafer, thereby forming a first flip-flop (102, 202); Depositing a first set of conductive structures (520) over the first set of transistors, wherein the first set of conductive structures extends in a first direction and is arranged on a first plane; Performing wafer dilution on the back side of the wafer that is opposite the front side of the wafer; Creating an initial set of vias on the back side of the wafer; and Deposition of a set of busbars (404, 504, 604) at least on the back side of the wafer, wherein the set of busbars (404, 504, 604) extends in the first direction, wherein each busbar is separated from an adjacent busbar in a second direction which is different from the first direction, wherein the first set of conductive structures is separated in the second direction from a center of a first busbar of the set of busbars (404, 504, 604).

Images