Semiconductor device

Abstract

Semiconductor device (100), comprising: a first semiconductor layer (1); a second semiconductor layer (2) arranged on a front surface of the first semiconductor layer (1) and having a conductivity type different from that of the first semiconductor layer (1); a buffer layer (5) arranged on a front surface of the second semiconductor layer (2) and having at least one opening in plan view; and an electrode (3) arranged above the second semiconductor layer (2) and the buffer layer (5) and through which at least one opening is in contact with the second semiconductor layer (2), wherein the buffer layer (5) has a higher Vickers hardness than the electrode (3), a width w of each of the at least one opening w < W th fulfilled, where s is a thickness of the buffer layer (5), t is a thickness of the electrode (3) and W th = 2 × (s × t - s2 ) 0,5 applies, and whereby the electrode (3) in an area where at least one opening is not in contact with the first semiconductor layer (1).

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present disclosure relates to semiconductor devices. Description of the background technology

[0002] In a semiconductor device, a semiconductor layer may be damaged when an external wiring used for connection to an external circuit is connected to an electrode.

[0003] For example, damage to the semiconductor layer causes a problem in a diode, as described below.

[0004] An example of the performance required for the diode is reducing recovery loss. There are various methods for reducing recovery loss, including a method for reducing the impurity concentration of an anode layer, a method for reducing the thickness of the semiconductor layer, and a method for reducing the lifetime of carriers in the semiconductor layer. Of these methods, the method for reducing the impurity concentration of the anode layer is a method for reducing the density of carriers in the semiconductor layer in an on-state to reduce the recovery current during switching, thereby reducing loss.

[0005] In the diode, a breakdown voltage is held by a depletion layer that propagates in the semiconductor layer of a PN junction in a sustained breakdown voltage state or in a reverse bias state, such as in recovery mode. The depletion layer propagates predominantly toward a drift layer, but can also propagate toward the anode layer if the anode layer has a lower impurity concentration to reduce recovery loss. Consequently, the breakdown voltage is reduced when the anode layer is thin.

[0006] The effective thickness of the anode layer can be locally reduced due to damage such as scratches, dents, and even cracks in the anode layer. The concentration and thickness of the anode layer are usually designed to prevent breakdown due to the spreading of the depletion layer to the anode electrode. However, if the anode layer has an extremely thin portion compared to the designed thickness, the depletion layer will reach the anode electrode, causing a problem of reduced breakdown voltage or device breakdown due to difficulty in maintaining the breakdown voltage.

[0007] JP 2014 - 29 975 A discloses, as a structure for preventing damage to a semiconductor layer when an external wiring is connected to an electrode, a structure in which an insulating layer is disposed immediately below a region where the external wiring is connected to the electrode to separate, in plan view, the region where the external wiring and the electrode are connected to each other and a region where the electrode and the semiconductor layer are in contact with each other.

[0008] However, the structure in which the region where the external wiring and the electrode are connected to each other and the region where the electrode and the semiconductor layer are in contact with each other are separated in plan view as disclosed in JP 2014 - 29 975 A causes a problem in that a wiring resistance corresponding to the distance from the external wiring to the semiconductor layer is generated, so that a loss in an on-state increases.

[0009] One cause of damage to the semiconductor layer is a foreign object on or inside the anode electrode. If the foreign object is located directly below the area where the external wiring is connected, the foreign object will be pushed or pressed into the anode electrode when the external wiring is connected. If the pushed foreign object reaches the semiconductor layer, the semiconductor layer will be damaged.

[0010] It is required to prevent such damage to the semiconductor layer caused by the foreign matter and to suppress resistance between the external wiring and the semiconductor layer compared with that in JP 2014 - 29 975 A.

[0011] Further semiconductor devices are known from JP 2002 - 319 685 A, JP H10 - 335 679 A, ​​JP 2003 - 188 391 A and US 2004 / 0 009 638 A1. SUMMARY

[0012] It is an object of the present disclosure to provide a semiconductor device that can suppress a resistance between an external wiring and a semiconductor layer and suppress a frequency of damage to the semiconductor layer caused by a foreign matter at a connection of the external wiring.

[0013] This problem is solved by the features of the independent claims. The subclaims contain advantageous embodiments of the invention.

[0014] A semiconductor device according to a first aspect of the present disclosure includes: a first semiconductor layer; a second semiconductor layer disposed on a front surface of the first semiconductor layer and having a different conductivity type from the first semiconductor layer; a buffer layer disposed on a front surface of the second semiconductor layer and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer and in contact with the second semiconductor layer through the at least one opening. The buffer layer has a higher Vickers hardness than the electrode. The width w of each of the at least one opening satisfies w < W th, where its thickness is the buffer layer, t is a thickness of the electrode and W th = 2 × (s × t - s 2 ) 0,5 applies.

[0015] Since the buffer layer is included, which is arranged on the front surface of the second semiconductor layer and has at least one opening in plan view, resistance between the external wiring and the semiconductor layer can be suppressed. Since the width w of each of the at least one opening w < W th In addition, if the requirements are met, the frequency of damage to the semiconductor layer caused by the foreign matter during connection of the external wiring can be suppressed.

[0016] A semiconductor device according to a second aspect of the present disclosure includes: a first semiconductor layer; a second semiconductor layer disposed on a front surface of the first semiconductor layer and having a different conductivity type from the first semiconductor layer; a conductive buffer layer at least selectively disposed on a front surface of the second semiconductor layer; and an electrode disposed on a front surface of the buffer layer. The buffer layer has a higher Vickers hardness than the electrode.

[0017] Because the buffer layer is conductive, resistance between the external wiring and the semiconductor layer can be suppressed. Furthermore, because the buffer layer has a higher Vickers hardness than the electrode, the frequency of damage to the semiconductor layer caused by foreign matter during connection of the external wiring can be suppressed.

[0018] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1; Fig. 2 is a plan view illustrating the shape of a buffer layer of the semiconductor device according to Embodiment 1; Fig. 3 is a cross-sectional view of the semiconductor device according to Embodiment 1; Fig. 4 is a plan view illustrating the shape of a buffer layer of a modification of the semiconductor device according to Embodiment 1; Fig. 5 is a plan view illustrating the shape of a buffer layer of a modification of the semiconductor device according to Embodiment 1; Fig. 6 is a plan view illustrating the shape of a buffer layer of a modification of the semiconductor device according to Embodiment 1; Fig. 7 is a cross-sectional view of a semiconductor device according to an aspect of Embodiment 2; and Fig. 8 is a plan view illustrating the shape of a buffer layer of the semiconductor device according to an aspect of Embodiment 2. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In describing embodiments of the present disclosure, N-type and P-type conductivity types are interchangeable. If N-type and P-type are interchanged, notations depending on the conductivity types in the embodiments should be read differently; for example, an anode electrode should be read as a cathode electrode, and an anode layer should be read as a cathode layer. <A. Ausführungsform 1><A-1. Konfiguration und Betrieb>

[0020] Fig. 1 is a cross-sectional view of a semiconductor device 100 according to Embodiment 1.

[0021] The semiconductor device 100 comprises a drift layer 1 as a first semiconductor layer, an anode layer 2 as a second semiconductor layer, an anode electrode 3 as an electrode, and a buffer layer 5. A Fig. 1 is a wiring for establishing electrical connection between the semiconductor device 100 and the external environment.

[0022] Drift layer 1 is an N-type semiconductor layer. Anode layer 2 is a semiconductor layer with a different conductivity type than drift layer 1, i.e., a P-type.

[0023] The semiconductor device 100 is, for example, a diode and is used particularly as a freewheeling diode (FWD), which is one of the devices forming a power module. If the semiconductor device 100 is the diode, the semiconductor device 100 further includes an N-type cathode layer and a cathode electrode arranged in Fig. 1. In this case, the cathode layer is disposed on a back surface of the drift layer 1, which is opposite to a surface on which the anode layer 2 is disposed, and the cathode electrode is disposed on a back surface of the cathode layer. However, the semiconductor device 100 does not have to be the diode and may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). The semiconductor device 100 may also be a module or device that includes the diode, MOSFET, or IGBT as part thereof.

[0024] The drift layer 1 and the anode layer 2 are, for example, silicon semiconductors.

[0025] The anode layer 2 is arranged on the front surface of the drift layer 1. The buffer layer 5 is selectively arranged on the front surface of the anode layer 2 and has a mesh shape in plan view. That is, the buffer layer 5 has openings in plan view.

[0026] An area consisting of the openings of the buffer layer 5 and the buffer layer 5 in plan view occupies the entire front surface of the drift layer 1, as shown in Fig. 2. The influence of position variations when connecting the external wiring 4 can thereby be suppressed.

[0027] The anode electrode 3 is arranged on front sides of the anode layer 2 and the buffer layer 5 and is in contact with the anode layer 2 through the openings of the buffer layer 5.

[0028] The buffer layer 5 has a higher Vickers hardness than the anode electrode 3. For example, aluminum with a Vickers hardness of 0.44 GPa or copper with a Vickers hardness of 0.80 GPa is used as the material for the anode electrode 3. The buffer layer 5 is an insulator containing, for example, silicon oxide or silicon nitride, with a higher Vickers hardness than aluminum or copper.

[0029] Since the buffer layer 5 has a higher Vickers hardness than the anode electrode 3, the frequency or degree of penetration of a foreign matter located inside the anode electrode 3 and adhering to an upper surface of the anode electrode 3 into the semiconductor device 100 beyond the buffer layer 5, that is, into the anode layer 2 beyond the buffer layer 5, can be suppressed compared to a case without the buffer layer 5. The frequency of damage to the anode layer 2 can thereby be suppressed.

[0030] Since the buffer layer 5 has the mesh shape in plan view and has the openings in plan view, a resistance between the external wiring 4 and the anode layer 2 can be suppressed to reduce the loss upon energization even in a case where the buffer layer 5 is the insulator such as silicon oxide and silicon nitride.

[0031] The openings of the mesh of the buffer layer 5 are provided such that a width w of each of the openings of the mesh w < W th fulfilled, where W th = 2 × (s × t - s 2 ) 0,5 Here, s is the thickness of the buffer layer 5 and t is the thickness of the anode electrode 3, as in Fig. 3. The thickness of the anode electrode 3 refers to the distance from an interface between the anode electrode 3 and the anode layer 2 to the front surface of the anode layer 3.

[0032] The condition that w < W this obtained from a condition that in a case where a spherical foreign body 7 with a diameter t or larger is pressed from the anode electrode 3 toward the anode layer 2 when the external wiring 4 is connected, the foreign body 7 does not reach the anode layer 2 by being stopped by the buffer layer 5. It is assumed that the buffer layer 5 and the anode layer 2 are not deformed. A spherical foreign body with a diameter smaller than t does not reach the anode layer 2 even if it is pressed from the anode electrode 3 toward the anode layer 2 when the external wiring 4 is connected, since the thickness of the anode electrode 3 is t. The width w of each of the openings of the mesh of the buffer layer 5 satisfies w < W as described above. th, so that, compared with the case without the buffer layer 5, a frequency or degree of penetration of the foreign matter located within the anode electrode 3 and adhering to the upper surface of the anode electrode 3 into the semiconductor device 100 beyond the buffer layer 5, that is, into the anode layer 2 beyond the buffer layer 5, can be suppressed. The frequency of damage to the anode layer 2 can thereby be suppressed.

[0033] For example, if the anode electrode 3 has a thickness t of 4 µm and the buffer layer 5 has a thickness s of 1 µm, a foreign body with a diameter greater than 4 µm may damage the anode layer 2 by being pushed through the external wiring 4, assuming that the foreign body is spherical. Damage to the anode layer 2 caused by such a foreign body can be prevented if the width w of each of the openings of the mesh of the buffer layer 5 is w < W. th ≈ 3.5 µm is met.

[0034] In summary, the semiconductor device 100 includes the buffer layer 5, and the width w of each of the openings of the buffer layer 5 satisfies w < W th, so that resistance between the external wiring 4 and the anode layer 2 can be suppressed, and the frequency of damage to the anode layer 2 caused by the foreign matter when the wiring is connected can be suppressed. By suppressing the frequency of damage to the anode layer 2, the frequency of a reduction in the breakdown voltage and the occurrence of breakdown of the semiconductor device 100 caused by variations in an effective depth of the anode layer 2 can be suppressed.

[0035] With the structure of the semiconductor device 100 of the present disclosure, the resistance between the external wiring 4 and the anode layer 2 can be suppressed, and the frequency of damage to the anode layer 2 caused by the foreign matter can be suppressed not only when the external wiring 4 is connected to the anode electrode 3, but also when the external wiring 4 and the anode electrode 3 are only in contact with each other such as in a case where a test terminal is brought into contact. <A-2. Effekte>

[0036] The buffer layer 5 has a higher Vickers hardness than the anode electrode 3, the buffer layer 5 has at least one opening in plan view and the width w of each of the at least one opening satisfies w < W th. Thus, the resistance between the external wiring 4 and the anode layer 2 can be suppressed, and the frequency of damage to the anode layer 2 caused by the foreign matter can be suppressed.

[0037] The area consisting of the openings of the buffer layer 5 and the buffer layer 5 in plan view occupies the entire front surface of the drift layer 1 in plan view. The influence of position variations when the external wiring 4 is connected can thereby be suppressed.

[0038] Buffer layer 5 contains silicon oxide or silicon nitride. A configuration in which buffer layer 5 has a higher Vickers hardness than anode electrode 3 can thus be easily achieved. <A-3. Modifikationen>

[0039] The shape of the buffer layer 5 in plan view is not limited to the<A-1. Konfiguration> The buffer layer 5 can have any shape as long as it has at least one opening in plan view and the width w of each of the at least one opening w < W th The anode electrode 3 is in contact with the anode layer 2 through the at least one opening of the buffer layer 5. A resistance between the external wiring 4 and the anode layer 2 can be reduced if the buffer layer 5 has the at least one opening, and the frequency of damage caused by the foreign matter can be suppressed if the width w of each of the at least one opening w < W th fulfilled.

[0040] Fig. 4 to 6 illustrate modifications of the semiconductor device 100, each including the buffer layer 5 having a different shape in plan view.

[0041] Fig. 4 illustrates an example in which the buffer layer 5 has the mesh shape, but the area consisting of the openings of the buffer layer 5 and the buffer layer 5 occupies only a partial area of ​​the front surface of the anode layer 2. If the buffer layer 5 is arranged so that the area consisting of the openings of the buffer layer 5 and the buffer layer 5 occupies only the partial area of ​​the front surface of the anode layer 2, the buffer layer 5 is arranged so that the area consisting of the openings of the buffer layer 5 and the buffer layer 5 includes an area 8 for connection to an external wiring where the external wiring 4 is connected.Since the area consisting of the openings of the buffer layer 5 and the buffer layer 5 occupies only the partial area of ​​the front surface of the anode layer 2, an area where the buffer layer 5 is not arranged in plan view can be enlarged to further suppress resistance between the external wiring 4 and the anode layer 2.

[0042] Each of the openings of the mesh of the buffer layer 5 does not have to have a rectangular shape as in Fig. 2 and Fig. 4 and can have any shape that fits within a rectangle that, in plan view, has a length of W on each side. th Each of the openings has a shape such that resistance between the external wiring 4 and the anode layer 2 can be suppressed and the frequency of damage to the anode layer 2 caused by the foreign matter can be suppressed.

[0043] The buffer layer 5 does not have to have a net shape and can be shaped so that each of the openings of the buffer layer 5 has a linear shape with a width w of less than W th has. Fig. 5 and Fig. 6 illustrate examples in which each of the openings of the buffer layer 5 has the linear shape with the width w of less than W th has.

[0044] Fig. 5 illustrates an example in which the buffer layer 5 has a striped shape in plan view.

[0045] Fig. 6 illustrates an example in which the buffer layer 5 has a concentric ring shape in plan view.

[0046] The buffer layer 5 may have a different shape in plan view than that shown in Fig. 5 and Fig. 6 illustrated shapes such as a spiral shape.

[0047] Since the buffer layer 5 has the at least one opening in plan view and each of the at least one opening of the buffer layer 5 has the linear shape with the smaller width than W th resistance between the external wiring 4 and the anode layer 2 can be suppressed, and the frequency of damage to the anode layer 2 caused by the foreign matter can be suppressed. <B. Ausführungsform 2><B-1. Konfiguration und Betrieb>

[0048] A semiconductor device 101 according to the present embodiment includes a buffer layer 6 instead of the buffer layer 5 of the semiconductor device 100 according to Embodiment 1. The buffer layer 6 is made of a different material from the buffer layer 5. The buffer layer 6 may have a different shape from the buffer layer 5, and with the difference, the semiconductor device 101 may differ from the semiconductor device 100 in how the anode electrode 3 and the anode layer 2 are in contact with each other or whether the anode electrode 3 and the anode layer 2 are in contact with each other. The semiconductor device 101 is otherwise the same as the semiconductor device 100.

[0049] The buffer layer 6 has a higher Vickers hardness than the anode electrode 3 and the external wiring 4. Thus, a frequency with which the foreign matter located inside the anode electrode 3 and adhering to the upper surface of the anode electrode 3 reaches the anode layer 2 when the external wiring 4 is connected can be suppressed, and the frequency of damage to the anode layer 2 caused by the foreign matter can be suppressed.

[0050] The buffer layer 6 is a conductor. Since the buffer layer 6 is the conductor, resistance between the external wiring 4 and the anode layer 2 can be suppressed even if the buffer layer 6 is provided.

[0051] The buffer layer 6 contains, for example, one of titanium, tungsten, molybdenum, and hafnium. Titanium, tungsten, molybdenum, and hafnium have higher Vickers hardness than aluminum and copper, which are used for the anode electrode 3 and the external wiring 4. Titanium, tungsten, molybdenum, and hafnium are conductive materials commonly used in semiconductor manufacturing processes, and their process control is simple.

[0052] The buffer layer 6 is at least selectively disposed on the front surface of the anode layer 2. The buffer layer 6 may, for example, have the same shape as any of the buffer layer 5 according to Embodiment 1 and the buffer layer 5 according to the modifications of Embodiment 1. Unlike Embodiment 1, the buffer layer 6 may have a shape without any openings in plan view. The buffer layer 6 having the shape without any openings in plan view may be as shown in Fig. 7 and Fig. 8, for example, may be selectively arranged on the anode layer 2 or may be arranged on the entire anode layer 2 according to the present invention.

[0053] If the buffer layer 6 is selectively disposed on the anode layer 2, the buffer layer 6 is disposed in a region including the external wiring connection region 8 where the external wiring 4 is connected to the anode electrode 3, in plan view, as shown in Fig. 8 is illustrated. <B-2. Effekte>

[0054] The semiconductor device 101 includes the conductive buffer layer 6, which is at least selectively disposed on the front surface of the anode layer 2 and has a higher Vickers hardness than the anode electrode 3. Thus, resistance between the external wiring 4 and the anode layer 2 can be suppressed, and the incidence of damage to the anode layer 2 caused by the foreign matter can be suppressed.

[0055] Buffer layer 6 contains one of titanium, tungsten, molybdenum, and hafnium. Titanium, tungsten, molybdenum, and hafnium are conductive materials commonly used in semiconductor manufacturing processes, and their process control is simple.

[0056] The embodiments can be combined with each other.

Claims

[1] A semiconductor device (100) comprising: a first semiconductor layer (1); a second semiconductor layer (2) arranged on a front surface of the first semiconductor layer (1) and having a different conductivity type from the first semiconductor layer (1); a buffer layer (5) arranged on a front surface of the second semiconductor layer (2) and having at least one opening in plan view; and an electrode (3) arranged above the second semiconductor layer (2) and the buffer layer (5) and through which at least one opening is in contact with the second semiconductor layer (2), wherein the buffer layer (5) has a higher Vickers hardness than the electrode (3), a width w of each of the at least one opening w < W th where s is a thickness of the buffer layer (5), t is a thickness of the electrode (3) and W th = 2 × (s × t - s 2) 0,5 applies, and where the electrode (3) is not in contact with the first semiconductor layer (1) in a region of the at least one opening. [2] The semiconductor device (100) according to claim 1, wherein a region consisting of the at least one opening and the buffer layer (5) in plan view occupies only a partial region of the front surface of the first semiconductor layer (1) in plan view. [3] The semiconductor device (100) according to claim 1, wherein a region consisting of the at least one opening and the buffer layer (5) in plan view occupies the entire front surface of the first semiconductor layer (1) in plan view. [4] The semiconductor device (100) according to any one of claims 1 to 3, wherein each of said at least one opening has a shape contained within a rectangle having a length of W on each side in plan view th has. [5] The semiconductor device (100) according to any one of claims 1 to 4, wherein the buffer layer (5) has a net shape in plan view. [6] The semiconductor device (100) according to any one of claims 1 to 3, wherein each of said at least one opening has a linear shape with a width less than W th has. [7] The semiconductor device (100) according to claim 6, wherein the buffer layer (5) has a striped shape in plan view. [8] The semiconductor device (100) according to claim 6, wherein the buffer layer (5) has a concentric ring shape in plan view. [9] A semiconductor device (100) according to any one of claims 1 to 8, wherein the buffer layer (5) contains silicon oxide or silicon nitride. [10] A semiconductor device (101) comprising: a first semiconductor layer (1); a second semiconductor layer (2) arranged on a front surface of the first semiconductor layer (1) and having a different conductivity type from the first semiconductor layer (1); a conductive buffer layer (6) which is at least selectively arranged on a front surface of the second semiconductor layer (2); and an electrode (3) arranged on a front surface of the buffer layer (6), wherein the buffer layer (6) has a higher Vickers hardness than the electrode (3); and wherein the buffer layer (6) is arranged on the entire surface of the second semiconductor layer (2). [11] The semiconductor device (101) according to claim 10, wherein the buffer layer (6) contains one of titanium, tungsten, molybdenum and hafnium.

Images