Non-volatile memory device and method of operation of a non-volatile memory

Abstract

An operating method of a non-volatile memory device (100) comprising at least one memory block (BLK) having a plurality of cell strings (NS11~NS33; STR1~STRm), each of which has a string selection transistor (SST; SST1~SSTm), a plurality of memory cells (MC1~MC8), and a ground selection transistor (GST; GST1~GSTm) connected in series and arranged in a vertical direction between a bit line (BL; BL1~BL3) and a source line (CSL), the method comprising: during (S100) a word line setup period (WL_STP) and during application of a first voltage (V11; V21; V31) to a block word line (BLKWL) connected to each gate of a plurality of pass transistors (GPT; PT1~PTn; SSPT) each having a string selection line (SSL; SSL1~SSLm), a plurality of word lines (WL; WL1~WLn) and a ground select line (GSL;GSL1~GSL3) to a plurality of driver lines (S1~Sn), applying a second voltage (V12; V22; V32) to the plurality of driver lines (S1~Sn) which are commonly connected to a sense node (SO) to provide a third voltage (V13; V23; V33) to the plurality of word lines (WL; WL1~WLn), wherein the string selection line (SSL; SSL1~SSLm) is connected to the string selection transistor (SST; SST1~SSTm), the plurality of word lines (WL; WL1~WLn) is connected to the plurality of memory cells (MC1~MC8), and the ground selection line (GSL; GSL1~GSL3) is connected to the ground selection transistor (GST; GST1~GSTm); during (S200) a word line development period (DVL) and during a Precharging the plurality of driver lines (S1~Sn) with the second voltage (V12; V22; V32), applying a fourth voltage (V14; V24; V34) to the block word line (BLKWL) to precharge the plurality of pass transistors (GPT; PT1~PTn;SSPT) to develop target word lines from the plurality of word lines (WL; WL1~WLn); and during (S300) a measurement period (SEN), applying a fifth voltage (V15; V25) that is smaller than the first voltage (V11; V21; V31) to the block word line (BLKWL), detecting a voltage drop of the measurement node (SO), and detecting a leakage current (LKG) of the target word lines based on the voltage drop.;

Description

BACKGROUND1. Technical FieldMethods, apparatuses, and systems consistent with example embodiments relate to semiconductor memory devices, and more particularly, to a non-volatile memory device and method of operation of a non-volatile memory device.2. Related ArtSemiconductor memory devices for storing data include volatile memory devices and nonvolatile memory devices. Volatile memory devices, such as random access memory (DRAM) devices, are typically configured to store data in memory cells by charging or discharging capacitors, and to lose the stored data when the power supply is turned off. Non-volatile memory devices, such as flash memory devices, may maintain the stored data even with the power supply turned off. Volatile memory devices are often used as main memory of various devices, while nonvolatile memory devices are frequently used to store program codes and / or data in various electronic devices such as computers, mobile devices, etc.Recently, nonvolatile memory devices having a three-dimensional structure such as vertical NAND memory devices have been developed to increase the integration degree and the storage capacity of the nonvolatile memory devices. As the integration degree and the storage capacity increase, leakage currents may occur in the word lines of the nonvolatile memory device, and user operations such as program, read, and erase operations may proceed erroneously.US 2017 / 0316834 A1 and US 2011 / 0019487 A1 each disclose a leakage current measurement for word lines in a block or sector by means of the measurement of a voltage drop after a certain time in the floating state of the word lines.US 2019 / 0006021 A1 discloses a leakage current measurement between different blocks.SUMMARYSome example embodiments provide a nonvolatile memory device capable of simultaneously sensing word lines in which leakage current occurs.Some example embodiments provide an operation method of a nonvolatile memory device capable of simultaneously detecting word lines in which leakage currents occur.According to example embodiments, an operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes at least one memory block including a plurality of cell strings each including a string selection transistor, a plurality of memory cells, and a ground selection transistor that are connected in series and arranged in a vertical direction between a bit line and a source line. The method includes: during a wordline device period and during application of a first voltage to a block wordline coupled to each gate of a plurality of pass transistors (engl. A pass transistor) each connecting a string select line, a plurality of word lines, and a ground select transistor to a plurality of driver lines, applying a second voltage to the plurality of driver lines commonly connected to a sense node to provide a third voltage to the plurality of word lines, the string select line being connected to the string select transistor, the plurality of word lines to the plurality of memory cells, and the ground select line being connected to the ground select transistor; during a word line developing period and during a pre-charging of the plurality of driver lines to the second voltage, applying a fourth voltage to the block word line to turn off the plurality of pass transistors to develop target word lines from the plurality of word lines; and during a sensing period, applying a fifth voltage less than the first voltage to the block word line, detecting a voltage drop of the sensing node, and detecting a leakage current of the target word lines based on the voltage drop.According to example embodiments, a nonvolatile memory device includes at least one memory block including a plurality of cell strings each including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and arranged in a vertical direction between a bit line and a source line; A control circuit configured to control a leakage current sensing operation by: during a wordline setup period and during application of a first voltage to a block wordline connected to each gate of a plurality of pass transistors each connecting a string select line, a plurality of wordlines, and a ground select transistor to a plurality of drive lines, applying a second voltage to the plurality of drive lines commonly connected to a sense node to provide a third voltage to the plurality of wordlines, wherein the string select line is connected to the string select transistor, the plurality of wordlines is connected to the plurality of memory cells, and the ground select line is connected to the ground select transistor; during a word line developing period and during precharging of the plurality of drive lines with the second voltage, applying a fourth voltage to the block word line to turn off the plurality of pass transistors to develop target word lines from the plurality of word lines; and during a sensing period, applying a fifth voltage, which is smaller than the first voltage, to the block word line, detecting a voltage drop of the sensing node, and detecting a leakage current of the target word lines based on the voltage drop.According to example embodiments, a nonvolatile memory device includes at least one memory block including a plurality of cell strings each including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series and arranged in a vertical direction between a bit line and a source line; a voltage generator configured to generate word line voltages based on a control signal; an address decoder configured to provide the word line voltages to the at least one memory block; a leakage current detector connected to the address decoder at a sensing node; and a control circuit configured to control the voltage generator, the address decoder, and the leakage current detector. The control circuit is configured to control a leakage current sensing operation by: during a wordline setup period and during application of a first voltage to a block wordline connected to each gate of a plurality of pass transistors each connecting a string select line, a plurality of wordlines, and a ground select transistor to a respective one of a plurality of drive lines, applying a second voltage to the plurality of drive lines commonly connected to the sense node to provide a third voltage to the plurality of wordlines, wherein the string select line is connected to the string select transistor, the plurality of wordlines is connected to the plurality of memory cells, and the ground select line is connected to the ground select transistor; during a word line developing period and during precharging of the plurality of drive lines with the second voltage, applying a fourth voltage to the block word line to turn off the plurality of pass transistors to develop target word lines from the plurality of word lines; and during a sensing period, applying a fifth voltage, which is smaller than the first voltage, to the block word line, sensing a voltage drop of the sensing node, and sensing a leakage current of the target word lines based on the voltage drop. The control circuit is configured to perform the leakage current sensing operation during a programming operation of a programming loop on the at least one memory block, and the control circuit is configured to terminate the programming loop on the at least one memory block based on the leakage current occurring in at least one of the plurality of word lines.The nonvolatile memory device and the operation method of the nonvolatile memory device can quickly detect a leakage current of at least a portion of word lines by pre-charging drive lines connected to the word lines via pass transistors, applying a voltage lower than a turn-on voltage to the pass transistors, and detecting a voltage drop of a sensing node commonly connected to the drive lines.BRIEF DESCRIPTION OF THE DRAWINGSIllustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a flowchart illustrating an operation method of a nonvolatile memory device according to an exemplary embodiment. FIGS. 2, 3, and 4 are timing diagrams illustrating an operation method of a nonvolatile memory device according to example embodiments. FIG. 5 is a block diagram illustrating a memory system according to example embodiments. FIG. 6 is a block diagram illustrating the nonvolatile memory device in the memory system of FIG. 5, according to example embodiments. FIG. 7 is a block diagram illustrating an example of the memory cell array (or memory cell array) in FIG. 6, according to example embodiments. FIG. 8 is a circuit diagram illustrating one of the memory blocks in FIG. 7 according to example embodiments. FIG. 9 is a diagram illustrating an example structure of a cell string. FIG. 10 is a diagram illustrating a memory cell included in the cell string of FIG. 9. FIG. 11 is a block diagram illustrating the control circuit in the nonvolatile memory device of FIG. 6 according to example embodiments. FIG. 12 is a block diagram illustrating an example of the address decoder in the nonvolatile memory device of FIG. 6, according to example embodiments. FIG. 13 is a block diagram illustrating an example of the voltage generator in the nonvolatile memory device of FIG. 6 according to example embodiments. FIG. 14 illustrates a portion of the nonvolatile memory device of FIG. 6, according to example embodiments. FIG. 15 illustrates operation of the nonvolatile memory device of FIG. 14 during the wordline setup period. FIG. 16 illustrates an operation of the nonvolatile memory device of FIG. 14 during the word line development period. FIG. 17 illustrates an operation of the nonvolatile memory device of FIG. 14 during the measurement period. FIG. 18 illustrates an example of the leakage current detector in the nonvolatile memory device of FIG. 14, according to example embodiments. FIG. 19A is a flowchart illustrating an example in which a leakage current detection operation is applied to an erase loop of the nonvolatile memory device. FIG. 19B is a flowchart illustrating an example in which a leakage current detection operation is applied to an erase loop of the nonvolatile memory device. FIG. 20A is a view illustrating a structure of the nonvolatile memory device including the first and second semiconductor layers according to example embodiments. FIG. 20B is a plan view illustrating a top surface of the second semiconductor layer contacting the first semiconductor layer of the nonvolatile memory device according to example embodiments. FIG. 20C is a plan view illustrating a top surface of the first semiconductor layer overlapping the plan view of FIG. 20B. FIG. 20D is a cross-sectional view of the nonvolatile memory device according to example embodiments. FIG. 20E is a cross-sectional view taken along line VII-VII' of FIG. 20C illustrating configurations of the first and second semiconductor layers. FIG. 21 is a circuit diagram illustrating a structure of a memory cell array according to example embodiments. FIG. 22 is a perspective view illustrating a memory block corresponding to a structure of FIG. 21. FIG. 23 is a cross-sectional view for describing an example of a boundary portion included in a memory block according to example embodiments. FIG. 24 is a block diagram illustrating a storage device including a nonvolatile memory device according to an exemplary embodiment. FIG. 25 is a cross-sectional view of a nonvolatile memory device according to example embodiments.DETAILED DESCRIPTIONExemplary embodiments will be described in more detail below with reference to the accompanying drawings.FIG. 1 is a flowchart illustrating an operation method of a nonvolatile memory device according to example embodiments.FIG. 1 shows an operating method of a nonvolatile memory device including at least one memory block including a plurality of cell strings, each cell string including a string selection transistor, a plurality of memory cells, and a ground selection transistor connected between a bit line and a source line. According to example embodiments, the nonvolatile memory device may include a three-dimensional NAND flash memory device or a vertical NAND flash memory device.Referring to FIG. 1, during a word line device period, while a first voltage is applied to a block word line, the voltage is applied to each gate of a plurality of pass transistors (engl. A pass transistor) connecting a string selection line, a plurality of word lines, and a ground selection transistor to a respective one of a plurality of drive lines, applying a second voltage to the plurality of drive lines commonly connected to a sense node to supply a third voltage to the plurality of word lines, wherein the string selection line is connected to the string selection transistor, the plurality of word lines are connected to the memory cells, and the ground selection line is connected to the ground selection transistor (operation S 100).During a word line development period, while the plurality of drive lines are precharged with the second voltage, target word lines are developed from the plurality of word lines by applying a fourth voltage to the block word line to turn off the plurality of pass transistors (operation S 200). The fourth voltage may correspond to a ground voltage (or ground voltage).During a sensing period, a leakage current in at least a portion of the target word lines is sensed by applying a fifth voltage less than the first voltage to the block word line and sensing a voltage drop of the sensing node (operation S 300).FIGS. 2, 3, and 4 are timing diagrams illustrating an operation method of a nonvolatile memory device according to an exemplary embodiment.Each of FIGS. 2, 3 and 4 shows a word line device period (engl. Word-line set-up period) WL_STP, a word line development period (engl. Word-line development period) DVL, a measurement period SEN, and a recovery period (engl. Recovery Period) RCV of a leakage current detection operation for detecting a leakage current of a plurality of word lines. The time points T0 ~ T4 represent the limits of the periods.Referring to FIG. 2, during the word line device period WL_STP, a first voltage V 11 is applied to a block word line BLKWL, and a second voltage V 12 is applied to drive lines SI. A level of the second voltage V 12 may be greater than a level of the first voltage V 11. When the pass transistors are turned on (activated) in response to the first voltage V 11 applied to the block word line BLKWL, the voltages of the word lines WL connected to the drive lines SI via the pass transistors rise from a ground voltage (ground voltage) to a level of a third voltage V 13, and the word lines WL are set to the third voltage V 13. When a level of the third voltage V 13 becomes lower than the level of the first voltage V 11 by a first threshold voltage Vt 1, the pass transistors may be turned off.During the word line developing period DVL, while the drive lines SI are precharged with the second voltage V12, a fourth voltage V14 corresponding to the ground voltage is applied to the pass transistors to turn off the pass transistors. Since the pass transistors are turned off, the voltages of the target word lines selected from the word lines WL decrease from the third voltage V13, and the target word lines are developed.During the sensing period SEN, a leakage current of at least a portion of the target word lines is sensed (determined) by applying a fifth voltage V 15 lower than the first voltage V 11 to the block word line BLKWL and detecting a voltage drop of the sensing node. The level of the fifth voltage V 15 may be greater than the first voltage V 11 by the first threshold voltage Vt 1.Since at least one pass transistor connected to at least one word line in which a leakage current occurs is turned on by the fifth voltage V 15, charge sharing occurs between a drive line connected to the at least one pass transistor and the at least one word line in which a leakage current occurs, and a voltage level of the drive line connected to the at least one word line in which a leakage current occurs decreases. Therefore, a voltage drop occurs at the measurement node.When no leakage occurs in any of the target word lines, none of the pass transistors is turned on by the fifth voltage V 15, and the voltage drop does not occur at the sensing node.During the recovery period RCV, the voltage level of the drive line connected to the at least one word line in which a leakage current occurs further decreases.Referring to FIG. 3, during the word line device period WL_STP, a first voltage V 21 is applied to the block word line BLKWL, and a second voltage V 22 is applied to the drive lines SI. A level of the first voltage V 21 may be greater than a level of the second voltage V 22. When the pass transistors are turned on (activated) in response to the first voltage V21 applied to the block word line BLKWL, the voltage of the word lines WL connected to the drive lines SI via the pass transistors rises from the ground voltage to a level of a third voltage V23, and the word lines WL are set to the third voltage V23. A level of the third voltage V 23 becomes substantially equal to the second voltage V 22.During the word line developing period DVL, while the drive lines SI are precharged with the second voltage V22, a fourth voltage V24 corresponding to the ground voltage is applied to the pass transistors to turn off the pass transistors. Since the pass transistors are turned off, the voltages of the target word lines selected from the word lines WL decrease from the third voltage V23, and the target word lines are developed.During the sensing period SEN, a leakage current of at least a portion of the target word lines is detected (determined) by applying a fifth voltage lower than the first voltage V 21 to the block word line BLKWL and detecting a voltage drop of the sensing node. A level of the fifth voltage V 25 may be greater than the first voltage V 21 by the first threshold voltage.Since at least one pass transistor connected to at least one word line in which a leakage current occurs is turned on by the fifth voltage V 25, charge sharing occurs between a drive line connected to the at least one pass transistor and the at least one word line in which a leakage current occurs, and a voltage level of the drive line connected to the at least one word line in which a leakage current occurs decreases. Therefore, a voltage drop occurs at the measurement node.When a leakage current does not occur in any of the target word lines, none of the pass transistors is turned on by the fifth voltage V 15, and the voltage drop does not occur at the sensing node.During the recovery period RCV, the voltage levels of the at least one word line in which a leakage current occurs and the drive line connected to the at least one word line in which a leakage current occurs are continuously decreased.Referring to FIG. 4, during the word line device period WL_STP, a first voltage V 31 is applied to the block word line BLKWL, and a second voltage V 32 is applied to the drive lines SI. A level of the first voltage V 31 may be greater than a level of the second voltage V 32. When the pass transistors are turned on (activated) in response to the first voltage V 31 applied to the block word line BLKWL, the voltage of the word lines WL connected to the drive lines SI via the pass transistors increases from the ground voltage to a level of a third voltage V 33, and the word lines WL are set to the third voltage V 33. A level of the third voltage V 33 becomes substantially the same as the second voltage V 32.During the word line developing period DVL, while the drive lines SI are precharged with the second voltage V32, a fourth voltage V34 corresponding to the ground voltage is applied to the pass transistors to turn off the pass transistors. Since the pass transistors are turned off, the voltages of the target word lines selected from the word lines WL decrease from the third voltage V33, and the target word lines are developed.During the sensing period SEN, a leakage current of at least a portion of the target word lines is sensed (determined) by applying a fifth voltage V 35 having a level substantially corresponding to the level of the first voltage V 31 to the block word line BLKWL and detecting a voltage drop of the sensing node.Since at least one pass transistor connected to at least one word line in which leakage current occurs is turned on by the fifth voltage V 35, charge sharing occurs between a drive line connected to the at least one pass transistor and the at least one word line in which leakage occurs, and a voltage level of the drive line connected to the at least one word line in which leakage occurs decreases. Therefore, a voltage drop occurs at the measurement node.During the recovery period RCV, the voltage levels of the at least one word line in which a leakage current occurs and the drive line connected to the at least one word line in which a leakage current occurs continuously decrease.FIG. 5 is a block diagram illustrating a memory system (i.e., a memory device) according to example embodiments.Referring to FIG. 5, a storage device (i.e., a storage system) 10 may include a storage controller 50 and at least one nonvolatile storage device 100.In example embodiments, both the memory controller 50 and the nonvolatile memory device 100 may be in the form of a chip, package (or package. The package) or a module may be provided. Alternatively, the memory controller 50 and the nonvolatile memory device 100 may be provided in various assemblies.The nonvolatile memory device 100 may perform an erase operation, a program operation, or a write operation under the control of the memory controller 50. The nonvolatile memory device 100 receives, from the memory controller 50, a command CMD, an address ADDR, and data DATA for performing such operations via input / output lines. In addition, the nonvolatile memory device 100 receives a control signal CTRL from the memory controller 50 via a control line.FIG. 6 is a block diagram illustrating the nonvolatile memory device in the memory system of FIG. 5 according to example embodiments.Referring to FIG. 6, the nonvolatile memory device 100 includes a memory cell array 200, an address decoder 300, a page buffer circuit 410, a data input / output (I / O) circuit 420, a control circuit 450, a voltage generator 500, and a leakage current detector 570.The memory cell array 200 may be connected to the address decoder 300 via a string selection line SSL, a plurality of word lines WLs, and a ground selection line GSL. In addition, the memory cell array 200 may be connected to the page buffer circuit 410 via a plurality of bit lines BLs. The memory cell array 200 may include a plurality of memory cells connected to the plurality of word lines WLs and the plurality of bit lines BLs.In some example embodiments, the memory cell array 200 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 200 may include vertical cell strings vertically oriented such that at least one memory cell is disposed over another memory cell.The control circuit 450 may receive a command (a command signal) CMD and an address (an address signal) ADDR from the memory controller 50, and control a user operation and a leakage current detection operation of the nonvolatile memory device 100 based on the command signal CMD and the address signal ADDR. The user operation may include an erase loop, a program loop, and a read operation of the nonvolatile memory device 100. The program loop may include a program operation and a program verification operation. The erase loop may include an erase operation and an erase verify operation.For example, the control circuit 450 may generate control signals CTLs to control the voltage generator 500, may generate a page buffer control signal PCTL to control the page buffer circuit 410, and may generate a control signal DCTL to control the leakage current detector 570 based on the command signal CMD. The control circuit 450 may generate a row address R_ADDR and a column address C_ADDR based on the address signal. The control circuit 450 may provide the row address R_ADDR to the address decoder 300 and provide the column address C_ADDR to the data input / output circuit 420. In addition, the control circuit 450 may generate switching control signals SCS based on the command signal CMD and provide the switching control signals SCS to the address decoder 300.The address decoder 300 may be connected to the memory cell array 200 via the string selection line SSL, the plurality of word lines WLs, and the ground selection line GSL. During the program operation or the read operation, the address decoder 300 may determine one of the plurality of word lines WLs as a selected word line and the rest of the plurality of word lines WLs except the selected word line as unselected word lines based on the row address R_ADDR.The voltage generator 500 may generate wordline voltages VWLs required for the operation of the nonvolatile memory device 100 based on the control signals CTLs. The voltage generator 500 may receive the power PWR from the memory controller 50. The word line voltages VWLs may be applied to the plurality of word lines WLs via the address decoder 300.For example, during the erase operation, voltage generator 500 may apply an erase voltage to a well of the memory block and apply a ground voltage to each of the word lines of the memory block. During the erase verify operation, the voltage generator 500 may apply an erase verify voltage to each of the word lines of the memory block or sequentially apply the erase verify voltage to word lines on a word line basis.For example, during the program operation, voltage generator 500 may apply a program voltage to the selected word line and a program pass voltage (narrow. Program Pass Voltage) to the unselected word lines. In addition, during the program verify operation, the voltage generator 500 may apply a program verify voltage to the selected word line and apply a verify pass voltage to the unselected word lines.The page buffer circuit 410 may be connected to the memory cell array 200 via the plurality of bit lines BLs. The page buffer circuit 410 may include a plurality of page buffers. The page buffer circuit 410 may temporarily store data to be programmed into a selected page or data read out from the selected page.Data input / output circuit 420 may be connected to page buffer circuit 410. During the program operation, the data input / output circuit 420 may receive program data DATA from the memory controller 50 and provide the program data DATA to the page buffer circuit 410 based on the column address C_ADDR received from the control circuit 450. During the read operation, the data input / output circuit 420 may provide read data DATA stored in the page buffer circuit 410 to the memory controller 50 based on the column address C_ADD received from the control circuit 450.The leakage current detector 570 may be connected to the address decoder 300, may be connected to drive lines connected to the word lines WLs at a sensing node in the address decoder 300 to detect a leakage current of at least a portion of the word lines WLs, and may provide a leakage current detection signal LDS to the control circuit 450 when the leakage current is detected.FIG. 7 is a block diagram showing an example of the memory cell array in FIG. 6, according to example embodiments.Referring to FIG. 7, the memory cell array 200 may include a plurality of memory blocks BLK 1 to BLKz extending along the first to third directions D 1, D 2, and D 3. In an exemplary embodiment, memory blocks BLK 1 through BLKz are selected by address decoder 300 in FIG. 6. For example, the address decoder 300 may select a memory block BLK corresponding to a block address from the memory blocks BLK 1 to BLKz.Hereinafter, the first direction D 1 denotes a direction perpendicular to an upper surface of a semiconductor substrate, and the second direction D 2 and the third direction D 3 denote two directions parallel to the upper surface of the semiconductor substrate. For example, the second direction and the third direction D 3 may be perpendicular to each other. The first direction D 1 may be referred to as a vertical direction, the second direction D 2 may be referred to as a row direction, and the third direction D 3 may be referred to as a column direction. The direction indicated by an arrow in the figures and the opposite direction may be regarded as the same direction.FIG. 8 is a circuit diagram showing one of the memory blocks in FIG. 7 according to example embodiments.The memory block BLKi of FIG. 8 may be formed on a substrate in a three-dimensional structure (or a vertical structure). For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.Referring to FIG. 8, the memory block BLKi may include memory cell strings NS 11 to NS 33 connected between the bit lines BL 1, BL 2, and BL 3 and a common source line CSL.Each of the memory cell strings NS 11 to NS 33 may include a string selection transistor SST, a plurality of memory cells MC 1 to MC 8, and a ground selection transistor GST. In FIG. 6A, it is shown that each of the memory cell strings NS 11 to NS 33 includes eight memory cells MC 1 to MC 8. However, the exemplary embodiments are not limited thereto. In some example embodiments, each of the memory cell strings NS 11 to NS 33 may include any number of memory cells. For example, each of the memory cell strings NS 11 to NS 33 may include more than eight memory cells or less than eight memory cells.The string selection transistor SST may be connected to corresponding string selection lines SSL 1 to SSL 3. The plurality of memory cells MC 1 to MC 8 may be connected to the associated word lines WL 1 to WL 8. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL 1 to GSL 3. The string selection transistor SST may be connected to corresponding bit lines BL 1, BL 2, and BL 3, and the ground selection transistor GST may be connected to the common source line CSL. Equal height word lines (e.g., WL 1) may be commonly connected, and the ground select lines GSL 1 to GSL 3 and the string select lines SSL 1 to SSL 3 may be separated.FIG. 9 is a diagram illustrating an example structure of a cell string, and FIG. 10 is a diagram illustrating a memory cell included in the cell string of FIG. 9.Referring to FIGS. 9 and 10, a column PL extending in a vertical direction may be formed on a substrate SUB to provide the cell string NS. The ground selection line GSL, the word lines WL, and the string selection lines SSL may be formed of conductive materials such as metals, which are parallel to the substrate SUB. The pillar PL may penetrate the conductive materials forming the ground selection line GSL, the word lines WL, and the string selection lines SSL to contact the substrate SUB. The word lines WL may include dummy word lines.Fig. 10 is a cross-sectional view taken along line E-E' in Fig. 9, for example, Fig. 10 is a cross-sectional view of a memory cell MC associated with a word line. The pillar PL may include a cylindrical body BD, and an air gap AG may be provided in the body BD. The body BD may include P-type silicon, and the body BD may be a region where a channel is formed.The pillar PL may further include a tunnel insulating layer TI surrounding the body BD and a charge trapping layer CT surrounding the tunnel insulating layer T 1. Between a word line and the pillar PL, a barrier insulating layer BI may be provided. The body BD, the tunnel insulating layer TI, the charge trapping layer CT, the barrier insulating layer BI, and the one word line may form a charge trapping type transistor. In some example embodiments, the string selection transistor SST, the ground selection transistor GST, and the other memory cells may have the same structure as that illustrated in FIG. 10.As illustrated in FIGS. 9 and 10, the width or the cross-sectional area of the column PL may become smaller as the distance from the substrate SUB decreases.When the same voltage is applied to the bodies of the ground selection transistor GST, the memory cells MC, and the string selection transistor SST, and the same voltage is applied to the ground selection line GLS, the word lines WL, and the string selection line SSL, the electric field formed in the memory cell located close to the substrate SUB is larger than the electric field formed in the memory cell located far from the substrate SUB. These characteristics affect the program disturbance during the program operation.FIG. 11 is a block diagram illustrating the control circuit in the nonvolatile memory device of FIG. 6 according to example embodiments.Referring to FIG. 11, the control circuit 450 includes a command decoder 460, an address buffer 470, and a control signal generator 480.The command decoder 460 decodes the command CMD and provides a decoded command D_CMD to the control signal generator 480.The address buffer 470 receives the address signal ADDR, provides the row address R_ADDR to the address decoder 300, and provides the column address C_ADDR to the data input / output circuit 420.The control signal generator 480 receives the decoded command D_CMD, generates the control signals CTLs based on an operation arranged by the decoded command D_CMD, provides the control signals CTLs to the voltage generator 500, generates a page buffer control signal PCTL, provides the page buffer control signal PCTL to the page buffer circuit 410, generates the control signal DCTL, and provides the control signal DCTL to the leakage current detector 570. In addition, the control signal generator 480 generates the switching control signals SCS based on the decoded command D_CMD, and provides the switching control signals SCS to the address decoder 300.FIG. 12 is a block diagram showing an example of the address decoder in the nonvolatile memory device of FIG. 6 according to example embodiments.Referring to FIG. 12, the address decoder 300 may include a driver circuit 310 and a pass switch circuit 360.The driver circuit 310 may transmit voltages provided from the voltage generator 500 to the memory cell array 200 in response to a block address. The driver circuit 310 may include a block selection driver BLKWL DRIVER 320, a string selection driver SS DRIVER 330, a drive line driver SI DRIVER 340, and a ground selection driver GS DRIVER 350.The block selection driver 320 may supply a high voltage from the voltage generator 500 to the pass transistor circuit 360 in response to the block address. The block selection driver 320 may supply the high voltage of the block word line BLKWL connected to gates of a plurality of pass transistors GPT, PT1_PTn, and SSPT in the pass transistor circuit 360. Here, n is an integer greater than one. The block selection driver 320 may apply various voltages, such as a pass voltage (DC). Pass Voltage), a program voltage, a read voltage, to control the memory cell array 200.The string selection driver 330 may supply a selection voltage SS from the voltage generator 500 as the string selection signal SS to the string selection line SSL via the pass transistor SSPT. During a program operation, string select driver 330 may provide select voltage SS to turn on all string select transistors in a selected memory block.During a program operation, the drive line driver 340 may supply the program voltage, the pass voltage, and the read voltage from the voltage generator 500 to the word lines WL 1WLn via the drive lines S 1WL And the pass transistors PT 1PTn.The ground selection driver 350 may supply a ground selection signal GS from the voltage generator 500 to the ground selection line GSL via the pass transistor GPT.The pass transistors GPT, PT1_PTn, and SSPT are configured such that the ground selection transistors GSL, the word lines WL1_WLn, and the string selection transistors SSL are electrically connected to corresponding drive lines in response to activation of the high voltage on the block word line BLKWL. In exemplary embodiments, each of the pass transistors GPT, PT 1_PTn, and SSPT may include a high voltage transistor capable of withstanding high voltage.FIG. 13 is a block diagram illustrating an example of the voltage generator in the nonvolatile memory device of FIG. 6 according to example embodiments.Referring to FIG. 13, the voltage generator 500 may include a high voltage generator VPP GENERATOR 510, a selection voltage generator Va GENERATOR 520, a programming voltage generator VPGM GENERATOR 530, a through voltage generator VPASS GENERATOR 540, and a read voltage generator VREAD GENERATOR 550.The high voltage generator 510 may generate a high voltage to be supplied to the block selection driver 320. The selection voltage generator 520 may generate selection voltages (SS and GS in FIG. 12 ) to be supplied to the string selection line SSL and the ground selection line GSL, respectively, and may provide the selection voltages to the string selection driver 330 and the ground selection driver 350.The program voltage generator 530 may generate a program voltage to be applied to a selected word line during a program operation. The program voltage generator 530 may generate a step voltage according to an incremental step pulse programming method (Engl. Incremental Step Pulse Programming) (ISPP) and provide the step voltage to the drive line driver 340. The pass voltage generator 540 may generate a pass voltage to be provided to the unselected word lines during a program operation and provide the pass voltage to the drive line driver 340. The read voltage generator 550 may generate a read voltage to be provided to the unselected word lines during a read operation and provide the read voltage to the drive line driver 340.FIG. 14 illustrates a portion of the nonvolatile memory device of FIG. 6, according to example embodiments.FIG. 14 shows address decoder 300, voltage generator 500, and leakage current detector 570 associated with a leakage current sensing operation. The pass voltage generator 540 and the read voltage generator 550 of the voltage generator 500 are shown.Referring to FIG. 14, the address decoder 300 may include the pass transistor circuit 360, a selection switch circuit 340 a, a first voltage transfer circuit 340 b, and a second voltage transfer circuit 370. The selection switch circuit 340 a, the first voltage transfer circuit 340 b, and the second voltage transfer circuit 370 may correspond to the drive line driver 340 in FIG. 12.The pass transistor circuit 360 may include a plurality of pass transistors PTj, PTj, and PTk that are disposed between word lines WLi, WLj, and WLk and driver lines Si, Sj, and Sk, and each of the word lines WLi, WLj, and WLk connects to a respective one of the driver lines Si, Sj, and Sk. Each gate of the pass transistors PTi, PTj, and PTk is connected to the block word line BLKWL, and each of the pass transistors PTi, PTj, and PTk may connect each of the word lines WLi, WLj, and WLk to one of the respective drive lines Si, Sj, and Sk in response to the high voltage on the block word line BLKWL. Here, i is an integer greater than zero, j is an integer greater than i, and k is an integer greater than j.In example embodiments, each of the pass transistors PTi, PTj, and PTk may include a high voltage N-channel metal oxide semiconductor (NMOS) transistor.The selection switch circuit 340 amay include selection transistors SPTi, SPTj, and SPTk connected to the first voltage transfer circuit 340 band to each of the pass transistors PTi, PTj, and PTk. Each of the selection transistors SPTi, SPTj, and SPTk may be selectively turned on in response to the respective drive line selection signal SISi, SISj, and SISk applied to a gate of the respective selection transistor SPTi, SPTj, and SPTk, and may provide voltages from the first voltage transfer circuit 340 bto at least a part of the drive lines Si, Sj, and Sk.The drive line selection signals SISi, SISj, and SISk may be included in the switching control signal SCS in FIG. 6.In example embodiments, each of the selection transistors SPTi, SPTj, and SPTk may include an NMOS transistor.The first voltage transfer circuit 340 bmay include a plurality of NMOS transistors 341, 342, 343, 344, 345, and 346 connected between a connection line CL 1 and a connection line CL 2.The NMOS transistor 341 is connected between the connection line CL 1 and an internal node NIi connected to the selection transistor SPTi, and has a gate receiving a selection signal SS 1. The NMOS transistor 342 is connected between the connection line CL 2 and the internal node NIi, and has a gate receiving a selection signal SS 2.The NMOS transistor 343 is connected between the connection line CL 1 and an internal node NIj connected to the selection transistor SPTj, and has a gate receiving the selection signal SS 1. The NMOS transistor 344 is connected between the connection line CL 2 and the internal node NIj, and has a gate receiving the selection signal SS 2.The NMOS transistor 345 is connected between the connection line CL 1 and an internal node NIk connected to the selection transistor SPTk, and has a gate receiving the selection signal SS 1. The NMOS transistor 346 is connected between the connection line CL 2 and the internal node Nlk, and has a gate receiving the selection signal SS 2.The NMOS transistors 341, 343, and 345 are turned on in response to the selection signal SS 1, and can apply voltages from the connection line CL 1 to the drive lines Si, Sj, and Sk via the selection transistors SPTi, SPTj, and SPTk. The NMOS transistors 342, 344, and 346 are turned on in response to the selection signal SS 2, and can apply voltages from the connection line CL 2 to the drive lines Si, Sj, and Sk via the selection transistors SPTi, SPTj, and SPTk.The selection signals SS 1 and SS 2 may be included in the switching control signal SCS of FIG. 6.The second voltage transfer circuit 370 may include NMOS transistors 371, 372, 373, and 374.The NMOS transistor 371 is connected between a sensing node SO connected to the connection line CL 1 and a node N 11, and has a gate receiving a switching control signal SSV 1. The NMOS transistor 372 is connected between the node N 11 and the pass voltage generator 540 to receive a pass voltage VPASS, and has a gate receiving a switching control signal SSV 2. The NMOS transistors 371 and 372 may be selectively turned on in response to the switching control signals SSV 1 and SSV 2, and may transmit the through voltage VPASS to the drive lines Si, Sj, and Sk via the node N 11 and the sensing node SO.The NMOS transistor 374 is connected between the node N 11 and the leakage current detector 570, and has a gate receiving a switching control signal LSS. The NMOS transistor 374 may be selectively turned on in response to the switching control signal LSS and may provide a voltage of the sensing node SO to the leakage current detector 570 via the node N 11.The NMOS transistor 373 is connected between the connection line CL 2 and the read voltage generator 550 to receive a read voltage VREAD, and has a gate receiving a switching control signal SSV 3. The NMOS transistor 373 may be selectively turned on in response to the switching control signal SSV 3, and may transmit the read voltage VREAD to the drive lines Si, Sj, and Sk via the connection line CL 2.The switching control signals SSV 1, SSV 2, SSV 3, and LSS may be included in the switching control signal SCS in FIG. 6.FIG. 15 shows an operation of the nonvolatile memory device of FIG. 14 during the word line establishment period (engl. Word-Line Set-Up Period).Referring to FIG. 15, during the word line device period, the word lines WLi, WLj, and WLk are configured (supplied) with a third voltage by applying a second voltage to the drive lines Si, Sj, and Sk using the read voltage VREAD provided from the read voltage generator 550. The second voltage may be applied to the drive lines Si, Sj, and Sk by turning on the NMOS transistor 373, turning off the NMOS transistors 371 and 372, turning off the NMOS transistors 341, 343, 345, turning on the NMOS transistors 342, 344, 346, turning on the selection transistors SPTi, SPTj, and SPTk, and applying a first voltage to the block word line BLKWL to turn on the pass transistors PTj, PTj, and PTk.In FIG. 15, word lines WLi and WLk may correspond to selected word lines SEL, and word line WLj may correspond to an unselected word line UNSEL.FIG. 16 illustrates an operation of the nonvolatile memory device of FIG. 14 during the word line development period.Referring to FIG. 16, during the word line development period, the word lines (even word lines) WLi, WLk are developed while the drive lines Si, Sj, and Sk are precharged with the second voltage using the read voltage VREAD provided from the read voltage generator 550 by applying a fourth voltage to the block word line BLKWL to turn off the pass transistors PTj, PTj, and PTk, turning off the NMOS transistor 373, turning on the NMOS transistor 371, turning on the NMOS transistor 372, turning on the NMOS transistors 341 and 345, turning off the NMOS transistors 342, 343, 344, and 346, and turning off the selection transistors SPTi, SPTj and SPTk are turned on. The connection line CL 1 connected to the leakage current detector 570 may be precharged with the second voltage.In FIG. 16, word lines WLi and WLk may correspond to selected word lines SEL, and word line WLj may correspond to an unselected word line UNSEL.FIG. 17 illustrates an operation of the nonvolatile memory device of FIG. 14 during the measurement period.Referring to FIG. 17, during the measurement period, one or more of the drive lines Si and Sk may be connected to the respective word lines (even word lines) WLi and WLk by applying a fifth voltage to each gate of the pass transistors PTj, PTj, and PTk via the block word line BLKWL, turning on the NMOS transistor 373, turning off the NMOS transistor 372, turning on the NMOS transistors 341 and 345, turning off the NMOS transistors 342, 343, 344, 346, and turning on the selection transistors SPTi, SPTj, and SPTk. The connection line CL 1 connected to the leakage current detector 570 may be precharged with the second voltage.Assuming that a leakage current LKG occurs in the word line WLk and the word line WLi is a normal word line in which no leakage current NO LKG occurs, a threshold voltage of the pass transistor PTk is decreased because a voltage level at a terminal of the pass transistor PTk connected to the word line WLk is decreased. Thus, the pass transistor PTk is turned on by the fifth voltage while the pass transistor PTi remains in an off state.Since the pass transistor PTk is turned on, charge sharing occurs between the word line WLk and the drive line Sk, a voltage level of the drive line Sk is reduced, and a voltage level of the sense node SO is reduced because the sense node SO is connected to the drive line Sk via the NMOS transistor 345 and the selection transistor SPTk. The leakage current detector 570, which is connected to the sensing node SO via the NMOS transistors 374 and 371, compares the voltage level of the sensing node SO with a reference voltage, and may provide the leakage current detection signal LDS to the control circuit 450 in FIG. 6 when the comparison result indicates that the voltage level of the sensing node SO has decreased below the reference voltage.The control circuit 450 may determine that a leakage current occurs at at at least one of the selected word lines WLi and WLj in response to activation of the leakage current detection signal LDS.FIG. 18 illustrates an example of the leakage current detector in the nonvolatile memory device of FIG. 14, according to example embodiments.Referring to FIG. 18, the leakage current detector 570 may include a comparator 571. The comparator 571 may include a negative (-) input terminal connected to the measurement node SO, a positive (+) input terminal to receive a reference voltage VREF, and an output terminal to provide the leakage current detection signal LDS.As described with reference to FIG. 17, when the comparator 571 is connected to the sensing node SO via the NMOS transistors 374 and 371 during the sensing period, it may compare the voltage level of the sensing node SO with the reference voltage VREF and provide the leakage current detection signal LDS to the control circuit 450 in FIG. 6 when the comparison indicates that the voltage level of the sensing node SO has decreased below the reference voltage VREF.In Figs. 12 and 14 to 18, it is described that the leakage current detecting operation is performed on the word lines WL1 - WLn. However, the example embodiments are not limited thereto, and the leakage current detection operation according to the example embodiments may be performed on the string selection line SSL and the ground selection line GSL in FIG. 12.FIG. 19A is a flowchart showing an example in which a leakage current detection operation is applied to an erase loop of the nonvolatile memory device.Referring to FIGS. 6 and 19A, an erase loop starts, the control circuit 450 may perform an erase operation on a selected memory block (operation S410). The control circuit 450 may perform an erase verify operation on word lines of the selected memory block (operation S 420).The control circuit 450 determines whether the word lines pass the erase operation (operation S430). When the word lines do not pass the erase verify operation (NO in operation S 430), the control circuit 450 increases an erase voltage VERS (operation S 440), and performs operations S 410, S 420, and S 430 based on the increased erase voltage.If the word lines pass the erase verify operation (YES in operation S 430), the control circuit 450 may perform the leakage current sensing operation on the word lines of the selected memory block as described above (operation S 450).The control circuit 450 may perform the leakage current sensing operation by applying a first voltage to a block word line connected to each gate of a plurality of pass transistors that connect a string selection line, a plurality of word lines, and a ground selection line to one of a plurality of drive lines, respectively, applying, during a word line device period, a second voltage to the plurality of drive lines commonly connected to a sense node to establish the plurality of word lines with a third voltage, the string selection line connected to the string selection transistor, the plurality of word lines connected to the memory cells, and the ground selection line connected to the ground selection transistor; during precharging of a plurality of drive lines with the second voltage, developing, during a word line developing period, target word lines from the plurality of word lines by applying a fourth voltage to the block word line to turn off the plurality of pass transistors; and detecting whether leakage occurs in at least a portion of the target word lines by applying a fifth voltage, which is smaller than the first voltage, to the block word line and by detecting a voltage drop of the sense node.FIG. 19B is a flowchart showing an example in which a leakage current detection operation is applied to an erase loop of the nonvolatile memory device.Referring to FIGS. 6 and 19B, an erase loop starts, the control circuit 450 performs a leakage current sensing operation on word lines of a selected memory block (operation S 510).The control circuit 450 may determine whether a leakage current is detected (or occurs) in at least a portion of the word lines of the selected memory block (operation S 520).When no leakage current is detected (NO in operation S 520), the control circuit 450 may perform a program operation on a selected word line of the selected memory block (operation S 530). The control circuit 450 may perform a program verification operation on the selected word line (operation S 540).The control circuit 450 determines that the selected word line passes the program verification operation (operation S 550). When the selected word line fails the program verification operation (NO in operation S 550), the control circuit 450 boosts a program voltage VPGM (operation S 440), and performs operations S 530, S 540, and S 550 based on the boosted program voltage.When the selected word line passes the program verification operation (YES in operation S 550), the control circuit 450 may complete the program loop.When the leakage current is detected (YES in operation S 520), the control circuit 450 may complete the program loop without performing the program operation on the selected memory block.FIG. 20A is a view illustrating a structure of the nonvolatile memory device including the first and second semiconductor layers according to example embodiments. FIG. 20B is a plan view showing a top surface of the second semiconductor layer contacting the first semiconductor layer of the nonvolatile memory device according to an exemplary embodiment. FIG. 20C is a plan view showing an upper surface of the first semiconductor layer and overlapping the plan view of FIG. 20B.In FIGS. 20A to 20C, the first and second semiconductor layers L1 and L2 are spaced apart from each other in the third direction for convenience of explanation. However, a lower surface of the first semiconductor layer L 1 and the upper surface of the second semiconductor layer L 2 actually contact each other (e.g., directly).Referring to FIGS. 20A to 20C, the first and second address decoders 301 and 303, which may be included in the address decoder 300 in FIG. 6, may extend in a direction (e.g., the second direction in which the word lines WL are arranged) perpendicular to a direction in which the word lines WL extend. In addition, the first and second page buffer circuits 411 and 413 that may be included in the page buffer circuit 410 in FIG. 6 may extend in a direction (e.g., the first direction in which the bit lines BL are arranged) perpendicular to the bit lines BL. In other words, in the nonvolatile memory device 100 having a COP structure, the address decoder 300 (see FIG. 6 ) and the page buffer circuit 410 (see FIG. 6 ) may be divided into two or more parts and arranged as shown in FIGS. 20A and 20B to increase the area of the address decoder 300 and the page buffer circuit 410 that overlap the memory cell array 200 (see FIG. 6 ) of the first semiconductor layer L 1 in the third direction.Referring to FIG. 20B, the second semiconductor layer L2 may be divided into first to fourth regions R1 to R4 by a first virtual line X0-X0' in the first direction parallel to the word lines WL and a second virtual line Y0-Y0' in the second direction parallel to the bit lines BL.For example, the first virtual line X 0-X 0' and the second virtual line Y 0-Y 0' may overlap the memory cell array 200 (see FIG. 6 ) located on the first semiconductor layer L 1 in the third direction. In other words, at least a part of each of the first to fourth regions R 1 to R 4 may overlap the memory cell array 200 located on the first semiconductor layer L 1 in the third direction. The first and second address decoders 301 and 303 may be located in the second and third areas R2 and R3, respectively, and the first and second page buffer circuits 411 and 413 may be located in the first and fourth areas R1 and R4, respectively.Referring to FIG. 20C, the memory cell array 200 may be disposed on the first semiconductor layer L 1, and the memory cell array 200 may include a first vertical structure VS 1 and a second vertical structure VS 2. As shown in FIG. 20C, the memory cell array 200 may include a plurality of memory blocks BLKa-BLKr formed as the first and second vertical patterns VS 1 and VS 2. The memory blocks BLK 1BLKr may be arranged in the second direction. Each of the memory blocks BLKa_BLKr may include a first sub-block and a second sub-block. The memory block BLKa includes a first sub-block SBa1 and a second sub-block SBa2. The memory block BLKi includes a first sub-block SBi1 and a second sub-block SBi2. The memory block BLKr includes a first sub-block SBr 1 and a second sub-block SBr 2.As shown in FIG. 20C, the first vertical structure VS 1 may include a plurality of first sub-blocks of the memory blocks BLKa-BLKr and a plurality of first via regions EVA 11, VA 11, VA 12, and EVA 12 spaced apart from each other in a vertical direction. In addition, the second vertical structure VS 2 may include a plurality of second sub-blocks of the memory blocks BLKa-BLKr and a plurality of second via regions EVA 21, VA 21, VA 22, and EVA 22 spaced apart from each other in a second direction. The first sub-blocks may be disposed between the first via regions EVA 11, VA 11, VA 12, and EVA 12, and the second sub-blocks may be disposed between the second via regions EVA 21, VA 21, VA 22, and EVA 22.The first via regions EVA 11 and EVA 12, which are adjacent to edges in a second direction and located in the first sub-blocks, may be referred to as first and second edge via regions, respectively. The second via regions EVA 21 and EVA 22, which are adjacent to edges in a second direction and located in the second sub-blocks, may be referred to as third and fourth edge via regions, respectively.For example, in the first via regions VA 11 and VA 12, one or more first via vias may be formed, each of which passes through the first vertical structure VS 1 and is connected to the first page buffer circuit 411. In addition, in the second via regions VA 21 and VA 22, one or more second via holes may be formed, each of which passes through the second vertical pattern VS 22 and is connected to the second page buffer circuit 413. For example, the first and second edge via regions EVA 11 and EVA 12 may have one or more edge via via holes formed therein, each of which passes through the first vertical structure VS 1 and is connected to the second address decoder 603. In addition, in the third and fourth edge via regions EVA 21 and EVA 22, one or more edge via holes may be formed, each of which passes through the second vertical structure VS 22 and is connected to the first address decoder 601.FIG. 20D is a cross-sectional view of the nonvolatile memory device according to example embodiments. For example, FIG. 20D is a cross-sectional view taken along line VI-VI' of FIG. 20C, showing configurations of the first and second semiconductor layers.Referring to FIG. 20D, the second semiconductor layer L 2 may include a lower substrate L_SUB, and the second address decoder 303 and the second page buffer circuit 413 formed on the lower substrate L_SUB. In addition, the second semiconductor layer L 2 may include a plurality of first lower contacts LMC 1 electrically connected to the second address decoder 603, a first lower conductive line PM 1 electrically connected to the plurality of first lower contacts LMC 1, and a lower insulating layer IL 1 covering the plurality of first lower contacts LMC 1 and the first lower conductive line PM 1.The second address decoder 303 and the second page buffer circuit 413 may be formed on portions of the lower substrate L_SUB. In other words, the second address decoder 303 and / or the second page buffer circuit 413 may be formed by forming a plurality of transistors TR on the lower substrate L_SUB.The first semiconductor layer L 1 may include a first upper substrate U_SUB_ 1, a second upper substrate U_SUB_ 2, the first vertical structure VS 1 disposed on the first upper substrate U_SUB_ 1, and the second vertical structure VS 2 disposed on the second upper substrate U_SUB_ 2. In addition, the first semiconductor layer L 1 may include a plurality of first upper contacts UMC 1, a plurality of first bit lines BL 1, a plurality of first edge contacts EC 1, and a plurality of first upper conductive lines RPM 1 electrically connected to the first vertical structures.In addition, the first semiconductor layer L 1 may include a plurality of second upper contacts UMC 2, a plurality of second bit lines BL 2, a plurality of second edge contacts EC 2, and a plurality of second upper conductive lines RPM 2 electrically connected to the second vertical structure VS 2. In addition, the first semiconductor layer L 1 may include an upper insulating layer IL 2 covering the first and second vertical structures VS 1 and VS 2 and various conductive lines.The first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may be support layers respectively supporting the first and second gate conductor layers GS_ 1 and GS_ 2. The first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may be base substrates, for example. The first vertical structure VS 1 may include the first gate conductor layers GS_ 1 located on the first upper substrate U_SUB_ 1, and a plurality of pillars P 1 passing through the first gate conductor layers GS_ 1 and extending in the third direction on an upper surface of the first upper substrate U_SUB_ 1. The first gate conductor layers GS_ 1 may include a ground selection line GSL_ 1, word lines WL 1_ 1 to WL 4_ 1, and a string selection line SSL_ 1. The ground selection line GSL_ 1, the word lines WL 1_ 1 to WL 4_ 1, and the string selection line SSL_ 1 may be sequentially formed on the first upper substrate U_SUB_ 1, and an insulating layer 52 may be disposed below or above each of the first gate conductor layers GS_ 1. Since the configurations corresponding to the first and second vertical patterns VS1 and VS2 in the cross-sectional view taken along the line VI-VI' of the first memory block BLK1 of FIG. 20D, repeated explanation of the elements of the second vertical pattern VS2 corresponding to those of the first vertical pattern VS1 may be omitted.The second vertical structure VS 2 may include a plurality of pillars P 2 passing through the second gate conductor layers GS_ 2. Each of the pillars P 2 may include a surface layer S 2 and an inner side I 1. The second gate conductor layers GS_ 2 may include a ground selection line GSL 2, word lines WL 1_ 2 to WL 4_ 2, and a string selection line SSL_ 2. An insulating layer 62 may be disposed under or over each of the second gate conductor layers GS_ 2.Each of the plurality of pillars P 1 may include a surface layer S 1 and an interior I 1. For example, the surface layer S 1 of each of the pillars P 1 may include a silicon material doped with a dopant or a silicon material not doped with a dopant.For example, the ground selection line GSL_ 1 and a portion of the surface layer S 1 adjacent to the ground selection line GSL_ 1 may form the ground selection transistor GST (see FIG. 6 ). In addition, the word lines WL 1_ 1 to WL 4_ 1 and a portion of the surface layer S 1 adjacent to the word lines WL 1_ 1 to WL 4_ 1 may form the memory cell transistors MC 1_MC 8 (see FIG. 6 ). In addition, the string selection line SSL_ 1 and a portion of the surface layer S 1 adjacent to the string selection line SSL_ 1 may form the string selection transistor SST (see FIG. 6 ).A drain region DR 1 may be formed on the pillar P 1. A drain region DR 2 may be formed on the pillar P 2. The drain region DR 1 may include, for example, a silicon material doped with a dopant. An etch stop layer 53 may be formed on a sidewall of the drain region DR 1. An etch stop layer 63 may be formed on a sidewall of the drain region DR 2.The first vertical structure VS 1 may include a peripheral region EG 1. The second vertical structure VS 2 may include a peripheral region EG 2. As shown in FIG. 20D, a cross section of the edge portion EG 1 may form a stepped pad structure. The stepped pad structure may be referred to as a "wordline pad". The plurality of first edge contacts EC 1 may be connected to the edge region EG 1, and an electrical signal may be applied from a peripheral circuit, e.g., the second address decoder 603, via the first edge contacts EC 1. For example, a contact plug MCP 1 passing through the first vertical structure VS_ 1, the first upper substrate U_SUB_ 1, and a part of the second semiconductor layer L 2 may be electrically connected to the first lower conductive path PM 1 on one side and to the peripheral region EG 1 via the first upper conductive paths RPM 1 on the other side.At least some of the first edge contacts EC 1 may pass through portions of the first and second semiconductor layers L 1 and L 2 in the third direction between the first and second upper substrates U_SUB_ 1 and U_SUB_ 2, and may have a side electrically connected to a contact plug connected to the lower conductive line (e.g., PM 1).FIG. 20E is a cross-sectional view taken along line VII-VII' of FIG. 20C, showing the configurations of the first and second semiconductor layers. For example, FIG. 20E may be a cross-sectional view showing the second semiconductor layer L 2 overlapping the first sub-block SB_ 1 and the via regions VA 11 and VA 21 provided in the first semiconductor layer L 1. Repeated explanation of the same elements in FIG. 20D may be omitted in FIG. 20C.Referring to FIG. 20E, a plurality of via holes THV 1 passing through the first vertical pattern VS 1, the first upper substrate U_SUB_ 1, and a part of the second semiconductor layer L 2 may be formed in the first via region VA 11. Each of the through hole via THV 1 may include an insulating layer pattern IP 4 and a conductive pattern MP 4.As shown in FIG. 20E, each of the through-hole vias THV may electrically connect the second page buffer 413 and the second upper contact UMC 2. A plurality of through hole vias THV 2 passing through the second vertical structure VS 2, the second upper substrate U_SUB_ 2, and a part of the second semiconductor layer L 2 may be formed in the second via region VA 21. Each of the through hole vias THV 2 may include an insulating layer pattern IP 3 and a conductive pattern MP 3.As shown in FIG. 20E, each of the through-hole vias THV 2 may electrically connect the second page buffer circuit 413 and the second upper contact UMC 2, and each of the through-hole vias THV 2 may electrically connect the second page buffer circuit 413 and the first upper contact UMC 1. The first upper contact UMC 1 may be connected to the first bit line BL 1. The second upper contact UMC 2 may be connected to the second bit line BL 2.In other words, the first bit lines BL 1 may be electrically connected to the second page buffer circuit 413 formed on the second semiconductor layer L 2 via the plurality of through-hole vias THV 1 formed in the first via region VA 11, and the second bit lines BL 2 may be electrically connected to the second page buffer circuit 413 formed on the second semiconductor layer L 2 via the plurality of through-hole vias THV 2 formed in the second via region VA 21. In example embodiments, no conductive patterns, e.g., contacts, may be formed in the edge region EG_V 1 of the first via region VA 11 and in the edge region EG_V 2 of the second via region VA 21.FIG. 21 is a circuit diagram illustrating a structure of a memory cell array according to example embodiments, and FIG. 22 is a perspective view illustrating a memory block corresponding to a structure of FIG. 21.FIG. 21 shows a two-dimensional version of a memory block including cell strings connected to a bit line BL and a source line CSL, but it should be understood that the memory block may have a three-dimensional structure with a plurality of bit lines as described with reference to FIGS. 7 and 8.Referring to FIGS. 21 and 22, a memory block may include a plurality of cell strings STR 1STRm connected between a bit line BL and a source line CSL. The cell strings STR1_STRm may include string selection transistors SST1_SSTm controlled by string selection lines SSL1_SSLm, memory cells controlled by word lines WL, intermediate switching transistors MST1_MSTm controlled by an intermediate switching line MSL, and a ground selection transistor GST1_GSTm controlled by a ground selection line GSL. Here, m is a natural number larger than 1. the memory cells connected to word lines arranged in edge portions of the stacks ST 1 and ST 2 may be dummy cells.FIG. 21 shows an exemplary embodiment in which the ground selection transistors GST1 - GSTm are connected to the same ground selection line GSL. In other exemplary embodiments, the ground selection transistors are connected to the respective ground selection lines.In some example embodiments, as illustrated in FIGS. 21 and 22, the boundary portion BND may include a gate line MSL that simultaneously switches or activates the intermediate switching transistors connected thereto.To perform the leakage current sensing operation according to example embodiments, the control circuit 450 may turn on the switching transistors MST 1_MSTm therebetween to perform a leakage current sensing operation on word lines of the upper stack ST 2. After the leakage current sensing operation is completed on word lines of the upper stack ST 2, the control circuit 450 may turn off the switching transistors MST 1_MSTm therebetween to perform a leakage current sensing operation on word lines of the lower stack ST 1.FIG. 23 is a cross-sectional view for describing an example of a boundary portion included in a memory block according to example embodiments.Referring to FIG. 23, a channel hole of each cell string STR may include a first sub-channel hole 610 and a second sub-channel hole 630. A channel hole may also be referred to as a column. The first sub-channel hole 610 may include a channel layer 611, an inner material 612, and an insulating layer 613. The second sub-channel hole 630 may include a channel layer 631, an inner material 632, and an insulating layer 633. The channel layer 611 of the first channel hole 610 may be connected to the channel layer 631 of the second sub-channel hole 630 through a P-type silicone pad SIP. The sub-channel holes 610 and 630 may be formed using a stopper layer GTL 5 having an appropriate etching rate. For example, the stop layer GTL5 may be formed of polysilicon and the other gate lines GTL1GTL4 and GTL6GTL8 may be formed of metal such as tungsten to achieve the appropriate etch rate.The boundary portion BND described above may correspond to the stop layer GTL 5 used to form the plurality of sub-channel holes. The cells in the stop layer GTL 5 may be unsuitable for storing data, and the stop layer may be used as the boundary portion BND to the switching transistors therebetween. Example embodiments are not limited to a boundary portion of a stop layer, and the boundary portion may include two or more gate layers.FIG. 24 is a block diagram illustrating a storage device including a nonvolatile memory device according to an exemplary embodiment.Referring to FIG. 24, a storage device 1000 includes a plurality of nonvolatile storage devices 1100 and a controller 1200. The storage device 1000 may be, for example, any storage device such as an embedded multimedia card (eMMC), a universal flash memory (UFS), a solid state disc or a solid state drive (SSD), etc.The controller 1200 may be connected to the nonvolatile memory devices 1100 via a plurality of channels CCH 1, CCH 2, CCH 3,..., CCHk. The controller 1200 may include one or more processors 1210, a buffer memory 1220, an error correction code (ECC) engine 1230, a host interface 1250, and a non-volatile memory (NVM) interface 1260.The buffer memory 1220 may store data used for driving the controller 1200. The ECC circuit 1230 may calculate error correction code values of data to be programmed during a program operation, and may correct an error of read data using an error correction code value during a read operation. In a data recovery operation, the ECC engine 1230 may correct an error of data recovered from the nonvolatile devices 1100. The host interface 1250 may provide an interface to an external device. The nonvolatile memory interface 1260 may provide an interface to the nonvolatile memory devices 1100.Each of the nonvolatile memory devices 1100 may correspond to the nonvolatile memory device according to example embodiments, and may be optionally supplied with an external high voltage VPP.FIG. 25 is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment.Referring to FIG. 25, a nonvolatile memory device or a memory device 2000 may have a chip-to-chip structure (C 2C). The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell region or a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer separated from the first wafer, and then bonding (or bonding) the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip to a bonding metal formed on an uppermost metal layer of the lower chip. The bond metals may include copper (Cu), for example, and form a Cu-to-Cu interconnection. However, example embodiments are not limited thereto. The bond metals can also consist, for example, of aluminum (Al) or tungsten (W).Each of the peripheral circuit region PERI and the cell region CELL of the memory device 2000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.The peripheral circuit region PERI may include a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements 2220 a, 2220 b, and 2220 cformed on the first substrate 2210, first metal layers 2230 a, 2230 b, and 2230 cconnected to the plurality of circuit elements 2220 a, 2220 b, and 2220 c,respectively, and second metal layers 2240 a, 2240 b, and 2240 cformed on the first metal layers 2230 a, 2230 b, and 2230 c. In an exemplary embodiment, the first metal layers 2230 a, 2230 b, and 2230 cmay be formed of tungsten having a relatively high electrical resistance, and the second metal layers 2240 a, 2240 b, and 2240 cmay be formed of copper having a relatively low electrical resistance.Although only the first metal layers 2230 a, 2230 b, and 2230 cand the second metal layers 2240 a, 2240 b, and 2240 care shown and described in an exemplary embodiment illustrated in FIG. 25, exemplary embodiments are not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 2240 a, 2240 b, and 2240 c. At least a portion of the one or more additional metal layers formed on the second metal layers 2240 a, 2240 band 2240 cmay be formed of aluminum or the like having a lower electrical resistivity than copper from which the second metal layers 2240 a, 2240 band 2240 care formed.The interlayer insulating layer 2215 may be disposed on the first substrate 2210 and cover the plurality of circuit elements 2220 a, 2220 band 2220 c, the first metal layers 2230 a, 2230 band 2230 c, and the second metal layers 2240 a, 2240 band 2240 c. The interlayer insulating layer 2215 may include an insulating material such as silicon oxide, silicon nitride, or the like.Lower bonding metals 2271 band 2272 bmay be formed on the second metal layer 2240 bin the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271 band 2272 bin the peripheral circuit region PERI may be electrically connected to the upper bonding metals 2371 band 2372 bof the cell region CELL. The lower bonding metals 2271 band 2272 band the upper bonding metals 2371 band 2372 bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bond metals 2371 band 2372 bin the cell region CELL may be referred to as first metal pads and the lower bond metals 2271 band 2272 bin the peripheral circuit region PERI may be referred to as second metal pads.The cell area CELL may include at least one memory block. The cell region CELL may include a second substrate 2310 and a common source line 2320. On the second substrate 2310, a plurality of word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, and 2338 (i.e., 2330) may be stacked in a third direction D3 (e.g., a Z-axis direction), perpendicular to an upper surface of the second substrate 2310. At least one string selection line and at least one ground selection line may be disposed on or below the plurality of word lines 2330, and the plurality of word lines 2330 may be disposed between the at least one string selection line and the at least one ground selection line.In the bit line bonding region BLBA, a channel pattern CH may extend in the third direction D 3 (e.g., the Z-axis direction) perpendicular to the upper surface of the second substrate 2310, and pass through the plurality of word lines 2330, the at least one string selection line, and the at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer 2350 cand a second metal layer 2360 c. For example, the first metal layer 2350 cmay be a bit line contact and the second metal layer 2360 cmay be a bit line. In an exemplary embodiment, the bit line 2360 cmay extend in a second direction D 2 (e.g., in the Y-axis direction), parallel to the top surface of the second substrate 2310.As illustrated in FIG. 23, a region where the channel pattern CH, the bit line 2360 c, and the like are disposed may be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 2360 cmay be electrically connected to the circuit elements 2220 cprovided a page buffer 2393 in the peripheral circuit region PERI. The bit line 2360 cmay be connected to the upper bond metals 2371 cand 2372 cin the region of the cell CELL, and the upper bond metals 2371 cand 2372 cmay be connected to the lower bond metals 2271 cand 2272 cand to the circuit elements 2220 cof the page buffer 2393.In the word line bonding region WLBA, the plurality of word lines 2330 may extend in a first direction D 1 (e.g., an X-axis direction) parallel to the upper surface of the second substrate 2310 and perpendicular to the second direction D 2, and may be connected to a plurality of cell contact plugs 2341, 2342, 2343, 2344, 2345, 2346, and 2347 (i.e., 2340). The plurality of word lines 2330 and the plurality of cell contact plugs 2340 may be connected to each other via pads provided by at least a portion of the plurality of word lines 2330 extending in different lengths in the first direction D 1. A first metal layer 2350 band a second metal layer 2360 bmay be sequentially connected to an upper portion of the plurality of cell contact plugs 2340 connected to the plurality of word lines 2330. The plurality of cell contact plugs 2340 may be connected to the peripheral circuit region PERI through the upper bonding metals 2371 band 2372 bof the cell region CELL and the lower bonding metals 2271 band 2272 bof the peripheral circuit region PERI in the word line bonding region WLBA.The plurality of cell contact plugs 2340 may be electrically connected to the circuit elements 2220 bforming a row decoder 2394 in the peripheral circuit region PERI. In an exemplary embodiment, the operating voltages of circuit elements 2220b forming row decoder 2394 may be different than the operating voltages of circuit elements 2220c forming page buffer 2393. For example, operating voltages of circuit elements 2220c forming page buffer 2393 may be greater than operating voltages of circuit elements 2220b forming row decoder 2394.A common source line contact plug 2380 may be disposed in the external pad bonding region PA. The common source line contact plug 2380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line 2320. A first metal layer 2350 aand a second metal layer 2360 amay be sequentially stacked on an upper portion of the common source line contact plug 2380. For example, a region where the common source line contact plug 2380, the first metal layer 2350 a, and the second metal layer 2360 aare disposed may be defined as the external pad bonding region PA.Input / output pads 2205 and 2305 may be disposed in the external pad bonding area PA. A lower insulating layer 2201 covering a lower surface of the first substrate 2210 may be formed under the first substrate 2210, and a first input / output pad 2205 may be formed on the lower insulating layer 2201. The first input / output pad 2205 may be connected to at least one of the plurality of circuit elements 2220 a, 2220 b, and 2220 cdisposed in the peripheral circuit region PERI via a first input / output contact plug 2203, and may be separated from the first substrate 2210 by the lower insulating layer 2201. In addition, a lateral insulating layer may be disposed between the first input / output contact plug 2203 and the first substrate 2210 to electrically separate the first input / output contact plug 2203 and the first substrate 2210.An upper insulating layer 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and a second input / output pad 2305 may be disposed on the upper insulating layer 2301. The second input / output pad 2305 may be connected to at least one of the plurality of circuit elements 2220 a, 2220 b, and 2220 cdisposed in the peripheral circuit region PERI via a second input / output contact plug 2303. In the exemplary embodiment, the second input / output pad 2305 is electrically connected to a circuit element 2220 a.According to example embodiments, the second substrate 2310 and the common source line 2320 may not be disposed in a region where the second input / output contact plug 2303 is disposed. In addition, the second input / output pad 2305 may not overlap the word lines 2330 in the third direction D 3 (e.g., in the Z-axis direction). The second input / output contact plug 2303 may be separated from the second substrate 2310 in a direction parallel to the top surface of the second substrate 2310, and may pass through the interlayer insulating layer 2315 of the cell region CELL to be connected to the second input / output pad 2305.According to example embodiments, the first input / output pad 2205 and the second input / output pad 2305 may be selectively formed. For example, the memory device 2000 may include only the first input / output pad 2205 disposed on the first substrate 2210 or the second input / output pad 2305 disposed on the second substrate 2310. Alternatively, the storage device 2000 may include both the first input / output pad 2205 and the second input / output pad 2305.A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern, or the uppermost metal layer may be absent, in each of the external pad bonding region PA and the bit line bonding region BLBA included in the cell region and the peripheral circuit region PERI, respectively.In the external pad bonding region PA, the memory device 2000 may include a lower metal pattern 2273 athat corresponds to an upper metal pattern 2372 aformed in an uppermost metal layer of the cell region CELL and that has the same cross-sectional shape as the upper metal pattern 2372 aof the cell region CELL to be connected to each other in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 2273 aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern 2372 athat corresponds to the lower metal pattern 2273 aformed in an uppermost metal layer of the peripheral circuit region PERI and has the same shape as a lower metal pattern 2273 aof the peripheral circuit region PERI may be formed in an uppermost metal layer of the cell region CELL.The lower bonding metals 2271 band 2272 bmay be formed on the second metal layer 2240 bin the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271 band 2272 bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals 2371 band 2372 bof the cell region CELL through a Cu-to-Cu bond.Further, in the bit line bonding region BLBA, an upper metal pattern 2392 corresponding to a lower metal pattern 2252 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same cross-sectional shape as the lower metal pattern 2252 of the peripheral circuit region PERI may be formed in an uppermost metal layer of the cell region CELL. No contact may be formed on the upper metal pattern 2392 formed in the uppermost metal layer of the cell region CELL.In an exemplary embodiment corresponding to a metal pattern formed in an uppermost metal layer in one of the cell area CELL and the peripheral circuit area PERI, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other of the cell area CELL and the peripheral circuit area PERI. No contact may be formed on the reinforcing metal pattern.The above-mentioned first to fifth voltages may be applied to at least one memory block in the cell area CELL via the lower bond metals 2271 band 2272 bin the peripheral circuit area PERI and the upper bond metals 2371 band 2372 bof the cell area CELL. The control circuit may perform the leakage current sensing operation by, while applying a first voltage to a block word line connected to each gate of a plurality of pass transistors connecting a string selection line, a plurality of word lines, and a ground selection line to a respective one of a plurality of drive lines, applying a second voltage to the plurality of drive lines commonly connected to a sense node to establish the plurality of word lines with a third voltage during a word line establishment period, the string selection line being connected to the string selection transistor, the plurality of word lines being connected to the memory cells, and the ground selection line being connected to the ground selection transistor; during precharging of a plurality of drive lines with the second voltage, developing target word lines from the plurality of word lines by applying a fourth voltage to the block word line to turn off the plurality of pass transistors during a word line developing period; and detecting a leakage current of at least a portion of the target word lines by applying a fifth voltage, which is less than the first voltage, to the block word line and by detecting a voltage drop of the sense node.A nonvolatile memory device or a storage device according to an exemplary embodiment may be packaged using various types of packages or configurations of packages.At least one of the buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other element represented by a block as shown in FIGS. 5, 6, 11-17, and 24 may be embodied as a hardware, software, and / or firmware structure that performs the respective functions described above, according to example embodiments. For example, at least one of buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other element may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc., that may perform the respective functions through the control of one or more microprocessors or other devices. Also, at least one of buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other element may be specifically embodied by a module, program, or portion of code that includes one or more executable instructions for performing certain logic functions and executed by one or more microprocessors or other devices. In addition, at least one of buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other element may include or be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Two or more of the buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other elements may be combined into a single component, element, module, or unit that performs all operations or functions of the combined two or more of buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other elements. Also, at least a portion of the functions of at least one of buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other elements may be taken over by another of these components. Although a bus is not shown in each of the above block diagrams, communication between the components may be performed via the bus. Functional aspects of the above example embodiments may be implemented using algorithms executing on one or more processors. Moreover, the buffers, control circuits, controllers, decoders, drivers, engines, generators, I / O circuits, interfaces, leakage current detectors, processors, or other elements represented by a block or processing steps may use any related techniques for electronic configuration, signal processing and / or control, data processing, and the like.The inventive concept may be applied to various devices and systems including the nonvolatile memory devices. For example, the inventive concept may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smartphone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a portable device, an Internet of Things (IoT) device, an Internet of Things (IoE) device, an E-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robot device, a drone, etc. can be applied.

Claims

An operation method of a nonvolatile memory device (100) comprising at least one memory block (BLK) including a plurality of cell strings (NS11~NS33; STR1~STRm), each of which includes a string selection transistor (SST; SST1~SSTm), a plurality of memory cells (MC1~MC8), and a ground selection transistor (GST; GST1~GSTm) connected in series and arranged in a vertical direction between a bit line (BL; BL1~BL3) and a source line (CSL), the method comprising: during (S100) a word line establishment period (WL_STP), and during application of a first voltage (V11; V21; V31), to a block word line (BLKWL) connected to each gate of a plurality of pass transistors (GPT; PT1~PTn; SSPT) each connecting a string selection line (SSL; SSL1~SSLm), a plurality of word lines (WL; WL1~WLn) and a ground selection line (GSL; GSL1~GSL3) to a plurality of drive lines (S1~Sn), apply a second voltage (V12; V22; V32) to the plurality of drive lines (S1~Sn) commonly connected to a sense node (SO) around the plurality of word lines (WL; wl1wln) to provide a third voltage (V13; V23; V33), wherein the string selection line (SSL; SSL1~SSLm) is connected to the string selection transistor (SST; SST1STm), the plurality of word lines (WL; WL1WLn) is connected to the plurality of memory cells (MC1WLMC8), and the ground selection line (GSL; GSL1~GSL3) is connected to the ground selection transistor (GST; GST1GSTm); during (S200) a word line developing period (DVL), and during precharging of the plurality of drive lines (S1~Sn) with the second voltage (V12; V22; V32), application of a fourth voltage (V14; V24; V34) to the block word line (BLKWL) to turn off the plurality of pass transistors (GPT; PT1~PTn; SSPT) to develop target word lines from the plurality of word lines (WL; WL1~WLn); and during (S300) a measurement period (SEN), application of a fifth voltage (V15; V25) smaller than the first voltage (V11; V21; V 31) is, to the block word line (BLKWL), detecting a voltage drop of the sensing node (SO), and detecting a leakage current (LKG) of the target word lines based on the voltage drop.The method of claim 1, wherein: the measurement period (SEN) precedes a program operation of a program loop on the at least one memory block (BLK), and the method further comprises terminating the program loop based on determining that the leakage current (LKG) occurs in at least one (WLk) of the plurality of word lines (WL; WL1WLn).The method of claim 1, wherein during the word line device period (WL_STP), a level of the second voltage (V12) is greater than a level of the first voltage (V11), and a level of the third voltage (V13) is less than the level of the first voltage (V11) by a first threshold voltage (Vt1).The method of claim 3, wherein during the measurement period (SEN), a level of the fifth voltage (V15; V25; V35) is greater than a level of each of the target word lines by the first threshold voltage, and the method further comprises: determining that the leakage current (LKG) has occurred in a word line connected to at least one pass transistor of the plurality of pass transistors (GPT; PT1-PTn; SSPT) that is turned on by the fifth voltage (V15).The method of claim 1, wherein during the word line device period (WL_STP), a level of the first voltage (V21; V31) is greater than a level of the second voltage (V22; V32), and a level of the third voltage (V23; V33) is substantially equal to the level of the second voltage (V22; V32).The method of claim 5, wherein during the measurement period (SEN), a level of the fifth voltage (V15; V25; V35) is greater than a level of each of the target word lines by a first threshold voltage, and the method further comprises: determining that the leakage current (LKG) has occurred in a word line (WLk) connected to at least one pass transistor of the plurality of pass transistors (GPT; PT1-PTn; SSPT) that is turned on by the fifth voltage (V15; V25; V35).The method of claim 1, wherein the plurality of drive lines (S1 ~Sn) are connected to the sensing node (SO) through a plurality of selection switches.The method of claim 7, wherein the target word lines correspond to those of the plurality of word lines (WL; WL1WLn) selected by activation of the plurality of selection switches.The method of claim 7, wherein the destination word lines correspond to either even word lines or odd word lines selected from the plurality of word lines (WL; WL1 - WLn) by activating a part of the plurality of selection switches.The method of claim 1, further comprising performing (S410) an erase operation on the at least one memory block (BLK), wherein the detecting (S450) the leakage current (LKG) of the target word lines is performed after the erase operation.A nonvolatile memory device comprising: at least one memory block (BLK) including a plurality of cell strings (NS11_NS33; STR1_STRm), wherein each of the plurality of cell strings (NS11_NS33; STR1_STRm) includes a string selection transistor (SST; SST1_SSTm), a plurality of memory cells (MC1_MC8), and a ground selection transistor (GST; GST1_GSTm) connected in series and arranged in a vertical direction between a bit line (BL; BL1_BL3) and a source line (CSL); A control circuit (450) configured to control a leakage current sensing operation by: during (S100) a word line device period (WL_STP), and during application of a first voltage (V11; V21; V31) to a block word line (BLKWL) connected to each gate of a plurality of pass transistors (GPT; PT1_PTn; SSPT), each including a string selection line (SSL; SSL1~SSLm), a plurality of word lines (WL; WL1_WLn), and a ground selection line (GSL; gsl1~gsl3) having a plurality of drive lines (S1~Vl), applying a second voltage (V12; V22; V32) to the plurality of drive lines (S1~Vl) commonly connected to a sense node (SO) to provide a third voltage (V13; V23; V33) to the plurality of word lines (WL; WL1~WLn), the string select line (SSL; SSL1~SSLm) being connected to the string select transistor (SST; SST1~SSTm), the plurality of word lines (WL; wl1wln) is connected to the plurality of memory cells (MC1WMC8), and the ground selection line (GSL; GSL1~GSL3) is connected to the ground selection transistor (GST; GST1WGSTm); during (S200) a word line development period (DVL) and during precharging of the plurality of drive lines (S1wln) with the second voltage (V12; V22; V32), application of a fourth voltage (V14; V24; V34) to the block word line (BLKWL) by the plurality of pass transistors (GPT; PT1WPTn; SSPT) to develop target word lines from the plurality of word lines (WL; WL1WLn); and during (S300) a measurement period (SEN), apply a fifth voltage (V15; V25; V35) smaller than the first voltage (V11; V21; V31) to the block word line (BLKWL), detect a voltage drop of the measurement node (SO), and detect a leakage current (LKG) of the target word lines based on the voltage drop.The nonvolatile memory device of claim 11, wherein: the control circuit (450) is configured to perform the leakage current sensing operation during a program operation (S530) of a program loop on the at least one memory block (BLK); and the control circuit (450) is configured to end the program loop on the at least one memory block (BLK) based on the leakage current (LKG) occurring in at least one (WLk) of the plurality of word lines (WL; WL1WLn).The nonvolatile memory device of claim 11, further comprising: a voltage generator (500) configured to generate word line voltages (VWLs) based on a control signal (CTL); an address decoder (300) configured to provide the word line voltages (VWLs) to the at least one memory block (BLK); and a leakage current detector (570) connected to the sensing node (SO), wherein the address decoder (300) comprises: a pass switch circuit (360) including a plurality of pass transistors (GPT; PT1_PTn; SSPT); a first voltage transfer circuit (340b); a second voltage transmission circuit (370) connected to the voltage generator (500) and the first voltage transmission circuit (340b) at the measurement node (SO); and a selection switch circuit (340a) connected between the first voltage transmission circuit (340b) and the plurality of drive lines (S1~Sn), the selection switch circuit (340a) including a plurality of selection transistors configured to connect the first voltage transmission circuit (340b) to the plurality of drive lines (S1~Sn).The nonvolatile memory device of claim 13, wherein the control circuit (450) is configured to control the voltage generator (500) and the address decoder (300) such that: a level of the second voltage (V12) is greater than a level of the first voltage (V11), and during the word line establishment period (WL_STP), a level of the third voltage (V13) is less than the level of the first voltage (V11; V21; V31) by a first threshold voltage (Vt1); and during the sensing period (SEN), a level of the fifth voltage (V15) is greater than a level of each of the target word lines by the first threshold voltage (Vt1), and wherein the leakage current detector (570) is configured to determine that a leakage current (LKG) is occurring based on a voltage level of the sensing node (SO) dropping during the sensing period (SEN).The nonvolatile memory device of claim 13, wherein the control circuit (450) is configured to control the voltage generator (500) and the address decoder (300) such that: a level of the first voltage (V21; V31) is greater than a level of the second voltage (V22; V32), and during the word line establishment period (WL_STP), a level of the third voltage (V23; V33) approximately corresponds to the level of the second voltage (V22; V32); and during the measurement period (SEN), a level of the fifth voltage (V25; V35) is greater than a level of each of the target word lines by a first threshold voltage, and wherein the leakage current detector (570) is configured to determine that a leakage current (LKG) is occurring based on a voltage level of the sense node (SO) dropping during the sense period (SEN).The nonvolatile memory device according to claim 13, wherein the control circuit (450) is configured to perform the leakage current detection operation on all of the plurality of word lines (WL; WL1WLn) simultaneously by activating the plurality of selection transistors during the word line development period (DVL) and the sensing period (SEN).The nonvolatile memory device of claim 13, wherein the control circuit (450) is configured to perform the leakage current sensing operation on a part of the plurality of word lines (WL; WL1WLn) simultaneously by activating a part of the plurality of selection transistors during the word line development period (DVL) and the sensing period (SEN).The non-volatile memory device of claim 13, wherein the leakage current detector (570) comprises a comparator (571) configured to perform a comparison of a voltage level of the sensing node (SO) with respect to a reference voltage (VREF), and provide a detection signal (LDS) to the control circuit (450) based on a result of the comparison.The nonvolatile memory device of claim 11, wherein the plurality of cell strings (NS11_NS33; STR1_STRm) are divided into a plurality of vertically arranged stacks (ST1, ST2), wherein the at least one memory block (BLK) further includes a plurality of intermediate switching transistors (MST1~MSTm) arranged in a boundary portion (BND) between two adjacent stacks (ST1, ST2) in the vertical direction, wherein the plurality of intermediate switching transistors (MST1~MSTm) are configured to perform a switching operation to control a respective electrical connection of the plurality of cell strings (STR1_STRm), and wherein the control circuit (450) is configured to:, controlling the leakage current detecting operation by controlling the switching operation of the plurality of switching transistors (MST1~MSTm) therebetween.A nonvolatile memory device comprising: at least one memory block (BLK) including a plurality of cell strings (NS11~NS33; STR1~STRm), each of which includes a string selection transistor (SST; SST1~SSTm), a plurality of memory cells (MC1~MC8), and a ground selection transistor (GST; GST1~GSTm) connected in series and arranged in a vertical direction between a bit line (BL; BL1~BL3) and a source line (CSL); a voltage generator (500) configured to generate word line voltages (VWLs) based on a control signal (CTL); an address decoder (300) configured to provide the word line voltages (VWLs) to the at least one memory block (BLK); a leakage current detector (570) connected to the address decoder (300) at a sensing node (SO); and a control circuit (450) configured to control the voltage generator (500), the address decoder (300), and the leakage current detector (570), wherein the control circuit (450) is configured to control a leakage current sensing operation by: during (S 100) a word line device period (WL_STP), and during application of a first voltage (V11; V21; V31) to a block word line (BLKWL) connected to each gate of a plurality of pass transistors (GPT; pt1~ptn; SSPT) each connecting a string selection line (SSL; SSL1~SSLm), a plurality of word lines (WL; WL1~WLn) and a ground selection line (GSL; GSL1~GSL3) to a respective one of a plurality of drive lines (S1~Sn), applying a second voltage (V12; V22; V32) to the plurality of drive lines (S1~Sn) commonly connected to the sense node (SO) to apply a third voltage (V13; V23; to the plurality of word lines (WL; WL1~WLn); V33), wherein the string selection line (SSL; SSL1~SSLm) is connected to the string selection transistor (SST; SST1~SSTm), the plurality of word lines (WL; WL1~WLn) is connected to the plurality of memory cells (MC1~MC8), and the ground selection line (GSL; GSL1~GSL3) is connected to the ground selection transistor (GST; GST1~GSTm); during (S200) a word line development period (DVL) and during pre-charging the plurality of driver lines (S1~Sn) with the second voltage (V12; V22; V32), apply a fourth voltage (V14; V24; V34) to the block word line (BLKWL) to turn off the plurality of pass transistors (GPT; PT1~PTn; SSPT) to develop target word lines from the plurality of word lines (WL; WL1~WLn); and during (S300) a sensing period (SEN), apply a fifth voltage (V15; V25; V35) being less than the first voltage to the block word line (BLKWL), detecting a voltage drop of the sense node (SO), and detecting a leakage current (LKG) of the target word lines based on the voltage drop, wherein the control circuit (450) is configured to perform the leakage current detection operation during a program operation (S530) of a program loop on the at least one memory block (BLK), and wherein the control circuit (450) is configured to end the program loop on the at least one memory block (BLK) based on the leakage current (LKG) occurring in at least one of the plurality of word lines (WL; WL1 -WLn).

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