Semiconductor component with varying numbers of channel layers and methods for its manufacture

Abstract

Method comprising: providing a structure with a front and a back, the structure comprising a substrate (201), two or more semiconductor channel layers (215) arranged above the substrate (201) connecting a first source / drain structural element (S / D structural element) (260) and a second S / D structural element (260), and a gate structure (240) engaging the semiconductor channel layers (215), wherein the substrate (201) is located on the back of the structure and the gate structure (240) is located on the front of the structure; recessing the first S / D structural element (260) to expose a terminal end of one of the semiconductor channel layers (215);and depositing a dielectric layer (276) on the first S / D structural element (260) and thereby covering the exposed terminal end of one of the semiconductor channel layers (215), wherein one of the semiconductor channel layers (215) is the bottom semiconductor channel layer (215a) in the structure, and the etching of the first S / D structural element (260) comprises etching the first S / D structural element (260) from the back side of the structure.

Description

BACKGROUNDThe industry of integrated circuit (IC) has experienced exponential growth. Technical advances in IC materials and design have produced generations of ICs, each generation having smaller and more complex circuits than the previous generation. As IC development progresses, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry size (i.e., the smallest component (or line) that can be generated using a fabrication process) has decreased. This downsizing process generally offers advantages by improving production efficiency and lowering the associated cost. This downsizing has also increased the complexity of processing and manufacturing ICs.For example, as IC technologies develop toward smaller technology nodes, multigate devices have been introduced to improve gate control by enhancing gate channel coupling, reducing reverse current, and reducing short channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed over more than one side of a channel region. Gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high-power and low-leakage applications. GAA transistors get their name from the gate structure, which may extend around the channel region, thereby allowing access to the stacked semiconductor channel layers on four sides. Such a configuration provides better channel control compared to planar transistors and significantly reduces SCEs (particularly by reducing subthreshold leakage). The number of stacked semiconductor channel layers is selected based on considerations on device performance, particularly current driving capability of the transistors.IC devices include transistors that perform different functions, such as input / output (I / O) functions and kernel functions. These different functions require the transistors to be constructed differently. At the same time, it is advantageous to fabricate these different transistors with similar processes and in similar process windows to reduce cost and improve yield. While the existing GAA transistors and processes are generally suitable for intended purposes, they are not fully satisfactory in all respects. For example, in an IC chip, there are various regions that perform various functions, such as high power consumption regions for a high performance computing (HPC) unit or a central processing unit (CPU) that requires GAA transistors having high current driving capability to achieve high speed operation, and low power consumption regions for I / O or system on chip (SoC) units that require GAA transistors having low current driving capability to achieve low leakage current. Accordingly, the number of stacked semiconductor channel layers required in GAA transistors in different regions on an IC chip may be different. Thus, the manner in which different numbers of stacked semiconductor channel layers suitable for different applications may be achieved on a chip presents a challenge to the semiconductor industry in the development of integrated circuits. The present disclosure aims to solve the above problems and other related problems.With regard to the prior art, reference is made to the publications U.S. Pat. No. 2018 / 0 090 624 A1, U.S. Pat. No. 9,660,028 B1, U.S. Pat. No. 2019 / 0 157 310 A1 and U.S. Pat. No. 2010 / 0 295 021 A1.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with common industry practice, various features are not drawn to scale and are for illustration purposes only. Indeed, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1A and 1B show a flow chart of a method for forming a semiconductor device having different numbers of stacked semiconductor channel layers in different areas and back side metal wiring layers, according to various aspects of the present disclosure. FIG. 1C shows a flow chart of a method for forming a semiconductor device having different numbers of stacked semiconductor channel layers in different areas without the need for back side metal wiring layers according to various aspects of the present disclosure. FIG. 2 illustrates a top view of a portion of a semiconductor device, in accordance with some embodiments. FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A illustrate cross-sectional views along line A-A of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIGS. 1A and 1B, in accordance with some embodiments of the present disclosure. FIGS. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B illustrate cross-sectional views along line B-B of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIGS. 1A and 1B, in accordance with some embodiments of the present disclosure. FIGS. 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, and 15C illustrate cross-sectional views along line C-C of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIGS. 1A and 1B, in accordance with some embodiments of the present disclosure. FIGS. 3D, 4D, 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, 14D, and 15D illustrate cross-sectional views along line D-D of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIGS. 1A and 1B, in accordance with some embodiments of the present disclosure. FIGS. 3E, 4E, 5E, 6E, 7E, 8E, 9E, 10E, 11E, 12E, 13E, 14E, and 15E illustrate cross-sectional views along line E-E of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIGS. 1A and 1B, in accordance with some embodiments of the present disclosure. FIGS. 3F, 4F, 5F, 6F, 7F, 8F, 9F, 10F, 11F, 12F, 13F, 14F, and 15F illustrate cross-sectional views along line F-F of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIGS. 1A and 1B, in accordance with some embodiments of the present disclosure. FIGS. 16A, 17A, 18A, 19A, 20A, 21A, and 22A illustrate cross-sectional views along line A-A of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIG. 1C, in accordance with some embodiments of the present disclosure. FIGS. 16B, 17B, 18B, 19B, 20B, 21B, and 22B illustrate cross-sectional views along line B-B of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIG. 1C, in accordance with some embodiments of the present disclosure. FIGS. 16C, 17C, 18C, 19C, 20C, 21C, and 22C illustrate cross-sectional views along line C-C of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIG. 1C, in accordance with some embodiments of the present disclosure. FIGS. 16D, 17D, 18D, 19D, 20D, 21D, and 22D illustrate cross-sectional views along line D-D of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIG. 1C, in accordance with some embodiments of the present disclosure. FIGS. 16E, 17E, 18E, 19E, 20E, 21E, and 22E illustrate cross-sectional views along line E-E of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIG. 1C, in accordance with some embodiments of the present disclosure. FIGS. 16F, 17F, 18F, 19F, 20F, 21F, and 22F illustrate cross-sectional views along line F-F of the portion of the semiconductor device in FIG. 2 during manufacturing processes according to the method of FIG. 1C, in accordance with some embodiments of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments for implementing different features of the provided subject matter. In order to simplify the present disclosure, concrete examples of components and arrangements will be described below. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower / r / s," "above," "upper / r / s," and the like may be used herein to simplify the description to describe the relationship of an element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The object may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may also be interpreted accordingly. Still further, when a number or range of numbers is described as "about", "about", and the like, the term encompasses numbers within certain variations of the described number (such as + / -10%, or other variations), as would be known to one of ordinary skill in the art with respect to the specific technology disclosed herein, unless otherwise specified. For example, the term "about 5 nm" may encompass a dimensional range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.This application relates generally to semiconductor structures and fabrication processes, and more particularly to integrated circuit (IC) chips having transistors with different numbers of stacked semiconductor channel layers in different areas to enable different applications on a chip. In various embodiments, at least two gate-all-around transistors (GAA transistors) having a different (or varying) number of stacked semiconductor channel layers (e.g., nanowires or nanosheets) are disposed on the same substrate in a core region (e.g., for high power applications) and in an I / O region (for low leakage current applications), respectively, of an IC chip. Different numbers of stacked semiconductor channel layers may be implemented from the back side of a semiconductor structure or from the front side of the semiconductor structure, according to various aspects of the present disclosure.Details of the structure and the manufacturing methods of the present disclosure will be described below in conjunction with the accompanying drawings illustrating a process for manufacturing a GAA device according to some embodiments. A GAA device refers to a device having vertically stacked horizontally oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. GAA devices are promising candidates for bringing CMOS to the next phase of the design plan due to their better gate controllability, lower leakage current and complete FinFET device layout compatibility. For the sake of simplicity, the present disclosure uses a GAA device as an example. Those of ordinary skill in the art should understand that it may readily use the present disclosure as a basis for designing or modifying other processes and structures (such as FinFET devices) to perform the same purposes and / or achieve the same advantages of the embodiments introduced herein.FIGS. 1A and 1B show a flow chart of a method 10 of manufacturing a semiconductor device having back side metal wiring layers and different numbers of stacked semiconductor channel layers in different areas, according to some embodiments of the present disclosure. Metal wiring layers on the back side of a structure, such as back side power rails, increase the number of metal traces available in the structure for directly connecting to source / drain contacts and vias in addition to an interconnect structure (which may also include power rails) on the front side (or front side) of the structure. In addition, the gate density increases for greater device integration than existing structures without back side power rails. The back side power rails may have a wider dimension than the first level metal (Mo) lines on the front side of the structure, which advantageously reduces power rail resistance. The method 10 will be described below in connection with FIGS. 2-15F, which show various plan and cross-sectional views of a semiconductor device (or device) 200 at various manufacturing steps according to the method 10 in accordance with some embodiments. Additional processing steps are contemplated in the present disclosure. Additional method steps may be performed before, during, and after method 10, and in further embodiments of method 10, some of the described method steps may be moved, replaced, or omitted.In some embodiments, device 200 is a portion of an IC chip, a system-on-chip (SoC), or a portion thereof that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, further suitable components or combinations thereof. For clarity, FIGS. 2 and 3A- 15F have been simplified to provide a better understanding of the inventive concepts of the present disclosure. Additional features may be added in device 200, and some of the features described below may be replaced, modified, or omitted in other embodiments of device 200. FIG. 2 illustrates a plan view of the device 200, and FIGS. 3A to 15F illustrate cross-sectional views of a part of the device 200 along the lines A-A, B-B, C-C, D-D, E-E, and F-F in FIG. 2, respectively. In particular, the line A-A and the line D-D are cuts in the longitudinal direction of the semiconductor fins (X direction), the line B-B, and the line E-E are cuts in the source regions of the transistors and are parallel to the gate stacks of the transistors (Y direction), and the line C-C and the line F-F are cuts in the drain regions of the transistors and are parallel to the gate stacks of the transistors. It should be noted that in various embodiments, lines B-B and E-E may alternatively intersect with the drain regions of the transistors and lines C-C and F-F may alternatively intersect with the source regions of the transistors. In the present disclosure, a source and a drain are used interchangeably.In method 10 (FIG. 1A ), in method step 12 a component 200 is provided, which has a substrate 201 and transistors formed on the front side of substrate 201. Referring to FIG. 2, device 200 includes a region I for low power and / or low leakage applications, such as an I / O region, and a region II for high power and / or high speed applications, such as a core region. Region I may include I / O cells, ESD cells, and other circuitry. The area II may include high performance computing (HPC) units, central processing unit (CPU) logic circuits, memory circuits, and other core circuits.Device 200 includes a substrate 201 and a plurality of semiconductor fins (or fins) protruding from substrate 201, including a fin 204 ain region I and a fin 204 bin region II (collectively referred to as fins 204). The fins 204 are longitudinally oriented in the X direction. Each of the fins 204 may be configured to form an NFET or a PFET. Device 200 also includes a plurality of gate structures (or gate stacks) disposed over fins 204, including a gate stack 240 ain region I and a gate stack 240 bin region II (collectively referred to as gate stack 240). The gate stacks 240 are longitudinally oriented in the Y direction. The gate stacks 240 engage the fins 204 in their respective channel regions to thereby form a GAA transistor 202 ain the region I and a GAA transistor 202 bin the region II. Generally, GAA transistor 202b requires a greater current driving capability than GAA transistor 202a due to its performance-hungry applications.Referring to FIGS. 3A to 3F, the device 200 includes the substrate 201 on its back side and various elements built on the front side of the substrate 201. These elements include an isolation structure 230 over the substrate 201, where fins 204 (including fin 204 ain region I and fin 204 bin region II) extend from the substrate 201 adjacent to the isolation structure 230. In region I, device 200 includes two source / drain (S / D) features 260 aand 260 bover fin 204 a, semiconductor channel layers (or channel layers) 215 a, 215 b, 215 c, 215 dhending over fin 204 aand connecting the two S / D features 260 a / 260 b, and a gate stack 240 abetween the two S / D features 260 a / 260 bsurpping each of the channel layers. In region II, device 200 includes two source / drain (S / D) features 260 cand 260 d(collectively referred to as S / D features 260 by 260 ato 260 b) over fin 204 b, channel layers 215 e, 215 f, 215 g, 215 h(collectively referred to as channel layers 215 by 215 ato 215 d) suspended over fin 204 band connecting the two S / D features 260 c / 260 d, and a gate stack 240 bbetween the two S / D features 260 c / 260 d sheathing each of the channel layers. In each of the regions, device 200 further includes inner spacers 255 between S / D features 260 and gate stacks 240, an (outer) gate spacer 247 over sidewalls of gate stacks 240, a contact etch stop layer (CESL) 269 adjacent gate spacer 247 and over S / D features 260 and isolation structure 230, and an inter-layer dielectric layer (ILD) 270 over CESL 269. Over the S / D features 260, the device 200 further includes silicide features 273 and S / D contacts 275.Referring to FIGS. 4A to 4F, the device 200 further includes one or more interconnect layers 277 having lines and vias embedded in dielectric layers. The one or more interconnect layers 277 connect the gate, source, and drain electrodes of various transistors, as well as other circuits in the device 200 to partially or fully form an integrated circuit. The device 200 may further include passivation layers, adhesion layers and / or other layers formed on the front side of the device 200. These layers and the one or more interconnection layers are collectively denoted by reference numeral 277. Note that in FIGS. 4A to 4F, the device 200 is upside down. For simplicity, in FIGS. 4B, 4C, 4E, 4F and in the following drawings with the suffix B, C, E, F, some of the features already shown in FIGS. 4A and 4B are omitted; this relates in particular to the interconnection layer 277 and the carrier 370. The various elements of device 200 are described in more detail below.In one embodiment, substrate 201 is a bulk silicon substrate (i.e., comprises bulk single crystal silicon). In various embodiments, the substrate 201 may include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In an alternative embodiment, the substrate 201 is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.In embodiments, the fins 204 may include silicon, silicon germanium, germanium, or other suitable semiconductors and may be doped with n- or p-type dopants. The fins 204 may be patterned by any suitable method. The fins 204 may be patterned using, for example, one or more photolithography processes, including dual or multi-patterning processes. Generally, in dual or multiple patterning processes, photolithography and self-aligned processes are combined, allowing for the fabrication of structures with smaller dimensions than is achievable using, for example, a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels may then be used as a masking element to pattern the fins 204. For example, the masking element may be used to etch recesses in the semiconductor layers over or in the substrate 201 such that the fins 204 remain on the substrate 201. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process may employ an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4, SF 6, CH 2 F 2, CHF 3 and / or C 2 F 6), a chlorine-containing gas (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, a wet etching process may include etching in dilute hydrofluoric acid (dHF); a solution of potassium hydroxide (KOH); ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3) and / or acetic acid (CH 3 COOH), or another suitable wet etchant. Numerous other embodiments of methods for forming the fins 204 may be suitable.The isolation structure 230 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituents), or combinations thereof. The isolation structure 230 may include various structures, such as shallow trench isolation (STI) features and / or deep trench isolation (DTI) features. In an embodiment, the isolation structure 230 may be formed by filling the trenches between the fins 204 with isolation material (e.g., using a CVD process or a spin-on-glass process), performing a chemical mechanical polishing (CMP) process to remove excess isolation material and / or to planarize a top surface of the isolation material layer, and etching back the isolation material layer to form the isolation structure 230. In some embodiments, the isolation structure 230 includes a plurality of dielectric layers, such as a silicon nitride layer, disposed over a liner layer of a thermally-generated oxide.The S / D structure elements 260 comprise semiconductor materials applied by epitaxial growth, such as epitaxially grown silicon, germanium or silicon germanium. S / D features 260 may be formed by any epitaxial process, including chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy and / or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S / D features 260 may be doped with n-type dopants and / or p-type dopants. In some embodiments, the S / D features 260 for n-type transistors include silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopant, or combinations thereof (e.g., forming Si:C-S / D epitaxial features, Si:P-S / D epitaxial features, or Si:C:P-S / D epitaxial features). In some embodiments, the S / D features 260 for n-type transistors include silicon germanium or germanium, and may be doped with boron, other p-type dopant, or combinations thereof (e.g., forming Si:Ge:B S / D epitaxial features). S / D features 260 may include multiple epitaxial semiconductor layers having different dopant density levels. In some embodiments, anneal processes (e.g., rapid thermal anneal (RTA) and / or laser anneal) are performed to activate dopants in the S / D features 260.In embodiments, the channel layers 215 include a semiconductor material suitable for transistor channels, such as silicon, silicon germanium, or other semiconductor material. The channel layers 215 may be rod-shaped, strip-shaped, leaflet-shaped, or otherwise shaped, in various embodiments. In an embodiment, the channel layers 215 are first part of a stack of semiconductor layers including the channel layers 215 and other sacrificial semiconductor layers that are alternately stacked layer by layer. The sacrificial semiconductor layers and the channel layers 215 include different material compositions (such as different semiconductor materials, different atomic percentages of the constituents, and / or different weight percentages of the constituents) to achieve etch selectivity. During a gate replacement process to form the gate stacks 240, the sacrificial semiconductor layers are selectively removed, leaving the channel layers 215 suspended over the fins 204. In the illustrated embodiment, channel layer 215 ais the lowermost channel layer and channel layer 215 dis the uppermost channel layer in region I; channel layer 215 eis the lowermost channel layer and channel layer 215 his the uppermost channel layer in region II. It should be noted that in each region four (4) channel layers 215 are vertically stacked, which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It will be appreciated that any number of channel layers may be formed depending on the performance requirements of the device. In some embodiments, the number of channel layers 215 in each region is between (and including) 2 and 10. Although the number of channel layers 215 in region I and region II appear to be the same, method 10 reduces the number of channel layers 215 actually used in region I to achieve a weaker current drive capability and maintains the maximum available number of channel layers 215 in region II to achieve a stronger current drive capability, as discussed in more detail below.In some embodiments, the inner spacers 255 comprise a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the inner spacers 255 comprise a low-k dielectric material, such as those described herein. The inner spacers 255 may be formed by deposition and etching processes. For example, after the etching of the S / D trenches and before the epitaxial growth of the S / D features 260 from the S / D trenches, an etching process may be used to recess the sacrificial semiconductor layers between adjacent channel layers 215 to vertically form gaps between the adjacent channel layers 215. Subsequently, one or more dielectric materials are deposited (e.g., using CVD or ALD) to fill the gaps. Another etching process is performed to remove the dielectric materials outside the gaps, thereby forming the inner spacers 255.In the illustrated embodiment, the gate stacks 240 include a high-k dielectric layer 349, a gate electrode layer 350, and an interfacial layer 348 between the high-k dielectric layer 349 and the channel layers 215. The high-k dielectric layer 349 includes a high-k dielectric material such as HfO 2, HfSiO, HfSiO 4, HfSiON, HfLaO, HfTaO, HfTiO, HfNbO, HfAlO x, ZrO, ZrO 2, ZrSiO 2, AlO, AlSiO, Al 2 O 3, TiO, TiO 2, LaO, LaSiO, and the like, Ta 2 O 3, Ta 2 O 5, Y 2 O 3, SrTiO 3, BaSrO, BaTiO 3( BTO), (Ba,Sr)TiO 3( BST), Si 3 N4, hafnia-alumina alloy (HfO2-Al2O3), Other suitable high-k dielectric material or combinations thereof. "High-k dielectric material" generally refers to high-dielectric materials having a high dielectric constant, for example, greater than that of silicon oxide (k≈3.9). The high-k dielectric layer 349 may be formed by ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation, and / or other suitable methods. The interfacial layer 348 may include silicon dioxide, silicon oxynitride, or other suitable materials. The interfacial layer 348 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, the gate electrode layer 350 includes an n- or p-type work function layer and a metal fill layer. For example, an n-type work function layer may comprise a metal having a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer may comprise a metal having a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal fill layer may include aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 may be formed by CVD, PVD, plating, and / or other suitable processes. Since the gate stacks 240 include a high-k dielectric layer and one or more metal layer(s), they are also referred to as high-k metal gates or high-k metal gates (HKMGs).In an embodiment, the gate spacer 247 includes a dielectric material, such as a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In embodiments, the gate spacer 247 may include La 2 O 3, Al 2 O 3, SiOCN, SiOC, SiCN, SiO 2, SiC, ZnO, ZrN, Zr 2 Al 3 O 9, TiO 2, TaO 2, ZrO2, HfO2, Si3N4, Y may comprise 2 O 3, AlON, TaCN, ZrSi or other suitable material. For example, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, may be deposited over a dummy gate stack (which is subsequently replaced by the high-k metallic gate 240) and then etched (e.g., anisotropically etched) to form the gate spacers 247. In some embodiments, the gate spacers 247 include a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers is formed adjacent to dummy gate stack 240, such as seal structure spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers. In embodiments, the gate spacer 247 may have a thickness of about 1 nm to about 40 nm.In embodiments, the CESL 269 may include La 2 O 3, Al 2 O 3, SiOCN, SiOC, SiCN, SiO 2, SiC, ZnO, ZrN, Zr 2 Al 3 O 9, TiO 2, TaO 2, ZrO2, HfO2, Si3N4, Y may comprise 2 O 3, AlON, TaCN, ZrSi, or other suitable material and may be formed by CVD, PVD, ALD, or other suitable methods. The ILD layer 270 may comprise tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride doped fused silica (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), a low-k dielectric material, other suitable dielectric material, or combinations thereof. The ILD layer 270 may be formed by PE-CVD (plasma enhanced CVD), F-CVD (flowable CVD), or other suitable methods.In some embodiments, silicide features 273 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.In an embodiment, the S / D contacts 275 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted from the S / D contacts 275.In the method 10 (FIG. 1A ), in method step 14, the component 200 is placed upside down and the front side of the component 200 is attached to a carrier 370, as shown in FIGS. 4A and 4D. This makes the device 200 accessible from the back side of the device 200 for further processing. In process step 14, any suitable attachment process may be used, such as direct bonding, hybrid bonding, use of adhesives, or other bonding methods. The method step 14 may further include alignment, annealing, and / or other processes. The carrier 370 may be a silicon wafer in some embodiments. In FIGS. 3A to 22F, the "z" direction points from the back side of the device 200 to the front side of the device 200, while the "z" direction points from the front side of the device 200 to the back side of the device 200.In method 10 (FIG. 1A ), in method step 16, device 200 is thinned from the back side of device 200 until fins 204 and isolation structures 230 are exposed from the back side of device 200. The resulting structure is shown in FIGS. 5A to 5F according to an embodiment. The thinning process may include a mechanical grinding process and / or a chemical thinning process. During a mechanical grinding process, a substantial amount of substrate material may first be removed from the substrate 201. Thereafter, in a chemical thinning process, an etching chemical may be applied to the back surface of the substrate 201 to further thin the substrate 201.In method 10 (FIG. 1A ), an etching mask 360 is formed over the back side of component 200 in method step 18. The etch mask 360 provides openings 362 over the back side of one of the S / D features 260 to be recessed from the back side of the device 200. The resulting structure is shown in FIGS. 6A to 6F according to an embodiment. In the illustrated embodiment, the opening 362 is provided over the back side of the source feature 260 a, while the drain feature 260 band the region II are covered by the etch mask 360. In various embodiments, the openings 362 may be provided over the back side of only the drain features, only the source features, or both the source and drain features. The etch mask 360 includes a material different from the material of the fin 204 ato achieve etch selectivity during the backside trench etch. For example, the etch mask 360 comprises a resist material (and may thus be referred to as a patterned resist layer and / or patterned resist layer). In some embodiments, the etch mask 360 has a multi-layer structure, such as a photoresist layer disposed over an anti-reflective coating (ARC) and / or a hard mask layer comprising silicon nitride or silicon oxide. Other materials are also conceivable for the etch mask 360 within the scope of the present disclosure, as long as an etch selectivity is achieved during the etching of the fin 204 a. In some embodiments, a lithography process is used in process step 18 that includes forming a photoresist layer (e.g., by spin coating) over the back side of device 200, performing a heat treatment process preceding the exposure, performing an exposure process using a mask, performing a heat treatment process following the exposure, and performing a development process. During the exposure process, the photoresist layer is exposed to radiation energy (e.g. UV light, DUV light or EUV light), wherein the mask blocks, transmits and / or reflects the radiation depending on the mask structure of the mask and / or the mask type (e.g. binary mask, phase shift mask or EUV mask), such that an image corresponding to the mask structure is projected onto the photoresist layer. Since the photoresist layer is sensitive to radiant energy, exposed portions of the photoresist layer chemically change, and exposed (or unexposed) portions of the photoresist layer dissolve during the development process depending on the properties of the photoresist layer and the properties of the developing solution used in the development process. After development, the patterned photoresist layer (e.g., etch mask 360) includes a photoresist pattern corresponding to the mask. Alternatively, the exposure process may be implemented by other methods or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or combinations thereof.In method 100 (FIG. 1A ), in method step 20, fin 204 ais etched by etch mask 360 to form an S / D trench 272. The etch mask 360 is then removed, for example, by a resist stripping process or other suitable process. The S / D trench 272 exposes surfaces of the source feature 260 afrom the back side. The resulting structure is shown in FIGS. 7A-7F, according to one embodiment. In the present embodiment, in process step 20, an etching process is applied that is adapted to selectively act with respect to the materials of the semiconductor material (e.g., silicon) in the fin 204 aand not (or minimal) etch the gate stacks 240, the isolation structure 230, the inner spacers 255, and the CESL 269. In the present embodiment, the etching process also etch the source feature 260 ato recess it to a level that is below the lowermost channel layer 215 a. A terminal end of the lowermost channel layer 215 ais exposed in the trench 272. The recessed source feature 260A will not have contact with the lowermost channel layer 215 a, as illustrated in FIG. 7A. It should be noted that in the illustrated embodiment, the source feature 260 ais recessed below a (1) channel layer, which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It should be appreciated that the source feature 260 amay be recessed below more than one channel layer depending on the device performance requirements. The well depth of the source feature 260a is in a range from about 10 nm to about 30 nm for each overlying channel layer. In process step 20, more than one etching process may be applied. For example, a first etching process may be applied to selectively remove the fin 204 aand then a second etching process may be applied to selectively recess the source feature 260 ato the desired level, wherein the first and second etching processes use different etch parameters, such as due to the use of different etchants. The etching process(s) may be dry etching, wet etching, reactive ion etching, or other etching processes. In some embodiments, the etching of the source feature 260 aincludes a dry etching process that includes an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4, SF 6, CH 2 F 2, CHF 3 and / or C 2 F 6), a chlorine-containing gas (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, The gases and / or plasmas may be other suitable gases and / or combinations thereof. The etch time for recessing the source feature 260A under a channel layer may be about 10 seconds to about 50 seconds.In method 10 (FIG. 1A ), an etching mask 364 is formed over the back side of component 200 in method step 22. The etch mask 364 provides openings 366 over the back side of one of the S / D features 260 to be recessed from the back side of the device 200. The resulting structure is shown in FIGS. 8A to 8F according to an embodiment. In the illustrated embodiment, the opening 366 is provided over the back side of the source feature 260 c, whereas the drain feature 260 dand the region I are covered by the etch mask 364. The S / D trench 272 in the region I is likewise filled with the photoresist material of the etching mask 364. In various embodiments, the openings 366 may be provided over the back side of only the drain features, only the source features, or both the source and drain features. The etch mask 364 includes a material different from the material of the fin 204 bto achieve etch selectivity during the backside trench etch. For example, the etch mask 364 includes a resist material (and may thus be referred to as a patterned resist layer and / or patterned resist layer). In some embodiments, the etch mask 364 comprises a material composition substantially similar to that of the etch mask 360, and forming the etch mask 364 and the opening 366 is analogous to the method step 18.In method 100 (FIG. 1B ), in method step 24, fin 204 bis etched by etch mask 360 to form an S / D trench 273 in region II. The S / D trench 273 in the region II exposes surfaces of the source feature 260 cfrom the back side. The etch mask 364 is then removed, for example, by a resist stripping process or other suitable process. After removal of the etching mask 364, the S / D trench 272 appears again in the region I. The resulting structure is shown in FIGS. 9A to 9F according to an embodiment. In the present embodiment, in process step 24, an etching process is applied that is adapted to selectively act with respect to the materials of the semiconductor material (e.g., silicon) in the fin 204 band not (or minimally) etch the gate stacks 240, the isolation structure 230, the inner spacers 255, and the CESL 269. In the present embodiment, the etching process also etch the source feature 260 cto recess it to a level that is flush with or below an interface between the isolation structure 230 and the CESL 269. The recessed source feature 260 cremain higher than the lowermost channel layer 215 e, such that the recessed source feature 260 cis still in contact with the lowermost channel layer 215 eand the lowermost inner spacer 255, as illustrated in FIG. 9D. In process step 24, more than one etching process may be applied. For example, a first etching process may be applied to selectively remove the fin 204 band then a second etching process may be applied to selectively recess the source feature 260 cto the desired level, wherein the first and second etching processes use different etch parameters, such as due to the use of different etchants. The etching process(s) may be dry etching, wet etching, reactive ion etching, or other etching processes.In the method 10 (FIG. 1B ), a dielectric layer 276 is deposited with one or more dielectric materials in step 26 to fill the S / D trenches 272 in the regions I and II. The resulting structure is shown in Figs. 10A to 10F. Dielectric layer 276 covers the otherwise exposed terminal end of lowermost channel layer 215a. In some embodiments, the dielectric layer 276 may include one or more of La2O 3, Al2O 3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al 3 O 9, TiO2, TaO2, ZrO2, HfO2, Si 3 N 4, Y2O 3, AlON, TaCN, ZrSi, or other suitable material, and may be formed by PE-CVD, F-CVD, or other suitable methods. Further, in operation 26, a CMP process may be performed on the dielectric layer 276 to remove excess dielectric material from the back side of the device 200 and expose the fins 204 and the isolation structure 230.In method 10 (FIG. 1B ), in method step 28, fins 204 are selectively etched to form S / D trenches 274 over the back side of gate stacks 240 and drain features 260 band 260 d, respectively. The S / D trenches 274 expose surfaces of the drain features 260 band 260 dfrom the back side. The resulting structure is shown in FIGS. 11A to 11F according to an embodiment. In the present embodiment, an etching process is applied in process step 28 that is adapted to selectively act with respect to the materials of the semiconductor material (e.g., silicon) in the fins 204 and not (or minimal) etch the gate stacks 240, the isolation structure 230, the inner spacers 255, and the CESL 269. In the present embodiment, the etching process also etch the drain features 260 band 260 dto recess them to a level that is flush with or below an interface between the isolation structure 230 and the CESL 269. The recessed drain feature 260b remains higher than the lowermost channel layer 215a such that the recessed drain feature 260B is still in contact with the lowermost channel layer 215A and the lowermost inner spacer 255; the recessed drain feature 260d remains higher than the lowermost channel layer 215e such that the recessed drain feature 260d is still in contact with the lowermost channel layer 215e and the lowermost inner spacer 255, as illustrated in FIGS. 11A and 11D. In process step 28, more than one etching process may be applied. For example, a first etching process may be applied to selectively remove the fins 204 and then a second etching process may be applied to selectively recess the drain features 260 band 260 dto the desired level, wherein the first and second etching processes use different etching parameters, such as due to the use of different etchants. The etching process(s) may be dry etching, wet etching, reactive ion etching, or other etching processes.In the method 10 (FIG. 1B ), in method step 30, a dielectric liner 304 is deposited on the sidewalls of the S / D trenches 274 from the back side of the device 200, as shown in FIGS. 12A to 12F. In the illustrated embodiment, at process step 30, the dielectric liner 304 is first conformally deposited to have a substantially uniform thickness along the various surfaces of the dielectric layer 276, the isolation structure 230, the gate stack 240 (i.e., the interfacial layer 348), the inner spacers 255, and the drain features 260 band 260 d. In various embodiments, the dielectric liner 304 may include La 2 O 3, Al 2 O 3, SiOCN, SiOC, SiCN, SiO 2, SiC, ZnO, ZrN, Zr 2 Al 3 O 9, TiO 2, TaO 2, ZrO2, HfO2, Si3N4, Y may comprise 2 O 3, AlON, TaCN, ZrSi, combinations thereof, or other suitable material. In some embodiments, the dielectric liner 304 comprises the same material composition as the dielectric layer 276. The dielectric liner 304 may be deposited using ALD, CVD, or other suitable methods, and may have a thickness of about 1 nm to about 5 nm in various embodiments. Next, in process step 30, an etching process is performed to break through and largely remove the horizontal portions of the dielectric liner 304. The etching process is also referred to as a breakdown etching process. In some embodiments, the breakdown etching process may include an anisotropic dry etching process or the like. In some embodiments where the dielectric liner 304 is formed of an oxide compound, the breakdown etching process is a reactive ion etching (RIE) process with etching gases including CHF 3, Ar, CF 4, N 2, O 2, CH 2 F 2, SF 3, the like, or a combination thereof. The RIE process can be performed with an etch time between about 2 seconds and about 20 seconds, a pressure between about 0.267 Pa (2 mTorr) and about 4 Pa (30 mTorr), a temperature between about 10° C. and about 100° C., a radio frequency (RF) power between about 100 W and about 1500 W, and a bias voltage between about 10 V and about 800 V. As a result of the method step 30, in the illustrated embodiment, portions of the dielectric liner 304 remain on sidewalls of the dielectric layer 276, the isolation structure 230, and the inner spacers 255 while upper surfaces of the gate stacks 240 (i.e., the interfacial layer 348), the inner spacers 255, and the drain features 260 band 260D are exposed in the S / D trenches 274.In method 10 (FIG. 1B ), silicide features 280 are formed in S / D trenches 274 over drain features 260 band 260 din step 32. The resulting structure is shown in FIGS. 12A to 12F according to an embodiment. In an embodiment, at operation 32, one or more metals are first deposited into the S / D trenches 274, an annealing process is performed on the device 200 to cause a reaction between the one or more metals and the drain features 260 band 260 dto generate the silicide features 280, and unreacted portions of the one or more metals are removed, leaving the silicide features 280 in the S / D trenches 274. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or combinations thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide features 280 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), a combination thereof, or other suitable compounds.In the method 10 (FIG. 1B ), in method step 34, S / D trenches 274 are formed over silicide features 280 in regions I and II S / D contacts 282. The resulting structure is shown in Figs. 13A to 13F. In an embodiment, the S / D contacts 282 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted from the S / D contacts 282.The dielectric liner 304 serves as a dielectric barrier layer that prevents the metallic material in the subsequently formed S / D contacts from diffusing into the dielectric layer 276. In the method 10, in some alternative embodiments, in operation 26, a barrier layer 279 may be deposited in the S / D trenches 272 (FIGS. 9A-9F ) before the dielectric layer 276 is deposited in forming a two-layer isolation feature between the dielectric layer 276 and the S / D contact 282. The resulting structure after process step 34 is shown in Figures 14A-14F. The two-layer isolation structure element includes the barrier layer 279 and the dielectric liner 304. The two-layer isolation feature provides better isolation between the subsequently formed S / D contacts and the dielectric layer 276. Further, the barrier layer 279 prevents the covered epitaxial structure from oxidizing. In the illustrated embodiment, the barrier layer 279 is conformally deposited in the S / D trenches 272. In some embodiments, the barrier layer 279 comprises SiO 2, SiN, SiCN, SiOC, combinations thereof, or other suitable material, and the dielectric liner 304 comprises SiN, SiCN, SiOCN, combinations thereof, or other suitable material. In a further development of the embodiments, the barrier layer 279 and the dielectric liner 304 may comprise different dielectric materials. The barrier layer 279 may be deposited using ALD, CVD, or other suitable methods, and may have a thickness of about 1 nm to about 5 nm in various embodiments.Still referring to FIGS. 14A and 14D, in the GAA transistor 202 ain the region I, the source pattern 260 ais in contact with the channel layers 215 bto 215 dbut not with the channel layer 215 a, and the drain pattern 260 bis in contact with the channel layers 215 ato 215 d. Accordingly, there is no current path from source feature 260a through channel layer 215a to drain feature 260b. Channel layer 215a has been isolated from the channel region of GAA transistor 202a. The isolation is provided by the recessed source feature 260 aand the dielectric layer 276. In the GAA transistor 202 a, the number of (effective) channel layers is three (3). In comparison, in the GAA transistor 202 bin the region II, the source pattern 260 cand the drain pattern 260 dare in contact with the channel layers 215 e- 215 h, respectively. Accordingly, each of the channel layers 215 e- 215 hprovide a current path from the source feature 260 cto the drain feature 260 d. In the GAA transistor 202 b, the number of (effective) channel layers is four (4). Thus, by the method 10, different numbers of channel layers for GAA transistors are provided in different regions of an IC chip that perform different functions.In some alternative embodiments of method 10, drain feature 260 bmay also be recessed in region I in GAA transistor 202 a. For example, in operation 28, after forming the S / D trench 274, exposing the drain feature 260 b, the drain feature 260 bmay be further recessed to a level below the lowermost channel layer 215 abefore proceeding to operation 30 to form silicide features. The resulting structure after process step 34 is shown in Figures 15A to 15F. Neither the recessed source feature 260a nor the recessed drain feature 260b are in contact with the lowermost channel layer 215a, thereby forming an insulated channel layer 215a. In various embodiments, the recessed drain feature 260 bmay be level with, below, or above the recessed source feature 260 a.In method 10 (FIG. 1B ), further manufacturing processes are carried out on component 200 in method step 36. For example, a metal wiring layer (not shown), such as back side supply rails, may be formed on the back side of the device 200. The metal wiring layer makes electrically conductive connections to the back side S / D contacts 282 in the regions I and II. In an embodiment, the metal wiring layer may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable processes. The metal wiring layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. The presence of a back side metal wiring layer usefully increases the number of metal traces in the device 200 available for direct connection to source / drain contacts and the vias. In addition, the gate density increases for greater device integration than for other structures without the back side metal wiring layer. In the method 10, one or more interconnection layers may also be formed on the back side of the device 200, passivation layers may be formed on the back side of the device 200, other BEOL processes may be performed, and the carrier 370 may be removed in method step 36.FIG. 1C shows a flow diagram of a method 100 for manufacturing a semiconductor device having different numbers of stacked semiconductor channel layers in different areas without the need for back side metal wiring layers, according to some embodiments of the present disclosure. The method 100 will be described below in connection with FIGS. 2 and 16A- 22F, which show various plan and cross-sectional views of a semiconductor device (or device) 200 at various manufacturing steps according to the method 100 in accordance with some embodiments. FIGS. 16A to 22F illustrate cross-sectional views of a portion of the device 200 taken along lines A-A, B-B, C-C, D-D, E-E, and F-F, respectively, in FIG. 2 ; in particular, line A-A and line D-D are cuts in the longitudinal direction of the semiconductor fins (X direction), line B-B, and line E-E are cuts in the source regions of the transistors and are parallel to the gate stacks of the transistors (Y direction), and the line C-C and the line F-F are cuts in the drain regions of the transistors and are parallel to the gate stacks of the transistors. It should be noted that in various embodiments, lines B-B and E-E may alternatively intersect with the drain regions of the transistors and lines C-C and F-F may alternatively intersect with the source regions of the transistors. In the present disclosure, a source and a drain are used interchangeably. Additional processing steps are contemplated in the present disclosure. Additional method steps may be performed before, during, and after method 100, and in further embodiments of method 100, some of the described method steps may be moved, replaced, or omitted. Some aspects of method 100 are identical to method 10 and are discussed briefly below. Other aspects of method 100 are different from method 10 and will be described in more detail.Referring to FIGS. 2 and 16A- 16F, in method step 102, a device 200 is provided by method 100 (FIG. 1C ) that includes a substrate 201 and transistors formed on the front side of substrate 201. The device 200 includes a region I for low power and / or low leakage applications such as an I / O region and a region II for high power and / or high speed applications such as a core region. Many aspects of device 200 are the same as described above. For ease of understanding, the reference numerals are repeated. Some differences are discussed below.The channel layers 215 are part of a stack of semiconductor layers including channel layers 215 and other sacrificial semiconductor layers 217 that are alternately stacked layer by layer. The sacrificial semiconductor layers 217 and the channel layers 215 include different material compositions (such as different semiconductor materials, different atomic percentages of the constituents, and / or different weight percentages of the constituents) to achieve etch selectivity. For example, the channel layers 215 may include Si, and the sacrificial semiconductor layers 217 may include SiGe. However, other embodiments are possible, including those providing etch selectivity. For example, in some embodiments, the channel layer 215 and the sacrificial semiconductor layer 217 may each include other materials, such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. The epitaxial growth of the channel layers 215 and the sacrificial semiconductor layers 217 may be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or another suitable epitaxy process, as an example.In the illustrated embodiment, as shown in FIGS. 16A-16F, the gate stacks 240 are place holders and are replaced with a final metal gate stack in a so-called gate load process. Therefore, the gate stacks 240 are also referred to as dummy gate stacks 240. The dummy gate stacks 240 include a dummy interface layer 242, a dummy gate electrode layer 244, and a hard mask layer 246. The dummy interface layer 242 may include a dielectric material, such as a silicon oxide layer (e.g., SiO 2) or silicon oxynitride (e.g., SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The dummy gate electrode layer 244 may include polycrystalline silicon (poly-Si) and may be formed by suitable deposition processes such as low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD). The hard mask layer 246 may include one or more layers of material such as silicon oxide and / or silicon nitride. The dummy gate stacks 240 may include other suitable layers, in embodiments. The various layers of dummy gate stacks 240 may be formed by photolithography and etching processes.In the method 100 (FIG. 1C ), in method step 104, an etch mask 360 is formed over the front side of the device 200 covering the region II while the region I of the device 200 is exposed. The resulting structure is shown in FIGS. 17A to 17F according to an embodiment. In some embodiments, the etch mask 360 comprises a resist material (and may thus be referred to as a patterned resist layer and / or patterned resist layer). In one example, in process step 104, a patterned photoresist may be formed over region II by photoresist coating, exposing, heat treating after exposure, and developing.In method 100 (FIG. 1C ), in method step 106, S / D feature 260 (which includes source feature 260 aand drain feature 260 b) in region I is selectively etched. In the present embodiment, in method step 20, an etching process is applied that is adapted to selectively act with respect to the epitaxy materials of the S / D features 260 and not (or minimal) etch the dummy gate stacks 240, the isolation structure 230, the gate spacer 247, the inner spacers 255, and the channel layers 215. The resulting structure is shown in FIGS. 17A to 17F according to an embodiment. The etching process etch the S / D features 260 in region I to be recessed to a level below the top channel layer 215 d. The recessed S / D features 260 in region I do not contact the top channel layer 215 d, as illustrated in FIG. 17A. Further, in some embodiments, the recessed S / D features 260 may or may not be in contact with the uppermost inner spacers 255. It should be noted that in the illustrated embodiment, the S / D features 260 are recessed below a (1) channel layer, which is for illustration purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It should be appreciated that the S / D features 260 may be recessed below more than one channel layer depending on the device performance requirements. The well depth of the S / D features 260 is in a range from about 10 nm to about 30 nm for each overlying channel layer. The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods. In some embodiments, the etching of the S / D features 260 includes a dry etching process that includes an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4, SF 6, CH 2 F 2, CHF 3 and / or C 2 F 6), a chlorine-containing gas (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, The gases and / or plasmas may be other suitable gases and / or combinations thereof. The etch time for recessing the S / D features 260 under a channel layer may be about 10 seconds to about 50 seconds. The etch mask 360 is then removed, for example, by a resist stripping process or other suitable process.In the method 100 (FIG. 1C ), in method step 108, various features are formed, including a contact etch stop layer (CESL) 269 over the S / D features 260 in the two regions I and II and an interlayer dielectric layer (ILD) 270 over the CESL 269. The resulting structure is shown in FIGS. 18A-18F, according to one embodiment. The CESL 269 may include La 2 O 3, Al 2 O 3, SiOCN, SiOC, SiCN, SiO 2, SiC, ZnO, ZrN, Zr 2 Al 3 O 9, TiO 2, TaO 2, ZrO2, HfO2, Si3N4, Y may comprise 2 O 3, AlON, TaCN, ZrSi, or other suitable material and may be formed by CVD, PVD, ALD, or other suitable methods. The CESL 269 covers the otherwise exposed terminal ends of the uppermost channel layer 215 d. The ILD 270 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric material. The ILD layer 270 may be formed by PECVD, FCVD, or other suitable methods. In operation 108, one or more CMP processes may be performed to planarize the top surface of the device 200, remove the hard mask layer 246, and expose the dummy gate electrode layer 244.In the method 100 (FIG. 1C ), in method step 110, the dummy gate stacks 240 are removed to form gate trenches 271. The resulting structure is shown in FIGS. 19A to 19F according to an embodiment. The gate trenches 271 expose surfaces of the channel layers 215 and the sacrificial semiconductor layers 217. The method step 110 may include one or more etch processes that are selective with respect to the materials in the dummy interface layer 242 and the dummy gate electrode layer 244. The etching process may include any suitable etching techniques, such as wet etching, dry etching, RIE, ashing, and / or other etching methods, with an etchant in which the gate spacers 238 and the ILD layer 270 are etch resistant. In an example, the etching process is a dry etching process using a fluorine-based etchant (e.g., CF 4, CHF 3, CH 2 F 2 etc.). In addition, the channel layers 215 are detached from the gate trenches 271 by the method step 110. In the present embodiment, the channel layers 215 include Si and the sacrificial semiconductor layers 217 include SiGe. The plurality of sacrificial semiconductor layers 217 may be selectively removed. In some embodiments, the selective removal process includes oxidizing the plurality of sacrificial semiconductor layers 217 using a suitable oxidizing agent, such as ozone. Thereafter, the oxidized sacrificial semiconductor layers 217 may be selectively removed. To further bring this embodiment, the method step 110 comprises a dry etching process to selectively remove the sacrificial semiconductor layers 217, for example by applying an HCl gas at a temperature of 500° C. to 700° C. or by applying a gas mixture of CF 4, SF 6 and CHF 3.In the method 100 (FIG. 1C ), in method step 112, so-called metal gate stacks (e.g. high-k metal gates) are deposited in the gate trenches 271. The resulting structure is shown in FIGS. 20A to 20F according to an embodiment. The metal gate stacks include a high-k dielectric layer 349, a gate electrode layer 350, and an interfacial layer 348 between the high-k dielectric layer 349 and the channel layers 215. The high-k dielectric layer 349 includes a high-k dielectric material such as HfO 2, HfSiO, HfSiO 4, HfSiON, HfLaO, HfTaO, HfTiO, HfNbO, HfAlO x, ZrO, ZrO 2, ZrSiO 2, AlO, AlSiO, Al 2 O 3, TiO, TiO 2, LaO, LaSiO, and the like, Ta 2 O 3, Ta 2 O 5, Y 2 O 3, SrTiO 3, BaSrO, BaTiO 3( BTO), (Ba,Sr)TiO 3( BST), Si 3 N4, hafnium dioxide-aluminum oxide alloy (HfO2-Al2O3), Other suitable high-k dielectric material or combinations thereof. "High-k dielectric material" generally refers to high-dielectric materials having a high dielectric constant, for example, greater than that of silicon oxide (k≈3.9). The high-k dielectric layer 349 may be formed by ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation, and / or other suitable methods. The interfacial layer 348 may include silicon dioxide, silicon oxynitride, or other suitable materials. The interfacial layer 348 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, the gate electrode layer 350 includes an n- or p-type work function layer and a metal fill layer. For example, an n-type work function layer may comprise a metal having a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer may comprise a metal having a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal fill layer may include aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 may be formed by CVD, PVD, plating, and / or other suitable processes.In method 100 (FIG. 1C ), S / D contacts 275 are formed in method step 114 over S / D structure elements 260 in regions I and II. The resulting structure is shown in FIGS. 21A to 21F according to an embodiment. In process step 114, first, the ILD layer 270 may be selectively etched to form S / D vias (not shown). The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods. In an embodiment, the selective etching process may be a dry etch. For example, the etchant may be a mixed gas of C 4 F 6, CO, CO 2 and Ar. Subsequently, through process step 114, portions of the CESL 269 exposed in the S / D vias are removed. The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods. In an embodiment, silicide features 273 may be formed in the S / D vias over the S / D features 260 by the process step 114. In some embodiments, silicide features 273 are formed by silicided, such as by a so-called salicide process, where a metal material is formed over S / D features 260, then the temperature is raised to anneal and cause a reaction between the underlying silicon and the metal in which silicide is formed, and unreacted metal is etched away. The silicide features 273 help to reduce the contact resistance. In process step 114, conductive material is then deposited in the S / D vias over the silicide features 273 to form the S / D contacts 275. In an embodiment, the S / D contacts 275 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted from the S / D contacts 275.Still referring to FIGS. 21A and 21D, in the GAA transistor 202 ain region I, in various embodiments, the recessed drain feature 260 bmay be level with, below, or above the recessed source feature 260 a. However, both the source feature 260 aand the drain feature 260 bare in contact with the channel layers 215 ato 215 cbut not with the uppermost channel layer 215 d. Accordingly, there is no current path from source feature 260a through channel layer 215d to drain feature 260b. Thus, channel layer 215 ais isolated from the channel region of GAA transistor 202 aby recessed S / D features 260 aand 260 band CESL 269. In the GAA transistor 202 a, the number of (effective) channel layers is three (3). In comparison, in the GAA transistor 202 bin the region II, the source pattern 260 cand the drain pattern 260 dare in contact with the channel layers 215 e- 215 h, respectively. Accordingly, each of the channel layers 215 e- 215 hprovide a current path from the source feature 260 cto the drain feature 260 d. In the GAA transistor 202 b, the number of (effective) channel layers is four (4). Accordingly, the method 100 provides different numbers of channel layers for GAA transistors in different regions of an IC chip that perform different functions.In some alternative embodiments of the method 100, the drain feature 260 bin the GAA transistor 202 amay be further in contact with the top channel layer 215 din the region I after recessing. For example, in method step 104, the etch mask 360 may also cover the drain feature 260 bin the region I and have the opening over the source feature 260 a. Thus, in process step 106, only the source feature 260 ais recessed to a level that is below the lowermost channel layer 215 a. The resulting structure after process step 114 is shown in Figures 22A-22F. The recessed source feature 260a does not contact the top channel layer 215d, while the drain feature 260b remains in contact with the top channel layer 215d. Nevertheless, this results in an insulated channel layer 215d.In method 100 (FIG. 1C ), further manufacturing processes are carried out on component 200 in method step 116. For example, one or more interconnect layers may be formed on the front side of the device 200 to electrically connect the source, drain and gate terminals of different transistors and thus form a complete integrated circuit (IC).Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure form different numbers of stacked channel layers in different regions of an IC chip that perform different functions. This advantageously satisfies the requirements for different current driving capabilities of the various transistors. Further, by some embodiments of the present disclosure, back side wiring layers are formed, such as back side power rails, to increase the number of metal traces available in the integrated circuit and increase the gate density for better device integration. Embodiments of the present disclosure may be readily incorporated into existing semiconductor manufacturing processes.In an exemplary aspect, the present disclosure relates to a method. The method comprises: providing a structure having a front side and a back side, the structure comprising a substrate, two or more semiconductor channel layers disposed over the substrate connecting a first source / drain (S / D) feature and a second S / D feature, and a gate structure engaging the semiconductor channel layers, wherein the substrate is on the back side of the structure and the gate structure is on the front side of the structure; recessing the first S / D feature to thereby expose a terminal end of one of the semiconductor channel layers; and depositing a dielectric layer on the first S / D feature and thereby cover the exposed terminal end of the one of the semiconductor channel layers. In some embodiments, after recessing the first S / D feature, the first S / D feature is not in contact with the one of the semiconductor channel layers. In some embodiments, the one of the semiconductor channel layers is the lowermost semiconductor channel layer in the structure, and recessing the first S / D feature includes etching the first S / D feature from the back side of the structure. In some embodiments, the method further comprises etching the substrate from the back side of the structure to form a trench exposing the first S / D feature, wherein recessing the first S / D feature comprises etching the first S / D feature through the trench. In some embodiments, the gate structure is a high-k metal gate structure. In some embodiments, the one of the semiconductor channel layers is the uppermost semiconductor channel layer in the structure, and recessing the first S / D feature includes etching the first S / D feature from the front side of the structure. In some embodiments, the gate structure is a sacrificial gate structure. In some embodiments, the method further comprises removing the sacrificial gate structure to thereby expose the semiconductor channel layers; and forming a high-k metal gate structure that engages the semiconductor channel layers. In some embodiments, after recessing the first S / D features, the second S / D features remain in contact with each of the semiconductor channel layers. In some embodiments, recessing the first S / D feature includes recessing the second S / D feature to thereby expose another terminal end of the one of the semiconductor channel layers. In some embodiments, the method further comprises partially removing the dielectric layer to thereby expose the S / D feature; and forming an S / D contact on the first S / D feature.In another exemplary aspect, the present disclosure relates to a method. The method comprises: providing a structure having a front side and a back side, the structure comprising a substrate, a semiconductor fin over the substrate, a first source / drain (S / D) feature and a second S / D feature over the semiconductor fin, two or more semiconductor channel layers over the semiconductor fin connecting the first and second S / D features, and a gate structure engaging the semiconductor channel layers, wherein the substrate is on the back side of the structure and the gate structure is on the front side of the structure; thinning the structure from its back side until the semiconductor fin is exposed; etching the semiconductor fin from the back side of the structure to form a first trench exposing the first S / D feature; recessing the first S / D feature through the first trench such that a terminal end of the lowermost semiconductor channel layer is exposed in the first trench; and depositing a dielectric layer in the first trench, the dielectric layer covering the terminal end of the lowermost semiconductor channel layer. In some embodiments, the method further comprises etching the semiconductor fin from the back side of the structure to form a second trench exposing the second S / D feature; and forming an S / D contact pad on the second S / D feature. In some embodiments, the second S / D feature is in contact with the lowermost semiconductor channel layer. In some embodiments, the method further comprises recessing the second S / D feature by the second trench before forming the S / D contact such that the other terminal end of the lowermost semiconductor channel layer is exposed in the second trench. In some embodiments, the gate structure is a high-k metal gate structure.In yet another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure comprises: two or more semiconductor channel layers vertically stacked one above the other; a gate structure engaging the semiconductor channel layers; and first and second source / drain (S / D) features, wherein the first and second S / D features, the semiconductor channel layers, and the gate structure are on the front side of the semiconductor structure, and wherein at least one of the semiconductor channel layers is not in contact with at least one of the first and second S / D features. In some embodiments, the at least one of the semiconductor channel layers is the lowermost semiconductor channel layer. In some embodiments, the semiconductor structure further includes a metal wiring layer on a back surface thereof. In some embodiments, the at least one of the semiconductor channel layers is not in contact with either the first or second S / D features.

Claims

A method comprising: providing a structure having a front side and a back side, the structure comprising a substrate (201), two or more semiconductor channel layers (215) disposed over the substrate (201) connecting a first source / drain feature, S / D feature, (260) and a second S / D feature (260), and a gate structure (240) engaging the semiconductor channel layers (215), wherein the substrate (201) is on the back side of the structure and the gate structure (240) is on the front side of the structure; recessing the first S / D feature (260) to thereby expose a terminal end of one of the semiconductor channel layers (215); and depositing a dielectric layer (276) on the first S / D feature (260) thereby covering the exposed terminal end of the one of the semiconductor channel layers (215), wherein the one of the semiconductor channel layers (215) is the lowermost semiconductor channel layer (215a) in the structure, and recessing the first S / D feature (260) comprises etching the first S / D feature (260) from the back side of the structure.The method of claim 1, wherein after recessing the first S / D feature (260), the first S / D feature is not in contact with the one (215a) of the semiconductor channel layers (215).The method of claim 1 or 2, further comprising: etching the substrate (201) from the back side of the structure to form a trench (272) exposing the first S / D feature (260), wherein recessing the first S / D feature (260) comprises etching the first S / D feature (260) through the trench (272).The method of any preceding claim, wherein the gate structure (240) is a high-k metal gate structure.The method of any preceding claim, wherein after recessing the first S / D feature (260), the second S / D feature (260) is further in contact with each of the semiconductor channel layers (215).The method of any of the preceding claims 1 to 4, wherein recessing the first S / D feature (260) comprises recessing the second S / D feature (260) to thereby expose another terminal end of the one (215a) of the semiconductor channel layers (215).The method of any preceding claim, further comprising: partially removing the dielectric layer (276) to thereby expose the first S / D feature (260); and forming an S / D contact on the first S / D feature (260).A method comprising: providing a structure having a front side and a back side, the structure comprising a substrate (201), a semiconductor fin (204) over the substrate (201), a first source / drain feature, S / D feature, (260), and a second S / D feature (260) over the semiconductor fin (204), two or more semiconductor channel layers (215) over the semiconductor fin (204) connecting the first (260) and second S / D features (260), and a gate structure (240) engaging the semiconductor channel layers (215), wherein the substrate (201) is on the back side of the structure and the gate structure (240) is on the front side of the structure; thinning the structure from its back side until the semiconductor fin (204) is exposed; etching the semiconductor fin (204) from the back side of the structure to form a first trench (272) exposing the first S / D feature (260); recessing the first S / D feature (260) through the first trench (272) such that a terminal end of a lowermost semiconductor channel layer (215a) is exposed in the first trench (272); and depositing a dielectric layer (276) in the first trench (272), the dielectric layer (276) covering the terminal end of the lowermost semiconductor channel layer (215a), wherein recessing the first S / D feature (260) comprises etching the first S / D feature (260) from the back side of the structure through the first trench (272).The method of claim 8, further comprising: etching the semiconductor fin (204) from the back side of the structure to form a second trench exposing the second S / D feature (260); and forming an S / D contact pad on the second S / D feature (260).The method of claim 9, wherein the second S / D feature (260) is in contact with the lowermost semiconductor channel layer (215a).The method of claim 9 or 10, further comprising: recessing the second S / D feature (260) by the second trench before forming the S / D contact such that another terminal end of the lowermost semiconductor channel layer (215a) is exposed in the second trench.The method of any of the preceding claims 8 to 11, wherein the gate structure (240) is a high-k metal gate structure.A semiconductor structure comprising: two or more semiconductor channel layers (215) vertically stacked one above the other; a gate structure (240) engaging the semiconductor channel layers (215); and first (260) and second source / drain, S / D, features (260), wherein the first (260) and second S / D features (260), the semiconductor channel layers (215), and the gate structure (240) are on the front side of the semiconductor structure, and wherein at least one of the semiconductor channel layers (215) is not in contact with at least one of the first (260) and second S / D features (260), wherein the at least one of the semiconductor channel layers (215) is a lowermost semiconductor channel layer (215a), wherein the lowermost semiconductor channel layer (215a) has two terminal ends on opposite sides of the lowermost semiconductor channel layer (215a), one terminal end of which contacts one of the first (260) and the second S / D structural elements (260) and another terminal end of which contacts a dielectric layer (276).The semiconductor structure of claim 13, further comprising: a metal wiring layer on a back side of the semiconductor structure.

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