Structuring of semiconductor components and the resulting structures

Abstract

Procedures, exhibiting: Deposition of a first mask (106, 108) over a first area (100C) of a target layer (104) and a second area (110A, 110B) of the target layer (104); Forming a multitude of thorns (124) above the first mask (106, 108); Forming a plurality of spacers (128) on side walls of the plurality of spines (124); Deposition of a second mask (150) over the plurality of spines (124) and the plurality of spacers (128); Forming a cover layer (152) over the second mask (150), wherein the cover layer (152) contains carbon; and Structuring the second mask (150) and the cover layer (152) to expose a first mandrel (124) of the plurality of mandrels (124) and upper surfaces and side walls of first spacers (128) of the plurality of spacers (128), wherein the first mandrel (124) and the first spacers (128) overlap the first area (110C) of the target layer (104), wherein the cover layer (152) remains above the second area (110A, 110B) of the target layer (104) after the first mandrel (124) of the plurality of mandrels (124) and the upper surfaces and side walls of the first spacers (128) of the plurality of spacers (128) are exposed, wherein the second mask (150) is conformally deposited on side walls of the plurality of spacers (128), on upper surfaces of the plurality of mandrels (124) and on upper surfaces of the first mask (106, 108) which are arranged laterally next to the plurality of spacers (128) and next to the plurality of mandrels (124), such that the second mask (150) extends on upper surfaces of the first mask (106, 108) between spacers (128) which are formed on side walls of adjacent mandrels (124), the top layer (152) is formed on the second mask (150).

Description

BACKGROUND

[0001] With the ongoing miniaturization of semiconductor devices, various processing techniques (e.g., photolithography) are employed to enable the production of devices with increasingly smaller dimensions. For example, as gate density increases, processes for producing various features within the device (e.g., overlying interconnect features) are adapted to be compatible with the miniaturization of the overall device. However, as semiconductor processes exhibit ever-smaller process windows, the production of these devices has approached, and even exceeded, the theoretical limits of photolithography equipment. As semiconductor devices continue to shrink, the desired pitch between elements (i.e., the pitch spacing) of a device becomes smaller than the pitch spacing achievable using conventional optical masks and photolithography equipment.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in DE 10 2016 123 943 A1, US 10 692 728 B2, US 2013 / 0 001 750 A1 and DE 10 2017 127 390 A1.

[0003] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by referring to the following detailed description, when read in conjunction with the accompanying figures. It should also be noted that, in accordance with standard industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as desired for the clarity of the discussion. Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 and Fig. Figure 20 illustrates cross-sectional and perspective views of various intermediate stages in the manufacture of a semiconductor device according to different embodiments. Fig. 21, Fig. 22 and Fig. Figure 23 illustrates cross-sectional and perspective views of various intermediate stages in the manufacture of a semiconductor device according to various other embodiments. Fig. 24 and Fig. Figure 25 illustrates cross-sectional and perspective views of various intermediate stages in the manufacture of a semiconductor device according to various other embodiments. Fig. 26 and Fig. Figure 27 illustrates cross-sectional and perspective views of various intermediate stages in the manufacture of a semiconductor device according to various other embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or exemplary embodiments for implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various discussed embodiments and / or configurations.

[0006] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the component in use or operation. The object may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptions used here can be interpreted accordingly.

[0007] Various embodiments are described with reference to a specific structuring process, namely a self-aligned double patterning (SADP) process, in which mandrels are structured, spacers are formed along the sidewalls of the mandrels, and at least one section of the mandrels is removed, leaving the spacers to define a structure with half the pitch of the mandrels. However, various embodiments may refer to other structuring processes, such as self-aligned quadruple patterning (SAQP) and the like.

[0008] According to some embodiments, a semiconductor device and a method are provided. In particular, a self-aligning dual structuring process is performed to structure features (e.g., semiconductor fins, gate structures, conductive traces, or the like) in a target layer of a semiconductor device. At least some of the structured features have a pitch spacing that is at least half of a minimum pitch achievable using photolithographic processes. The structured features may include features structured using the mandrels, spacers, and / or a combination thereof described above. In particular, different regions of the target layer may be structured using different combinations of the mandrels and spacers to achieve structured features with different sizes and / or spacings.

[0009] The mandrels and spacers can be selectively removed from different areas above the target layer, depending on the desired resulting feature size. To achieve this selective removal, one or more masks can be deposited over the mandrels and spacers. In various embodiments, a high-carbon layer can be deposited over the spacers (e.g., between different masks) to reduce etch damage (e.g., loss of spacer material) resulting from the selective removal of the mandrels and / or spacers. Therefore, mandrels and spacers can be precisely patterned with desired dimensions, and the control of critical dimensions during patterning of the target layer can be improved.

[0010] Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 to Fig. Figure 19 illustrates cross-sectional views of intermediate stages in the formation of features in a target layer 104 of a semiconductor device 100 according to some exemplary embodiments. The target layer 104 is a layer in which, according to embodiments of the present disclosure, a plurality of structures are to be formed. In some embodiments, the semiconductor device 100 is processed as part of a larger wafer. In such embodiments, after the formation of various features of the semiconductor device 100 (e.g., active components, interconnect structures, and the like), a singulation process can be applied to scribing line regions of the wafer to separate the individual semiconductor dies from the wafer (also referred to as singulation).

[0011] In some embodiments, the target layer 104 is a semiconductor substrate. The semiconductor substrate may contain doped or undoped silicon or comprise an active layer of a semiconductor-on-insulator (SOI) substrate. The target layer 104 may include other semiconductor materials, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The semiconductor substrate may be structured by a process according to one embodiment, and subsequent process steps may be used to create shallow trench isolation regions.STI regions) are formed in the substrate. Semiconductor fins can protrude between the formed STI regions. Source / drain regions can be formed in the semiconductor fins, and a gate dielectric and electrode layers can be formed over channel regions of the fins, thus forming semiconductor devices such as fin field-effect transistors (FinFETs).

[0012] In some embodiments, the target layer 104 is a conductive layer, such as a metal layer or a polysilicon layer, which is deposited over the entire surface. Structuring processes according to these embodiments can be applied to the target layer 104 to structure semiconductor gates and / or dummy gates of FinFETs. By using processes according to these embodiments to structure a conductive target layer 104, the distance between adjacent gates can be reduced and the gate density increased. In such embodiments, the target layer 104 can be formed on top of a semiconductor substrate, e.g., as described above.

[0013] In some embodiments, the target layer 104 is an inter-metal dielectric (IMD) layer. In such embodiments, the target layer 104 contains a dielectric material with a low k-value, having a dielectric constant (k-value) of, for example, less than 3.8, less than about 3.0, or less than about 2.5. In alternative embodiments, the target layer 104 is an IMD layer containing a dielectric material with a high k-value, having a k-value greater than 3.8. Openings can be structured in the target layer 104 by the processes according to these embodiments, and conductive traces and / or vias can be formed in these openings. In such embodiments, the target layer can be formed over a semiconductor substrate (e.g., as described above), and components such as transistors, diodes, capacitors, resistors, etc., can be embedded within it.can be formed in and / or on an active surface of the semiconductor substrate.

[0014] The component 100 comprises three regions: 100A, 100B, and 100C. Within each of these regions, different types of components and / or geometries (e.g., sizes) can be formed. For example, region 100A can be processed to create features (e.g., semiconductor fins) with a first width in target layer 104; region 100B can be processed to create features with a second width in target layer 104 that is larger than the first width; and region 100C can be processed to create features with a third width in target layer 104 that is larger than the first width but smaller than the second width. For example, the first width can be less than approximately 15 nm; the second width can be greater than approximately 15 nm to approximately 30 nm; and the third width can be in the range of approximately 15 nm to approximately 30 nm.In some embodiments, n-type components may be formed in regions 100A and 100C, while p-type components are formed in region 100B. In other embodiments, different feature sizes and / or components of other types may be formed in various regions of component 100. Furthermore, although regions 100A, 100B, and 100C are illustrated as directly adjacent, any number of intervening features and / or a gap may be arranged between regions 100A, 100B, and 100C.

[0015] An adhesive layer 102 is deposited over the target layer 104. The adhesive layer 102 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. In some embodiments, the adhesive layer 102 can serve as an adhesive layer and, during the subsequent formation of fins, as an etch stop layer. This is illustrated Fig. 1 the adhesive layer 102 in physical contact with the target layer 104, however any number of intermediate layers can be arranged between the adhesive layer 102 and the target layer 104.

[0016] The film stack further includes a hard mask layer 106 formed over the adhesive layer 102. The hard mask layer 106 can be formed from a material that can be selectively etched compared to the adhesive layer 102. For example, in embodiments where the adhesive layer 102 contains an oxide, the hard mask layer 106 can be a nitride, such as silicon nitride, or the like. The hard mask layer 106 can be deposited, for example, by PVD, CVD, ALD, or the like. In some embodiments, the hard mask layer 106 can, for example, have a thickness ranging from about 20 nm to about 30 nm.

[0017] The film stack further encloses a hard mask 108 over the hard mask layer 106. In some embodiments, the hard mask 108 can contain a material that can be selectively etched with respect to the hard mask layer 106. For example, in embodiments where the hard mask layer 106 contains a nitride, the multilayer hard mask 108 can contain an oxide. In particular, in some embodiments, the hard mask layer 108 contains silicon oxide (e.g., SiO₂ or the like), silicon oxynitride (SiON₂), silicon oxycarbonitride (SiOC₄), combinations thereof, or the like. The hard mask layer 108 can be deposited, for example, by PVD, CVD, ALD, or the like.

[0018] The film stack further includes a mandrel layer 112 formed over the hard mask 108. The mandrel layer 112 can contain silicon (e.g., amorphous silicon) or the like. The mandrel layer 112 can be deposited using any suitable process, such as ALD, CVD, PVD, or the like.

[0019] A three-layer photoresist 120 is formed on the film stack above the mandrel layer 112. The three-layer photoresist 120 comprises a bottom layer 114, a middle layer 116 above the bottom layer 114, and an top layer 118 above the middle layer 116. The bottom layer 114 and the top layer 118 can be formed from photoresists (e.g., photosensitive material) that enclose organic material. In some embodiments, the bottom layer 114 can also be a bottom anti-reflective coating (BARC layer). The middle layer 116 can contain an inorganic material, which may be a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), or the like. The middle layer 116 exhibits high etch selectivity with respect to the upper layer 118 and the lower layer 114.The various layers of the three-layer photoresist 120 can be deposited sequentially over the entire surface, for example, using spin deposition processes. Although a three-layer photoresist 120 is discussed here, in other embodiments the photoresist 120 can also be a single-layer or a two-layer photoresist (e.g., with only the bottom layer 114 and the top layer 118, without the middle layer 116). The type of photoresist used (e.g., single-layer, double-layer, or triple-layer) can depend on the photolithography process used to structure the mandrel layer 112. For example, a single-layer or a two-layer photoresist 120 can be used in advanced extreme ultraviolet (EUV) lithography processes.

[0020] In some embodiments, the upper layer 118 is structured using a photolithographic process. Subsequently, the upper layer 118 is used as an etching mask for structuring the middle layer 116 (see Fig. 2) The middle layer 116 is then used as an etching mask to structure the lower layer 114, and the lower layer 114 is then used to structure the mandrel layer 112 (see Fig. 3 and Fig. 4) It has been observed that by using a three-layer photoresist (e.g., the three-layer photoresist 120) to etch a target layer (e.g., the mandrel layer 112), an improved definition of fine pitch structures in the target layer (e.g., the mandrel layer 112) can be achieved.

[0021] The top layer 118 is patterned using any suitable photolithography process to form openings 122 in it. In one example of patterning the openings 122 in the top layer 118, a photomask can be placed over the top layer 118. The top layer 118 can then be exposed to a beam of ultraviolet (UV) radiation or excimer laser radiation, such as a 248 nm beam of a krypton fluoride (KrF) excimer laser, a 193 nm beam of an argon fluoride (ArF) excimer laser, or a 157 nm beam of an F2 excimer laser, or the like, while the photomask masks areas of the top layer 118. Exposure of the top photoresist layer can be performed using an immersion lithography system to increase the resolution and reduce the minimum achievable parting line.A baking or curing process can be carried out to harden the top layer 118, and a developer can be used to remove either the exposed or the unexposed sections of the top layer 118, depending on whether a positive or a negative resist is used.

[0022] After structuring the upper layer 118, the structure of the upper layer 118 is transferred to the middle layer 116 in an etching process. The etching process is anisotropic, so that the openings 122 in the upper layer 118 are extended through the middle layer 116 and have essentially the same size in the middle layer 116 as in the upper layer 118. The resulting structure is in Fig. 2 illustrated.

[0023] Optionally, a trimming process can be performed to increase the size of the openings 122 in the middle layer 116. In one embodiment, the trimming process is an anisotropic plasma etching process with process gases containing O2, CO2, N2 / H2, H2, the like, a combination thereof, or any other gases suitable for trimming the middle layer 116.

[0024] In Fig. 3. An etching process is carried out to transfer the structure of the middle layer 116 to the lower layer 114, thereby widening the openings 122 through the lower layer 114. The etching process of the lower layer 114 is anisotropic, so that the openings 122 in the middle layer 116 are widened through the lower layer 114 and are essentially the same size in the middle layer 116 as in the lower layer 114. The upper layer 118 (see Fig. 1 and Fig. 2) can be consumed when etching the lower layer 114.

[0025] In Fig. 4 will be the structure of the lower layer 114 (see Fig. 3) transferred to the mandrel layer 112 using an etching process. The etching process of the mandrel layer 112 is anisotropic, so that the openings 122 in the lower layer 114 are enlarged through the mandrel layer 112. The openings 122 have approximately the same width in the mandrel layer 112 as in the lower layer 114. The etching can be a dry etching (e.g., plasma etching) or the like.

[0026] A layer immediately beneath the mandrel layer 112 (e.g., the hard mask 108) can be used as an etch stop layer during the structuring of the mandrel layer 112. In particular, the etching process can employ an etchant that selectively etches the mandrel layer 112 without substantially etching the hard mask layer 108. For example, in embodiments where the mandrel layer 112 contains silicon and the hard mask layer contains silicon oxide, the etching process can employ HBr, CF4, Cl2, NF3, or the like as the etchant.

[0027] Accordingly, mandrels 124 are formed from the remaining sections of the mandrel layer 112 (e.g., sections of the mandrel layer 112 between the openings 122). As illustrated, the mandrels 124 in each of the regions 100A, 100B, and 100C can have different sizes, which can correspond to a desired size of and / or spacing between features that are subsequently structured in the target layer 104. For example, the mandrels 124A and 124C in regions 100A and 100C can be thinner than the mandrel 124B in region 100B. In other embodiments, the mandrels 124 in each of the regions 100A, 100B, and 100C can have different relative dimensions. For example, in other embodiments, the mandrel 124C in region 100C can be wider than the mandrel 124A but thinner than the mandrel 100A. During the etching of the mandrel layer 112, the middle layer 116 is consumed, and the lower layer 114 can be at least partially consumed.

[0028] In embodiments where the lower layer 114 is not completely consumed during the etching of the mandrel layer 112, an ashing process can be carried out to remove any remaining traces of the lower layer 114. The ashing process can include oxygen plasma detachment, which exposes the mandrels 124 to an oxygen plasma.

[0029] In Fig. 5 A spacer layer 126 is formed over the mandrels 124 and along their side walls. The spacer layer 126 can also extend into the openings 122 along the upper surfaces of the hard mask 108. The material of the spacer layer 126 is selected to exhibit high etch selectivity with respect to the hard mask layer 108 and the mandrels 124. For example, the spacer layer 126 can contain SiN, SiCON, SiON, metals, metal alloys, and the like, and can be deposited using any suitable process, such as ALD, CVD, or the like. In some embodiments, the deposition process of the spacer layer 126 is conformed such that the thickness of the spacer layer 126 on side walls of the mandrels 124 is essentially (e.g. within production tolerances) equal to the thickness of the spacer layer 126 on the upper surface of the mandrels 124 and bottom surfaces of the openings 122.

[0030] In Fig. 6. The spacer layer 126 is structured to remove lateral sections of the spacer layer 126, leaving spacers 128 on the side walls of the mandrels 124. Etching the spacer layer 126 exposes the mandrels 124 and sections of the layer below the mandrels 124 (e.g., the hard mask 108). The structuring of the spacer layer 126 can include a dry etching process that selectively etches the spacer layer 126 at a higher etch rate than the mandrels 124. Exemplary etchants for etching the spacer layer 126 can include a reactive fluorine gas such as CF4, NF3, HCl, HBr, or the like. Other process gases, for example, oxygen (O2), nitrogen (N2), argon (Ar), combinations thereof, or the like, can be used in combination with the etchants.The dry etching process can be anisotropic and etch exposed lateral sections of the spacer layer 126, leaving vertical sections of the spacer layer 126 (the spacers 128) on the mandrels 124.

[0031] In Fig. 7 A mask 150 is formed over the mandrels 124 and the spacers 128 and along their side walls. The mask 150 can also extend into the openings 122 along the upper surfaces of the hard mask 108. The material of the mask 150 is selected to have high etch selectivity with respect to a cover layer subsequently formed over the mandrels 124 and the spacers 126 (see, e.g., Fig. 8) For example, the mask can contain 150 silicon oxide or the like and be deposited using any suitable process, such as ALD, CVD or the like.

[0032] The deposition process of the mask 150 can be conformed such that the thickness of the mask 150 on the side walls of the spacers 128 is substantially (e.g., within production tolerances) equal to the thickness of the mask 150 on the upper surface of the mandrels 124 and the bottom surfaces of the openings 122. In some embodiments, the deposition of the mask 150 can involve streams of a first carbon-containing precursor and oxygen (e.g., O2, N2O, CO2, or the like) in an ALD deposition chamber. The first carbon-containing precursor can be bis(diethylamino)silane, SiH4, SiH2Cl2, or the like, and the first carbon-containing precursor can be a compound having, for example, a carbon-to-nitrogen ratio of 4:1. The first carbon-containing precursor and the oxygen react to form monolayers of silicon oxide on exposed surfaces of the component 100.The first carbon-containing precursor and the oxygen can be cyclically pulsed and purged, with RF power (e.g., in the range of approximately 200 W to 800 W) applied between each pulse and purge cycle. The RF power can improve the surface condition of the individual atomic monolayers to facilitate the growth of subsequent monolayers during the ALD process.

[0033] In Fig. 8. A topcoat 152 is formed on the mask 150. The topcoat 152 can be a layer of pure carbon or a carbon-rich composite layer (e.g., a SiO1N layer, a SiOC layer, or the like). For example, the carbon concentration of the topcoat 152 can be at least 30%, which advantageously enables the topcoat 152 to adequately protect the underlying spacers 128 during subsequent processing steps (e.g., subsequent etching steps for the selective removal of the spacers 128 and / or the mandrels 126). It has been observed that a sufficiently high carbon concentration improves the etch resistance compared to a material of the mask 150. For example, the wet etching rate of the topcoat 152 using dilute hydrogen fluoride (dHF) can be at least half that of the mask 150.

[0034] In some embodiments, the cover layer 152 can have a thickness of less than approximately 2 nm, in the range of approximately 0.5 nm to approximately 1.5 nm or approximately 0.8 nm to approximately 0.9 nm. It has been observed that advantages can be gained by forming the cover layer 152 with a thickness in the aforementioned ranges. For example, forming a cover layer 152 with a thickness of less than approximately 0.5 nm may provide insufficient protection to the underlying features (e.g., the spacers 128) during subsequent etching steps, leading to damage of the underlying features. Furthermore, forming a cover layer 152 with a thickness greater than approximately 2 nm may make it difficult to remove the cover layer 152, particularly in areas with small critical dimensions, resulting in undesirable cover layer residue remaining in subsequent processing steps.

[0035] In some embodiments, the top layer 152 is formed in situ with the mask 150. For example, the top layer 152 can be formed in the same process chamber as the mask 150 without breaking the vacuum. In such embodiments, the formation of the top layer 152 can involve shutting off an oxygen flow into the process chamber and simultaneously flowing a second carbon-containing precursor into the deposition chamber to deposit monolayers of pure carbon or monolayers of the carbon-rich composite material (which, for example, has a carbon concentration of more than 30%). In some embodiments, the second carbon-containing precursor used to deposit the top layer 152 can be the same as the first carbon-containing precursor described above, which flows during the deposition of the mask 150.For example, the second carbon-containing precursor can be bis(diethylamino)silane, SiH4, SiH2Cl2, or the like, and the second carbon-containing precursor can be a compound having a carbon-to-nitrogen ratio of 4:1. In other embodiments, the second carbon-containing precursor can be a different compound than the first carbon-containing precursor used to deposit the mask 150. Furthermore, the second-containing precursor can have a carbon-to-nitrogen ratio greater than that of the first carbon-containing precursor. The deposition of the cover layer 152 can optionally include the simultaneous flow of one or more additional carbon-containing precursors (e.g., tetraethoxysilane (TEOS), tetramethyl orthosilicate, or the like) and a second carbon-containing precursor.By controlling the carbon ratio of the second carbon-containing precursor and / or by introducing one or more additional carbon-containing precursors, the carbon concentration of the cover layer 152 can be adjusted to a desired level. In other embodiments, a different process can be used to form the cover layer 152, such as an ex-situ deposition process in which the cover layer 152 is formed in a different process chamber than the mask 150.

[0036] In Fig. In Figure 9, a photoresist 154 is deposited over the top layer 152 in areas 100A, 100B, and 100C. The photoresist 154 can be deposited, for example, using a spin deposition process. Although the photoresist 154 is illustrated as a single layer, in some embodiments the photoresist 154 can be applied in a manner similar to the one shown above. Fig. 1 described three-layer photoresist 120, exhibit a three-layer structure.

[0037] In Fig. In 10, the photoresist 154 and the top layer 152 are structured such that the mask 150 is exposed in region 100C. The structuring of the photoresist 154 can be carried out using a photolithographic process. For example, the photoresist 154 can be exposed and developed to remove it from region 100C, leaving it exposed in regions 100A and 100B. Furthermore, in embodiments where the photoresist 154 has a three-layer structure, the structuring of the photoresist 154 can also include suitable etching processes, as described above with reference to the structuring of the photoresist 120. In some embodiments, removing the photoresist 154 from region 100C can involve an O 2-The ashing process also removes the top layer 152 from area 100C. The remaining sections of the photoresist 154 in areas 100A and 100B can act as masking sections of the top layer 152, ensuring that the top layer 152 remains in areas 100A and 100B.

[0038] In Fig. In Figure 11, the mask 150 is selectively removed from area 100C. The structuring of the mask 150 can be carried out by a wet etching process using the photoresist 154 and the top layer 152 as masks. The wet etching process can use dHF or the like as the etchant. Accordingly, the mandrels 124 and the spacers 128 in area 100C are exposed. In various embodiments, the top layer 152 protects the spacers 128 in areas 100A and 100B during the structuring of the mask 150. For example, the wet etchants used to etch the mask 150 (e.g., dHF) tend to penetrate the photoresist 154 and etch the mask 150 in areas 100A and 100B, leading to damage to the spacers 128 (e.g., material loss). As described above, the top layer 152 (e.g. a carbon-rich material) is resistant to etching with such etchants (e.g.dHF), and the top layer 150 provides an additional protective layer in areas 100A and 100B, reducing damage to the spacers 128 (e.g., reducing material loss in the spacers 128). Accordingly, the accuracy of the structuring can be increased. Furthermore, the spacers 128 can be removed from area 100C in subsequent processing steps, and damage to the spacers 128 in area 100C as a result of structuring the mask 150 need not lead to reduced control of the structuring.

[0039] In Fig. 12. Remaining sections of the photoresist 154 and the topcoat 152 are removed from areas 100A and 100B by etching. The removal of the photoresist 154 and the topcoat 152 can include a cleaning process using, for example, a hot sulfuric acid peroxide mixture (HTSPM), which removes both the photoresist 154 and the topcoat 152. As a result, the mask 150 is exposed in areas 100A and 100B. Optionally, a comparatively fast cleaning process (e.g., less than 30 s) using dHF can be performed to clean exposed surfaces of the mask 150 without damaging the underlying spacers 128. This cleaning can facilitate the removal of residual photoresist 154 from the surfaces of the mask 150.

[0040] In Fig. 13. The spacers 128 are removed from area 100C using a suitable etching process that selectively removes the spacers 128 without removing the mask 150. In some embodiments, the spacers 128 can be removed from area 100C using H3PO4, ozone, or the like as an etchant. The spacers 128 in areas 100A and 100C are masked by the mask 150 and are not removed.

[0041] In Fig. In 14, the mask 150 is removed from areas 100A and 100B by an etching process. In some embodiments, an etching process can be used to remove the mask 150 (e.g., an oxide) that etches the mask 150 at a lower rate than the underlying hard mask layer 106 (e.g., a nitride layer). The etching process for removing the mask 150 uses, for example, dHF or the like as the etchant. In other embodiments, other etching processes can be used.

[0042] In Fig. In section 15, a photoresist 156 is deposited over the spacers 138 and the mandrels 124 in areas 100A, 100B, and 100C. The photoresist 156 can be deposited, for example, using a spin deposition process. Although the photoresist 156 is illustrated as a single layer, in some embodiments the photoresist 156 can be applied in a manner similar to the one shown above. Fig. The three-layer photoresist 120 described in section 1 has a three-layer structure. As also described in... Fig. As illustrated in Figure 15, the photoresist 156 can be textured to expose the spacers 128 and the mandrels 124 in area 100A. Texturing the photoresist 156 can be carried out using a suitable lithography and / or etching process as described above (e.g., with respect to the texturing of photoresist 120).

[0043] In Fig. In Figure 16, the mandrels 124 are removed from area 100A. The mandrels 124 are removed using an etching process. Since the mandrels 124 and the spacers 128 exhibit etch selectivity in an etching process, the mandrels 124 can be removed without removing the spacers 128. Etching the mandrels 124 exposes the underlying hard mask 108, which can act as an etch stop layer. In some embodiments, etching the mandrels 124 can reduce the height of the spacers 128 without removing them. Removing the mandrels 124 can involve a dry etching process similar to the process used to pattern the mandrels 124, as described above. Fig. 4 is used. Subsequently, the photoresist 156 is removed using an acceptable cleaning and / or O2 ashing process. The resulting structure is in Fig. 17 illustrated.

[0044] In Fig. Figure 18 describes how the hard mask 108 is etched using the spacers 128 and the mandrels 124 as an etching mask. Specifically, the hard mask 108 is structured in area 100A using the spacers 128 as a mask; the hard mask 108 is structured in area 100B using a combination of the spacers 128 and the mandrels 124 as a mask; and the hard mask 108 is structured in area 100C using the mandrel 124 as a mask. Thus, the hard mask 108 can be structured by using different combinations of the spacers 128 and / or the mandrels 124 such that it has different spacings and feature sizes in each of the areas 100A, 100B, and 100C.

[0045] In some embodiments, the etching of the hard mask 108 comprises anisotropic dry etching and / or wet etching. For example, the hard mask 108 can be structured by dry etching (e.g., using CF4, NF3, HCl, HBr, or the like), subsequent wet etching (e.g., using dilute hydrogen fluoride (DHF), a sulfur peroxide mixture (SPM), or the like) to remove by-products, and a cleaning process (e.g., Standard Clean 1 (SC-1) or the like) to remove particles. The etching of the hard mask 108 may consume the spacers 128.

[0046] Then in Fig. 19 The hard mask 108 is used as an etching mask to structure openings 140 in the target layer 104, which can define fins 142. Etching the target layer 104 can involve an anisotropic dry etching process and / or a wet etching process. Remaining sections of the target layer 104 can have the same structure as the spacers 128 and mandrels 124. Fig. 17 exhibit. Since different combinations of the spacers 128 and the mandrels 124 are used as masks, different sizes of fins 142 and distances between fins 142 can be achieved in the target layer 104 in each of the areas 100A, 100B and 100C.

[0047] Additional process steps can be applied to the structure 100 to form Fin field-effect transistor (FinFET) devices. Fig. Figure 20 illustrates a FinFET device in a perspective view. In various embodiments, isolation regions can be deposited around the fins 142, and then the isolation regions can be recessed to expose upper sections of the fins 142. Openings can be structured in the upper sections of the fins 142, and epitaxial source / drain regions can be grown in the openings. Furthermore, gate structures can be formed over upper sections of the fins 142 and along their sidewalls. The FinFET comprises a fin 142, which, according to the above, Fig. The processes described in Figures 1-19 can be structured. The fin 142 projects upwards between adjacent insulation regions 56. A gate dielectric layer 92 is located along side walls and over an upper surface of the fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are arranged on opposite sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94.

[0048] The target layer 104 in the above embodiment is a single layer of material. In other embodiments, the target layer 104 in various regions 100A, 100B or 100C can have a multilayer structure or a combination of single layers / multilayer structures.

[0049] For example, illustrate Fig. 21 and Fig. 22 An embodiment in which the target layer 104 has a multilayer structure with alternating semiconductor layers 104A and 104B. The semiconductor layers 104A can contain a first semiconductor material, and the semiconductor layers 104B can contain a second semiconductor material that can be selectively etched with respect to the first semiconductor material. For example, the semiconductor layers 104A can contain silicon, while the semiconductor layers 104B can contain silicon germanium. The semiconductor layers 104B can subsequently be removed, and the semiconductor layers 104A can be patterned to form channel regions of a nanostructured transistor device. In some embodiments, the nanostructured transistor can be a nanowire transistor, a nanosheet transistor, a gate all-around transistor, or the like.

[0050] Fig. Figure 21 illustrates an initial component 200, which corresponds to component 100. Fig. 1 is similar, where the same reference symbols denote the same elements that are formed using the same processes. Fig. Figure 22 illustrates the component 200 after the structuring of the target layer 104, in order to use a process as above with reference to Fig. Figures 1-19 describe how to define the fins 142. For example, different combinations of spacers and / or mandrels are used to define fins 142 that have different sizes and spacings in different regions 100A, 100B, and 100C of the component 200. A carbon layer or carbon-rich layer can be used as a cover layer to protect spacers in regions 100A and 100B, while the spacers are selectively removed from region 100C. Accordingly, improved control of the fin structuring 142 can be achieved.

[0051] Further process steps can be applied to the device 200 to form nanostructured transistor devices. For example, isolation areas can be deposited around the fins, and these isolation areas can then be recessed to expose upper sections of the fins. Openings can be structured in the upper sections of the fins, and epitaxial source / drain regions can be grown in these openings. Additionally, the semiconductor layers 104A can be removed, and the semiconductor layers 104B can be structured to define channel regions. Gate structures can be formed around these channel regions.

[0052] Fig. Figure 23 illustrates a three-dimensional view of an example of a nanostructured transistor according to some embodiments. The nanostructured transistors comprise nanostructures 55 (e.g., nanosheets, nanowires, or the like) over fins on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 act as channel regions of the nanostructured transistors. The nanostructures 55 can be formed by structuring the semiconductor layers 104A. The nanostructure 55 can include p-type nanostructures, n-type nanostructures, or a combination thereof. Insulation regions 68 are arranged between adjacent fins 66, which can project upwards between neighboring insulation regions 68.Although the isolation regions 68 are described / illustrated as separate from the substrate 50, the term "substrate," as used here, can refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the isolation regions. Additionally, although the base section of the fins 66 is illustrated as a single, contiguous material with the substrate 50, the base section of the fins 66 and / or the substrate 50 can comprise a single material or a multitude of materials. In this context, the fins 66 refer to the section extending between the adjacent isolation regions 68.

[0053] Fig. 24 and Fig. Figure 25 illustrates an alternative embodiment in which the target layer 104 comprises a multilayer structure (e.g., the semiconductor layers 104A / 104B) embedded in a semiconductor substrate 104C. The multilayer structure may be located in region 100B, and the multilayer structure may not extend into regions 100A or 100C. The semiconductor substrate 104C may contain doped or undoped silicon or comprise an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 104 may include other semiconductor materials, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The target layer 104 from Fig. 24 and Fig. 25 can be formed, for example, by structuring a depression in the semiconductor substrate 104C in the area 100B using a combination of photolithography and etching. Next, the semiconductor layers 104A and 104B can be grown alternately in the depression of the semiconductor substrate 104C. The semiconductor layers 104A and 104B can be oriented as described above with reference to Fig. 21 and Fig. 22 described similarly.

[0054] Fig. Figure 24 illustrates an initial component 300, which corresponds to component 100. Fig. 1 is similar, where the same reference symbols denote the same elements that are formed using the same processes. Fig. Figure 25 illustrates the component 300 after the structuring of the target layer 104, in order to use a process as above with reference to Fig. Figures 1-19 describe how to define the fins 142. For example, different combinations of spacers and / or mandrels are used to define fins 142 that have different sizes and spacings in different regions 100A, 100B, and 100C of the device 300. A carbon layer or carbon-rich layer can be used as a cover layer to protect the spacers in regions 100A and 100B, while the spacers are selectively removed from region 100C. The fins 142 can have a monolithic composition in regions 100A and 100C, while the fins 142 in region 100B have a multilayer structure (which includes, for example, the semiconductor layers 104A and 104B). Additional process steps, as described above, can be applied to the component 300 to form nanostructured transistor devices in the 100B area and FinFET transistors in the 100A and 100C areas.

[0055] The target layer 104 can enclose a multilayer structure in any of the regions 100A, 100B, or 100C. For example, illustrate... Fig. 26 and Fig. 27 a device 400 in which the target layer 104 includes a multilayer structure (e.g. the semiconductor layers 104A / 104B) embedded in a semiconductor substrate 104C. The multilayer structure may be located in the regions 100B and 100C, and the multilayer structure may not extend into the region 100A.

[0056] Fig. Figure 26 illustrates an initial component 400, which corresponds to component 300. Fig. 24 and Fig. 25 is similar, where the same reference symbols denote the same elements that are formed using the same processes. Fig. Figure 27 illustrates the component 400 after the structuring of the target layer 104, in order to use a process as above with reference to Fig.Figures 1-19 describe how to define the fins 142. For example, different combinations of spacers and / or mandrels are used to define fins 142 that have different sizes and spacings in different regions 100A, 100B, and 100C of the device 400. A carbon layer or carbon-rich layer can be used as a cover layer to protect the spacers in regions 100A and 100B, while the spacers are selectively removed from region 100C. The fins 142 can have a monolithic composition in regions 100A and 100C, while the fins 142 in region 100B have a multilayer structure (which includes, for example, the semiconductor layers 104A and 104B). Additional process steps, as described above, can be applied to the 400 component to form nanostructured transistor devices in areas 100B and 100C and FinFET transistors in area 100A.

[0057] Various embodiments provide dual structuring processes in which spacers are formed on the sidewalls of mandrels. Depending on the desired resulting feature size, the mandrels and spacers can be selectively removed from different regions above a target layer. To achieve selective removal, one or more masks can be deposited over the mandrels and spacers. In various embodiments, a high-carbon layer can be deposited over the spacers (e.g., between different masks) to reduce etch damage (e.g., loss of spacer material) resulting from the selective removal of the mandrels and / or spacers. Therefore, mandrels and spacers can be structured with the correct dimensions, and control of critical dimensions during structuring of the target layer can be improved.

[0058] In some embodiments, a method includes depositing a first mask over a first region of a target layer and a second region of the target layer; forming a plurality of mandrels over the first mask; forming a plurality of spacers on sidewalls of the plurality of mandrels; depositing a second mask over the plurality of mandrels and the plurality of spacers; forming a cover layer over the second mask, the cover layer comprising carbon; and structuring the second mask and the cover layer to expose a first mandrel of the plurality of mandrels and first spacers of the plurality of spacers, the first mandrel and the first spacer overlapping the first region of the target layer.In some embodiments, the method further includes removing the first spacers; after removing the first spacers, removing any remaining sections of the cover layer and remaining sections of the second mask; after removing the remaining sections of the cover layer and the remaining sections of the second mask, structuring the first mask, wherein structuring the first mask comprises transferring a structure of the first mandrel to the first mask; and transferring a structure of the first mask to the target layer. In some embodiments, structuring the first mask comprises transferring a structure of second spacers to the first mask, wherein the plurality of spacers comprises the second spacers and wherein the second spacers overlap the second region of the target layer.In some embodiments, structuring the first mask comprises transferring a second mandrel structure to the first mask, wherein the second mandrel is arranged between the second spacers. In some embodiments, the cover layer has a carbon concentration of at least 30%. In some embodiments, forming the cover layer comprises forming the cover layer in the same process chamber in which the second mask was deposited. In some embodiments, depositing the second mask comprises flows of a first carbon-containing precursor and oxygen over the plurality of spacers and the plurality of mandrels, wherein forming the cover layer comprises flows of a second carbon-containing precursor over the second mask without flows of oxygen. In some embodiments, the second carbon-containing precursor is the same chemical compound as the first carbon-containing precursor.In some embodiments, the second carbon-containing precursor is a different chemical compound than the first carbon-containing precursor.

[0059] In some embodiments, a method includes depositing a first hard mask over a target layer; forming a first mandrel and a second mandrel over the first hard mask; forming first spacers on side walls of the first mandrel and second spacers on side walls of the second mandrel; depositing an oxide layer over the first mandrel, the second mandrel, the first spacers, and the second spacers; forming a carbonaceous cover layer over the oxide layer; structuring the carbonaceous cover layer to expose the oxide layer; structuring the oxide layer to expose the second mandrel and the second spacers, masking the first spacers and the first mandrel with the carbonaceous cover layer; removing the second spacers; after removing the second spacers,Removing remaining sections of the carbonaceous top layer and the oxide layer; transferring a structure of the first spacers, the first mandrel, and the second mandrel onto the first hard mask; and structuring the target layer using the first hard mask as a mask. In some embodiments, the method further includes forming a photoresist over the carbonaceous top layer; and structuring the photoresist, wherein the structuring of the photoresist includes an ashing process, and wherein the structuring of the carbonaceous top layer includes using the ashing process to remove a section of the carbonaceous top layer.which overlaps the second spacers and the second mandrel. In some embodiments, structuring the oxide layer comprises a wet etching process with dilute hydrogen fluoride (dHF). In some embodiments, the carbonaceous top layer has a carbon concentration of at least 30%. In some embodiments, forming the carbonaceous top layer comprises forming the carbonaceous top layer in the same atomic layer deposition (ALD) chamber in which the oxide layer was deposited. In some embodiments, the carbonaceous top layer has a thickness in the range of 0.5 nm to 1.5 nm. In some embodiments, depositing the oxide layer comprises flows of a first carbonaceous precursor,wherein the formation of the carbonaceous cover layer comprises flows of a second carbonaceous precursor and wherein the first carbonaceous precursor and the second carbonaceous precursor are identical. In some embodiments, the deposition of the oxide layer comprises flows of a first carbonaceous precursor, wherein the formation of the carbonaceous cover layer comprises flows of a second carbonaceous precursor and wherein the second carbonaceous precursor has a higher carbon-to-nitrogen ratio than the first carbonaceous precursor.

[0060] In some embodiments, a process includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; selectively removing the second spacers and masking the first spacers, wherein masking the first spacers comprises covering the first spacers with a second mask and a cover layer over the second mask, the cover layer containing at least 30% carbon; structuring the first mask, wherein structuring the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers; and transferring a structure of the first mask to the target layer. In some embodiments, the target layer comprises a multilayer structure.In some embodiments, the method further includes forming a third mandrel; forming third spacers on the third mandrel; and, after selectively removing the second spacers, selectively removing the third mandrel and thereby masking the first mandrel, the first spacers and the second mandrel, wherein structuring the first mask further comprises masking the first mask with the third spacers.

Claims

[1] Method, comprising: Deposition of a first mask (106, 108) over a first area (100C) of a target layer (104) and a second area (110A, 110B) of the target layer (104); Forming a multitude of thorns (124) above the first mask (106, 108); Forming a plurality of spacers (128) on side walls of the plurality of spines (124); Deposition of a second mask (150) over the plurality of spines (124) and the plurality of spacers (128); Forming a cover layer (152) over the second mask (150), wherein the cover layer (152) contains carbon; and Structuring the second mask (150) and the cover layer (152) to expose a first mandrel (124) of the plurality of mandrels (124) and upper surfaces and side walls of first spacers (128) of the plurality of spacers (128), wherein the first mandrel (124) and the first spacers (128) overlap the first area (110C) of the target layer (104), wherein the cover layer (152) remains above the second area (110A, 110B) of the target layer (104) after the first mandrel (124) of the plurality of mandrels (124) and the upper surfaces and side walls of the first spacers (128) of the plurality of spacers (128) are exposed, wherein the second mask (150) is conformally deposited on side walls of the plurality of spacers (128), on upper surfaces of the plurality of mandrels (124) and on upper surfaces of the first mask (106, 108) which are arranged laterally next to the plurality of spacers (128) and next to the plurality of mandrels (124), such that the second mask (150) extends on upper surfaces of the first mask (106, 108) between spacers (128) which are formed on side walls of adjacent mandrels (124), the top layer (152) is formed on the second mask (150). [2] Method according to claim 1, further comprising: Removing the first spacers (128); after removing the first spacers (128), removing remaining sections of the top layer (152) and remaining sections of the second mask (150); after removing the remaining sections of the top layer (152) and the remaining sections of the second mask (150), structuring the first mask (106, 108), wherein the structuring of the first mask (106, 108) comprises transferring a structure of the first mandrel (124) to the first mask (106, 108); and Transferring a structure from the first mask (106, 108) to the target layer (104). [3] Method according to claim 2, wherein the structuring of the first mask (106, 108) comprises transferring a structure of second spacers (128) to the first mask (106, 108), wherein the plurality of spacers (128) comprise the second spacers (128) and wherein the second spacers (128) overlap the second region (100A, 100B) of the target layer (104). [4] Method according to claim 3, wherein the structuring of the first mask (106, 108) comprises transferring a structure of a second mandrel (124) to the first mask (106, 108), wherein the second mandrel (124) is arranged between the second spacers (128). [5] Method according to any of the preceding claims, wherein the top layer (152) has a carbon concentration of at least 30%. [6] Method according to any of the preceding claims, wherein the formation of the cover layer (152) comprises the formation of the cover layer (152) in the same process chamber in which the second mask (150) was deposited. [7] Method according to claim 6, wherein the deposition of the second mask (150) comprises streams of a first carbon-containing precursor and of oxygen via the plurality of spacers (128) and the plurality of mandrels (124), wherein the formation of the cover layer (152) comprises streams of a second carbon-containing precursor via the second mask (150) without streams of oxygen. [8] The method of claim 7, wherein the second carbon-containing precursor is the same chemical compound as the first carbon-containing precursor. [9] The method of claim 7, wherein the second carbon-containing precursor is a different chemical compound than the first carbon-containing precursor. [10] Methods comprising: Deposition of a first hard mask (106, 108) over a target layer (104); Formation of a first spine (124) and a second spine (124) over the first hard mask (106, 108); Forming first spacers (128) on side walls of the first mandrel (124) and second spacers (128) on side walls of the second mandrel (124); Deposition of an oxide layer (150) over the first mandrel (124), the second mandrel (124), the first spacers (128) and the second spacers (128); Formation of a carbonaceous top layer (152) over the oxide layer (150); Structuring the carbonaceous cover layer (152) to expose the oxide layer (150); exposing the surfaces and sidewalls of the second spacers (128) while masking the first spacers (128) and the first mandrel (124) with the carbonaceous cover layer (152); Removing the second spacer (128); after removing the second spacers (128), removing remaining sections of the carbonaceous top layer (152) and the oxide layer (150); Transferring a structure of the first spacers (128), the first mandrel (124) and the second mandrel (124) to the first hard mask (106, 108); and Structuring the target layer (104) using the first hard mask (106, 108) as a mask, wherein the oxide layer (150) is conformally deposited on side walls of the first and second spacers (128), on upper surfaces of the first and second mandrels (124) and on upper surfaces of the first hard mask (106, 108), which are arranged laterally next to the first and second spacers (128) and next to the first and second mandrels (124), such that the oxide layer (150) extends on upper surfaces of the first hard mask (106, 108) between one of the first spacers (128) and one of the second spacers (128) between the first mandrel (124) and the second mandrel (124), wherein the carbon-containing top layer (152) is formed on the oxide layer (150). [11] Method according to claim 10, further comprising: Formation of a photoresist (154) over the carbon-containing top layer (152); and Structuring the photoresist (154), wherein the structuring of the photoresist (154) comprises an ashing process and wherein the structuring of the carbon-containing top layer (152) comprises using the ashing process to remove a section of the carbon-containing top layer (152) that overlaps the second spacers (128) and the second mandrel (124). [12] Method according to claim 10 or 11, wherein the structuring of the oxide layer (150) comprises a wet etching process with dilute hydrogen fluoride, dHF. [13] Method according to any one of the preceding claims 10 to 12, wherein the carbon-containing cover layer (152) has a carbon concentration of at least 30%. [14] Method according to any one of the preceding claims 10 to 13, wherein the formation of the carbon-containing cover layer (152) comprises the formation of the carbon-containing cover layer (152) in the same atomic layer deposition chamber in which the oxide layer (150) was deposited. [15] Method according to any one of the preceding claims 10 to 14, wherein the carbon-containing cover layer (152) has a thickness in the range of 0.5 nm to 1.5 nm. [16] Method according to any one of the preceding claims 10 to 15, wherein the deposition of the oxide layer (152) comprises currents of a first carbon-containing precursor, wherein the formation of the carbon-containing cover layer (152) comprises currents of a second carbon-containing precursor and wherein the first carbon-containing precursor and the second carbon-containing precursor are identical. [17] Method according to any one of the preceding claims 10 to 16, wherein the deposition of the oxide layer (150) comprises currents of a first carbon-containing precursor, wherein the formation of the carbon-containing cover layer (152) comprises currents of a second carbon-containing precursor and wherein the second carbon-containing precursor has a higher carbon-to-nitrogen ratio than the first carbon-containing precursor. [18] Methods, comprising: Deposition of a first mask (106, 108) over a target layer (104); Forming a first thorn (124) and a second thorn (124) above the first mask (106, 108); Forming first spacers (128) on the first mandrel (124) and second spacers (128) on the second mandrel (124); selective removal of the second spacers (128) and masking of the first spacers (128), wherein the masking of the first spacers (128) comprises covering the first spacers (128) with a second mask (150) and a cover layer (152) over the second mask (150), and wherein the cover layer (152) contains at least 30% carbon; mask (106, 108) comprises masking the first mask (106, 108) with the second mandrel (124), the first mandrel (124), and the first spacers (128); and Transferring a structure from the first mask (106, 108) to the target layer (104), where covering the first spacers (128) with the second mask (150) and the top layer (152) over the second mask (150) has the following effect: conformal deposition of the second mask (150) on side walls of the first and second spacers (128), on upper surfaces of the first and second mandrels (124) and on upper surfaces of the first mask (106, 108) which are arranged laterally next to the first and second spacers (128) and next to the first and second mandrels (124), such that the second mask (150) extends on upper surfaces of the first mask (106, 108) between one of the first spacers (128) and one of the second spacers (128) between the first mandrel (124) and the second mandrel (124); and Forming the top layer (152) on the second mask (150). [19] Method according to claim 18, wherein the target layer (104) has a multilayer structure. [20] Method according to claim 18 or 19, further comprising: Forming a third thorn (124); Forming third spacers (128) on the third mandrel (124); and, after selective removal of the second spacers (128), selective removal of the third mandrel (124) and masking of the first mandrel (124), the first spacers (128) and the second mandrel (124), wherein the structuring of the first mask (106, 108) further comprises masking of the first mask (106, 108) with the third spacers (128).

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