Back-end-of-line equipment and corresponding manufacturing process

Abstract

Semiconductor structure with: a transistor (260); and an interconnect structure (300) arranged above the transistor (260), wherein the interconnect structure (300) comprises the following: a first dielectric layer (218), a first conductive structural element (220) in the first dielectric layer (218), a first etch stop layer (224) arranged above the first dielectric layer (218) and the first conductive structural element (220), a dielectric structural element (228) arranged in the first etch stop layer (224), an electrode (230, 500) arranged above the dielectric structural element (228), a second etch stop layer (232) arranged above the first etch stop layer (224) and the electrode (230, 500), a second dielectric layer (234) arranged on the second etch stop layer (232), a via (236) which is arranged in the second etch stop layer (232) and the second dielectric layer (234) and is coupled to the electrode (230, 500), and a second conductive structural element (238) which is arranged in the second dielectric layer (234) and is coupled to the via (236).

Description

BACKGROUND

[0001] The IC (integrated semiconductor circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Throughout IC evolution, feature density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while feature size (i.e., the smallest component or trace that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production output and reducing associated costs. However, this miniaturization has also increased the complexity of machining and manufacturing ICs.

[0002] The ever-shrinking dimensions of high-voltage devices present challenges in their fabrication. These devices are larger, can cause topographical problems, and compress the space available for other structural elements. The higher operating voltage of high-voltage devices can rupture gate oxide layers and lead to unintended device activation. While OTP memory structures are generally adequate for their intended purpose, they are not satisfactory in every respect.

[0003] US 2007 / 0040276 A1 discloses an anti-fuse structure which contains a buried electrically conductive, e.g. metallic, layer as an anti-fuse material, and a method for forming such an anti-fuse structure is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. It should also be noted that the accompanying drawings merely show typical embodiments of the present invention, and the invention may also apply to other embodiments. Fig. Figure 1 is a flowchart showing a process for manufacturing a semiconductor structure according to various aspects of the present disclosure. The Fig. Figures 2-9 show schematic, fragmentary sectional views of a workpiece undergoing various manufacturing steps according to the process in Fig. 1, according to various aspects of the present revelation. Fig. 10 is a circuit diagram that is for the in Fig. The semiconductor structure shown in 9 is representative. The Fig. Figures 11-13 show schematic layout top views of a one-time programmable memory device (OTP memory device) (OTP: one-time programmable) designed using the method of Fig. 1 is produced according to various aspects of the present revelation. The Fig. Figures 14-15 show a schematic fragmentary sectional view of an alternative semiconductor structure produced using the method of Fig. 1 is produced according to various aspects of the present revelation. The Fig. Figures 16-19 show schematic layout top views of a high-resistance device (Hi-R device) or a high-resistance resistor (Hi-R resistor) produced using the method of Fig. 1 is produced according to various aspects of the present revelation. Fig. Figure 20 shows a semiconductor structure that incorporates both an OTP storage device and a high-resistance device (Hi-R device) according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The invention is defined by claims 1, 12, and 17, which define a semiconductor structure, a semiconductor assembly, and a method, respectively. Embodiments of the invention are provided in the dependent claims, the description, and the figures. The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure.For example, the fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, so that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in this disclosure. This repetition serves for simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] Furthermore, when a number or range of numbers is described using terms such as "about," "approximately," and the like, the term is intended to encompass numbers that lie within a reasonable range containing the stated number, taking into account variations that generally occur during manufacturing, as should be clear to any person skilled in the art. For example, the number or range encompasses a reasonable range containing the stated number, such as ±10% of the stated number, based on known manufacturing tolerances associated with the production of a structural element possessing a property related to the number. For example, a material layer with a thickness of "about 5 nm" may encompass a dimensional range from 4.25 nm to 5.75 nm, and it should be known to a person skilled in the art that manufacturing tolerances associated with the deposition of the material layer are ±15%.Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0008] Semiconductor memory devices can generally be divided into two types: volatile and non-volatile. A volatile memory device loses stored data when the circuit is powered off. In contrast, a non-volatile memory device retains stored data even after the power is turned off. Non-volatile memory devices can be further divided into two subcategories: multiple-time programmable (MTP) devices, which can perform multiple programming operations, and one-time programmable (OTP) devices, which can perform only one irreversible programming operation.With some existing technologies, OTP memory devices can be fabricated using transistor structures in a front-end-of-line (FEOL) process. In these existing technologies, the dielectric gate layer can serve as a fuse element or programming element. However, as the dimensions of semiconductor devices continue to decrease, it can become difficult to fabricate OTP memory devices using transistor structures while still maintaining satisfactory endurance or reliability at high voltages.

[0009] The present disclosure provides methods for fabricating an OTP memory device in an interconnect structure, which is manufactured in back-end-of-line (BEOL) processes together with high-resistance (Hi-R) resistors. The OTP memory devices of the present disclosure comprise a metal-insulator-metal (MIM) structure and a U-shaped breakdown layer enclosing an upper electrode structural element. According to the present disclosure, fabricating the OTP memory devices and Hi-R resistors in the BEOL structure can reduce the circuit area and lower the manufacturing costs associated with photolithography masks.

[0010] The various aspects of the present revelation will now be described in more detail with reference to the figures. In this respect, Fig. Figure 1 is a flowchart illustrating a method 100 for fabricating a semiconductor structure according to embodiments of the present disclosure. The method 100 is merely an example and is in no way intended to limit the present invention to what is expressly shown in the method 100. Further steps may be provided before, during, and / or after the method 100, and some of the described steps may be replaced or omitted or performed in a different order in further embodiments of the method. For the sake of simplicity, not all steps are described in detail here. The method 100 is subsequently described with reference to the Fig. References 2-9 describe fragmentary sectional views of a workpiece 200 at various stages of manufacturing according to embodiments of the method 100. Since the workpiece 200 is incorporated into a semiconductor structure or semiconductor device at the end of the manufacturing process, the workpiece 200 can also be referred to as a semiconductor structure 200 or a semiconductor device 200, depending on the context. Furthermore, the same reference numerals are used throughout the application to denote identical elements, with exceptions reserved.

[0011] With reference to the Fig. 1 and Fig. 2. The process 100 comprises a block 102 in which a workpiece 200 is taken. As in Fig. As shown in Figure 2, the workpiece 200 can have a substrate 202 and an interconnect structure 300 arranged above the substrate 202. The substrate 202 can be a silicon (Si) substrate. In some other embodiments, the substrate 202 can have other semiconductors, such as germanium (Ge), silicon-germanium (SiGe), or a III-V semiconductor material. Exemplary III-V semiconductor materials can include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 can also include an insulating layer, such as a silicon oxide layer, and thus have a silicon-on-insulator (SOI) structure.

[0012] The workpiece 200 further comprises a transistor 260, which is fabricated on the substrate 202. The transistor 260 can be a multi-gate device, such as a fin-like field-effect transistor (FinFET) or a multi-bridge-channel transistor (MBC). A FinFET has a raised channel that is enclosed on more than one side by a gate (for example, the gate encloses a top and side walls of a "fin" made of semiconductor material extending from a substrate). An MBC transistor has a gate structure that extends partially or completely around a channel region to provide access to the channel region on two or more sides. Because the gate structure of an MBC transistor encloses the channel regions, an MBC transistor can also be called a surrounding-gate transistor (SGT) or gate-all-around transistor (GAA).The channel region of an MBC transistor can be in the form of nanowires, nanolayers, or other nanostructures, and for these reasons, an MBC transistor can also be referred to as a nanowire transistor or a nanolayer transistor. As in . Fig. As shown in Figure 2, the transistor 260 comprises a source structural element 208S, a drain structural element 208D, an active region 203 located between the source structural element 208S and the drain structural element 208D, a dielectric gate layer 204 located above the active region 203, and a gate electrode 206 located above the dielectric gate layer 204. Depending on the type of transistor 260, the active region 203 may have a fin-like shape or may have a plurality of channel elements extending between the source structural element 208S and the drain structural element 208D. Detailed structures of the active region 203 may not be explicitly shown in the figures.

[0013] Transistor 260 can be an n-type or a p-type transistor. If transistor 260 is an n-type transistor, the source structural element 208S and the drain structural element 208D can comprise silicon (Si) and an n-type dopant, such as phosphorus (P) or arsenic (As). If transistor 260 is a p-type transistor, the source structural element 208S and the drain structural element 208D can comprise silicon germanium (SiGe) and a p-type dopant, such as boron (B) or boron difluoride (BF₂). In one embodiment, the dielectric gate layer 204 can comprise hafnium oxide or other suitable high-k dielectric materials whose dielectric constant is greater than that of silicon dioxide (~3.9). The gate electrode 206 can have a single-layer or alternatively a multi-layer structure, such as various combinations of a metallic fill layer and a plurality of metallic exit working layers.For example, the gate electrode 206 can comprise titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other low-melting-point metals, or other suitable metallic materials, or a combination thereof. The dielectric gate layer 204 and the gate electrode 206 can be collectively referred to as a gate structure. The transistor 260 can be configured to serve as a logic device or a selection transistor for an OTP storage device.If transistor 260 serves as a selection transistor for an OTP storage device, the gate electrode 206 is a word line (WL) or the gate electrode 206 is coupled to a word line (WL) and the source structural element 208S is coupled to a source line (SL).

[0014] The workpiece 200 has middle-end-of-line (MEOL) structural elements for electrically connecting the transistor to the interconnect structure 300. In the illustrated embodiments, the transistor 260 in the workpiece 200 comprises a source contact 210S above the source structural element 208S, a drain contact 210D above the drain structural element 208D, a source via 212S located on the source contact 210S, and a drain via 212D located on the drain contact 210D. The source contact 210S, the drain contact 210D, the source via 212S and the drain via 212D can each have a metallic fill layer made of ruthenium (Ru), tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo).In some embodiments, the source contact 210S, the drain contact 210D, the source via 212S, and the drain via 212D may each further comprise a barrier layer to prevent unwanted oxygen diffusion or electromigration. During fabrication, the barrier layer may contain titanium nitride or tantalum nitride. Although not explicitly shown in the figures, the source contact 210S, the drain contact 210D, the source via 212S, and the drain via 212D are arranged in at least one interlayer dielectric (ILD) layer. The at least one ILD layer may comprise tetraethyl orthosilicate oxide (TEOS oxide), undoped silica glass or doped silicon dioxide, such as boron phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.

[0015] The Interconnect Structure 300 is fabricated using BEOL processes and is considered a BEOL structure. The Interconnect Structure 300 can have multiple interconnect layers. Each interconnect layer comprises conductive conductors and vias embedded in an intermetal dielectric (IMD) layer. The conductive conductors and vias can contain aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), copper (Cu), or a combination thereof. The IMD layers can contain tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon dioxide, such as boron phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials.The dielectric materials used for the ILD and IMD layers are low-k dielectric materials, with a dielectric constant lower than that of silicon dioxide (~3.9). The low dielectric constants of the ILD and IMD layers support lower parasitic capacitances between adjacent conductive structural elements.

[0016] In some embodiments, a fully fabricated interconnect structure 300 can have approximately 8 and approximately 16 interconnect layers. In the Fig. In the embodiment shown in Figure 2, the interconnect structure 300 has a first conductive line 214 above and in direct contact with the drain via 212D. The first conductive line 214 is located in a bottom interconnect layer of the interconnect structure 300. A second conductive line 220 is arranged above the first conductive line 214 and can be a conductive line in an intermediate interconnect layer, located above the bottom interconnect layer but below the top interconnect layer of the interconnect structure. For example, if the interconnect structure 300 has 10 interconnect layers, the second conductive line 220 can be located in one of the second, third, fourth, fifth, sixth, seventh, eighth, or ninth interconnect layers.The first conductive line 214 can be coupled to the interconnect layers above it via a first via 216. As in . Fig. As shown in Figure 2, the second conductive conductor 220 and other conductive conductors in the same interconnect layer are arranged in a first IMD layer 218, which may comprise tetraethyl orthosilicate oxide (TEOS oxide), undoped silica glass or doped silicon dioxide, such as boron phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.

[0017] Conductive traces and vias in different interconnect layers can have varying dimensions. In some instances, the first four or five interconnect layers, which are closer to the FEOL structures, may have smaller dimensions, while the interconnect layers further up may have larger dimensions. As described below, steps of Procedure 100 are to be performed above the second conductive trace 220 in an intermediate interconnect layer. It may be more economical for this intermediate interconnect layer to be among those with larger conductive structural elements because performing photolithography and etching processes on such higher layers requires less accuracy and has a greater tolerance. The presence of other BEOL structures is another factor in deciding in which interconnect layer to perform Procedure 100.If an interconnect layer has a high density of BEOL structures, this can lead to greater difficulties in the process and a lower yield.

[0018] With reference to the Fig. 1, Fig. 2 and Fig. 3. Method 100 comprises a block 104 in which a first etch stop layer (ESL) 222 and a second ESL 224 are deposited over the workpiece 200. The composition of the first ESL 222 differs from the composition of the second ESL 224. In some embodiments, the first ESL 222 can be a nitrogen-containing layer and the second ESL 224 is an oxygen-containing layer. The second ESL 224 is arranged on top of the first ESL 222. The first ESL 222 can comprise silicon nitride, silicon oxide carbonitride, or silicon carbonitride. The second ESL 224 can comprise silicon oxide. The rectangular area marked with a dashed line in Fig. 2 is enlarged in Fig. Figure 3 shows a fragmentary sectional view of workpiece 200. As in Fig. As shown in Figure 3, the first total thickness TT1 of the first ESL 222 and the second ESL 224 along the Z-direction can be between approximately 50 nm and approximately 1000 nm. In the illustrated embodiments, the second thickness T2 of the second ESL 224 is between approximately 10.0 nm and approximately 15.0 nm greater than the first thickness T1 of the first ESL 222, so that the second ESL 224 can have a thickness sufficient for performing a planarization process. In some instances, the second thickness T2 of the second ESL 224 can be between approximately 130 nm and approximately 400 nm. The first thickness T1 of the first ESL 222 can be between approximately 10 nm and approximately 100 nm. If the first thickness T1 is less than 10 nm, it may not provide a sufficient differential signal with respect to the etch rate to determine the etching endpoint. If the first thickness T1 is greater than 100 nm, the penetration of the first ESL 222 can cause undesirable damage to the second ESL 224.The ratio of the second thickness T2 to the first thickness T1 can range from approximately 4 to approximately 15. In Block 104, the first ESL 222 and the second ESL 224 can be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). It should be noted that, depending on the processes, different interconnect layers may have different numbers of etch stop layers. Fig. Although two etch stop layers are shown in Figure 3, the present disclosure is not limited thereto and the workpiece 200 can have 3 or even 4 etch stop layers. Details of embodiments with multiple etch stop layers are omitted.

[0019] With reference to the Fig. 1 and Fig. In section 4, process 100 comprises a block 106 in which an opening 226 is produced in the workpiece 200 to expose the second conductive trace 220. In an exemplary process, a spin-deposited photoresist layer is deposited over the second ESL 224. After deposition of the photoresist layer, photolithography and etching processes are performed to structure the photoresist layer. The structured photoresist layer is then used as an etching mask when etching the workpiece 200, which has the second ESL 224 and the first ESL 222, to form the opening 226. In Block 106, the first ESL 222 and the second ESL 224 can be processed using a reactive ion etching process (RIE process) (RIE: reactive-ion-etching), which uses oxygen, hydrogen, a fluorine-containing gas (e.g. CF4, NF3, SF6, CH2F2, CHF3 and / or C2F6), a hydrocarbon (e.g. methane), a chlorine-containing gas (e.g.Cl2, CHCl3, CCl4 and / or BCl3), a brominated gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof, are used for anisotropic etching. In some implementations, the etching process in block 106 can be timed to stop when a portion of the second conductive line 220 is exposed. As described below, the exposed portion of the second conductive line 220 can be considered a lower electrode. As in . Fig. As shown in Figure 4, the second conductive line 220 can have a first width W1 along the X-direction, and the opening 226 can have a second width W2 along the X-direction. The second width W2 can be equal to, greater than, or less than the first width W1 to meet different breakdown voltage requirements of the OTP storage device being manufactured. All else being equal, a larger second width W2 is likely to result in a lower breakdown voltage because more defects can be present over a larger area, and defects can lead to the formation of breakdown paths. The first width W1 and the second width W2 can each be between approximately 50 nm and approximately 500 nm.

[0020] With reference to the Fig. 1 and Fig. In section 5, process 100 comprises a block 108 in which a breakdown layer 228 is deposited over the interconnect structure 300. The breakdown layer 228 comprises a dielectric layer with a high dielectric constant (high-k dielectric layer), whose dielectric constant is greater than that of silicon dioxide (approximately 3.9). In some embodiments, the breakthrough layer 228 may comprise hafnium oxide (HfO), aluminum oxide (AlO), aluminum nitride (AlN), titanium oxide (TiO), hafnium zirconium oxide (HfZrO), tantalum oxide (TaO), hafnium aluminum oxide (HfAlO), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), lanthanum oxide (LaO), yttrium oxide (YO), strontium titanium oxide (SrTiO), barium titanium oxide (BaTiO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HITaO), hafnium titanium oxide (HfTiO).In one embodiment, the breakdown layer 228 can be made of aluminum oxide (AlO), hafnium oxide (HfO), or aluminum nitride (AlN). The breakdown layer 228 can be deposited using ALD, PECVD, or CVD. Depending on the design, the breakdown layer 228 can have a thickness between approximately 1.0 nm and approximately 10.0 nm. Assuming the same quality and a defined area of ​​the breakdown layer 228, the thickness of the breakdown layer 228 essentially determines the breakdown voltage of the OTP storage device it forms. For example, if the breakdown layer 228 has a thickness of approximately 2.0 nm, the breakdown voltage of the breakdown layer 228 (or the OTP storage device it forms) will be between approximately 1.5 V and approximately 2 V. If the breakdown layer 228 is thinner than 1.0 nm, premature breakdown may occur at a lower than the design voltage across the breakdown layer 228.If the breakdown layer 228 is thicker than 10.0 nm, the breakdown voltage of the breakdown layer 228 can be higher than the highest operating voltage of the semiconductor device 200.

[0021] With reference to the Fig. 1 and Fig. In Section 6, the process 100 comprises a block 110 in which an upper electrode layer 230 is deposited over the opening 226. The upper electrode layer 230 can comprise a metal or a conductive metal nitride. In some embodiments, the upper electrode layer 230 can comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), copper (Cu), other refractory metals, or other suitable metallic materials, or a combination thereof. The upper electrode layer 230 can be deposited over the breakdown layer 228 and the opening 226 by ALD, PVD, CVD, E-beam evaporation, or another suitable process. In some embodiments, the upper electrode layer 230 can function as an ohmic element of a high-resistance resistor.In these embodiments, the upper electrode layer 230 can be made of a relatively less conductive material, such as tantalum nitride (TaN), and the composition of the upper electrode layer 230 differs from the composition of the second conductive conductor 220. Alternatively, if the upper electrode layer 230 serves as a resistive element and is made of a relatively more conductive material, such as tungsten (W) or cobalt (Co), the opening 226 can have an elongated shape to achieve the desired resistance value.

[0022] With reference to the Fig. 1 and Fig. 7 The process 100 comprises a block 112 in which the workpiece 200 is planarized to produce an upper electrode 230. After deposition of the upper electrode layer 230, a planarization process, such as a chemical mechanical planarization (CMP) process, can be performed to remove excess material and produce an essentially planar top surface. As in Fig. As shown in Figure 7, planarization in block 112 is carried out until the entire breakthrough layer 228 and the upper electrode layer 230 have been removed from a top surface of the second ESL 224. In some implementations, planarization in block 112 is also aimed at reducing the total thickness of the first ESL 222 and the second ESL 224 from the first total thickness TT1, which is shown in Figure 7. Fig. 3 shows a smaller second total thickness TT2, which is in Fig. As shown in Figure 7, the planarization in block 112 reduces the second thickness T2 of the second ESL 224 to a third thickness T3, which can range from about 3.0 nm to about 20.0 nm. The first thickness T1, as described above, can range from about 1.0 nm to about 10.0 nm. In some instances, the ratio of the third thickness T3 to the first thickness T1 can range from about 1 to 3. The first thickness T1 represents the thickness of the breakdown layer 228 and essentially determines the breakdown voltage of the OTP memory device it forms. If the first thickness T1 is less than 1.0 nm, premature breakdown at the breakdown layer 228 may occur at a lower than the design voltage. If the first thickness T1 is greater than 10.0 nm, the breakdown voltage of the breakdown layer 228 may be higher than the highest operating voltage of the semiconductor device 200.In some instances, the second total thickness TT2 can range from approximately 50 nm to approximately 500 nm. This means that the planarization in block 112 is essentially performed to reduce the total thickness of the first ESL 222 and the second ESL 224 by between approximately 10.0 nm and approximately 15.0 nm. Reducing the total thickness of the first ESL 222 and the second ESL 224 prevents the interconnect layer (where the second conductive line 220 is located) from becoming too thick to be integrated into the interconnect structure 300. As shown in . Fig. As shown in Figure 7, the upper electrode 230 is arranged in the breakdown layer 228, which has a U-shape when viewed along the Y-direction. The side walls and underside of the upper electrode 230 are enclosed by the breakdown layer 228, so that the upper electrode 230 is spaced apart from the second ESL 224, the first ESL 222, the first IMD layer 218, and the second conductive conductor 220.

[0023] With reference to the Fig. 1 and Fig. In Figure 8, the process 100 comprises a block 114 in which a third ESL 232 and a second IMD layer 234 are deposited over the workpiece 200. In some embodiments, the third ESL 232 may comprise a nitrogen-containing dielectric material, such as silicon nitride, silicon oxide carbonitride, or silicon carbonitride. The second IMD layer 234 may comprise materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon oxide, such as boron phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The third ESL 232 may be deposited using ALD or CVD. The second IMD layer 234 can be deposited by spin coating, flowable CVD (FCVD) or other suitable deposition methods.

[0024] Furthermore, with reference to the Fig. 1 and Fig. In section 8, the method 100 comprises a block 116 in which an OTP via 236 is fabricated such that it is coupled to the upper electrode 230, and a third conductive line 238 is fabricated such that it is coupled to the OTP via 236. In some embodiments, a dual damascene process can be used to fabricate vias and conductive lines in block 116. In the illustrated embodiments, an OTP via 236 is produced through the third ESL 232 and the second IMD layer 234 such that it is coupled to the upper electrode 230, a third conductive line 238 is produced over the OTP via 236, a second via 240 is produced such that it is coupled to another conductive line 221 in the first IMD layer 218, and a fourth conductive line 242 is produced over the second via 240.In an exemplary process, the second IMD layer 234 undergoes two structuring processes to create via holes and a trench over the via holes. A coating and a seed layer are then deposited in the via holes and the trench. In some instances, the coating may contain titanium nitride and the seed layer may contain titanium. Then, a conductive material, such as aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), or copper (Cu), is deposited in the via holes and in the trench by electroplating. As in . Fig. As shown in Figure 8, the OTP vias 236 are in direct contact with the upper electrode 230, and the third conductive line 238 is in direct contact with the OTP via 236. The second via 240 extends through the first ESL 222, the second ESL 224, the third ESL 232, and the second IMD layer 234 such that it is coupled to the other conductive line 221 in the first IMD layer 218. The fourth conductive line 242 is deposited on the second via 240. Although the conductive lines and the vias in the second IMD layer 234 may have similar compositions, as shown in Figure 8, their compositions are not directly related. Fig. As shown in Figure 8, they have different shapes. It should be noted that both the third conductive line 238 and the fourth conductive line 242 extend lengthwise along the Y-direction. In the Fig. In the embodiments shown in Figure 8, the height of the second via 240 is greater than the height of the OTP via 236 by the second total thickness TT2 along the Z-direction.

[0025] Furthermore, with reference to the Fig. 1 and Fig. The process includes a block 118 in which further processes are carried out. These further processes can include planarizing the workpiece 200 and producing further interconnect layers over the dielectric layer 248. In the Fig. In the embodiments shown in Figure 9, a third via 244 can be fabricated above the third conductive line 238 using the additional processes in Block 118, and a fifth conductive line 246 can be arranged above the third via 244. Like the OTP via 236 and the third conductive line 238, the third via 244 and the fifth conductive line 246 are arranged in an IMD layer (omitted) above the second IMD layer 234. In some embodiments, the fifth conductive line 246 can function as a bit line of an OTP storage device. The third via 244 and the fifth conductive line 246 are also part of the interconnect structure 300.

[0026] After completion of the steps in Block 118, an OTP storage device 400 (or an OTP storage cell or an OTP antifuse cell) is manufactured. As described in Fig. As shown in Figure 9, the OTP memory device 400 comprises a fusion junction, the gate electrode 206, which serves as the word line, and the fifth conductive line 246, which serves as the bit line. The fusion junction includes the second conductive line 220 (i.e., the lower electrode), the breakdown layer 228, and the upper electrode 230. When a voltage greater than a threshold voltage of the transistor 260 is applied to the gate electrode 206, the OTP memory device 400 is selected. When a high-resistance state is to be written, the voltage across the fifth conductive line 246 (i.e., the bit line) is 0 V. Since the voltage applied across the breakdown layer 228 is 0 V, the breakdown layer 228 remains intact under a high-resistance condition. When a low-resistance state is to be written, a breakdown voltage, such as 2 V, is applied to the fifth conductive line 246 (i.e., the bit line).The breakdown voltage can be controlled by an input / output transistor (I / O transistor). This high voltage will cause a breakdown at the breakdown layer 228, resulting in electrical communication between the upper electrode 230 and the second conductive line 220 (i.e., the lower electrode). A person skilled in the art should recognize that, depending on design preference, the high-impedance or low-impedance state can be referred to as either the "0" state or the "1" state. During a read operation, a voltage is applied to the gate electrode 206 (i.e., the word line) to turn on the transistor 260. A non-zero voltage lower than the breakdown voltage, such as 1.2 V, is applied to the fifth conductive line 246 (i.e., the bit line). A voltage at the source line, coupled to the source via 212S, can be 0 V.When the OTP storage device 400 is in a high-impedance state, a low current is detected on the bit line. When the OTP storage device 400 is in a low-impedance state, a high current is detected on the bit line. The bit line current is therefore used to determine the state of the OTP storage device 400.

[0027] It will be on Fig. 10 Reference is made to a circuit diagram showing the semiconductor structure 200, which is in Fig. Figure 9 is representative. The gate electrode 206 is coupled to the word line and controls the transistor 260. The source terminal of the transistor 260 is coupled to the source line, and the drain terminal of the transistor 260 is coupled to the fifth conductive line 246 via the fusible link. The fifth conductive line 246 serves as the bit line. The fusible link comprises the second conductive line 246, which serves as a lower electrode, the breakdown layer 228, and the upper electrode 230.

[0028] Now the focus shifts to the Fig. 11, Fig. 12 and Fig. 13 Referenced. In addition to the thickness of the breakthrough layer 228, a vertical projection area of ​​the breakthrough layer 228 can affect the breakdown stress of the breakthrough layer 228. In some embodiments described in Fig. As shown in Figure 11, opening 226 is shown in Figure 11. Fig. 4) wider than the second conductive line 220 along the X-direction and the Y-direction, wherein the probability that the large area of ​​the breakdown layer 228 has more defects that can lead to the formation of breakdown paths through the breakdown layer 228 is higher. In some other embodiments described in Fig. The 12 shown have the opening 226 (shown in Fig. 4) and the second conductive line 220 are of the same size and essentially overlap along the Z-direction. Compared to the breakthrough layer 228 in Fig. 11 shows the smaller area of ​​the breakthrough layer 228 in Fig. 12 probably fewer defects, leading to a higher breakdown voltage. In other embodiments, which Fig. The opening shown in 13 is 226 (shown in Fig. 4) smaller than the second conductive line 220. Compared to the breakthrough layer 228 in Fig. 12, shows the even smaller area of ​​the breakthrough layer 228 in Fig. 13 probably exhibits even fewer defects, leading to an even higher breakdown voltage. In all embodiments described in the Fig. 11, Fig. 12 and Fig. As shown in Figure 13, the second conductive line 220 and the third conductive line 238 extend lengthwise in different directions. The second conductive line 220 extends lengthwise along the Y-direction. The third conductive line 238 extends lengthwise along the X-direction.

[0029] It should be noted that in embodiments described in the Fig. 11, Fig. 12 and Fig. As shown in Figure 13, the upper electrode 230 is positioned entirely within the vertical projection plane of the breakdown layer 228 to ensure that the breakdown occurs in the breakdown layer 228 and not in other dielectric layers, such as the first ESL 222, the second ESL 224, or the first IMD 218. Otherwise, the breakdown voltage may be unpredictable, as different dielectric materials result in different breakdown voltages. This means, according to the present disclosure, that the area of ​​the electrode 230 on the XY plane is smaller than the area of ​​the breakdown layer 228 on the XY plane. The difference between the area of ​​the breakdown layer 228 on the XY plane and the area of ​​the upper electrode layer 230 on the XY plane depends on the coverage accuracy of the photolithography process.Higher coverage accuracy may require smaller area differences, and lower coverage accuracy may require larger area differences. In some instances, the area of ​​the breakthrough layer 228 on the XY plane exceeds the area of ​​the upper electrode 230 on the XY plane by between approximately 20% and approximately 50%.

[0030] In some existing technologies, high-resistance (Hi-R) resistors are fabricated in the interconnect structure, while the fusion links of the OTP memory devices are fabricated at the FEOL level. This results in the use of very different processes, increasing production costs and the number of photolithography steps. Fabricating the fusion links at the FEOL level can also increase the device dimensions, as they are fabricated next to the transistors rather than vertically above them. According to the present disclosure, the method 100 described above can also be used to fabricate a high-resistance (Hi-R) resistor. In fact, method 100 can be used to fabricate fusion links for OTP memory devices and Hi-R resistors simultaneously.In this case, only one photomask may be needed to create fusion connections for OTP memory devices and Hi-R resistors, and the fusion connections are positioned above, rather than next to, transistors. It has been observed that moving the fusion connections from the FEOL plane to the BEOL plane can reduce the device dimensions by between approximately 15% and 25%.

[0031] An enlarged view of a Hi-R 500 resistor is in Fig. 14 shown. The Hi-R resistor 500 in Fig. 14 resembles the upper electrode 230, which is in Fig. Figure 8 shows that the Hi-R resistor 500 is arranged above and enclosed by the U-shaped breakdown layer 228. The breakdown layer 228 is arranged on the second conductive line 220. In some embodiments where the breakdown layer 228 is wider than the second conductive line 220 along the X-direction, the breakdown layer 228 is also in contact with the first IMD layer 218. The breakdown layer 228 is located in the first ESL 222 and the second ESL 224. The Hi-R resistor 500 is spaced from the first ESL 222, the second ESL 224, the first IMD layer 218, and the second conductive line 220 by the breakdown layer 228. Unlike the structure in Figure 8, the breakdown layer 228 is located in the first ESL 222, the second ESL 224, the first IMD layer 218, and the second conductive line 220. Fig. 8 Several vias are arranged on the Hi-R resistor 500 and coupled to it. In the embodiments described in Fig. As shown in Figure 14, a first terminal via 2361 and a second terminal via 2362 are arranged on the high-resistor 500 and ohmically coupled to it. A first conductive lead 2381 is arranged on and in contact with the first terminal via 2361. A second conductive lead 2382 is arranged on and in contact with the second terminal via 2362. The first terminal via 2361 and the second terminal via 2362 extend through the third ESL 232 and the second IMD layer 234. The first conductive lead 2381 and the second conductive lead 2382 are arranged in the second IMD layer 234. The first ESL 232 and the second ESL 234 have the second overall thickness T2.

[0032] Fig. Figure 15 shows a workpiece 200 in which the high-resistance 500 is located in an interconnect structure 300, which is arranged above a transistor 260. In the Fig. In the embodiments shown in Figure 15, the first conductive connection 2381 is electrically coupled to a sixth conductive connection 2462 via a fourth via 2442, and the second conductive connection 2382 is electrically coupled to a seventh conductive connection 2464 via a fifth via 2444. The seventh conductive connection 2464 is electrically coupled to the drain via 212D via all vias and conductive lines in between, which include a via 2446, the fourth conductive connection 242, the second via 240, a conductive line 221, the first via 216, and the first conductive connection 214.

[0033] It will be revisited Fig. 14 Reference is made to this. In use, current flows through the Hi-R resistor 500 from the first terminal via 2361 or the second terminal via 2362 to the other of the first terminal via 2361 or the second terminal via 2362, respectively. Like the upper electrode 230, the Hi-R resistor 500 can comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), copper (Cu), other high-melting-point metals, or other suitable metallic materials, or a combination thereof. In some embodiments, the Hi-R resistor 500 can be made of a relatively less conductive material, such as tantalum nitride (TaN).In some other embodiments, where the Hi-R resistor 500 is made of a relatively more conductive material, such as copper (Cu) or tungsten (W), the dimension of the Hi-R resistor 500 in the X direction can be increased so that contact points of the first terminal via 2361 and the second terminal via 2362 can be arranged further apart to increase the resistance.

[0034] In some embodiments, the effective resistance of the Hi-R resistor 500 can be adjusted by increasing the number of terminal vias or by varying the distance between the terminal vias. Now, let's turn to the Fig. 16-19 are referenced. In the Fig. In the embodiments shown in Figure 16, the first conductive connection 2381 and the second conductive connection 2382 are each coupled to the high-resistor 500 by a via (the first via 2361 or the second via 2362). To ensure satisfactory contact between the via and the connection, the first via 2361 and the second via 2362 can each have a rectangular or an elongated shape. As shown in Figure 16, the first conductive connection 2381 and the second conductive connection 2382 are each connected to the high-resistor 500 by means of a via (the first via 2361 or the second via 2362). Fig. As shown in Figure 16, the first terminal via 2361 can have a via width (VW) along the X direction and a via length (VL) along the Y direction, where the via length (VL) is greater than the via width (VW). In some instances, the via width (VW) can be between about 25 nm and about 50 nm, and the via length (VL) can be between about 80 nm and about 120 nm. The first conductive lead 2381 or the second conductive lead 2382 can have a lead width (LW) along the Y direction, and the lead width (LW) can be between about 100 nm and about 200 nm. As a result, the first terminal via 2361 intersects the conductor width (LW) of the first conductive terminal 2381 with its longer via length (VL), instead of with the shorter via width (VW).In some implementations, the conductor width (LW) can be essentially identical to the via length (VL), so that the conductor width (LW) and the via length (VL) are essentially the same.

[0035] To ensure that the first via 2361 and the second via 2362 are properly seated on the Hi-R resistor 500, the edges of the first and second vias are each separated from a boundary of the Hi-R resistor 500 by a margin (M). The margin (M) is directly related to the accuracy and resolution of the photolithography process. For example, if the photolithography process uses a radiation source with a wavelength of approximately 248 nm, the margin (M) can be equal to or greater than approximately 30 nm. If the margin (M) is less than approximately 30 nm, unsatisfactory defects associated with misalignment of the vias may occur. The edge (M) should be smaller than about 100 nm, otherwise the Hi-R resistance 500 may be too large to be enclosed by the breakthrough layer 228.If a different radiation source with a shorter wavelength is used, the border area (M) can be smaller. For example, if the wavelength of the radiation source is approximately 193 nm, the border area (M) can range from 20 nm to approximately 60 nm. The border area (M) can also be characterized using the ratio of the border area (M) to the via length (VL). In some cases, the ratio (M / VL) can range from approximately 0.2 to approximately 0.3. If the ratio (M / VL) is less than 0.2, the probability of the terminal via being located outside the Hi-R resistance of 500 Ω is unsatisfactory. If the ratio (M / VL) is greater than 1.3, the packing density of the terminal vias may be too low, resulting in an unnecessary increase in device dimensions.To achieve the desired effective resistance using the Hi-R resistor 500, the gap (S) in the Y-direction between the first terminal via 2361 and the second terminal via 2362 can be between approximately 100 nm and approximately 12 µm. If the gap (S) in the Y-direction is less than approximately 100 nm, the resistance may not reach the desired level. If the gap (S) in the Y-direction is greater than approximately 12 µm, it may be difficult for the Hi-R resistor 500 to fit within the interconnect layer in which it is located.

[0036] To maximize the via-to-via distance (D) while maintaining a given gap (S) in the Y direction, the first terminal via 2361 and the second terminal via 2362 can be arranged to rest on diagonal corners of the upper electrode 230, as shown in Fig. Figure 17 shows that in some instances, the via-to-via distance (D) can range from approximately 1.2 to approximately 3 times the gap (S) in the Y-direction. That is, the ratio of the via-to-via distance (D) to the gap (S) in the Y-direction can be between approximately 1.2 and 3. However, it should be noted that if this ratio (D / S) is less than 1.2 or greater than 1.6, the diagonal placement of the vias cannot lead to significant absolute space savings because it merely changes the longitudinal orientation of the Hi-R resistor 500. Since the via-to-via distance (D) is directly related to the effective resistance, the values ​​shown in Figure 17 provide significant advantages for the design of the vias. Fig. The embodiments shown in Figure 17 offer flexibility in accommodating upper electrodes 230 with different orientations. Depending on the layout of the interconnect layer in which the Hi-R resistor 500 is located, the Hi-R resistor 500 can, for example, have a shape that is elongated along the X-direction instead of along the Y-direction, as shown in Figure 17. Fig. 17 is shown.

[0037] If one half (1 / 2) of the effective resistance of the Hi-R resistor is 500 in Fig. If desired, the first conductive connection line 2381 and the second conductive connection line 2382 are each coupled to the Hi-R resistor 500 by two connection vias, as shown in Fig. 18 is shown. Fig. In 18, the first conductive lead 2381 is coupled to the Hi-R resistor 500 via the first terminal via 2361 and a third terminal via 2363; and the second conductive lead 2382 is coupled to the Hi-R resistor 500 via the second terminal via 2362 and a fourth terminal via 2364. If one third (1 / 3) of the effective resistance of the Hi-R resistor 500 is in Fig. If 16 is desired, the first conductive connection line 2381 and the second conductive connection line 2382 are each coupled to the Hi-R resistor 500 by three connection vias, as shown in Fig. 19 is shown. Fig. In Figure 19, the first conductive connection 2381 is coupled to the Hi-R resistor 500 via the first connection via 2361, the third connection via 2363, and a fifth connection via 2365; and the second conductive connection 2382 is coupled to the Hi-R resistor 500 via the second connection via 2362, the fourth connection via 2364, and a sixth connection via 2366. It is understood that more connection vias can be implemented to further reduce the resistance of the Hi-R resistor 500. The connections shown in the Fig. Examples 16-19 show that the method 100 of the present disclosure can be used to produce Hi-R resistors having different effective resistances.

[0038] Fig. 20 shows that this in Fig. 9 shown workpiece 200 and that in Fig. The workpiece 200 shown could very well be a single workpiece 200 that includes both the Hi-R resistor 500 and the OTP storage device 400. Detailed descriptions of the Fig. For the sake of brevity, references 20 are omitted. It should be noted that throughout this disclosure, the same reference numbers are used to denote the same elements.

[0039] Embodiments of the present disclosure offer advantages. The methods of the present disclosure allow the simultaneous fabrication of a high-resistance resistor (Hi-R resistor) and an OTP storage device in a BEOL interconnect structure. Fabricating these two types of devices together in the BEOL interconnect structure can reduce manufacturing costs by using fewer photomasks and by reducing the device dimensions. The present disclosure also provides mechanisms or structures for adjusting the effective resistance of the high-resistance resistor or the breakdown voltage of the OTP storage device.

[0040] Accordingly, the present disclosure provides, in one aspect, a semiconductor structure. The semiconductor structure comprises a transistor and an interconnect structure arranged above the transistor. The interconnect structure comprises a first dielectric layer, a first conductive structural element in the first dielectric layer, a first etch-stop layer (ESL) arranged above the first dielectric layer and the first conductive structural element, a dielectric structural element arranged in the first ESL, an electrode arranged above the dielectric structural element, and a second ESL arranged on top of the first ESL and the electrode.

[0041] In some embodiments, the dielectric structural element comprises aluminum oxide, hafnium oxide, or aluminum nitride. In some instances, the electrode comprises titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium. In some implementations, the dielectric structural element has a thickness between approximately 1.0 nm and approximately 10.0 nm. In some embodiments, the interconnect structure further comprises a third ESL positioned between the first ESL and the first dielectric layer, with the dielectric structural element also located within the third ESL. In some embodiments, the composition of the third ESL differs from that of the second ESL. In some instances, the dielectric structural element is in direct contact with the first ESL, the third ESL, the second ESL, and the first conductive structural element.In some embodiments, the electrode is spaced from the first ESL, the third ESL, and the first conductive structural element by the dielectric structural element. In some embodiments, the width of the dielectric structural element is greater than the width of the first conductive structural element, the dielectric structural element is in further contact with the first dielectric layer, and the electrode is spaced from the first dielectric layer by the dielectric structural element. In some instances, the interconnect structure further comprises a second dielectric layer arranged on top of the second ESL, a via located in the second ESL and the second dielectric layer and coupled to the electrode, and a second conductive structural element located in the second dielectric layer and coupled to the via.In some instances, a drain terminal of the transistor is electrically coupled to the first conductive structural element.

[0042] Another aspect of the present disclosure relates to an image sensor. The image sensor comprises a transistor, an interlayer dielectric layer (ILD layer) arranged over the transistor, a first conductive structural element in the ILD layer, a first etch-stop layer (ESL) arranged over the ILD layer and the first conductive structural element, a high-k dielectric structural element arranged in the first ESL, a metallic structural element arranged over the high-k dielectric structural element, and a second ESL arranged on top of the first ESL and the metallic structural element.

[0043] In some embodiments, the composition of the metallic structural element differs from the composition of the first conductive structural element. In some instances, the semiconductor structure may further comprise: a second ILD layer arranged on top of the second ESL; a first via located in the second ESL and the second ILD layer and coupled to the metallic structural element; a second via located in the second ESL and the second ILD layer and coupled to the metallic structural element; a second conductive structural element located in the second ILD layer and coupled to the first via; and a third conductive structural element located in the second ILD layer and coupled to the first via.In some implementations, the first via is ohmically coupled to the second via via the metallic structural element. In some embodiments, a drain terminal of the transistor is electrically coupled to the second conductive structural element.

[0044] Another aspect of the present disclosure relates to a method. The method comprises taking a workpiece comprising a transistor, an interlayer dielectric layer (ILD layer) arranged over the transistor, a first conductive structural element in the ILD layer, a first etch stop layer (ESL) arranged over the ILD layer and the first conductive structural element, and a second ESL arranged on top of the first ESL.The process further includes creating an opening through the second ESL and the first ESL to expose the first conductive structural element, depositing a dielectric high-k layer over the opening, depositing a metal layer over the dielectric high-k layer, planarizing the workpiece to remove the dielectric high-k layer and the metal layer over a top surface of the second ESL, and after planarizing, creating a via to couple to a top surface of the metal layer.

[0045] In some embodiments, the first conductive structural element has a first width along one direction, the opening has a second width along the same direction, and the second width is greater than the first width. In some instances, the deposition of the dielectric high-k layer includes the deposition of aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, yttrium oxide, tantalum oxide, or aluminum nitride across the opening. In some implementations, the deposition of the metal layer includes the deposition of titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium.

Claims

[1] Semiconductor structure with: a transistor (260); and an interconnect structure (300) arranged above the transistor (260), wherein the interconnect structure (300) comprises the following: a first dielectric layer (218), a first conductive structural element (220) in the first dielectric layer (218), a first etch stop layer (224) arranged above the first dielectric layer (218) and the first conductive structural element (220), a dielectric structural element (228) arranged in the first etch stop layer (224), an electrode (230, 500) arranged above the dielectric structural element (228), a second etch stop layer (232) arranged above the first etch stop layer (224) and the electrode (230, 500), a second dielectric layer (234) arranged on the second etch stop layer (232), a via (236) which is arranged in the second etch stop layer (232) and the second dielectric layer (234) and is coupled to the electrode (230, 500), and a second conductive structural element (238) which is arranged in the second dielectric layer (234) and is coupled to the via (236). [2] Semiconductor structure according to claim 1, wherein the dielectric structural element (228) comprises aluminium oxide, hafnium oxide or aluminium nitride. [3] Semiconductor structure according to claim 1 or 2, wherein the electrode (230, 500) comprises titanium nitride, tantalum nitride, copper, tungsten, cobalt or ruthenium. [4] Semiconductor structure according to one of the preceding claims, wherein the dielectric structural element (228) has a thickness between about 1.0 nm and about 10 nm. [5] Semiconductor structure according to any one of the preceding claims, wherein the interconnect structure (300) further comprises a third etch stop layer (222) arranged between the first etch stop layer (224) and the first dielectric layer (218), wherein the dielectric structural element (228) is also arranged in the third etch stop layer (222). [6] Semiconductor structure according to claim 5, wherein the composition of the third etch stop layer (222) differs from the composition of the second etch stop layer (232). [7] Semiconductor structure according to claim 5 or 6, wherein the dielectric structural element (228) is in direct contact with the first etch stop layer (224), the third etch stop layer (222), the second etch stop layer (232) and the first conductive structural element (220). [8] Semiconductor structure according to one of claims 5 to 7, wherein the electrode (230, 500) is spaced apart from the first etch stop layer (224), the third etch stop layer (222) and the first conductive structural element (220) by the dielectric structural element (228). [9] Semiconductor structure according to any one of claims 5 to 8, wherein a width of the dielectric structural element (228) is greater than a width of the first conductive structural element (220), wherein the dielectric structural element (228) remains in contact with the first dielectric layer (218), wherein the electrode (230, 500) is spaced apart from the first dielectric layer (218) by the dielectric structural element (228). [10] Semiconductor structure according to one of the preceding claims, wherein the composition of the electrode (230, 500) differs from the composition of the first conductive structural element (220). [11] Semiconductor structure according to one of the preceding claims, wherein a drain terminal (208D) of the transistor (260) is electrically coupled to the first conductive structural element (220). [12] Semiconductor structure with: a transistor (260); an interlayer dielectric layer (218) arranged above the transistor (260); a first conductive structural element (220) in the interlayer dielectric layer (218); a first etch stop layer (222, 224) which is arranged above the interlayer dielectric layer (218) and the first conductive structural element (220); a dielectric high-k structural element (228) arranged in the first etch stop layer (222, 224); a metallic structural element (230, 500) arranged above the dielectric high-k structural element (228); and a second etch stop layer (232) which is arranged on the first etch stop layer (222, 224) and the metallic structural element (230, 500). [13] Semiconductor structure according to claim 12, wherein the composition of the metallic structural element (230, 500) differs from the composition of the first conductive structural element (220). [14] Semiconductor structure according to claim 12 or 13, further comprising: a second interlayer dielectric layer (234) arranged on the second etch stop layer (232); a first via (2361) which is arranged in the second etch stop layer (232) and the second interlayer dielectric layer (234) and is coupled to the metallic structural element (500); a second via (2362) which is arranged in the second etch stop layer (232) and the second interlayer dielectric layer (234) and is coupled to the metallic structural element (500); a second conductive structural element (2381) arranged in the second interlayer dielectric layer (234) and coupled to the first via (2361); and a third conductive structural element (2382) which is arranged in the second interlayer dielectric layer (234) and is coupled to the first via (2361). [15] Semiconductor structure according to claim 14, wherein the first via (2361) is ohmically coupled to the second via (2362) via the metallic structural element (500). [16] Semiconductor structure according to claim 14 or 15, wherein a drain terminal (208D) of the transistor (260) is electrically coupled to the second conductive structural element (2362). [17] Procedure with the following steps: Taking possession of a workpiece (200) comprising the following: a transistor (260), an interlayer dielectric layer (218) arranged above the transistor (260), a first conductive structural element (220) in the interlayer dielectric layer (218), a first etch stop layer (222) arranged above the interlayer dielectric layer (218) and the first conductive structural element (220), a second etch stop layer (224) arranged on top of the first etch stop layer (222); Creating an opening (226) through the second etch stop layer (224) and the first etch stop layer (222) to expose the first conductive structural element (220); Deposition of a dielectric high-k layer (228) over the opening (226); Deposition of a metal layer (230, 500) over the dielectric high-k layer (228); Planarizing the workpiece (200) to remove the dielectric high-k layer (228) and the metal layer (230, 500) above a top surface of the second etch stop layer (224); and After planarizing, a via (236) is created to establish a coupling to a top surface of the metal layer (230, 500). [18] Method according to claim 17, wherein the first conductive structural element (220) has a first width (W1) along a direction, wherein the opening (226) has a second width (W2) along the direction, wherein the second width (W2) is greater than the first width (W1). [19] Method according to claim 17 or 18, wherein the deposition of the dielectric high-k layer (228) comprises the deposition of aluminium oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, yttrium oxide, tantalum oxide or aluminium nitride over the opening (226). [20] Method according to any one of claims 17 to 19, wherein the deposition of the metal layer (230, 500) comprises the deposition of titanium nitride, tantalum nitride, copper, tungsten, cobalt or ruthenium.

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