SIGNAL AMPLIFICATION IN MRAM DURING READ

Abstract

Facility comprising: a control circuit (510, 520, 560) configured to be connected to a crosspoint memory array (750), the crosspoint memory array comprising a memory cell (700, M30_1) disposed between a first conductive line (WL3_1) and a second conductive line (BL0), and a first transistor pair comprising a pMOSFET (943) in parallel with an nMOSFET (947) and connected to the first conductive line (WL3_1), the memory cell (700) comprising a storage element (710) in series with a threshold switching selector (702); the control circuit for selecting the memory cell (M30_1) is configured to pull up a voltage of the first conductive line (WL3_1) with the pMOSFET (943) while the nMOSFET (947) is in a non-conductive state; and the control circuit is configured to subsequently read the memory cell (M30_1) while the pMOSFET (943) is in a non-conductive state and the nMOSFET (947) is in a conductive state.

Description

BACKGROUND

[0001] Memory is used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory can be non-volatile or volatile. Non-volatile memory allows information to be stored and retained even when not connected to a power source.

[0002] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that use electronic charges for data storage. In general, MRAM includes a large number of memory cells formed on a semiconductor substrate, with each memory cell representing (at least) one bit of data. A bit of data is written to a memory cell by changing the direction of magnetization of a magnetic element within the memory cell, and a bit is read by measuring the resistance of the memory cell. A low resistance typically represents a "0" bit, and a high resistance typically represents a "1" bit.

[0003] The documents US 2009 / 0 310 400 A1 and US 2013 / 0 077 384 A1 relate to non-volatile semiconductor memory devices having pairs of a PMOS transistor and an NMOS transistor connected to bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Like-numbered elements refer to common components in the different figures. Fig. 1 is a block diagram of an example implementation of a storage system connected to a host. Fig. 2 is a block diagram of an exemplary implementation of the FEP circuit 110 of Fig. 1. Fig. 3 is a block diagram of an exemplary implementation of the BEP circuit 112 of Fig. 1. Fig. 4 is a block diagram of an exemplary implementation of the memory package 104 of Fig. 1. Fig. 5A is a block diagram of an example storage system that may implement the technology described herein. Fig. 5B illustrates exemplary drivers among the row drivers 524 and column drivers 514 of Fig. 5A. Fig. 5C illustrates an example block diagram for a current driver 575. Fig. 5D shows an example of the DAC circuit 570 Fig. 5C. Fig. 6 is a block diagram of another example of a storage system that may implement the technology described herein. Fig. 7A illustrates a cross-sectional view of an exemplary memory cell in the memory array 502 of Fig. 5A or Fig. 6. Fig. Figure 7B illustrates a perspective view of an exemplary crosspoint memory array 750 of memory cells associated with the memory cell of Fig. 7A. Fig. Figure 8A illustrates an exemplary IU representation for the memory element 710 Fig. 7A. Fig. Figure 8B illustrates an example IU representation for selector 702 Fig. 7A. Fig. Figure 8C illustrates an exemplary IU representation for memory cell 700 Fig. 7A. Fig. 9A illustrates an exemplary circuit corresponding to the first level of the crosspoint memory array 750. Fig. Figure 9B shows an example circuit that can be used with Fig. 9A and the second level of the crosspoint memory array 750 of Fig. 7B. Fig. 10A represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is on and the nMOSFET is off when a voltage is pulled up on a selected word line WL3_1. Fig. 10B shows the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is off and the nMOSFET is on when a voltage is detected on a selected word line WL3_1. Fig. 10C represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is turned on and the nMOSFET is turned on when a voltage is detected on a selected word line WL3_1. Fig. 10D represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is off and the nMOSFET is on when a voltage is pulled up on a selected bit line BL0. Fig. 10E represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is off and the nMOSFET is on during a sense process in which the selected bit line BL0 is grounded. Fig. 10F represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is on and the nMOSFET is on during a sense process in which the selected bit line BL0 is grounded. Fig. 11A illustrates a flowchart of an exemplary process for performing a write operation for a selected memory cell, such as memory cell 700 of Fig. 7A. Fig. 11B illustrates a flowchart of an exemplary process for performing a single voltage sense read operation for a selected memory cell, such as memory cell 700 of Fig. 7A. Fig. 11C illustrates a flowchart of an exemplary process for performing a dual voltage sense read operation for a selected memory cell, such as memory cell 700 of Fig. 7A. Fig. Figure 12A illustrates an exemplary implementation of the read circuit 564 of Fig. 7B, which is related to the process of Fig. 11B. Fig. Figure 12B illustrates another exemplary implementation of the read circuit 564 of Fig. 7B, which is related to the process of Fig. 11C. Fig. Figure 12C shows exemplary parallel resistances of the pMOSFET and the nMOSFET of the transistor pair Wd3_1, which are Fig. 9A. Fig. Figure 13A shows an example of the current versus time for a memory cell that is connected to the write process in Fig. 11A. Fig. Figure 13B shows an example plot of voltage versus time for a memory cell connected to Fig. 13A. Fig. Figure 13C shows an example of the current versus time for a memory cell associated with the read process of Fig. 11B. Fig. Figure 13D shows an example plot of voltage versus time for a memory cell connected to Fig. 13C. Fig. Figure 13E illustrates an example plot of current versus time for a memory cell following steps 1100-1108 of the process of Fig. 11C. Fig. Figure 13F shows an example of the voltage versus time plot for a memory cell connected to Fig. 13E matches. Fig. Figure 13G illustrates an exemplary current versus time plot for a memory cell associated with step 1110 of the process of Fig. 11C. Fig. Figure 13H shows an example of the voltage versus time plot for a memory cell that is Fig. 15A. DETAILED DESCRIPTION

[0005] Devices and techniques for reading MRAM memory cells are described.

[0006] An MRAM memory cell comprises a magnetic switching material that can have different data states due to different magnetization states, each state having a different resistance. An MRAM memory cell may be a two-terminal device that is written to a low-resistance state (e.g., 25 kΩ) by a current applied in one direction for about 50 ns and to a high-resistance state (e.g., 50 kΩ) by a current applied in the opposite direction. This current may exceed that required to write to the low-resistance state for about 50 ns; for example, by 20% if the critical dimension (CD) is, for example, 20 nm and the resistance area product (RA) of the memory cell is 10. The current induces magnetic changes in a free layer of the memory cell.

[0007] Additionally, when many memory cells are arranged in a crosspoint memory array, each memory cell may include a memory element (e.g., comprising the magnetic switching material) in series with a selector, such as an ovonic threshold switch. The selector may be in a conductive or non-conductive state. To write to or read from a particular memory cell, a voltage and / or current signal is applied across the respective word line and bit line in contact with the memory cell to place the selector in the conductive state. This is referred to as selecting the memory cell. When the selector is in the conductive state, a voltage and / or current may be applied across the respective word line and bit line to the memory element for writing or reading.For example, a self-referenced read (SRR) can be performed in either direction, to AP (high impedance state) or to P (low impedance state), by selecting the bit in that direction, reading the bit to generate a level and storing the level, writing the bit in that direction, and reading the bit to compare it with the set stored level. Such an adjustment can be a positive increase in voltage for later comparison when the SRR is in the AP state, or a negative decrease in voltage for later comparison when the SRR is in the P state.

[0008] After writing, a read operation can be performed to determine the data state of the memory cell. The read operation may involve determining a voltage across the memory cell when a current is applied. One approach to reading is to measure the voltage a first time, then perform a potentially destructive write operation that ensures the memory cell is in a high-impedance state, and then measure the voltage a second time. If the voltage increases by more than a specified amount, it can be concluded that the memory cell was initially in the low-impedance state and has been programmed to the high-impedance state by the write operation. The write operation, in this case, is destructive.If the voltage hasn't increased by more than the specified amount, it can be concluded that the memory cell was initially in a high-resistance state and will remain in that state after the write operation. In this case, the write operation is non-destructive.

[0009] To provide bidirectional write capability, the word lines and bit lines connected to the memory cell may both include transistors such as MOSFETs to pass a voltage and / or current to the memory cell. A MOSFET, or metal-oxide-semiconductor field-effect transistor, is provided in a conducting state when biased with an appropriate gate-source voltage, referred to as Von. However, Von can change as the memory cell changes its resistance state. This affects the sensing of the voltage generated when the memory cell is read. This reading can occur in a path through the decoding transistors to the global node in the sense amplifier (sense circuit), bypassing the series connection of decoding transistors and the selected memory bit (cell).

[0010] Techniques provided herein address the above and other problems. Each bit line and each word line is connected to a transistor pair comprising a pMOSFET (a p-channel MOSFET) in parallel with an nMOSFET (an n-channel MOSFET). The bit lines and word lines are conductive lines. The conductive lines include first conductive lines connected to a first end (e.g., a bottom side) of each memory cell and second conductive lines connected to a second end (e.g., a top side) of each memory cell. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up (increased) to a positive voltage with a pMOSFET, while a voltage of a second conductive line may be pulled down (decreased), for example, to 0 V, with an nMOSFET. This approach minimizes capacitance while the selector is on.Such a turn-on of the selector can induce a transient current through the memory element when the voltage across the selector collapses from Vth(selector), for example, 2.2 V, to Vhold(selector), for example, 1.3 V, resulting in a discharge current through the memory bit as the voltage across it decreases. Such a current above the steady-state read current can cause a premature state change in the memory element before the level can be stored for comparison with the resulting read level after the bit is written.

[0011] One option allows the parallel nMOSFET of the first conductive line to be used when reading the selected memory cell. It is turned on after the selector of the selected memory bit is turned on, in addition to the pMOSFET used in series with the memory element to select and turn on the bit selector. The nMOSFET adds a resistance that compensates for the reduced resistance of the pMOSFET to enable more accurate sensing of the voltage across the memory cell at the global node behind the decode transistors that select the bit based on the address provided by the host when the cycle is enabled. The amplitude of the voltage tapped by the sense amplifier circuit is therefore better preserved.In the aforementioned type of read operation, where the voltage is sensed a first time and a second time, the nMOSFET can be turned on (conducted) each time along with the pMOSFET. The nMOSFET can remain on or be turned off (conducted) while the pMOSFET is turned on during the potentially destructive write operation. Then, the nMOSFET is turned on, so that the read operation after the potentially destructive write operation has the same conditions as the read operation before the write operation, allowing comparison of the result levels to determine whether the bit state of the memory element has changed after the write operation.

[0012] Another option involves turning off the pMOSFET while the parallel nMOSFET is turned on when the selected memory cell is read. This increases the total resistance of the transistor pair, amplifying the voltage sensed by a read circuit when the memory element transitions from the low-resistance to the high-resistance state (LRS to HRS) after the destructive write operation, with the second read also occurring with only the nMOSFET turned on. In the aforementioned type of read operation, where the voltage is sensed a first time and a second time, such as SRR, the nMOSFET can be turned on while the pMOSFET is turned off each time. The nMOSFET can remain on or be turned off while the pMOSFET is turned on during the potentially destructive write operation.

[0013] Using the pMOSFET, but not the nMOSFET, during the initial selection of a bit helps to reduce the capacitance and discharge the excess voltage across the memory cell more quickly, thereby reducing the resulting bit error rate (and noise) during the initial read.

[0014] In general, both writing and reading can be optimized by selecting which transistor or two transistors of a parallel transistor pair are in a conducting state during the selection versus the subsequent read and write operations.

[0015] These and other advantages are described below.

[0016] Fig. Figure 1 is a block diagram of an exemplary implementation of a storage system connected to a host. Storage system 100 may implement the technology proposed herein. Example storage systems include solid-state drives ("SSDs"), memory cards, and embedded storage devices. Other types of storage systems may also be used.

[0017] The storage system 100 from Fig. 1 includes a controller 102, non-volatile memory arranged in one or more memory packages 104 for storing data, and local memory 106 such as DRAM or ReRAM. The controller 102 includes a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one approach, the FEP circuit 110 is implemented on an ASIC and each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, a unified ASIC controller may combine both the front-end and back-end functions. The ASICs may be implemented on the same semiconductor, so that the controller 102 is manufactured as a system-on-a-chip (SoC). The FEP circuit 110 and the BEP circuit 112 may each include their own processors.In one approach, FEP circuitry 110 and BEP circuitry 112 operate in a master-slave configuration, with FEP circuitry 110 being the master and each BEP circuitry 112 being a slave. FEP circuitry 110 may, for example, implement a Flash Translation Layer (FTL) or Media Management Layer (MML). See also . Fig. 2. The BEP circuit 112 manages the memory operations in the memory packages / memory die at the request of the FEP circuit 110. For example, the BEP circuit 112 can perform read, erase, and program processes. Additionally, the BEP circuit 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), and control the toggle-mode interfaces to the memory packages. Each BEP circuit 112 can be responsible for its own set of memory packages. Alternatively, the interface can be the JEDEC industry standard DDR or LPDDR, such as DDR5 or LPDDR5.

[0018] The memory packages 104 may include one or more memory dies. Therefore, the controller 102 is connected to one or more non-volatile memory dies. In one approach, each memory die in the memory packages 104 uses a storage class memory (SCM) based on a resistive random access memory (such as ReRAM, MRAM, or FeRAM) or a phase change memory (PCM).

[0019] The controller 102 communicates with a host 120 via an interface 130. The interface may implement a protocol such as NVM Express (NVMe) over PCI Express (PCIe) or DDR5 or LPDDR5. To operate with the storage system 100, the host 120 includes a host processor 122, a host memory 124, and a PCIe interface 126 connected along bus 128. The host memory 124 is physical memory such as DRAM, SRAM, non-volatile memory, or another memory type. The host 120, in this example, is located external to and separate from the storage system 100. In another approach, the storage system 100 is embedded within the host 120.

[0020] Fig. 2 is a block diagram of an exemplary implementation of the FEP circuit 110 of Fig. 1. A PCle interface 150 communicates with the host 120 ( Fig. 1) and with a host processor 152. The host processor 152 communicates with a network-on-chip (NOC) 154. A NOC is a communications subsystem on an integrated circuit, typically between cores in a SoC. NOCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies network theory and techniques to on-chip communication. The NOC 154 communicates with a storage processor 156, an SRAM 160, and a DRAM controller 162. The DRAM controller 162 is used to operate and communicate with local memory 106, such as DRAM 106. The SRAM 160 is local RAM used by the storage processor 156. The storage processor 156 is used to operate the FEP circuitry and perform various memory operations. The NOC also communicates with two PCIe interfaces 164 and 166. In Fig. 1, the SSD controller includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 and 166. Each PCIe interface communicates with one of the BEP circuits 112. The number of BEP circuits 112 and PCIe interfaces may vary.

[0021] The FEP circuitry 110 may include a Flash Translation Layer (FTL) or, more generally, a Media Management Layer (MML) 158 that performs memory management (e.g., garbage collection, wear leveling, and load balancing), logical-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation of the SSD or other non-volatile memory system. The MML 158 may be integrated as part of the memory management that can handle memory errors and interact with the host. In particular, the MML may be a module in the FEP circuitry 110 and include an algorithm in the memory device firmware that translates writes from the host into writes to the memory structure of a die (such as the memory array 502 of Fig. 5 or 6A). MML 158 may be required because: 1) the memory may have a limited duration; 2) the memory structure can only be written to in multiples of pages; and / or 3) the memory structure cannot be written to unless erased as a block. MML 158 understands these potential limitations of the memory structure, which may not be visible to the host. Accordingly, MML 158 attempts to translate writes from the host into writes to the memory structure.

[0022] Fig. 3 is a block diagram of an exemplary implementation of the BEP circuit 112 of Fig. 1. In some approaches, the BEP circuit is part of a controller. The BEP circuit includes a PCIe interface 200 for communicating with the FEP circuit 110 (e.g., for communicating with one of the PCIe interfaces 164 and 166 of Fig. 2). The PCIe interface 200 communicates with two NOCs, 202 and 204. In one approach, the two NOCs are combined. The NOCs 202 and 204 are connected to SRAMs 230 and 260, buffers 232 and 262, processors 220 and 250, and data path controllers 222 and 252 via XOR engines 224 and 254, respectively, and ECC engines 226 and 256 (for performing error correction). The XOR engines enable data to be combined and stored in such a way that recovery is possible in the event of a programming error.

[0023] The datapath controllers 222 and 252 are connected to the interface modules 228 and 258, respectively, which each communicate via four channels, in this example with memory packets. Thus, the NOCs 202 and 204 each have four channels for communicating with memory packets. Each interface 228 / 258 includes four toggle mode (TM) interfaces, four buffers, and four schedulers. For each of the channels, there is a scheduler, a buffer, and a TM interface. The datapath controllers 222 and 252 may comprise a processor, an FPGA, a microprocessor, or another type of controller. The XOR engines 224 and 254 and the ECC engines 226 and 256 may be dedicated hardware circuits, such as hardware accelerators. In other approaches, the XOR engines 224 and 254 and the ECC engines 226 and 256 can be implemented in software. The scheduler, buffer, and TM interfaces can be hardware circuits.

[0024] Fig. 4 is a block diagram of an exemplary implementation of the memory package 104 of Fig. 1. The memory package includes a plurality of memory dies 292 connected to a memory bus 294 including data lines and chip enable lines. The memory bus 294 is connected to a toggle mode interface 296 for communicating with the TM interface of the BEP circuit 112 (see, for example, Fig. 3). The memory package may include a small controller connected to the memory bus and the TM interface, and may have one or more memory dies. In one approach, each memory package includes eight or sixteen memory dies; however, the number of dies can vary. Optionally, such control, ECC, and wear-leveling functions can be implemented in each memory die as an on-chip controller with ECC and wear-leveling functions.

[0025] Fig. 5A is a block diagram of an example of a memory system that can implement the technology described herein. The memory system 500 includes a memory array 502 of memory cells. The memory cells can be arranged, for example, in rows and columns in a cross-point memory array, with conductive lines such as word lines extending in the row direction and bit lines extending in the column direction. See, for example, Fig. 7B. The memory system 500 includes a row control circuit 520, whose outputs 508 are connected to the respective word lines of the memory array 502. The row control circuit 520 receives a group of M row address signals and various control signals from a system control logic circuit 560. The row control circuit may include circuits such as row decoders 522, row drivers 524, and block select circuits 526 for both read and write operations. The memory system 500 also includes a column control circuit 510, whose inputs / outputs 506 are connected to the respective bit lines of the memory array 502. The column control circuit 510 receives a group of N column address signals and various control signals from the system control logic circuit 560. The column control circuit may include circuits such as column decoders 512, column drivers 514, block select circuits 516, as well as read / write circuits and I / O multiplexers.See also . Fig. 5B

[0026] System control logic circuitry 560 receives data and commands from a host and provides output data and status to the host. In other approaches, system control logic circuitry 560 receives data and commands from a separate control circuitry and provides output data to that control circuitry, which control circuitry communicates with the host. System control logic circuitry 560 may include a state machine 561 that provides die-level control of memory operations. In one approach, the state machine is software-programmable. In other approaches, the state machine requires no software and is implemented entirely in hardware (e.g., electrical circuitry). In another approach, the state machine is replaced by a microcontroller.System control logic circuitry 560 may also include a power control circuitry 562 that controls the power and voltages supplied to the rows and columns of memory array 502 during memory operations. System control logic circuitry 560 may include one or more state machines, registers 563, and other control logic for controlling the operation of memory system 500. System control logic circuitry 560 may also include a sense circuitry 564, such as a sense amplifier. The sense circuitry may be used during read operations to determine the data state of a memory cell, as described herein. See, for example, FIG. Fig. 12B.

[0027] In some approaches, all elements of memory system 500, including system control logic circuitry 560, may be formed as part of a single die. In other approaches, some or all of system control logic circuitry 560 may be formed on a different die.

[0028] For the purposes of this document, the term "a control circuit," "one or more control circuits," or the like may include row control circuitry 520, column control circuitry 510, a controller, a state machine, a microcontroller, and / or other control circuitry such as that represented by system control logic circuitry 560, or other analog circuitry used to control non-volatile memory.

[0029] The memory array 502 may, for example, comprise a single-level crosspoint memory array or a multi-level crosspoint array ( Fig. 7B). The memory structure can be formed over a single substrate, such as a wafer.

[0030] In one approach, memory array 502 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed over a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory formed monolithically in one or more physical levels of memory cells having an active area disposed over a silicon substrate (or other type of substrate). In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material.

[0031] In another approach, memory array 502 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells with floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0032] The precise type of memory array architecture or memory cells included in memory array 502 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to formulate the memory structure. Other examples of suitable technologies for memory cells of memory array 502 include ReRAM (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architectures of memory array 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, and the like.

[0033] An example of a cross-point ReRAM memory includes reversible resistive switching elements arranged in cross-point arrays accessed via X-lines and Y-lines (e.g., word lines and bit lines, respectively). In another approach, the memory cells may include conductive bridge memory cells. A conductive bridge memory cell may also be referred to as a programmable metallization cell. A conductive bridge memory cell may be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory cell may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes.As temperature increases, ion mobility also increases, causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory cell can have a wide range of programming limits over temperature.

[0034] Magnetoresistive random access memory (MRAM) stores data using magnetic storage elements. The elements are formed from two ferromagnetic plates separated by a thin insulating layer, each of which can hold a magnetization. See also Fig. 7A. One of the two plates (a reference layer) is a permanent magnet set to a specific polarity, and the other plate (a free layer) has a magnetization that can be changed to match that of an external field to create storage space. A memory device is built from a grid of such memory cells. In one approach to programming, each memory cell lies between a pair of perpendicular conductive lines running parallel to the cell, one above and one below the cell. When current flows through the conductive lines, an induced magnetic field is created. MRAM-based memory approaches are described in more detail below.

[0035] Phase-change memory (PCM) devices exploit the unique behavior of chalcogenide glass. One approach uses a GeTe-Sb2Te3 superlattice to achieve nonthermal phase changes simply by changing the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). Therefore, the programming doses are laser pulses. The memory cells can be locked by preventing the memory cells from receiving the light. In other PCM approaches, the memory cells are programmed by current pulses. Note that the use of "pulse" in this document does not require a rectangular pulse, but includes a (continuous or discontinuous) oscillation or burst of sound, current, voltage, light, or other wave.

[0036] The technology described herein is not limited to a single specific memory structure, memory construction, or material composition, but covers, within the spirit and scope of the technology, many relevant memory structures as described herein and as understood by one of ordinary skill in the art.

[0037] The elements of Fig. 5A can be grouped into two parts: the memory array 502 and the peripheral circuitry that encloses all other elements. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of the memory system 500 dedicated to the memory array 502. However, this reduces the area of the memory die available for the peripheral circuitry. In addition, the functions of the system control logic circuitry 560 that can be provided on-chip are limited. Consequently, a fundamental trade-off in designing a memory die for the memory system 500 is how many areas to allocate to the memory array 502 and how many areas to allocate to the peripheral circuitry.

[0038] In addition, the memory array 502 and the peripheral circuits may use different manufacturing techniques such as NMOS, PMOS, and CMOS.

[0039] To address these concerns, the approaches described below can incorporate the elements of Fig. 5A into separately formed dies, which are then bonded together. In particular, the memory array 502 may be formed on one die, and some or all of the peripheral circuitry, including one or more control circuits, may be formed on a separate die. For example, a memory die may be formed from only the memory cells, such as the array of memory cells from Flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or another memory type. Some or all of the peripheral circuitry, including elements such as decoders and sense amplifiers, may then be offloaded to a separate die. This allows each of the memory dies to be individually optimized according to its technology.For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about the CMOS elements, which have now been moved to a separate peripheral circuit die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now accommodate additional capabilities that could not be easily accommodated if they were confined to the edges of the same die containing the memory cell array. The two dies can then be bonded together in a bonded multi-die memory circuit, with the array on one die connected to the peripheral elements on the other die. See . Fig. 6.

[0040] Fig. 5B illustrates exemplary drivers among the row drivers 524 and column drivers 514 of Fig. 5A. The drivers may include charge pumps and regulator circuits for generating and regulating voltages and currents on conductive lines, such as wordlines and bitlines. The drivers include a wordline driver (WL driver) 524a, a WL nMOSFET transistor driver 524b, a WL pMOSFET transistor driver 524c, and a WL isolation transistor driver 524d. The voltage drivers further include a bitline driver (BL driver) 513G, a BL nMOSFET transistor driver 513H, a BL pMOSFET transistor driver 514c, and a BL isolation transistor driver 514d. The WL driver and the BL drivers may be voltage and / or current drivers. See, for example, driver 575 in Fig. 5C.

[0041] Fig. 5C illustrates an exemplary block diagram for a current driver 575. A current driver may, for example, be part of the row control circuit 520 and / or the column control circuit 510 of Fig. 5A and can be implemented in different ways. The current driver may be a write current source used to set a desired current and / or voltage to perform tasks such as writing data to a memory cell, selecting a memory cell, and performing a potentially destructive write operation to a memory cell.

[0042] The example current driver is based on the DAC7811 model from Texas Instruments, Inc., and features a 12-bit serial input multiplying digital-to-analog converter. The current driver outputs a fixed or varying current based on a digital input. The current driver includes a 12-bit R-2R DAC 570, a DAC register 571, an input latch 572, control logic and an input shift register 574, and a power-on reset circuit 573.

[0043] The control logic and input shift register include the inputs NOT(SYNC), SCLK, and SDIN. NOT(SYNC) is an active-low control input. This is a frame synchronization signal for the input data. When SYNC goes low, the buffers for SCLK and SDIN are turned on and the input shift register is enabled. The data is loaded into the shift register on the active edge of the following clock pulses. The serial interface counts the clock pulses, and the data is latched into the shift register on the 16th active clock pulse edge. SCLK is a serial clock input. By default, the data is clocked into the input shift register on the falling edge of the serial clock input. SDIN is a serial data input. The active edge of the serial clock input clocks the data into the 16-bit input register. Upon power-up after a power-on reset, the data is clocked into the shift register on the falling edge of SCLK.SDO is a serial data output of the control logic and the input shift register, such as for daisy-chaining multiple devices.

[0044] RFB, IOUT1, and IOUT2 are included at the outputs of the DAC 570. RFB is the feedback resistor for the DAC. IOUT1 is the current output of the DAC. VOUT is an output voltage of the current source. IOUT2 is an analog ground of the DAC. Example current and voltage outputs are shown in Fig. 13E-13H provided.

[0045] Fig. 5D shows an example of the DAC circuit 570 Fig. 5C. The circuit is digitally controlled based on twelve data bits, DB0-DB11, where DB0 is the least significant bit (LSB) and DB11 is the most significant bit (MSB). The circuit includes a set of resistors 581 with resistance R arranged in series, and a set of resistors 582 with resistance 2R arranged in parallel in different legs of the ladder. Additionally, each 2R resistor is connected to a switch in a set of switches 583 that can connect the resistor to an output path IOUT1 or IOUT2 based on a value of a respective data bit. The circuit receives a reference voltage Vref, which is used to generate currents in the various branches and determines the DAC scaling current. Based on the data bits, a corresponding current is provided as an output.

[0046] Fig. Figure 6 is a block diagram of another example of a memory system that can implement the technology described herein. This is an alternative to the arrangement in Fig. 5A and can be implemented, for example, by wafer-to-wafer bonding to provide a bonded die pair in a memory system 600. A control die 611 and a separate memory die 601 are coupled. The control die includes peripheral circuitry, including system control logic circuitry 560, row control circuitry 520, and column control circuitry 510. Additional elements, such as functionality from controller 102, can also be relocated to control die 611.

[0047] Column control circuitry 510 is coupled to memory array 502 via continuous conductive paths. The conductive paths may provide electrical connection between column decoder 512, column drivers 514, and block select circuitry 516 and the bit lines of memory array 502. The conductive paths may extend from column control circuitry 510 in control die 611 through pads on control die 611. These pads are bonded to corresponding pads of memory die 601, which in turn are bonded to bit lines of memory array 502. Each bit line of memory array 502 may have a corresponding conductive path connected to column control circuitry 510. Similarly, row control circuitry 520 may be coupled to memory array 502 via conductive paths. Each of the conductive paths can correspond to a word line, a dummy word line, or a select gate line.Additional electrical paths may also be provided between the control die 611 and the memory die 601.

[0048] The system control logic circuit 560, the column control circuit 510, the row control circuit 520 and / or the controller 102 (or equivalent circuits) may be used in combination with all or a subset of the other circuits described in Fig. 5 or on the tax-Die 611 in Fig. 6 and similar elements in Fig. 5 may be considered part of one or more control circuits that perform the functions described herein. The control circuits may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit may include a processor, an FGA, an ASIC, an integrated circuit, or another type of circuit.

[0049] In the following discussion, the memory array 502 is primarily explained in the context of a cross-point architecture, although much of the discussion can be applied more generally. In a cross-point architecture, a first set of conductive lines or wires, such as wordlines, run in a first direction relative to the underlying substrate, and a second set of conductive lines or wires, such as bitlines, run in a second direction relative to the underlying substrate. The memory cells are located at the intersection of the wordlines and bitlines. The memory cells at these cross-points can be formed according to any number of technologies, including those described above. The following primarily discusses approaches based on a cross-point architecture with MRAM memory cells.

[0050] Fig. 7A illustrates a cross-sectional view of an exemplary memory cell in the memory array 502 of Fig. 5A or Fig. 6. The memory cell 700 comprises a memory element 710 in series with a selector 702. A memory array may be constructed from a large number of such memory cells. The exemplary memory cell 700 comprises a bottom electrode 701 and a top electrode 706 made of a metal such as titanium (Ti) or titanium nitride (TiN). The memory element is an MRAM in this example and includes a reference layer 703, a tunnel barrier 704, and a free layer 705. The reference layer may comprise a ferromagnetic metal, such as a bilayer of CoFeB and CoPt, coupled to a conductive spacer comprising, for example, conductive metals such as Ta, W, Ru, CN, TiN, and TaN. The free layer may comprise a ferromagnetic metal such as CoFe or a CoFeB alloy with a thickness on the order of 1-2 nm.An Ir layer, which may be doped with Ta, W, or Mo, can be provided between the free layer and the tunnel barrier. The tunnel barrier may comprise, for example, MgO or another insulating material. A cap layer, such as MgO, may be provided over the free layer to increase the anisotropy of the free layer. The resistance of the memory element changes depending on its magnetization.

[0051] An upper conductive line is connected to the upper end 731 of the memory cell, while a lower conductive line is connected to a lower end 721 of the memory cell. One end is a first end, and the other end is a second end. One of the conductive lines is a word line, and the other is a bit line.

[0052] The selector can be located in any position relative to the storage element, such as above, below, or to the side. In this example, the selector is located below the storage element.

[0053] The memory cell can be bipolar (bidirectional), meaning that a voltage of one polarity is applied to its terminals to write (program) it to a high-resistance state (HRS), and a voltage of opposite polarity is applied to its terminals to write it to a low-resistance state (LRS). See, for example, Fig. 8C. The memory element can thus be reversibly switched between two or more states. One resistance state can represent a binary "0," while another resistance state can represent a binary "1." However, for some types of memory element technologies, such as phase-change memories, more than two data / resistance states can be used, all of which can be advantageously selected and detected by the means described.

[0054] The selector may, for example, comprise an ovonic threshold switching material. Examples include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge-Se, Ge-Te, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te.

[0055] The selector controls access to the memory element. In particular, to apply a voltage or current to a memory element to change its resistance state, the corresponding selector must first be switched from a non-conductive state to a conductive state by applying a sufficiently high voltage, e.g., a voltage greater than the threshold voltage. See also Fig. 8B.

[0056] The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer and the free layer. If the two layers are magnetized in opposite directions, the memory cell is in an antiparallel (AP), high-resistance state (HRS). If the two layers are magnetized in the same direction, the memory cell is in a parallel (P), low-resistance state (LRS).

[0057] The magnetization direction is fixed for the reference layer and can change for the free layer. Data is written to an MRAM memory cell by programming the free layer to have either the same or opposite orientation as the reference layer. In one approach, an array of MRAM memory cells is used as in Fig. 7B is placed in an initial state by placing all memory cells in the LRS. A selected memory cell can then be programmed by placing its free layer in the HRS by orienting the magnetic field opposite that of the reference layer. The reference plane maintains its orientation while programming the free layer.

[0058] To capture (read) a data state stored in an MRAM, a voltage is applied to the memory cell to determine its resistance state. The voltage or current can be applied in either direction across the memory cell. In one approach, the voltage is applied by driving a current. See, for example, Fig. 13E and Fig. 13F.

[0059] One type of MRAM is perpendicular spin-transfer torque (STT) MRAM, in which the free layer has a switchable magnetization direction perpendicular to the plane of the free layer. STT is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction can be changed by a spin-polarized current. Charge carriers (such as electrons) have a property known as spin, which is a small amount of angular momentum intrinsic to the carrier. An electric current is generally unpolarized (e.g., it consists of 50% spin-up and 50% spin-down electrons). A spin-polarized current is one with more electrons with one of the spins (e.g., a majority of spin-up electrons or a majority of spin-down electrons). During a write operation, a spin-polarized current can be generated by passing a current through the reference layer.If this spin-polarized current is directed into the free layer, an angular momentum can be transferred to the free layer, changing its magnetization direction.

[0060] In a write operation from antiparallel to parallel (AP2P), an arrow 741 represents an electron write current, e.g., a direction of electron movement (E-movement), and an arrow 742 represents a direction of current flow (I). For example, to write an electron write current in the direction of the upward arrow 741 in Fig. 7A, the voltage of the upper conductive line 730 is set higher (+V) than the voltage of the lower conductive line 730 due to the negative charge of the electron. The electrons in an electron write current become spin-polarized as they pass through the reference layer 703. As the spin-polarized electrons tunnel through the tunnel barrier 704, angular momentum conservation can cause a spin-transfer torque to be exerted on both the free layer 705 and the reference layer 703. This torque is not sufficient to affect the magnetization direction of the reference layer, but it is sufficient to change the magnetization orientation in the free layer to become parallel (P) to that of the reference layer if the initial magnetization orientation of the free layer was antiparallel (AP) to the reference layer.The parallel magnetizations then remain stable before and after switching off the electron write current.

[0061] In a parallel to antiparallel (P2AP) write operation, an arrow 743 represents an electron write current, e.g., a direction of electron motion (E-motion), and an arrow 744 represents a direction of current flow (I). If the magnetizations of the free layer and the reference layer are initially parallel, the magnetization direction of the free layer can be switched to become antiparallel to that of the reference layer by applying an electron write current with the opposite direction to the aforementioned case, e.g., in the direction of the downward arrow 743 in Fig. 7A. In this case, the electron write current is directed from the upper conductive line 730 to the lower conductive line 720 by applying the higher voltage (+V) to the lower conductive line. This causes a P-state free layer to be written to an AP state. This allows the magnetization of the free layer to be set to one of two stable orientations depending on the direction of the electron write current.

[0062] The data ("0" or "1") in the memory cell can be read by measuring its resistance. The LRS can represent a "0" bit, while the HRS represents a "1" bit. During a read operation, a read current can be applied across the memory cell by applying an electron read current from the lower conductive line to the upper conductive line, for example, in the AP2P direction, or from the upper conductive line to the lower conductive line, for example, in the P2AP direction. During a read operation, an excessively high electron write current can disturb the data stored in a memory cell and change its state.For example, if the electron read current uses the P2AP direction, excessive current or voltage in the P2AP direction can switch a memory cell in the low-impedance P-state to the high-impedance AP state during the initial read operation, which is intended to store a level representing the initial bit state at the start of READ. Since more current is required to write P2AP, even though the MRAM memory cell can be read in either direction, the directionality of the write operation can lead to one read direction being favored over another to reduce the bit error rate (glitch).

[0063] To read or write a selected memory cell in a memory array, the bit line and word line corresponding to the selected memory cell are biased to apply a voltage across the selected memory cell and induce electron flow. This also applies a voltage to unselected memory cells in the array connected to the bit line and word line, resulting in leakage current and unnecessary power consumption. One approach to reducing leakage current is to connect a selector element in series with each MRAM.For example, a threshold switch selector has a high resistance (in an off or non-conducting state) when a bias voltage is held at a voltage lower than its threshold voltage, and a low resistance (in an on or conducting state) after it is biased to a voltage higher than its threshold voltage. The threshold switch selector remains on until its current is reduced below a holding current or the voltage is reduced below a holding voltage. See . Fig. 8B. When this occurs, the threshold switch selector returns to the off state until a voltage greater than the threshold voltage (or a current greater than the threshold current) is applied again. Accordingly, to program a memory cell, a voltage and / or current sufficient to turn on the associated threshold switch selector and write to the memory cell is applied at a crosspoint. To read a memory cell, the threshold switch selector must also be turned on before the resistance state of the memory cell can be determined.In one approach, the resistance state is determined by applying a read current, Iread, and sensing the resulting voltage across the memory cell (which includes the storage element and the series-connected selector) and the series-connected select transistors on the bit line and word line (global select node in the sense amplifier). For example, the voltage can be sensed before and after a potentially destructive write operation, as described herein.

[0064] The MRAM memory element 710 operates as described when the threshold switch selector is turned on, even though a voltage drop exists across the threshold switch selector. After the threshold switch selector is turned on by applying a voltage above its threshold voltage, the bias current or bias voltage should be sufficiently above the threshold switch selector's holding current or holding voltage to keep the selector turned on during the subsequent read or write operation. See also Fig. 8A to 8C.

[0065] Fig. Figure 7B illustrates a perspective view of an exemplary crosspoint memory array 750 of memory cells associated with the memory cell of Fig. 7A. A memory array can include one or more levels of memory cells. This example includes two levels, namely a first level L1 and a second level L2. More than two levels could also be used. In this simplified example, there are four word lines WL0_1-WL3_1 on L1, four bit lines BL0-BL3 for L1 and L2, and four word lines WL0_2-WL3_2 on L2. The bit lines are thus shared between the two adjacent levels. Each word line is assigned a row of memory cells, and each bit line is assigned two columns of memory cells (one column for each of the two levels). See also Fig. 9A and Fig. 9B. The orientation of the memory cells, based on the position of the storage element relative to the selector, can be the same or different in each layer. That is, the memory cell can be inverted on L2 relative to L1, so that the polarity of the bitline voltage and / or current operations is the same for each layer. Or, the memory cell can be equally oriented on L1 and L2, so that the bitline is selected by being negative when selecting L1 for reading and writing P2AP, or positive when selecting L2 for reading and writing P2AP; or the voltages are reversed when writing AP2P.

[0066] The wordlines and bitlines comprise a conductive material such as tungsten or copper, any suitable metal, a heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, or a conductive germanide. In this example, the conductive traces are rail-shaped, the wordlines run parallel to each other, and the bitlines run parallel to each other and perpendicular to the wordlines.

[0067] Each memory cell is located at the intersection of a respective word line and bit line. For example, memory cell 700 is located at the intersection of WL3_1 and BL3. To apply a voltage to the memory cell, the control circuit applies the voltage to WL3_1 and BL3.

[0068] The above examples show storage cells in cylindrical or columnar form and conductors in bar form. However, other options are possible.

[0069] Fig. 8A-8C represent a current on a logarithmic scale and a voltage on a linear scale.

[0070] Fig. Figure 8A illustrates an exemplary IU representation for the memory element 710 Fig. 7A. As in connection with Fig. As explained in Figure 7A, a bipolar switching memory element is switched from an HRS to an LRS in an AP2P write operation, for example, by applying a positive voltage to the memory element, and is switched from an LRS to an HRS in a P2AP write operation, for example, by applying a negative voltage to the memory element.

[0071] The IU representation applies to the memory element separated from the selector. The horizontal axis represents Vwrite_AP2P, a voltage at which the AP2P write operation occurs, and Vwrite_P2AP, a voltage at which the P2AP write operation occurs. In this example, Vwrite_AP2P is greater than Vwrite_P2AP.

[0072] During AP2P writing, the memory element is initially in HRS. As the voltage increases from 0 V to Vwrite_AP2P, the current increases, as shown in graph 800 ( Fig. 8A). A current increase during the write operation is shown in diagram 801 when the memory cell is switched to the low-resistance state (LRS). Subsequently, as the voltage decreases toward 0 V, the current also decreases, as shown in graphical diagram 802 ( Fig. 8A).

[0073] During a P2AP write operation, the memory element is initially in the LRS. As the voltage increases from 0 V to Vwrite_P2AP, the current increases, as shown in graph 803 ( Fig. 8A). A decrease in current during the write operation is illustrated by graph 804 when the memory element is switched to the high resistance state (HRS). Subsequently, as the voltage decreases toward 0 V, the current also decreases, as illustrated by graph 805.

[0074] Fig. Figure 8B illustrates an example IU representation for selector 702 Fig. 7A. The IV diagram is for the selector separate from the memory cell. The horizontal axis shows the holding threshold voltage Vhold and the operating threshold voltage Vth. The positive and negative polarities of these voltages are shown for use in write operations, in accordance with Fig. 8A.

[0075] During an AP2P write operation, as the voltage increases from 0 V to Vth, the current increases, as shown in plot 810. When the voltage increases above Vth, the selector turns on, and there is a sudden increase in current, as shown in plot 811. Plot 812 illustrates that the voltage can subsequently increase or decrease with only small changes in current. This depends on the resistance. In most cases, the current increases linearly with voltage for the P-state, but the AP resistance may decrease as the voltage increases. Due to voltage compliance, it is possible for the current to stop changing once the voltage increases above a certain level.When the AP2P write operation is completed, the voltage may drop to Vhold, after which the selector turns off, resulting in a sudden decrease in current (graph 813).

[0076] During a P2AP write operation, when the voltage increases from 0 V to -Vth, the current increases, as shown in plot 820. When the voltage increases above -Vth, the selector turns on, resulting in a sudden increase in current, as shown in plot 821. Plot 822 illustrates that the voltage can subsequently increase or decrease with only small changes in current. When the write operation is complete, the voltage can drop to Vhold, after which the selector turns off, resulting in a sudden decrease in current (plot 823).

[0077] Fig. Figure 8C illustrates an exemplary IU representation for memory cell 700 Fig. 7A. The memory cell has the storage element in series with the selector. The state of the memory cell can be changed by turning on the selector and then applying a voltage and / or current that changes the state of the selector.

[0078] A signal comprising a voltage and a current can only be applied to a memory element when the selector is turned on. The voltage can be increased after the selector is turned on to provide a suitable write or read voltage to the memory cell.

[0079] In an AP2P operation, as the voltage increases from 0 V to Vth, the current increases, as shown in graph 830. When the voltage increases above Vth, the selector turns on, resulting in a sudden increase in current, as shown in graph 831. The voltage can be further increased to Vwrite_AP2P, as shown in graph 832, after which the set operation occurs, resulting in a sudden increase in current (graph 833). Then, when the write operation is complete, graph 834 shows the voltage dropping to Vhold, after which the selector turns off, resulting in a sudden decrease in current (graph 835).

[0080] During a P2AP write operation, when the voltage increases from 0 V to -Vth, the current increases, as shown in graph 840. When the voltage increases above -Vth, the selector turns on, and a sudden increase in current occurs, as shown in graph 841. The voltage can be further increased to Vwrite_P2AP, as shown in graph 842, after which the write operation occurs, resulting in a sudden increase in current (graph 843). Then, when the write operation is complete, graph 844 shows the voltage level dropping to Vhold, after which the selector turns off, resulting in a sudden decrease in current (graph 845).

[0081] Fig. 9A illustrates an example circuit 900 corresponding to the first level of the crosspoint memory array 750. Wordlines WL0_1 through WL3_1 and bitlines BL0-BL3 are illustrated. There are sixteen example memory cells arranged in four rows and four columns, with each row connected to a corresponding wordline and each column connected to a corresponding bitline. Each memory cell may be a two-terminal device, with one terminal connected to a first conductive line and another terminal connected to a second conductive line. The conductive lines may be made of, for example, metal or doped silicon.

[0082] For example, memory cells M00_1, M01_1, M02_1, and M03_1 are connected to WL0_1 and BL0-BL3, respectively; memory cells M10_1, M11_1, M12_1, and M13_1 are connected to WL1_1 and BL0-BL3, respectively; memory cells M20_1, M21_1, M22_1, and M23_1 are connected to WL2_1 and BL0-BL3, respectively; and memory cells M30_1, M31_1, M32_1, and M33_1 are connected to WL3_1 and BL0-BL3, respectively. M30_1, connected to WL3_1 and BL0, is an example of a selected memory cell, as indicated by the dashed line.

[0083] Each bit line and each word line can be terminated in one approach by an open circuit, as illustrated by the circular terminals enclosing the exemplary terminals 915 and 916 for BL0 and WL3_1, respectively.

[0084] A transistor pair can be connected to each conductive line. For example, transistor pairs Wd0_1-Wd3_1 are each connected in series with word lines WL0_1 to WL3_1, and transistor pairs Bd0-Bd3 are each connected in series with bit lines BL0-BL3. Wd0_1-Wd3_1 can be used to select or deselect a respective word line, and Bd0-Bd3 can be used to select or deselect a respective bit line. Wd0_1-Wd3_1 are word line decoder transistors and can be, for example, part of row control circuit 520. Bd0-Bd3 are bit line decoder transistors and can be, for example, part of column control circuit 510.

[0085] In one approach, each transistor decoder pair includes a pMOSFET (represented with a circle on the control gate) in parallel with an nMOSFET. For example, Wd0_1-Wd3_1 include pMOSFETs 940-943 and nMOSFETs 944-947, respectively. Bd0-Bd3 include nMOSFETs 960-963 and pMOSFETs 964-967, respectively. The transistor pairs for the word lines may be connected to a common path 910, while the transistor pairs for the bit lines may be connected to a common path 920. The common path 910 may be connected to a WL driver 524a ( Fig. 5B), and the common path 920 can be connected to a BL driver 513G, for example, during a write operation. The common paths can also be connected to the read circuit 564 ( Fig. 5A), for example, during a read operation. Or, if one of the conductive lines is driven to 0 V or ground, the other conductive line can be connected to the read circuit 564 during a read operation.

[0086] To select memory cell M30_1 for writing or reading, Wd3_1 and Bd0 are provided in a conducting state to apply a voltage / current to the memory cell. Within transistor pair Wd3_1, one or both transistors 943 and 947 can be provided in a conducting state to connect a voltage / current from path 910 to WL3_1 during a write operation or to sense a voltage at WL3_1 via path 910 during a read operation. Similarly, within transistor pair Bd0, one or both transistors 960 and 964 can be provided in a conducting state to connect a voltage / current from path 920 to BL0 during a write operation or to sense a voltage at BL0 via path 920 during a read operation.In general, for enhancement-mode transistors, an nMOSFET is in a conducting state when a positive gate-source voltage is applied, and a pMOSFET is in a conducting state when a negative gate-source voltage is applied, with the magnitude of the gate-source voltage exceeding the transistor's Vth in both cases. See also . Fig. 10F to 10F.

[0087] The circuit also includes an isolation transistor connected to each word line and bit line. For example, WL0_1 to WL3_1 are connected to isolation standby transistors 930-933, respectively. A WL isolation transistor may be provided in a conducting state to pass an isolation standby voltage, e.g., 1.65 V, to a word line that is not selected during a write or read operation. In one approach, the WL isolation transistors may be nMOSFETs and have a source connected to a common voltage on path 920. For a selected word line, e.g., WL3_1, isolation transistor 933 is provided in a non-conducting state to separate the isolation voltage from the word line. This allows a drive voltage / current or a sensed voltage to flow through transistor pair Wd3_1 during a write or read operation.

[0088] Similarly, BL0-BL3 are connected to isolation transistors 950-953. A WL isolation transistor can be provided in the conducting state to pass an isolation voltage, e.g., 1.65 V, to a word line that is not selected during a write or read operation. The BL isolation transistors can be pMOSFETs in one approach and have a drain connected to a common voltage at a path 921. This voltage of path 921 can be identical to the voltage of path 920.

[0089] For the selected bit line, BL0, isolation transistor 950 is provided in a non-conductive state to separate the isolation voltage from the bit line. This allows a drive voltage / current or sensed voltage to flow through transistor pair Bd0 during a write or read operation.

[0090] In one approach, the unselected memory cells connected to both unselected word lines and unselected bit lines can be biased with an equal positive voltage (an isolation voltage) at both of their terminals during a write operation to prevent the unselected memory cells from being written to. An unselected memory cell is a memory cell that is not selected for a read or write operation. A selected memory cell is a memory cell that is selected for a read or write operation.The isolation voltage is sufficient to prevent unselected memory cells from being affected by a write or read operation of a selected memory cell; for example, at approximately the average of the minimum and maximum voltages applied to WL and BL during active operations, so that an unselected cell does not have more than Vth(selector) across it when unselected.

[0091] The pMOSFETs and nMOSFETs of the transistor pairs and the isolation transistors can be made conductive or non-conductive by setting the corresponding control gate voltages (Vcg) in the row decoder control circuits and the column decoder control circuits. Within a transistor pair, the control gate voltage can be controlled independently for the pMOSFET and the nMOSFET. The control gates of the nMOSFET and the pMOSFET can be controlled separately in each transistor pair, with each transistor being used to select or deselect the path.

[0092] Fig. Figure 9B illustrates an exemplary circuit 990 associated with Fig. 9A and the second level of the crosspoint memory array 750 of Fig. 7B. As in connection with Fig. As mentioned in Figure 7B, bit lines BL0-BL3 may be shared by the first and second levels of memory cells. The word line decoders may have a similar arrangement to that for the first level. Word lines WL0_2 to WL3_2 and bit lines BL0-BL3 are shown. There are sixteen exemplary memory cells. For example, memory cells M00_2, M01_2, M02_2, and M03_2 are connected to WL0_2 and BL0-BL3, respectively; memory cells M10_2, M11_2, M12_2, and M13_2 are connected to WL1_2 and BL0-BL3, respectively; memory cells M20_2, M21_2, M22_2, and M23_2 are connected to WL2_2 and BL0-BL3, respectively; and memory cells M30_2, M31_2, M32_2, and M33_2 are connected to WL3_2 and BL0-BL3, respectively. M30_2, connected to WL3_2 and BL0, is an example of a selected memory cell, as indicated by the dashed line.

[0093] Each bit line and each word line may be terminated in one approach by an open circuit, as illustrated by the circular terminals enclosing the example terminals 915a and 916a for BL0 and WL3_2, respectively.

[0094] A transistor pair can be connected to each conductive line. For example, transistor pairs Wd0_2-Wd3_2 are each connected in series with word lines WL0_2 to WL3_2. Wd0_2-Wd3_2 can be used to select or deselect a respective word line, and Bd0-Bd3 can be used to select or deselect a respective bit line. Wd0_2-Wd3_2 are word line decoder transistors and can, for example, be part of row control circuit 520.

[0095] In one approach, each transistor decoder pair includes a pMOSFET in parallel with an nMOSFET. For example, Wd0_2-Wd3_2 include pMOSFETs 980-983 and nMOSFETs 984-987, respectively. The transistor pairs for the word lines can be connected to a common path 910a. The common path 910a can be connected to a WL driver 524a ( Fig. 5B), for example, a current source that provides, for example, about 30 µA during a write operation for a 20 nm CD-MRAM. Or, the common path 910a can be connected to a current source that provides, for example, about 15 µA, and to the read circuit 564 ( Fig. 5A), such as during a reading operation.

[0096] To select the memory cell M30_2 for writing or reading, Wd3_2 and Bd0 are provided in a conducting state to apply a voltage to the memory cell. Within the transistor pair Wd3_2, one or both transistors 983 and 987 can be provided in a conducting state to connect a voltage / current from path 910a to WL3_2 during a write operation or to detect a voltage at WL3_2 on path 910a during a read operation. Similarly, within the transistor pair Bd0 ( Fig. 9A) one or both transistors 960 and 964 may be provided in a conducting state to connect a voltage / current from path 920 to BL0 during a write operation or to detect a voltage at BL0 on path 920 during a read operation.

[0097] In addition, WL0_2 to WL3_2 are each connected to isolation transistors 970-973. The WL isolation transistors may be nMOSFETs in one approach and have a source connected to a common voltage on path 920a. For a selected word line, e.g., WL3_2, isolation transistor 973 is provided in a non-conductive state to separate the isolation voltage from the word line. This allows a drive voltage / current or sensed voltage to flow through transistor pair Wd3_2 during a write or read operation.

[0098] The transistor pair connected to each conductive line (e.g., word line or bit line) provides optimized bidirectional write capability. As mentioned above, both writing and reading can be optimized by providing one or both transistors in a conductive state. In particular, when selecting a memory cell, a voltage of a first conductive line such as WL3_1 can be boosted (increased) to a positive voltage using a pMOSFET driven by a current source, while a voltage of a second conductive line such as BL0 can be boosted (increased) to a positive voltage using an nMOSFET, such as the nMOSFET 960 in Bd0 of Fig. 9A, can be pulled down (reduced) to approximately 0V. This approach minimizes capacitance while the selector is on by using only one transistor of the decoder pair, where a pMOSFET can pull the node higher than an nMOSFET because the loss of Vth is avoided. However, if the selected memory cell is read after the selector is turned on and the WL voltage is lower, one option is to use the parallel nMOSFET of the first conducting line in parallel or alone. The nMOSFET adds a resistance that compensates for the reduced resistance of the pMOSFET to enable accurate sensing of the voltage across the memory cell. The amplitude of the voltage sensed by the read circuit is therefore maintained (or increased if the nMOSFET is used alone).Another option involves turning off the pMOSFET while turning on the parallel nMOSFET when reading the selected memory cell. This increases the total resistance of the transistor pair, amplifying the voltage detected by the read circuit when the MRAM transitions from LRS to HRS.

[0099] Fig. 10A represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is turned on and the nMOSFET is turned off when a voltage is pulled up on a selected word line WL3_1. The word line voltage can be pulled up, for example, during a selection process for the selector of a decoded bit or during writing. In one approach, the voltage is pulled up using a read current source to select the bit and a write current source to write the bit, each using the pMOSFET, as shown in Fig. 5C. And the read operation can be performed with the pMOSFET. Or both the pMOSFETs and nMOSFETs can be turned on to enhance the differential signal to the sense amplifier from the MRAM, which changes state for a self-referenced read (SRR) after the write operation. Or the signal can be further increased by reading with the nMOSFET, by turning off only the pMOSFET and turning on the nMOSFET after the selector is turned on.

[0100] In Fig. 10A-10C, the transistor pair Wd3_1 has the pMOSFET 943 in parallel with the nMOSFET 947. In Fig. In Figures 10A-10F, the control gate, drain, and source of the pMOSFETs are labeled Gp, Dp, and Sp, respectively, and the control gate, drain, and source of the nMOSFETs are labeled Gn, Dn, and Sn, respectively. Furthermore, the pMOSFET and the nMOSFET can function as pass gates in some configurations.

[0101] The arrow passes through the pMOSFET from common path 910 to WL3_1 and represents a current flow direction from the source (Sp) to the drain (Dp). As mentioned above, a pMOSFET is in the conducting state when a negative gate-source voltage is applied that exceeds the transistor's Vth. This could be achieved, for example, by applying 0 V to the gate (Gp) and a positive voltage such as greater than 1 V to the source, assuming a Vth of, for example, 1 V. The nMOSFET is in the non-conducting state when a gate-source voltage does not exceed Vth. This could be achieved, for example, by applying 0 V to the gate.

[0102] Fig. 10B shows the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is off and the nMOSFET is on when a voltage on a selected word line WL3_1 is sensed. During sensing, a voltage from WL3_1 is sensed by the sense circuit via common path 910 and the transistor pair Wd3_1, and in this example, specifically via nMOSFET 947. The pMOSFET is turned off, e.g., by applying 3.3 V to the gate (Gp). The nMOSFET is turned on, e.g., by applying 3.3 V to the gate (Gn). The arrow passes through the nMOSFET of WL3_1 to common path 910 and represents a current flow direction from drain (Dn) to source (Sn).

[0103] Fig. 10C represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is turned on and the nMOSFET is turned on when a voltage on a selected word line WL3_1 is sensed. During sensing, a voltage from WL3_1 is sensed by the sense circuit via common path 910 and transistor pair Wd3_1, and in this example specifically via n-MOSFET 947 and pMOSFET 943. The pMOSFET is turned on, e.g., by applying 0 V to the gate (Gp). The voltage on Wd3_1 is a positive voltage at the source of the pMOSFET and is assumed to be high enough to provide |Vgs|>Vth. The nMOSFET is turned on, e.g., by applying 3.3 V to the gate (Gn). The voltage on Wd3_1 is a positive voltage at the drain (Dn) of the nMOSFET and may be lower than the control gate voltage (Gn). For two transistors connected in parallel, Dp is equal to Sn and Sp is equal to Dn.

[0104] Fig. 10D represents the WL transistor pair Wd3_1 of Fig. 9A in a configuration in which the pMOSFET is off and the nMOSFET is on when a selected bit line BL0 is pulled low, such as to approximately 0 V. The pulling down of the bit line voltage may occur, for example, during a selection process for the selector of a decoded bit or during reading or writing of that bit. The selection or writing may, as mentioned, be bidirectional. Accordingly, in one direction, the word line is biased higher than the bit line, and in the opposite direction, the bit line is biased higher than the word line. When the bit line is biased higher, it may be driven, for example, by the pMOSFET.

[0105] In Fig. 10D-10F, the transistor pair Bd0 has the pMOSFET 964 in parallel with the nMOSFET 960.

[0106] The arrow runs through the nMOSFET from common path 920 to BL0 and represents a current flow direction from drain (Dn) to source (Sn). This could be achieved, for example, by applying 3.3 V to the gate of the nMOSFET. The pMOSFET is turned off, for example, by applying 3.3 V to the gate.

[0107] Fig. 10E represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is off and the nMOSFET is on during a sense process in which the selected bit line BL0 is grounded. In a read option, a voltage from BL0 on the common path 920 may be grounded, e.g., set to 0 V. The pMOSFET is turned off, e.g., by applying 3.3 V to the gate, and the nMOSFET is turned on, e.g., by applying 3.3 V to the gate. The arrow passes through the nMOSFET from BL0 to the common path 920 and represents a current flow direction from drain (Dn) to source (Sn).

[0108] Fig. 10F represents the WL transistor pair Wd3_1 Fig. 9A in a configuration in which the pMOSFET is turned on and the nMOSFET is turned on during a sense process in which the selected bit line BL0 is grounded. In this option, the pMOSFET is turned on, e.g., by applying 0 V to the gate, and the nMOSFET is turned on, e.g., by applying 3.3 V to the gate.

[0109] Fig. 11A illustrates a flowchart of an exemplary process for performing a write operation for a selected memory cell, such as memory cell 700 of Fig. 7A. Step 1000 includes driving a current through an upper conductive line to place a memory cell in a memory array in the LRS (P) state. If this is repeated at all memory locations, all bits will be placed in the LRS state. In this approach, all memory cells are in the same known state. In one approach, the lower conductive line may be set to a fixed voltage. Step 1001 includes receiving data to be stored in the memory array. The data may be received, for example, via a communications interface. Step 1002 includes identifying memory cells to be programmed to the HRS (AP) state based on the data. These may be, for example, bits to store a 1-bit.Step 1003 involves driving a current through the lower conductive line to select the identified memory cell and program it from the P state to the AP state. In one approach, the upper conductive line may be set to a fixed voltage. Reference to the upper and lower conductive lines corresponds to the memory cell configuration of FIG. Fig. 7A. See also Fig. 13A and Fig. 13B.

[0110] Fig. 11B illustrates a flowchart of an exemplary process for performing a single voltage sense read operation for a selected memory cell, such as memory cell 700 of Fig. 7A. The process can be used for example for L1 or L2 of Fig. 7B. In step 1010, a process for decoding and enabling a selector of a memory cell is initiated. A first conductive line may be connected to a first end of the memory cell and to a first transistor pair, and a second conductive line may be connected to a second end of the memory cell and to a second transistor pair. Fig. 9A, for example, where M30_1 is the selected memory cell in L1, the first conductive line WL3_1 is connected to the first transistor pair Wd3_1, and the second conductive line BL0 is connected to the second transistor pair Bd0. In another example, in Fig. 9B, where M30_2 is the selected memory cell in L2, the first conductive line BL0 and connected to the first transistor pair Bd0 and the second conductive line WL3_2 is connected to the second transistor pair Wd3_2.

[0111] Step 1011 includes selecting the memory cell by pulling up a voltage of the first conductive line with a pMOSFET of the first transistor pair while an nMOSFET of the first transistor pair is in a non-conductive state, and by pulling down a voltage of the second conductive line with an nMOSFET of the second transistor pair while a pMOSFET of the second transistor pair is in a non-conductive state. Pulling up the voltage of the first conductive line may include applying a current Iread to the first conductive line, as shown in Fig. 13C and Fig. 13D. Pulling down the voltage of the second conductive line may involve driving the second conductive line to near 0 V. Selecting may, as mentioned, switch a selector of the memory cell from a non-conductive state to a conductive state. In accordance with Fig. 8C, for example, a voltage can be applied across the memory cell that increases from 0 V to Vth(selector). See Fig. 13C and Fig. 13D at t1-t2. In the selection step 1011, a read current source is used to provide the desired voltages and currents on a word line and bit line.

[0112] In general, an MRAM crosspoint array can select over a wider Vth range of the selector by using a pMOSFET for the conducting line instead of an nMOSFET for the conducting line, whose voltage is pulled up because the pMOSFET can pull approximately the positive voltage supply, whereas the nMOSFET can pull the positive voltage supply minus its Vth, a loss of about 1V in the range. If the memory cells in each layer have the same orientation, the conducting line that is pulled up in voltage can be a first conducting line below the memory cell, and the conducting line that is pulled down in voltage can be a second conducting line above the memory cell in the first layer. Turning on the selector induces a transient voltage across the memory cell as the excess voltage is dissipated by the memory element.The internal series resistance of the memory cell is on the order of 20 kΩ. The overvoltage is Vth-Vhold, which can be reduced by increasing Vhold or by reducing the capacitance and Vth. To minimize the risk of a state reversal of the memory element due to the overvoltage energy, the settling time should be minimized by reducing the capacitance.

[0113] The bit line has a higher number of layers due to its longer length and its placement between the two layers, as shown in Fig. 7B, tend to have a larger capacitance, so the leakage time is mainly determined by the capacitance of the wordline. The leakage time and read latency can be reduced by reducing the capacitance. One option is to shorten the length and increase the spacing between the tile wires. Another option is to reduce the size of the transistor used to drive the tile wire. Another option is to choose an nMOSFET for the wordline and a pMOSFET for the higher-capacity bitline, since the nMOSFET on the wordline can be three times smaller for the same drive. Pulling high with the pMOSFET and pulling low with the nMOSFET allows the widest range of allowable Vth for a given voltage supply because it avoids Vth leakage in the driver transistors. However, these approaches are problematic.For example, the fabrication of a multi-level memory device is simplified if the memory cells in each level have the same orientation. In this case, one of the levels must pull the word line high with a pMOSFET, and the other level must pull the word line low with an nMOSFET to achieve a higher allowable Vth(selector).

[0114] Selecting with a single n- or pMOSFET alone reduces the capacitance and allows for higher Vth, but reduces the signal difference when the memory element changes state. For example, if the memory cell has a resistance of 25 kΩ in the LRS and 50 kΩ in the HRS, and the read current Iread is 15 µA, the voltage across the memory cell will be 375 mV in the LRS and 750 mV in the HRS. This is a signal difference of 375 mV across the MRAM between the two states. However, the drain-source resistance, Rds, of the MOSFET will be reduced by a larger Von because the HRS of the memory cell increases the voltage across the read circuit. This could reduce the signal difference to, say, 250-300 mV, making it difficult to detect the memory cell's state change during readout.

[0115] Two options are provided to optimize the signal to the read circuit. A first option (step 1012a) is to select the selector with only one transistor for reduced capacitance, use a pMOSFET, for example, at level 1 to allow for a higher Vth, and then turn on the available nMOSFET during read while the pMOSFET remains on. In this case, during read, the increased Von of the pMOSFET is balanced by the decreased Von of the nMOSFET, so that the total resistance remains approximately constant and approximately the full signal difference is passed to the read circuit.

[0116] A second option (step 1012b) is to select the selector with only one transistor for reduced capacitance, use a pMOSFET at level 1 to enable a higher Vth, and then turn on the available nMOSFET during read while turning off the pMOSFET after the selector is turned on, thus using only one transistor for selecting to reduce capacitance during turn-on. The pMOSFET was chosen to allow a wider range of Vth(selector) during selection. Then, after selection, switch to only the nMOSFET for reading and storing the level during the initial read of an SRR. The higher resistance of the nMOSFET results in a higher signal at the read circuit. This approach is suitable when the resistance-area product (RA) of the memory cell is relatively low, such as five or less.If the RA is relatively high, such as ten or greater, the signal to the read circuit may become too high and exceed the range of the read circuit or the power supply. In this case, it may be beneficial to turn both on.

[0117] In the first option, step 1012a in the first transistor pair includes placing the nMOSFET into a conducting state and maintaining the pMOSFET in a conducting state. In one approach, after the memory cell is selected and in preparation for reading the memory cell, a control circuit is configured to place the nMOSFET from the non-conducting state to the conducting state and maintain the pMOSFET in the conducting state.

[0118] In the second option, step 1012b in the first transistor pair, after turning on the selector, involves setting the pMOSFET to a non-conductive state and maintaining the nMOSFET in a conductive state. For consistency, the first and second read operations before and after the destructive write operation of the SRR should use the same option. In one approach, after selecting the memory cell and in preparation for reading the memory cell, a control circuit is configured to change the pMOSFET from the conductive state to the non-conductive state and to turn the nMOSFET into the conductive state.

[0119] The common step 1013 includes sensing a voltage Vread on the first conductive line across the first transistor pair and comparing it with a reference voltage Vref. See the example of the read circuit in Fig. 12A. See also Fig. 13C and Fig. 13D at t2-t3.

[0120] Fig. 11C illustrates a flowchart of an exemplary process for performing a dual voltage sense read operation for a selected memory cell, such as memory cell 700 of Fig. 7A. Steps 1100, 1101, 1102a and 1102b correspond to steps 1010, 1011, 1012a and 1012b of Fig. 11B. See Fig. 13E and Fig. 13F, where the selection of step 1101 occurs at t1-t2.

[0121] The first option includes steps 1102a, 1104a and 1106a, while the second option includes steps 1102b, 1104b and 1106b.

[0122] In this dual voltage sensing approach, a first voltage is sensed in step 1103 and a second voltage is sensed in step 1107. In particular, the common step 1103 includes sensing and storing a first voltage on the first conductive line across the first transistor pair. For example, the first voltage Vread1 in the first capacitor C1 of the read circuit may be Fig. 12B. See also Fig. 13E and Fig. 13F at t2-t3.

[0123] In the first option, step 1104a in the first transistor pair includes setting the nMOSFET to a non-conducting state and maintaining the pMOSFET in a conducting state. In one approach, after sensing the first voltage and in preparation for the potentially destructive write operation of the memory cell, a control circuit is configured to set the nMOSFET from the conducting state to the non-conducting state and maintain the pMOSFET in the conducting state.

[0124] In the second option, step 1104b in the first transistor pair includes setting the nMOSFET to a non-conductive state and maintaining the pMOSFET in a conductive state. In one approach, after sensing the first voltage and in preparation for the potentially destructive write operation of the memory cell, a control circuit is configured to set the nMOSFET from the non-conductive state to the conductive state and maintain the pMOSFET in the conductive state.

[0125] The common step 1105 includes performing a potentially destructive write operation of the memory cell via the first transistor pair. This write operation ensures that the memory cell is in the HRS. If the memory cell is already in the HRS, the write is non-destructive. However, if the memory cell is in the LRS, the write is destructive because it changes the data state of the memory cell. See also Fig. 13E and Fig. 13F at t3-t5.

[0126] In the first option, step 1106a in the first transistor pair includes placing the nMOSFET into a conducting state and maintaining the pMOSFET in a conducting state. In one approach, after the potentially destructive write operation of the memory cell and in preparation for sensing the second voltage, the control circuit is configured to place the nMOSFET from the non-conducting state to the conducting state and maintain the pMOSFET in the conducting state.

[0127] In the second option, step 1106b in the first transistor pair includes setting the pMOSFET to a non-conducting state and maintaining the nMOSFET in a conducting state. In one approach, after the potentially destructive write operation of the memory cell and in preparation for sensing the second voltage, the control circuit is configured to set the pMOSFET from the conducting state to the non-conducting state and maintain the nMOSFET in the conducting state.

[0128] The common step 1107 includes sensing a second voltage (Vread2) on the first conductive line via the first transistor pair. The second voltage may, for example, be applied to the inverting input (-) of the comparator 1201 of the read circuit of Fig. 12B.

[0129] The common step 1108 includes determining whether the second voltage exceeds the first voltage by more than a specified amount. In one approach, a second capacitor C2 stores an offset voltage Voffset, which can be added to Vread1 by connecting C1 and C2 in series via a switch 1202. The combined input, Vread1+Voffset, is then provided to the non-inverting input of the comparator for comparison with Vread2. By adding an offset voltage, it can be more reliably determined whether the memory cell switches from an LRS to an HRS in step 1105.

[0130] Based on step 1108, step 1109a or 1109b is reached. Step 1109a determines that the memory cell stores a low-resistance data state if the second voltage exceeds the first voltage by more than the specified amount, and step 1109b determines that the memory cell stores a high-resistance data state if the second voltage does not exceed the first voltage by more than the specified amount. Step 1110 represents a write-back process following step 1109a in which a memory cell whose state was altered by the destructive write process is restored to its original state. See also Fig. 13G and Fig. 13H.

[0131] Fig. Figure 12A illustrates an exemplary implementation of the read circuit 564 of Fig. 7B, which is related to the process of Fig. 11B. The read circuit includes a comparator 1201. A reference voltage Vref is provided to the inverting input, and a sensed voltage Vread on the common path 1204 is provided to the non-inverting input when a switch 1210 is closed. Vref can be set to a level between a voltage expected for an LRS memory cell, V_LRS, and a voltage expected for an HRS memory cell, V_HRS. An output of the comparator thus indicates the data state of the memory cell.

[0132] Fig. Figure 12B illustrates another exemplary implementation of the read circuit 564 of Fig. 7B, which is related to the process of Fig. 11C. As in connection with Fig. As mentioned in Figure 11C, the read circuit may include a first capacitor C1 that stores a first voltage Vread1 at a selected memory cell and a second capacitor C2 that stores an offset voltage Voffset. In one example, Vread1 is 375 mV in the LRS and 750 mV in the HRS, and Voffset is 100-150 mV. Before sensing, C1 may be charged to Voffset by applying an appropriate voltage to nodes 1207 and 1208 and closing (making conductive) switches 1205 and 1206. These switches may then be opened (made non-conductive) to maintain Voffset in C2.

[0133] Node 1204 can be connected to the common path 910 of Fig. 9A. During sensing, the common path is connected to a selected word line such as WL3_1 via the transistor pair Wd3_1. This allows the word line voltage to be passed to node 1204. Switch 1203 is closed while switch 1202 is open to provide Vread1 via C1. Subsequently, switch 1203 is opened to disconnect C1 from the word line. Switch 1202 is then closed to provide C2 in series with C1. In one approach, C2 is connected to the non-inverting input of a comparator 1201. To obtain Vread2, switch 1209 is closed while switch 1203 is opened to connect node 1204 to the inverting input of the comparator. Alternatively, a capacitor can be connected, one end of which is connected to the stored level voltage, also to a capacitor.The other end of the capacitor can be driven positive when used in a sense amplifier to boost the voltage by about 150 mV for level 1, for example, when the SRR is P2AP. Or the other end of the capacitor can be driven negative to shift the stored voltage by -150 mV for level 1, for example, when the SRR is P2AP. Or the direction of the boost can be reversed when the SRR is AP2P.

[0134] Fig. Figure 12C shows exemplary parallel resistances of the pMOSFET and the nMOSFET of the transistor pair Wd3_1, which are Fig. 9A. The pMOSFET and the nMOSFET have resistances Rp and Rn, respectively, when they are in the conducting state, and the total resistance Rt of the transistor pair is determined by: 1 / Rt=1 / Rp+1 / Rn. As mentioned above, in a first option, a decreased resistance of the pMOSFET, Rp (represented by a downward arrow), can be compensated for by an increased resistance of the nMOSFET, Rn (represented by an upward arrow), when both transistors are in the conducting state. This preserves the signal amplitude. In a second option, which increases the signal amplitude, the decreased resistance of the pMOSFET, Rp, is replaced by the increased resistance of the nMOSFET, Rn, when the pMOSFET is in the non-conducting state and the nMOSFET is in the conducting state.Thus, a reduced resistance of the pMOSFET caused by selecting the memory cell is compensated by a resistance of the nMOSFET when the nMOSFET is in the conducting state. Furthermore, a reduced resistance of the pMOSFET caused by selecting the memory cell is replaced by a resistance of the nMOSFET when the nMOSFET is in the conducting state.

[0135] Fig. Figure 13A shows an example of the current versus time for a memory cell that is connected to the write process in Fig. 11A. Fig. Figure 13B shows an example plot of voltage versus time for a memory cell connected to Fig. 13A. The memory cell is selected at t1-t2. A current Iread is driven on one of the conductive lines, corresponding to step 1000, until the selector resistance switches to a lower level at t2. At this time, a voltage drop to the level of graph 1300 occurs if the memory cell is in the LRS. Or, the voltage is maintained at the level of graph 1301 if the memory cell is in the HRS. The selection process could be performed with a write current when writing is desired; however, bit lifetime can be improved by always selecting with a read current and then increasing the current to a write current. The LRS memory cell switches to the HRS at t3, and the process ends at t4.

[0136] Fig. Figure 13C shows an example of the current versus time for a memory cell associated with the read process of Fig. 11B. Fig. Figure 13D shows an example plot of voltage versus time for a memory cell connected to Fig. 13C. The memory cell is selected at t1-t2. A current Iread, which is lower than Iwrite, is driven on one of the conductive lines, corresponding to step 1011, until the selector resistance switches to a lower level at t2. At this time, a voltage drop occurs to a level that depends on whether the memory cell is in the LRS or HRS and on the configuration of the transistor pair. Specifically, for the LRS, the voltages of plots 1305, 1305a, and 1305b result when only the pMOSFET is on, when both the nMOSFET and the pMOSFET are on, or when only the nMOSFET is on, respectively. For the HRS, the voltages of the graphs 1306, 1306a and 1306b result when only the pMOSFET is turned on, when both the nMOSFET and the pMOSFET are turned on or respectively when only the nMOSFET is turned on.The detection of the voltage Vread occurs at t2-t3, in accordance with step 1013, and the process ends at t3.

[0137] Fig. Figure 13E illustrates an example plot of current versus time for a memory cell following steps 1100-1108 of the process of Fig. 11C. Fig. Figure 13F shows an example of the voltage versus time plot for a memory cell connected to Fig. 13E. The selection of the memory cell occurs at t1-t2. During this time, the memory cell is driven with a fixed current of, for example, 15 µA, denoted as Iread, while a voltage rises to, for example, Vth=3 V to select the memory cell. At t2, the selector changes from its non-conducting state to its low-resistance, conducting state, causing a voltage drop toward Vhold(selector). At t2-t3, the graphs represent the voltage V_HRS or V_LRS across the memory cell when it is in the HRS (the AP state) or the LRS (the P state), respectively. In particular, for the LRS, the voltages of the graphical representations 1311, 1311a and 1311b result when only the pMOSFET is switched on, when both the nMOSFET and the pMOSFET are switched on or respectively when only the nMOSFET is switched on.For the HRS, the voltages in plots 1310, 1310a, and 1310b result when only the pMOSFET is on, when both the nMOSFET and the pMOSFET are on, or when only the nMOSFET is on, respectively. Vread1 can be detected from t2-t3.

[0138] From t3-t5, the potentially destructive write operation occurs by driving a higher fixed current of Iwrite, e.g., 30 µA. From t3-t4, plot 1312 represents the case where the memory cell is in the HRS, and plot 1313 represents the case where the memory cell is in the LRS. At t4, the memory cell in the LRS transitions to the HRS in a destructive write operation, or the memory cell in the HRS remains in the HRS. At t5-t6, the current is reduced to Iread, and Vread2 is determined for comparison with Vread1. In particular, the voltages of plots 1320, 1320a, and 1320b result when only the pMOSFET is turned on, when both the nMOSFET and the pMOSFET are turned on, or when only the nMOSFET is turned on, respectively.The data state of the memory cell is determined until t6, then the process is completed by comparing it with the level stored during the first read and correcting it upwards by 150 mV (Voffset).

[0139] Fig. Figure 13G illustrates an exemplary current versus time plot for a memory cell associated with step 1110 of the process of Fig. 11C. Fig. Figure 13H shows an example of the voltage versus time plot for a memory cell that is Fig.13G. The current Iwrite flows through the memory cell and can be, for example, 30 µA. This current is driven to perform an AP2P write operation for a target cell in the AP state. At t1-t2, Iwrite is applied, and the voltage rises from 0 V to, for example, -3 V to select the memory cell and remains at -3 V from t2-t3. -3 V could be the Vth of the selector. At t3, the cell in the AP state switches to the P state, so the voltage level decreases. The process ends at t4.

[0140] In one approach, a device comprises: a control circuit configured to be connected to a cross-point memory array, the cross-point memory array comprising a memory cell disposed between a first conductive line and a second conductive line, and a first transistor pair comprising a pMOSFET in parallel with an nMOSFET and connected to the first conductive line, the memory cell comprising a storage element in series with a threshold switching selector; the control circuit configured to select the memory cell is configured to pull up a voltage of the first conductive line with the pMOSFET while the nMOSFET is in a non-conductive state; and the control circuit configured to subsequently read the memory cell while the pMOSFET is in a non-conductive state and the nMOSFET is in a conductive state.

[0141] In another approach, a method comprises switching a threshold switch selector of a memory cell from a high-impedance state to a low-impedance state, wherein a first conductive line is connected to a first end of the memory cell and a second conductive line is connected to a second end of the memory cell, and a first transistor pair comprising a pMOSFET in parallel with an nMOSFET is connected to the first conductive line, wherein the switching comprises setting a voltage of the first conductive line with the pMOSFET while maintaining the nMOSFET in a non-conductive state; and, when the threshold switch selector is in the low-impedance state, sensing a first voltage at the first conductive line across the first transistor pair while the pMOSFET is in a non-conductive state and the nMOSFET is in a conductive state.

[0142] In another approach, a device comprises: a cross-point memory array, the cross-point memory array comprising a memory cell, the memory cell comprising an MRAM in series with a threshold switch selector; a first conductive line connected to a first end of the memory cell; a second conductive line connected to a second end of the memory cell; a first transistor pair comprising a pMOSFET in parallel with an nMOSFET and connected to the first conductive line; a second transistor pair comprising a pMOSFET in parallel with an nMOSFET and connected to the second conductive line;and a control circuit, wherein for selecting the memory cell, the control circuit is configured to pull up a voltage of the first conductive line via the pMOSFET, but not the nMOSFET, of the first transistor pair and to pull down a voltage of the second conductive line via the nMOSFET, but not the pMOSFET of the second transistor pair, and wherein the control circuit for reading the memory cell is configured to detect a voltage of the first conductive line a first time via the nMOSFET, but not the pMOSFET of the first transistor pair.;

[0143] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described approaches were chosen to best explain the principles of the invention and their practical application, thereby enabling others skilled in the art to best utilize the invention in various approaches and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

[1] Facility comprising: a control circuit (510, 520, 560) configured to be connected to a crosspoint memory array (750), the crosspoint memory array comprising a memory cell (700, M30_1) disposed between a first conductive line (WL3_1) and a second conductive line (BL0), and a first transistor pair comprising a pMOSFET (943) in parallel with an nMOSFET (947) and connected to the first conductive line (WL3_1), the memory cell (700) comprising a storage element (710) in series with a threshold switching selector (702); the control circuit for selecting the memory cell (M30_1) is configured to pull up a voltage of the first conductive line (WL3_1) with the pMOSFET (943) while the nMOSFET (947) is in a non-conductive state; and the control circuit is configured to subsequently read the memory cell (M30_1) while the pMOSFET (943) is in a non-conductive state and the nMOSFET (947) is in a conductive state. [2] Device according to claim 1, wherein: for reading the memory cell (M30_1), the control circuit is configured to detect a voltage on the first conductive line (WL3_1) via the first transistor pair (Wd3_1) while the pMOSFET (943) is in the non-conductive state and the nMOSFET (947) is in the conductive state. [3] Device according to claim 1, wherein: after selecting the memory cell (M30_1) and in preparation for reading the memory cell (M30_1), the control circuit is configured to switch the nMOSFET (947) from the non-conductive state to the conductive state and to switch the pMOSFET (943) from the conductive state to the non-conductive state. [4] Device according to claim 1, wherein for reading the memory cell (M30_1) the control circuit is arranged to: Detecting a first voltage (Vread1) on the first conductive line (WL3_1) via the first transistor pair (Wd3_1) while the pMOSFET (943) is in the non-conductive state and the nMOSFET (947) is in the conductive state before performing a potentially destructive write operation of the memory cell (M30_1); Detecting a second voltage (Vread2) on the first conductive line (WL3_1) via the first transistor pair (Wd3_1) while the pMOSFET (943) is in the non-conductive state and the nMOSFET (947) is in the conductive state after the potentially destructive write operation of the memory cell (M30_1) has been performed; and Determining a data state of the memory cell (M30_1) based on the first voltage and the second voltage. [5] Device according to claim 4, wherein: after detecting the first voltage and in preparation for the potentially destructive write operation of the memory cell (M30_1), the control circuit is configured to switch the nMOSFET (947) from the conducting state to the non-conducting state and to switch the pMOSFET (943) from the non-conducting state to the conducting state. [6] Device according to claim 4, wherein: after the potentially destructive write operation of the memory cell (M30_1) and in preparation for detecting (1107) the second voltage, the control circuit is configured to switch the nMOSFET (947) from the non-conductive state to the conductive state and to switch the pMOSFET (943) from the conductive state to the non-conductive state. [7] Device according to claim 4, wherein: the control circuit is configured to keep the pMOSFET (943) in the conducting state and the nMOSFET (947) in the non-conducting state during the potentially destructive write operation of the memory cell (M30_1). [8] Device according to claim 4, wherein: the control circuit is configured to determine that the data state is a low-impedance data state when the second voltage exceeds the first voltage by more than a specified amount, and to determine that the data state is a high-impedance data state when the second voltage does not exceed the first voltage by more than a specified amount. [9] Device according to claim 4, wherein the control circuit comprises: a first capacitor (C1) arranged to store the first voltage (Vread1); a second capacitor (C2) arranged to store an offset voltage (Voffset); a switch (1202) arranged to connect the first capacitor (C1) and the second capacitor (C2) in series; and a comparator (1201) arranged to compare the second voltage (Vread2) with a voltage across the first capacitor (C1) and across the second capacitor (C2) connected in series. [10] Device according to claim 1, further comprising: a second transistor pair (Bd0) comprising a pMOSFET (964) in parallel with an nMOSFET (960) and configured to connect the second conductive line (BL0) to the control circuit, wherein the control circuit for selecting the memory cell (M30_1) is configured to pull down a voltage of the second conductive line (BL0) with the nMOSFET (960) of the second transistor pair (Bd0) while the pMOSFET (964) of the second transistor pair (Bd0) is in the non-conductive state. [11] Method comprising: Switching a threshold switching selector (702) of a memory cell (700, M30_1) from a high-resistance state to a low-resistance state, wherein a first conductive line (WL3_1) is connected to a first end of the memory cell (M30_1) and a second conductive line (BL0) is connected to a second end of the memory cell (M30_1), and a first transistor pair (Wd3_1) comprising a pMOSFET (943) in parallel with an nMOSFET (947) is connected to the first conductive line (WL3_1), wherein the switching comprises setting a voltage of the first conductive line (WL3_1) with the pMOSFET (943) while maintaining the nMOSFET (947) in a non-conductive state; and when the threshold switching selector (702) is in the low-impedance state, sensing a first voltage (Vread1) on the first conductive line (WL3_1) via the first transistor pair (Wd3_1) while the pMOSFET (943) is in a non-conductive state and the nMOSFET (947) is in a conductive state. [12] The method of claim 11, further comprising: Performing (1105) a potentially destructive write operation of the memory cell (M30_1) to ensure that the memory cell (M30_1) is in a high-resistance state after detecting the first voltage (Vread1); Detecting (1107) a second voltage (Vread2) on the first conductive line (WL3_1) via the first transistor pair (Wd3_1) while the pMOSFET (943) is in a non-conductive state and the nMOSFET (947) is in a conductive state after the potentially destructive write operation has been performed; and Compare the first voltage with the second voltage. [13] The method of claim 11, further comprising: Performing (1105) a potentially destructive write operation of the memory cell (M30_1) to ensure that the memory cell (M30_1) is in a high-resistance state after detecting the first voltage; detecting (1107) a second voltage on the first conductive line (WL3_1) via the first transistor pair (Wd3_1) while the pMOSFET (943) is in a non-conductive state and the nMOSFET (947) is in a conductive state after the potentially destructive write operation has been performed; and Comparing the first voltage with a sum of the second voltage. [14] The method of claim 13, further comprising: after detecting (1103) the first voltage and before the potentially destructive write operation of the memory cell (M30_1), switching the nMOSFET from the conducting state to the non-conducting state and switching the pMOSFET from the non-conducting state to the conducting state; and after the potentially destructive write operation of the memory cell (M30_1) and before detecting (1107) the second voltage, switching the nMOSFET from the non-conductive state to the conductive state and switching the pMOSFET from the conductive state to the non-conductive state. [15] Facility comprising: a crosspoint memory array (750), the crosspoint memory array comprising a memory cell (700, M30_1), the memory cell comprising an MRAM (710) in series with a threshold switching selector (702); a first conductive line (WL3_1) connected to a first end of the memory cell (M30_1); a second conductive line (BL0) connected to a second end of the memory cell (M30_1); a first transistor pair (Wd3_1) comprising a pMOSFET (943) in parallel with an nMOSFET (947) and connected to the first conductive line (WL3_1); a second transistor pair (Bd0) comprising a pMOSFET (964) in parallel with an nMOSFET (960) and connected to the second conductive line (BL0); and a control circuit (510, 520, 560), wherein for selecting the memory cell (M30_1), the control circuit is configured to pull up a voltage of the first conductive line (WL3_1) via the pMOSFET (943) but not the nMOSFET (947) of the first transistor pair (Wd3_1) and to pull down a voltage of the second conductive line (BL0) via the nMOSFET (960) but not the pMOSFET (964) of the second transistor pair (Bd0), and wherein the control circuit for reading the memory cell (M30_1) is configured to detect a voltage of the first conductive line (WL3_1) a first time via the nMOSFET (947) but not via the pMOSFET (943) of the first transistor pair (Wd3_1). [16] Device according to claim 15, wherein: for the first detection (1103) of a voltage of the first conductive line (WL3_1), the control circuit is configured to pull down a voltage of the second conductive line (BL0). [17] Device according to claim 15, wherein: for reading the memory cell (M30_1), the control circuit is configured to detect (1107) the voltage of the first conductive line (WL3_1) a second time via the nMOSFET (947), but not the pMOSFET (943) of the first transistor pair (Wd3_1) and to perform a potentially destructive write operation of the memory cell (M30_1) after the first time and before the second time (1105). [18] Device according to claim 17, wherein: to perform (1105) the potentially destructive write operation of the memory cell (M30_1), the control circuit is configured to pull up a voltage of the first conductive line (WL3_1) via the pMOSFET (943), but not the nMOSFET (947) of the first transistor pair (Wd3_1). [19] Device according to claim 17, wherein: for reading the memory cell, the control circuit is arranged to determine whether the voltage of the first conductive line (WL3_1) increases by more than a specified amount due to the potentially destructive write operation.

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