Semiconductor device and manufacturing method for a semiconductor device

Abstract

Semiconductor device (100, 200, 300), comprising: - a drift layer (1) of a first conductivity type arranged in a semiconductor substrate (1c) having a first main plane (1a) and a second main plane (1b) opposite the first main plane (1a); - a first semiconductor layer (2, 22, 32) of a second conductivity type, which is arranged between the first main plane (1a) of the semiconductor substrate (1c) and the drift layer (1) and has a higher impurity concentration than an impurity concentration of the drift layer (1); - a first buffer layer (5) of a first conductivity type, which is arranged between the second main plane (1b) of the semiconductor substrate (1c) and the drift layer (1) and has hydrogen-induced donors with a higher impurity concentration than an impurity concentration of the drift layer (1); and - a second semiconductor layer (3, 23) of a first conductivity type or a second conductivity type, which is arranged between the second main plane (1b) of the semiconductor substrate (1c) and the first buffer layer (5) and has a higher impurity concentration than an impurity concentration of the drift layer (1), wherein: - the first buffer layer (5) has a complex defect (9, CiOi) of interstitial carbon and interstitial oxygen with a density that decreases from the side of the second main plane (1b) towards the side of the first main plane (1a), and - a density of the complex defect (9, CiOi) of interstitial carbon and interstitial oxygen in the first buffer layer (5) is greater than a density of a complex defect (9, CiCs) of interstitial carbon and lattice site carbon in the first buffer layer (5).

Description

BACKGROUND OF THE INVENTIONField of InterestThe present disclosure relates to a semiconductor device and a manufacturing method of a semiconductor device.BackgroundIn a semiconductor device such as a diode or an IGBT (Insulated Gate Bipolar Transistor), protons are injected into the back surface side of a loop-thinned semiconductor substrate to form a buffer layer with hydrogen-induced donors and prevent a depletion layer extending from the front surface side of the semiconductor substrate from reaching the back surface of the semiconductor substrate. The semiconductor substrate is irradiated with charged particles such as electrons, protons, or helium to form crystal defects as life-time killers (life-time killers) that reduce a recombination lifetime of a carrier in the semiconductor substrate and improve a switching characteristic.In the conventional manufacturing method for the semiconductor device, after the semiconductor substrate to form the crystal defects is irradiated with an electron beam from the front surface side, heat treatment is performed for a duration of one hour or more and ten hours or less at a temperature of 300° C. or higher and 500° C. or lower, and an amount of the crystal defects is adjusted. After protons are injected from the back surface of the loop-thinned semiconductor substrate, thereafter, heat treatment is performed for a duration of one hour or more and ten hours or less at a temperature of 350° C. or higher and 550° C. or lower, and the injected protons are converted into the donors, and the buffer layer is formed with the hydrogen-induced donors. In the conventional semiconductor device, the crystal defects formed by the irradiation with an electron beam are used as the lifetime killers and are used to improve a donor generation rate by the proton injection (see, for example, JP 2015-130 524 A).JP 2019-71 503 A discloses a semiconductor device capable of reducing leakage current and suppressing vibration at turn-off or recovery. The semiconductor device includes a first n-type buffer layer containing a proton distribution having a plurality of peak concentrations and in which the injection amount decreases as the depth increases from a back surface of a semiconductor substrate, and a second n-type buffer layer containing phosphorus. A position of a peak concentration of the phosphorus is a position lower than 1 μm and shallower than 6 μm from the back side of the semiconductor substrate. Three or more peak concentrations of the proton distribution are located at depths of 6 μm or more and 30 μm or less from the back surface of the semiconductor substrate.DE 11 2015 000 206 T5 describes a semiconductor device which has an n-conducting semiconductor substrate, a p-conducting anode region which is formed on the front side of the semiconductor substrate, an n-conducting field interruption region which is formed on the rear side of the semiconductor substrate with protons as donor, and an n-conducting cathode region which is formed closer to the rear side of the semiconductor substrate than the field interruption region, wherein a concentration distribution of the donor in the field interruption region has a first peak in the depth direction and a second peak which is closer to the rear side of the semiconductor substrate than the first peak and which has a lower concentration than the first peak, and wherein a charge carrier lifetime in at least a sub-region between the anode region and the cathode region is longer than a charge carrier lifetime in both the anode region and the cathode region.SummaryIn the conventional semiconductor device, however, the crystal defects to serve as the lifetime killers are also formed to improve the donor generation rate by the proton injection. Therefore, there is a problem that variation in electrical characteristics such as switching characteristics caused by a change in crystal defects due to heat generated in a situation where the semiconductor device is actually used is not considered at all.An object of the present disclosure made to solve the above-described problem is to provide a semiconductor device having stable electrical characteristics even when crystal defects to serve as lifetime killers are formed in a semiconductor substrate, and a manufacturing method for the semiconductor device.The object on which the invention is based is achieved in a semiconductor device according to the invention having the features of claim 1 and in a production method for a semiconductor device according to the invention having the features of claim 9. Advantageous refinements are the subject matter of the respective dependent claims.A semiconductor device according to the present invention includes: a drift layer of a first conductivity type disposed in a semiconductor substrate having a first principal plane and a second principal plane opposite to the first principal plane; a first semiconductor layer of a second conductivity type disposed between the first principal plane of the semiconductor substrate and the drift layer and having an impurity concentration higher than an impurity concentration of the drift layer; a first buffer layer of a first conductivity type disposed between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors having an impurity concentration higher than an impurity concentration of the drift layer; a second semiconductor layer of a first conductivity type or a second conductivity type disposed between the second principal plane of the semiconductor substrate and the first buffer layer and having an impurity concentration higher than an impurity concentration of the drift layer, wherein the first buffer layer has a complex defect of interstitial carbon and interstitial oxygen having a density decreasing from the second principal plane side toward the first principal plane side. Here, a density of the interstitial carbon-interstitial oxygen complex defect in the first buffer layer is greater than a density of an interstitial carbon-interstitial carbon complex defect in the first buffer layer.A manufacturing method for a semiconductor device according to the present disclosure includes: preparing a first conductivity type semiconductor substrate having a first principal plane and a second principal plane opposite to the first principal plane and having carbon and oxygen; forming a first second conductivity type semiconductor layer having an impurity concentration higher than an impurity concentration of the semiconductor substrate on the first principal plane side of the semiconductor substrate; after forming the first semiconductor layer, grinding the semiconductor substrate from the second principal plane side; after grinding the semiconductor substrate, forming a second first conductivity type semiconductor layer or a second conductivity type having an impurity concentration higher than an impurity concentration of the semiconductor substrate on the second principal plane side of the semiconductor substrate; after grinding the semiconductor substrate, injecting protons from the second principal plane side; a first heat treatment step to heat the semiconductor substrate at a first temperature, convert the protons injected into the semiconductor substrate into hydrogen-induced donors, and form a first buffer layer of a first conductivity type having an impurity concentration higher than the impurity concentration of the semiconductor substrate; after the first heat treatment step, a charged particle irradiation step to irradiate the semiconductor substrate with charged particles and form a interstitial carbon-interstitial oxygen complex defect and a lattice position carbon (lattice position carbon) complex defect; and after the charged particle irradiation step, a second heat treatment step for heating the semiconductor substrate at a second temperature lower than the first temperature and extinguishing the interstitial carbon-lattice carbon complex defect.According to the semiconductor device according to the present invention, it is possible to provide a semiconductor device having stable electrical characteristics even when crystal defects to serve as lifetime killers are formed in the semiconductor substrate.Further, according to the manufacturing method for a semiconductor device according to the present invention, it is possible to provide a manufacturing method for a semiconductor device that exhibits stable electrical characteristics even when crystal defects to serve as lifetime killers are formed in the semiconductor substrate.Other and further objects, features and advantages of the invention will become more fully apparent from the following description.Brief Description of the DrawingsFIG. 1 is a sectional view illustrating a semiconductor device in the first embodiment. FIG. 2 is a diagram illustrating distributions of impurity concentrations of the first buffer layers and second buffer layers of the semiconductor device in the first embodiment and semiconductor devices in comparative examples. FIG. 3 is a diagram illustrating an example of a spectral distribution of photoluminescence of the semiconductor device in the first embodiment. FIG. 4 is a diagram illustrating changes in crystal defect amounts with respect to depths from the second principal planes of the semiconductor device in the first embodiment and the semiconductor devices in the comparative examples. FIG. 5 is a diagram illustrating changes in crystal defect amounts with respect to depths from the second principal planes of the semiconductor device in the first embodiment and the semiconductor devices in the comparative examples. FIG. 6 is a diagram illustrating changes in crystal defect amounts with respect to depths from the second principal planes of the semiconductor device in the first embodiment and the semiconductor devices in the comparative examples. FIG. 7 is a diagram illustrating changes in crystal defect amounts with respect to depths from the second principal planes of the semiconductor device in the first embodiment and the semiconductor devices in the comparative examples. FIG. 8 is a flowchart illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 9 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 10 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 11 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 12 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 13 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 14 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 15 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 16 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 17 is a sectional view illustrating the manufacturing method of the semiconductor device in the first embodiment. FIG. 18 is a plan view illustrating the configuration of a semiconductor device in a second embodiment. FIG. 19 is a sectional view, taken along a dotted line A-A, of a semiconductor device 200 illustrated in FIG. 18. FIG. 20 is a sectional view, taken along a dotted line B-B, of a semiconductor device 200 illustrated in FIG. 18. FIG. 21 is a sectional view illustrating a semiconductor device in the third embodiment.DESCRIPTION OF EMBODIMENTSFirst EmbodimentFirst, the configuration of a semiconductor device in the first embodiment will be explained. FIG. 1 is a sectional view illustrating a semiconductor device in the first embodiment.In the following explanation, n and p denote conductivity types of semiconductors. In the present invention, a first conductivity type is an n-type and a second conductivity type is a p-type, and n - indicates that an impurity concentration is lower than the impurity concentration of n, and n + indicates that an impurity concentration is higher than the impurity concentration of n. Similarly, p - indicates that an impurity concentration is lower than the impurity concentration of p, and p + indicates that an impurity concentration is higher than the impurity concentration of p.In FIG. 1, a semiconductor device 100 is a diode, and is formed using, for example, an n -- type silicon semiconductor substrate grown according to an FZ (floating zone) method or an MCZ (Czochralski with applied magnetic field) method. The semiconductor device 100 comprises a first main plane 1 aof the semiconductor substrate and a second main plane 1 b, which is opposite to the first main plane 1 a. Semiconductor layers are formed by introducing n-type impurities or p-type impurities between the first principal plane 1 aand the second principal plane 1 bof the semiconductor substrate. The rest of the semiconductor substrate is an n -- type drift layer 1. The n -- type drift layer 1 is a semiconductor layer including, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity ranges from 1.0×10 12 / cm 3 to 1.0×10 15 / cm 3.A p-type anode layer 2 is disposed between the first principal plane 1 aof the semiconductor substrate and the n -- type drift layer 1. The p-type anode layer 2 is a semiconductor layer including boron or aluminum as a p-type impurity, for example. The concentration of the p-type impurity ranges from 1.0×10 12 / cm 3 to 1.0×10 10 / cm 3. The p-type anode layer 2 is a first semiconductor layer having a higher impurity concentration than the impurity concentration of the n -- type drift layer 1.An anode electrode 6, which is a first electrode, is disposed on the first principal plane 1 aof the semiconductor substrate. The anode electrode 6 is in contact with the p-type anode layer 2 and is electrically connected to the p-type anode layer 2. Note that although not illustrated in FIG. 1, a p +- type contact layer having a higher concentration of p-type impurities than the p-type anode layer 2 may be disposed between the p-type anode layer 2 and the first principal plane 1 ato electrically connect the p-type anode layer 2 and the anode electrode 6 via the p +- type contact layer.The anode electrode 6 may be formed of an aluminum alloy such as an aluminum-silicon (Al-Si) alloy. The anode electrode 6 may be an electrode formed of a plurality of metal films obtained by electroless plating or electrolytic plating on an electrode formed of the aluminum alloy. The plating film formed by the electroless plating or the electrolytic plating may be, for example, a nickel plating film or may be, for example, a copper plating film. A gold plating film may be further formed on the nickel plating film or the copper plating film to prevent oxidation of nickel or copper. A barrier metal formed by a conductor containing titanium may be disposed between the anode electrode 6 and the first principal plane 1 aof the semiconductor substrate. The anode electrode 6 containing the barrier metal may be referred to as the anode electrode 6.The semiconductor device 100 includes gates 11 of diode trenches on the first principal plane 1 aside of the semiconductor substrate. The gates 11 of diode trenches include electrodes 11 aof diode trenches arranged in trenches via oxide films 11 bdisposed on the inner walls of the trenches that pass through the p-type anode layer 2 from the first principal plane 1 aof the semiconductor substrate and reach the n -- type drift layer 1. The electrodes 11 aof diode trenches are in contact with the anode electrode 6 on the first principal plane 1 aside and are electrically connected to the anode electrode 6. By disposing the gates 11 of diode trenches in the semiconductor device 100 that is a diode, it is possible to improve a withstand voltage of the semiconductor device 100. Since the semiconductor device 100 functions as a diode even when the gates 11 of diode trenches are absent, the gates 11 of diode trenches do not necessarily need to be provided.An n +- type cathode layer 3, a second buffer layer 4, and a first buffer layer 5 are sequentially arranged from the second principal plane 1 bside between the second principal plane 1 bof the semiconductor substrate and the n -- type drift layer 1. The first buffer layer 5 is an n-type buffer layer having hydrogen-induced donors formed by proton injection, and has a higher concentration of n-type impurities than the concentration of n-type impurities of the n -- type drift layer 1. The second buffer layer 4 is an n-type buffer layer having phosphorus as an n-type impurity and has a higher concentration of n-type impurities than the concentration of n-type impurities of the first buffer layer 5. the n +- type cathode layer 3 is an n-type semiconductor layer having phosphorus or arsenic as an n-type impurity and is a second semiconductor layer having a concentration of n-type impurities that is higher than the concentration of n-type impurities of the n -- type drift layer 1 and higher than the concentration of n-type impurities of the first buffer layer 5 or the second buffer layer 4. Note that although not illustrated, a p-type impurity may be dispersedly introduced into the n +- type cathode layer 3, so that p-type semiconductor layers may be dispersedly introduced into the n +- type cathode layer 3.Note that, in FIG. 1, the semiconductor device 100 includes the second buffer layer 4 between the n +- type cathode layer 3 and the first buffer layer 5. However, the semiconductor device 100 does not necessarily have to include the second buffer layer 4. That is, the semiconductor device 100 only needs to include the first buffer layer 5 disposed between the second principal plane 1 bof the semiconductor substrate and the n -- type drift layer 1 and the n +- type cathode layer 3 disposed between the second principal plane 1 bof the semiconductor substrate and the first buffer layer 5, which is the second semiconductor layer.A cathode electrode 7, which is a second electrode, is disposed on the second principal plane 1 bof the semiconductor substrate. The cathode electrode 7 is in contact with the n +- type cathode layer 3 and is electrically connected to the n +- type cathode layer 3. The cathode electrode 7 may be formed by sputtering or vapor depositing a metal layer containing at least one of Al, Ti, Ni, Au, Ag and Cu on the n +- type cathode layer 3 which is the second semiconductor layer. As with the anode electrode 6, the cathode electrode 7 can be obtained by forming a nickel plating film or a copper plating film on a metal film formed by sputtering or vapor deposition by electroless plating or electrolytic plating. Further, the cathode electrode 7 can be formed by forming a gold plating film on the nickel plating film or the copper plating film.In the semiconductor device 100, crystal defects 9 to serve as lifetime killers are formed in the semiconductor substrate, which reduces the recombination lifetime of a carrier. In FIG. 1, the crystal defects 9 to serve as the lifetime killers are illustrated in the first buffer layer 5. However, the crystal defects 9 to serve as the lifetime killers may be formed in the n -- type drift layer 1 or may be formed in the second buffer layer 4 if the crystal defects 9 are formed at least in the first buffer layer 5.The crystal defects 9 to serve as the lifetime killers can be classified into a plurality of types according to structures. When the semiconductor device 100 is manufactured using a silicon semiconductor substrate, as the crystal defects 9 to serve as the lifetime killers, there are, for example, a void (V), interstitial silicon (ISi), interstitial carbon (Ci), lattice site carbon (Cs), a complex defect of a void (V2, V4, or V6), a complex defect of interstitial silicon (ISi3or ISi4), a complex defect of interstitial carbon and interstitial oxygen (CiOi), and a complex defect of interstitial carbon and lattice site carbon (CiCs). I or i denotes a state (interstitial) in which atoms of silicon (Si), carbon (C), oxygen (O) or the like are located between lattice sites of an Si crystal, and s denotes a state (substitution) in which Si atoms at lattice sites of the Si crystal are substituted by other atoms.The complex defect of interstitial carbon and interstitial oxygen (CiOi) is also referred to as the C center. Emitted light of 0.790 eV is obtained by photoluminescence. The complex defect of interstitial carbon and lattice site carbon (CiMn) is also referred to as the G center. Emitted light of 0.969 eV is obtained by photoluminescence. The complex defect of interstitial silicon (ISi3) is also referred to as the W center. Emitted light of 1.019 eV is obtained by photoluminescence. The complex defect of interstitial silicon (ISi4) is also referred to as the X center. Emitted light of 1.040 eV is obtained by photoluminescence. The emitted lights of the C center, the G center, the W center and the X center obtained by photoluminescence are referred to as a C line, a G line, a W line and an X line, respectively. In the following explanation, in some cases, the interstitial carbon-interstitial oxygen complex defect is referred to as CiOi, the interstitial carbon-interstitial carbon complex defect is referred to as CiSr, and the interstitial silicon complex defect is referred to as ISi3or ISi4.The semiconductor device 100 has the interstitial carbon-interstitial oxygen (CiOi) complex defect in the semiconductor substrate, and has the interstitial carbon-interstitial oxygen (CiOi) complex defect at least in the first buffer layer 5. A crystal defect gradually disappears as the temperature of the semiconductor substrate is increased. However, a temperature at which the CiOi disappears is relatively higher compared to the other crystal defects. For example, the Ci Disappears at approximately 300° C.; however, the CiOi disappears at approximately 400° C. In the semiconductor device 100, the density of the CiOi contained in the semiconductor substrate is greater than the density of the CiCs, and the density of the CiOi contained in at least the first buffer layer 5 is greater than the density of the CiCs.FIG. 2 is a diagram illustrating distributions of impurity concentrations of first buffer layers and second buffer layers of the semiconductor device in the first embodiment and semiconductor devices in comparative examples. In FIG. 2, an "example" indicated by a solid line is an impurity concentration distribution of the semiconductor device 100 in the first embodiment, and an "Comparative Example 1" indicated by a broken line and an "Comparative Example 2" indicated by a dotted line are distributions of impurity concentrations of the semiconductor devices in the Comparative Examples. An impurity concentration is measured by a spreading resistance (SR) method. In FIG. 2, the axis of abscissa indicates the depth from a second principal plane, and the axis of ordinate indicates an impurity concentration measured by the propagation resistance method.The semiconductor device in the "example" which is the semiconductor device 100 in the first embodiment and the semiconductor devices in the "comparative example 1" and the "comparative example 2" are each manufactured by different manufacturing methods. In the "Example", the "Comparative Example 1" and the "Comparative Example 2", processes for forming the crystal defects 9 to serve as the lifetime killers are different from each other. The semiconductor device in the "example" which is the semiconductor device 100 in the first embodiment is manufactured by performing, after injecting protons from the second principal plane 1 bside of the semiconductor substrate from a heat treatment at 400° C. which is a first temperature for two hours, and thereafter, after irradiating the semiconductor substrate with an electron beam, a heat treatment at 345° C. which is a second temperature for 0.5 hours. The semiconductor device in "Comparative Example 1" is manufactured by injecting protons from the second principal plane 1 bside of the semiconductor substrate after irradiating the semiconductor substrate with an electron beam, and thereafter heating the semiconductor substrate at 400° C. for two hours. The semiconductor device in "Comparative Example 2" is manufactured by heating at 400° C. for two hours after injecting protons from the second principal plane 1 bside of the semiconductor substrate from the semiconductor substrate. In the semiconductor device in "Comparative Example 2", irradiation with an electron beam is not performed. Note that details of the manufacturing method of the semiconductor device 100 in the first embodiment will be explained below.As illustrated in FIG. 2, the semiconductor device 100 includes the second buffer layer 4 that has a concentration peak at 0.5 μm from the second principal plane 1 bof the semiconductor substrate and is present to the depth of 2 μm from the second principal plane 1 b, and the first buffer layer 5 that spreads further to the first principal plane 1 aside than the second buffer layer 4 and is present to the depth of approximately 34 μm from the second principal plane 1 b. A layer further on the first principal plane 1 aside than the first buffer layer 5 is the n -- type drift layer 1. The second buffer layer 4 is a buffer layer including phosphorus. The first buffer layer 5 is a buffer layer including hydrogen-induced donors. As with the semiconductor device 100 in the example, the semiconductor devices in Comparative Example 1 and Comparative Example 2 include the second buffer layer 4 and the first buffer layer 5, and have similar distributions of impurity concentrations.As illustrated in FIG. 2, the first buffer layer 5 has four concentration peaks 5 a, 5 b, 5 c, and 5 d. However, the first buffer layer 5 may have four or more, or four or less concentration peaks. The first buffer layer 5 only needs to have at least one concentration peak with hydrogen-induced donors. Depths from the second principal plane 1 bwhere the concentration peaks of the first buffer layer 5 illustrated in FIG. 2 are positioned are 28.0 μm for the concentration peak 5 a, 20.0 μm for the concentration peak 5 b, 10.5 μm for the concentration peak 5 c, and 3.5 μm for the concentration peak 5 d. A maximum impurity concentration of the first buffer layer 5 is less than 1.0×10 15 / cm 3. For example, at the concentration peak 5 d, a maximum impurity concentration of the first buffer layer 5 of the semiconductor device 100 in the example illustrated in FIG. 2 is 7.0×10 14 / cm 3.Next, the crystal defects 9 contained in the semiconductor substrate of the semiconductor device 100 to serve as the lifetime killers will be explained. As explained above, there are several kinds of crystal defects to serve as the lifetime killers. The crystal defects present in the semiconductor substrate of the semiconductor device 100 may be evaluated by, for example, irradiating the semiconductor substrate with a laser beam and measuring photoluminescence from the semiconductor substrate.FIG. 3 is a diagram illustrating an example of a spectral distribution of photoluminescence of the semiconductor device in the first embodiment. In FIG. 3, the axis of abscissa indicates the photon energy of photoluminescence and the axis of ordinate indicates the intensity of photoluminescence. The photon energy is converted from the relationship E=h·v=h·c / λ. E is the photon energy, h is the Planck constant, v is a frequency, c is the speed of light, and λ is a wavelength. The photoluminescence illustrated in FIG. 3 is obtained by cooling the semiconductor device 100 to a temperature of 30 K, irradiating the cross section of the semiconductor device 100 with a He-Ne laser beam having a wavelength of 633 nm, and detecting emitted light from the cross section of the semiconductor device 100 with a spectrometer. A beam diameter of the irradiated He-Ne laser beam is 1.3 μm. The irradiation energy to the cross section of the semiconductor device 100 is 4.5 mW. FIG. 3 is a spectral distribution of photoluminescence at a position 4 μm from the second principal plane 1 bof the semiconductor device 100.As illustrated in FIG. 3, in the spectral distribution of photoluminescence of the semiconductor device 100, a C line due to CiOi, a G line due to CiCs, a W line due to ISi3, and an X line due to ISi4are seen. A spectrum denoted by band end in FIG. 3 is light emitted at the band end from silicon.FIGS. 4 to 7 are diagrams illustrating changes in crystal defect amounts with respect to depths from the second principal planes of the semiconductor device in the first embodiment and the semiconductor devices in the comparative examples. The "Example", the "Comparative Example 1" and the "Comparative Example 2" illustrated in FIGS. 4 to 7 respectively correspond to those illustrated about the distributions of impurity concentrations in FIG. 2. In FIGS. 4 to 7, the axis of abscissa indicates a depth from the second principal plane 1 band indicates that the positions of the depths are irradiated with a He-Ne laser beam having a beam diameter of 1.3 μm. In FIGS. 4 to 7, on the axis of ordinates, photoluminescence intensities due to crystal defects from the cross section of the semiconductor device 100 are normalized such that the intensities of band-end emitted lights of silicon at the depths are 1. In FIGS. 4 to 7, a measurement result of the semiconductor device in "Example" is indicated by solid circles, a measurement result of the semiconductor device in Comparative Example 1 is indicated by open triangles, and a measurement result of the semiconductor device in Comparative Example 2 is indicated by open squares.In the spectrum of photoluminescence illustrated in FIG. 3, the intensity of photoluminescence on the axis of ordinates changes according to a factor different from the crystal defect amount as the depth changes from the second principal plane. However, the band-end emitted light of silicon indicated by the band end in FIG. 3 should not change according to the depth from the second principal plane, unlike the crystal defects. Therefore, by normalizing the intensities of the light of silicon emitted at the band end to be fixed among a plurality of measurement data in which the depths are different from the second principal plane, it is possible to exclude variation factors other than the crystal defect amount from the intensity changes of photoluminescence due to the crystal defects. It is possible to measure a crystal defect amount corresponding to the depth from the second principal plane.Note that the magnitude of intensity / BE intensity indicated on the ordinate axes in FIGS. 4 to 7 can be evaluated as indicating the crystal defect amount at the same photon energy relatively. However, the magnitude of intensity / BE intensity cannot be compared between different photon energies in, for example, the C-line and the X-line to judge whether the crystal defect amount is large or small.As illustrated in FIG. 4, in the semiconductor device in the "example" that is the semiconductor device 100 in the first embodiment 1, the C line that is photoluminescence of the CiOi appears at all measurement depths from a filled circle 9 aat 1 μm, which is a measurement depth closest to the second principal plane 1 b, to a filled circle 9 dat 40 μm, which is a measurement depth furthest from the second principal plane 1 b. On the other hand, in the semiconductor device in "Comparative Example 1" and the semiconductor device in "Comparative Example 2", the C-line does not appear to be significant magnitude. That is, the semiconductor device in "Comparative Example 1" and the semiconductor device in "Comparative Example 2" do not contain the CiOi in significant density in the first buffer layer 5.As illustrated in FIG. 2, in the "example", the first buffer layer 5 of the semiconductor device 100 is formed from the second principal plane 1 bto a depth of approximately 34 μm, and a layer on the first principal plane 1 aside from the second principal plane 1 bis wider than the depth 34 μm of the n -- type drift layer 1. As illustrated in FIG. 4, as shown by the fact that the C line is also observed at the position of a depth of 40 μm from the second principal plane 1 b, the semiconductor device 100 in the "example" includes the CiOi as the crystal defects 9 to be used as the lifetime killers in the first buffer layer 5, and also has the CiOi in the second buffer layer 4 and the n -- type drift layer 1. As illustrated in FIG. 2, since the depth from the second principal plane 1 bof the concentration peak 5 a, which is closest to the first principal plane 1 abetween the plurality of concentration peaks of the first buffer layer 5, is 28.0 μm, the CiOi is present on the first principal plane 1 aside further than the concentration peak 5 a, which is closest to the first principal plane 1 abetween the concentration peaks of the first buffer layer 5.The semiconductor device 100 in the "example" has, in the first buffer layer 5, the CiOi illustrated at observation points of a filled circle 9 bto the filled circle 9 cillustrated in FIG. 4. The density of CiOi in the first buffer layer 5 decreases from the second principal plane 1 bside toward the first principal plane 1 aside. The density of the CiOi of the first buffer layer 5 of the semiconductor device 100 decreases as the depth increases from the second principal plane 1 b. However, a rate of decrease in the density of the CiOi at a low depth position from the second principal plane 1 bis small, and increases as the depth from the second principal plane 1 bincreases.The semiconductor device 100 in the "example" further also includes the CiOi illustrated at an observation point of the filled circle 9 ain FIG. 4 in the second buffer layer 4 existing to the depth of 2 μm from the second principal plane 1 b. The magnitude on the axis of abscissa of the filled circle 9 aillustrated in FIG. 4 is smaller than the magnitude on the axis of ordinate of the filled circle 9 b. That is, in the semiconductor device 100 in the "example", the density of the CiOi of the second buffer layer 4 is lower than the maximum density of the CiOi of the first buffer layer 5.As illustrated in FIG. 5, observation values of the G lines of the semiconductor device in the "example" which is the semiconductor device 100 in the first embodiment, the semiconductor device in the "comparative example 1" and the semiconductor device in the "comparative example 2" indicate values of 0.3 to 0.4 regardless of the distance from the second principal plane 1 b. However, as can be seen from the spectral distribution of photoluminescence illustrated in FIG. 3, emitted light having a wide spectral distribution is observed near the G line, and the G line is superimposed on the wide emitted light and is weakly observed. That is, although the observation values of 0.3 to 0.4 are obtained in FIG. 5, most observation values are observation values by the wide emitted light. A contribution of the G line in FIG. 5 is extremely small. The G-line of significant magnitude is not observed. Therefore, the first buffer layer 5 of the semiconductor device 100 in the "example" does not include the CiCs having significant density. Similarly, the first buffer layer of the semiconductor device in "Comparative Example 1" and the first buffer layer of the semiconductor device in "Comparative Example 2" do not contain the CiCs having significant density. From the measurement results illustrated in FIGS. 4 and 5, it can be seen that the density of the CiOi of the first buffer layer 5 of the semiconductor device 100 in the "example" is greater than the density of the CiCs present in the first buffer layer 5.As illustrated in FIG. 6, in the depth of 2 μm to 34 μm from the second principal plane on which the first buffer layer is present, the magnitude of the W line is the largest in the semiconductor device 100 in the "example", the second largest in the semiconductor device in the "comparative example 2", and the smallest in the semiconductor device in the "comparative example 1". In all the semiconductor devices, the W line is not observed to a significant extent at a position where the depth from the second principal plane on which the n -- type drift layer is present is greater than 34 μm. That is, in all the semiconductor devices, the ISi3is not present in a significant density in the n -- drift layer.As illustrated in FIG. 6, the semiconductor device 100 in the "example" includes the ISi 3 in the first buffer layer 5 and the second buffer layer 4. The density of the ISi 3 of the first buffer layer 5 of the semiconductor device 100 decreases as the depth increases from the second principal plane 1 b. However, a rate of decrease in density of the ISi 3 is large at a low depth position from the second principal plane 1 band decreases as the depth increases from the second principal plane 1 b. This tendency of change in defect density is different from the tendency of CiOi illustrated in FIG. 4. That is, the first buffer layer 5 of the semiconductor device 100 has a region in which the rate of decrease in density of the CiOi increases and the rate of decrease in density of the ISi 3 decreases from the second principal plane 1 bside toward the first principal plane 1 aside.As illustrated in FIG. 7, in the depth of 2 μm to 34 μm from the second principal plane on which the first buffer layer is present, the magnitude of the X line is the largest in the semiconductor device in the "Comparative Example 1", the second largest in the semiconductor device 100 in the "Example", and the smallest in the semiconductor device in the "Comparative Example 2". In all the semiconductor devices, observation values on the axis of ordinates are extremely small at positions lower than 34 μm from the second principal plane on which the n -- type drift layer is present. In all the semiconductor devices, the density of the ISi4of the n -- type drift layer is 1 / 10 to 2 / 10 or less of the maximum density in the first buffer layer 5 or the second buffer layer 4.As illustrated in FIG. 7, the semiconductor device 100 in the "example" includes the ISi 4 in the first buffer layer 5 and the second buffer layer 4. As in the ISi 3 illustrated in FIG. 6, the density of the ISi 4 of the first buffer layer 5 of the semiconductor device 100 decreases as the depth increases from the second principal plane 1 b. However, a rate of decrease in density of the ISi 4 at a low depth position from the second principal plane 1 bis large and decreases as the depth increases from the second principal plane 1 b. This tendency of change in defect density is different from the tendency of CiOi illustrated in FIG. 4. That is, the first buffer layer 5 of the semiconductor device 100 has a region in which the rate of decrease in density of the CiOi increases and the rate of decrease in density of the ISi 4 decreases from the second principal plane 1 bside toward the first principal plane 1 aside.The semiconductor device 100 in the first embodiment is configured as explained above.Next, a manufacturing method of a semiconductor device in the first embodiment will be explained. FIG. 8 is a flowchart illustrating the manufacturing method of the semiconductor device in the first embodiment. FIGS. 9 to 17 are sectional views illustrating the manufacturing method of the semiconductor device in the first embodiment. In FIGS. 9 to 17, states in the middle of a manufacturing process of the semiconductor device 100 are illustrated.First, in a process for preparing a semiconductor substrate in step S 01 in FIG. 8, as illustrated in FIG. 9, a semiconductor substrate 1 cincluding the first principal plane 1 aand the second principal plane 1 bopposing the first principal plane 1 ais prepared. The semiconductor substrate 1 cis a semiconductor substrate containing carbon and oxygen as impurities, and may be, for example, a semiconductor substrate made of silicon grown by the FZ method or the MCZ method. In the semiconductor substrate of silicon grown by the FZ method or the MCZ method, oxygen and carbon are contained as impurities due to a growth process of the main part. The semiconductor substrate made of silicon grown by the FZ method or the MCZ method has an oxygen concentration of 1.0×10 15 to 2.0×10 18 / cm 3 and has a carbon concentration of 3.0×10 13 to 2.0×10 15 / cm 3. The semiconductor substrate of silicon grown by the MCZ method has a higher oxygen concentration than the oxygen concentration of the semiconductor substrate of silicon grown by the FZ method. When the semiconductor substrate 1 cis not the semiconductor substrate made of silicon grown by the FZ method or the MCZ method but is a semiconductor substrate in which a concentration of carbon or oxygen contained as a impurity is low, the semiconductor substrate 1 cmay be a semiconductor substrate in which, after carbon or oxygen is injected into the semiconductor substrate, heat is diffused in the semiconductor substrate. Oxygen may be introduced into the semiconductor substrate from the atmosphere or the oxidizing atmosphere through a heat treatment such as an oxide film forming process and an annealing process in the manufacturing process for the semiconductor device.Subsequently, in a front surface pattern forming step in step S 02 in FIG. 8, the p-type anode layer 2, which is the first semiconductor layer, is formed on the first principal plane 1 aside of the semiconductor substrate 1 c. When the semiconductor device 100 includes the gates 11 of diode trenches, the gates 11 of diode trenches are formed on the first principal plane 1 aside of the semiconductor substrate 1 c. A sectional view in a state in which the p-type anode layer 2, which is the first semiconductor layer, and the gates 11 of diode trenches are formed on the first principal plane 1 aside of the semiconductor substrate 1 cis illustrated in FIG. 10.First, after a p-type impurity such as boron (B) is injected from the first principal plane 1 aside of the semiconductor substrate 1 c, the semiconductor substrate 1 cis heated at a temperature equal to 1000° C. or higher for one to eight hours to diffuse impurity ions and form the p-type anode layer 2. Subsequently, as illustrated in FIG. 10, after trenches which pass through the p-type anode layer 2 from the first principal plane 1 aside of the semiconductor substrate 1 cand reach the n -- type drift layer 1 are formed, the semiconductor substrate 1 cis heated in an oxygen-containing atmosphere to form the oxide film 11 bon the inner walls of the trenches. Thereafter, polysilicon doped with an n-type or p-type impurity is deposited in the trenches on the inner walls of which the oxide film 11b is formed by CVD (chemical vapor deposition) or the like to form the electrodes 11a of diode trenches. The gates 11 of diode trenches are formed.Subsequently, as illustrated in FIG. 11, the anode electrode 6, which is the first electrode, is formed on the first principal plane 1 aof the semiconductor substrate 1 c. The anode electrode 6 is formed by forming aluminum (Al) on the first principal plane 1 aof the semiconductor substrate 1 cby sputtering or vapor deposition, and thereafter performing sintering treatment to heat the semiconductor substrate 1 c. The anode electrode 6 is formed in contact with the p-type anode layer 2. Further, to form the anode electrode 6, after the aluminum is formed by sputtering or vapor deposition, a nickel plating film or a copper plating film may be formed on an aluminum film by electroless plating or electrolytic plating. Note that the anode electrode 6 does not always need to be formed before a back surface grinding step for the semiconductor substrate 1 c, which is explained below, and may be formed after the process explained below. That is, a process for forming the anode electrode 6 may not necessarily be included in the front surface structure forming process in step S 02 in FIG. 8.Subsequently, in a back surface grinding step in step S 03 in FIG. 8, the second principal plane 1 bof the semiconductor substrate 1 cis ground to thin the semiconductor substrate 1 cto a predetermined thickness, as illustrated in FIG. 12. The thickness of the semiconductor substrate 1 cafter grinding may be, for example, 80 μm to 200 μm. Strictly speaking, after the back surface grinding step, the second principal plane 1 bof the semiconductor substrate 1 cis no longer present before the back surface grinding step. In the present disclosure, a surface opposite to the first principal plane 1 aof the semiconductor substrate 1 cis defined as the second principal plane 1 b. That is, the second principal plane 1 bis present closer to the first principal plane 1 awhen the semiconductor substrate 1 cis further thinned by the back surface grinding.Subsequently, in a proton injection step in step S 04 in FIG. 8, as illustrated in FIG. 13, protons 10 are injected into the semiconductor substrate 1 cfrom the second principal plane 1 bside of the semiconductor substrate 1 c. The protons 10 are injected into a region 51 in which the first buffer layer 5 is formed. A depth from the second principal plane 1 bto which the protons 10 are injected can be adjusted by changing the injection energy for the protons 10. In the semiconductor device 100 in the "example", the semiconductor device in the "comparative example 1" and the semiconductor device in the "comparative example 2" illustrated in FIG. 2, acceleration energies and injection amounts of the protons 10 are set to 400 keV and 3.0×10 13 / cm 2, 800 keV and 1.5×10 13 / cm 2, 1200 keV and 8.0×10 12 / cm 2 and 1500 keV and 4.0×10 12 / cm 2 respectively, and the first buffer layer 5 is formed by proton injection four times.Note that in the semiconductor device in the "Comparative Example 1" illustrated in FIG. 2, irradiation with an electron beam having an acceleration energy of 750 keV is performed as irradiation with charged particles from the first principal plane 1 aside of the semiconductor substrate before proton injection. In the semiconductor device 100 in the "example" and the semiconductor device in the "comparative example 2", irradiation with an electron beam is not performed before proton injection. However, in the semiconductor device 100 in the first embodiment, the irradiation with charged particles may be performed before the proton injection.Subsequently, in a first heat treatment step in step S 05 in FIG. 8, the protons 10 injected into the semiconductor substrate 1 care converted into donors, and the first n-type buffer layer 5 containing hydrogen-induced donors is formed as illustrated in FIG. 14. Note that, in FIG. 14, illustration of the protons 10 converted into the donors is omitted. In the first heat treatment step, the semiconductor substrate 1 cis heated for a period of 0.5 hours or more and 4 hours or less at a first temperature of 380° C. or higher and 525° C. or lower. The first temperature lower than 380° C. is undesirable because the conversion of the injected protons 10 into donors is insufficient. The first temperature higher than 525° C. is undesirable because a defect occurs in the semiconductor substrate 1 cduring heating. In the first heat treatment step, heating may be performed in a nitrogen atmosphere. In the semiconductor device 100 in the "example", the semiconductor device in the "comparative example 1" and the semiconductor device in the "comparative example 2" illustrated in FIG. 2, the first temperature is set to 400° C., and the heating is performed for two hours in the nitrogen atmosphere to convert the protons into donors.Thereafter, in a back surface pattern forming step in step S 06 in FIG. 8, phosphorus is injected from the second principal plane 1 bside of the semiconductor substrate 1 cto form the second buffer layer 4, and is further injected from the second principal plane 1 bside of the semiconductor substrate 1 cmade of arsenic or phosphorus to form the n +- type cathode layer 3 as illustrated in FIG. 15. In the second buffer layer 4, for example, phosphorus having an acceleration energy of 990 keV and an injection amount of 2.0×10 13 / cm 2 may be injected. In the n +- type cathode layer 3, phosphorus can be injected with an acceleration energy of 50 keV and an injection amount of 2.0×10 15 / cm 2. Thereafter, laser annealing to irradiate the second principal plane 1 bof the second semiconductor substrate 1 cwith a laser beam is performed to activate the phosphorus injected into the second buffer layer 4 and the arsenic or phosphorus injected into the n +- type cathode layer 3. Note that, in laser annealing, the semiconductor substrate 1 cis set in the air and the second principal plane 1 bis irradiated with the laser beam. At this time, nitrogen may be blown against the principal plane 1 birradiated with the laser beam to adjust an amount of oxygen incorporated into the semiconductor substrate 1 c.Note that the back surface structure forming step in step S 06 needs to be performed only before a charged particle irradiation step in step S 07, and may be performed between the proton irradiation step in step S 04 and the first heat treatment step in step S 05 or between the back surface grinding step in step S 03 and the proton injection step in step S 04. By performing the formation of the back surface structure in step S 06 before the charged particle irradiation step in step S 07, it is possible to also leave the CiOi formed in the charged particle irradiation step in step S 07 in the second buffer layer 4 formed in the back surface structure forming step in step S 06.Subsequently, in the charged particle irradiation step in step S 07 in FIG. 8, the semiconductor substrate 1 cis irradiated from the first principal plane 1 aside of the semiconductor substrate 1 cor the second principal plane 1 bside of the semiconductor substrate 1 cto form the crystal defects 9 to serve as lifetime killers in the semiconductor substrate 1 c, as illustrated in FIG. 16. At this time, the crystal defects 9 to serve as the lifetime killers are formed in the first buffer layer 5, the second buffer layer 4, and the n -- type drift layer 1. The irradiated charged particles may be electrons or protons.When the charged particles are protons, the protons can be irradiated using an irradiation device with which a high acceleration energy is obtained, such as a cyclotron, with an acceleration energy of 5 to 10 MeV. An aluminum absorber may be disposed on the first principal plane 1 aside or the second principal plane 1 bside of the semiconductor substrate 1 cto decelerate protons accelerated by the irradiation device and irradiate the semiconductor substrate 1 cwith the protons. By irradiating the protons with a high acceleration energy of 5 to 10 MeV, it is possible to widely distribute crystal defects formed in the semiconductor substrate 1 c. By retarding the protons with the aluminum absorber and injecting the protons, it is possible to control a peak depth of crystal defects formed in the semiconductor substrate 1 c.When the charged particles are electrons, since a range of the electrons is long, it is possible to form crystal defects in a region extending from the first principal plane 1 ato the second principal plane 1 bof the semiconductor substrate 1 cin spite of whether the semiconductor substrate 1 cis irradiated with an electron beam from the first principal plane 1 aside of the semiconductor substrate 1 cor is irradiated with the electron beam from the second principal plane 1 bside of the semiconductor substrate 1 c. The acceleration energy of the irradiated electrons can be, for example, 500 keV to 1000 keV. In the semiconductor device 100 in the "example" illustrated in FIG. 2, in the charged particle irradiation step in step S 07, after the first heat treatment step, irradiation with an electron beam from the first principal plane 1 aside of the semiconductor substrate 1 cis performed as charged particle irradiation with the acceleration energy of 750 keV. In the semiconductor devices in the "Comparative Example 1" and the "Comparative Example 2", irradiation with an electron beam is not performed after the first heat treatment step in step S 05.Subsequently, in a second heat treatment step in step S 08 in FIG. 8, among the crystal defects formed in the semiconductor substrate 1 cin the charged particle irradiation step in step S 07, crystal defects disappearing at a temperature lower than the second temperature are extinguished, and crystal defects not disappearing at the second temperature are left. The crystal defects that disappear at the temperature lower than the second temperature are, for example, CiCs, and the crystal defects that do not disappear at the second temperature are, for example, CiOi. The protons injected into the semiconductor substrate 1 cin the proton injection step in step S 04 are activated at 360° C. or more and converted into the hydrogen-induced donors. However, the second temperature is desirably a temperature lower than 360° C. which does not contribute to the activation of the protons. In the second heat treatment step, the semiconductor substrate 1 cis heated for a period of ten minutes or more and two hours or less at the second temperature of 250° C. or higher and 350° C. or lower. In the semiconductor device 100 in the "example" illustrated in FIG. 2, the second temperature is set to 345° C., and the CiCs is heated and extinguished in the nitrogen atmosphere for thirty minutes.As explained above, the Ci Disappears at approximately 300° C.; however, the CiOi disappears at approximately 400° C. Therefore, the CiCs can be quenched at a higher rate than the CiOi by setting the second temperature at 250° C. or higher and 350° C. or lower in the second heat treatment step in step S 08.Subsequently, the cathode electrode 7, which is the second electrode, is formed on the second principal plane 1 bof the semiconductor substrate 1 cas illustrated in FIG. 17. The semiconductor device 100 is completed by dicing the semiconductor substrate 1 cin a predetermined size.The cathode electrode 7, which is the second electrode, is formed via a film forming step to form a metal film containing Al, Ti, Ni, Au, Ag and / or Cu on the n +- type cathode layer 3 formed on the second principal plane 1 bside of the semiconductor substrate 1 c, which is the second semiconductor layer, with sputtering or vapor deposition, and a sintering treatment step to thereafter heat the metal film and perform a sintering treatment. The temperature for heating in the sintering treatment step may be equal to the second temperature in the second heat treatment step, and may be 250° C. or higher and 350° C. or lower, for example. Therefore, the second heat treatment step in step S 08 may be performed after the film forming step for forming the cathode electrode 7. The second heat treatment step may also be performed as the sintering treatment step. Since the second heat treatment step is also performed as the sintering treatment step, it is possible to simplify the manufacturing process for the semiconductor device 100 and reduce the cost of the semiconductor device 100.Note that the film forming step and the sintering treatment step for forming the cathode electrode 7, which is the second electrode, may be performed before the charged particle irradiation step in step S 07. In this case, the heating temperature in the sintering treatment step may be set higher than the second temperature in the second heat treatment step. The heating temperature in the sintering treatment step may be a temperature lower than the first temperature in the first heat treatment step and higher than the second temperature in the second heat treatment step. On the other hand, when the sintering treatment step is performed after the second heat treatment step in step S 08, the heating temperature in the sintering treatment step is desirably a temperature lower than the second temperature in the second heat treatment step. By setting the heating temperature lower than the second temperature in the sintering treatment step performed after the second heat treatment step, it is possible to prevent the CiOi left in the second heat treatment step from disappearing in the sintering treatment step.The semiconductor device 100 in the first embodiment is manufactured by the processes explained above.As explained above, the semiconductor device 100 in the first embodiment has more CiOi than the crystal defects 9 to serve as the lifetime killers in the semiconductor substrate compared with the CiCs. The semiconductor device 100 has more CiOi in the n -- type drift layer 1 compared to the CiCs, and also has more CiOi in the first buffer layer 5 and the second buffer layer 4 compared to the CiCs.Since the semiconductor device 100 is formed of silicon using the semiconductor substrate, a maximum temperature during an operation in actual use is approximately 175° C. The crystal defects formed in the semiconductor substrate as the lifetime killer gradually disappear when the semiconductor device 100 is continuously used in actual use for a long time even at a temperature of 175° C. low for recovery of the crystal defects. Electrical characteristics such as the switching speed fluctuate. That is, in the manufacturing method for the semiconductor device 100 illustrated in FIG. 8, when the second heat treatment step is not performed in step S 08, the CiOi and the CiCs remain in the semiconductor substrate as the crystal defects 9 to serve as the lifetime killers. However, both the CiOi and the CiCs disappear when the semiconductor device 100 is continuously used at 175° C. for a long time. Therefore, the variation of the electrical characteristics increases, making it difficult to guarantee long-term quality. In particular, since CiCs disappears at a temperature lower than the CiOi, a rate of disappearance of the CiCs is greater than a rate of the CiOi in a long-term use. It is difficult to guarantee long-term quality when the CiCs remains.On the other hand, in the semiconductor device 100 in the first embodiment, in the second heat treatment step in step S 08 in FIG. 8, the CiCs more than the CiOi is canceled. Therefore, as illustrated in FIGS. 4 and 5, the semiconductor device 100 has more CiOi than the CiCs in the first buffer layer 5, the second buffer layer 4, and the n -- type drift layer 1. In the semiconductor device 100 in the first embodiment in which the remaining amount of the CiNb is small and more CiOi remains, even if the semiconductor device 100 is continuously used at 175° C. for a long time, variation in electrical characteristics such as the switching speed is small, since the temperature at which the CiOi disappears according to the recovery of the crystal defects is higher than the temperature for the CiNb. It is possible to stabilize the electrical characteristics, and it is easy to guarantee long-term quality.Second EmbodimentFIG. 18 is a plan view illustrating the configuration of a semiconductor device in a second embodiment. FIGS. 19 and 20 are sectional views illustrating the configuration of the semiconductor device in the second embodiment. FIG. 19 is a sectional view taken along a dotted line A-A of a semiconductor device 200 illustrated in FIG. 18. FIG. 20 is a sectional view taken along a dotted line B-B of the semiconductor device 200 illustrated in FIG. 18. In FIG. 18, components denoted by the same reference numerals and characters as the reference numerals and characters in FIG. 1 are the same or corresponding components. Explanation of the components will be omitted. The semiconductor device 200 in the second embodiment is an IGBT (Insulated Gate Bipolar Transistor).As illustrated in FIG. 18, in the semiconductor device 200, active trench gates 12 and dummy trench gates 13 are arranged in a stripe shape. The gates 12 of active trenches are formed by disposing electrodes 12 aof gate trenches in trenches formed in a semiconductor substrate via insulating films 12 bof gate trenches. The gates 13 of dummy trenches are formed by disposing electrodes 13 aof dummy trenches in trenches formed in the semiconductor substrate via insulating films 13 bof dummy trenches. The electrodes 12 aof gate trenches of the gates 12 of active trenches are electrically connected to gate pads (not illustrated). The electrodes 13 aof dummy trenches of the gates 13 of dummy trenches are electrically connected to an emitter electrode 26 which is a first electrode and is disposed on a first main plane 1 aof the semiconductor device 200.On the both sides in the width direction of the gate active trenches 12, n +- type source layers 25 are disposed in contact with the gate trench insulating films 12 b. The n +- type source layers 25 are semiconductor layers including, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is 1.0×10 17 / cm 3 to 1.0×10 20 / cm 3. The n +- type source layers 25 are alternately arranged with p +- type contact layers 32 along a direction of extension of the active trench gates 12. The p +- type contact layer 32 is also disposed between adjacent two gates 13 of dummy trenches. Furthermore, the contact layers 32 of the p +- type are semiconductor layers which comprise boron or aluminum, for example, as a p-type impurity. The concentration of the p-type impurity is 1.0×10 15 / cm 3 to 1.0×10 20 / cm 3.As illustrated in FIG. 18, the semiconductor device 200 has a configuration in which three active trench gates 12 are arranged, three dummy trench gates 13 are arranged next to the three active trench gates 12, and three active trench gates 12 are arranged next to the three dummy trench gates 13. The semiconductor device 200 has a configuration in which sets of the active trench gates 12 and sets of the dummy trench gates 13 are alternately arranged. In FIG. 18, the number of active trench gates 12 included in a set of the active trench gates 12 is three, but need only be one or more. The number of dummy trench gates 13 included in a set of dummy trench gates 13 may be one or more. The number of dummy trench gates 13 may be zero. That is, all the trenches disposed in the semiconductor device 200 may be the active trench gates 12.FIG. 19 is a sectional view of the semiconductor device 200 taken along a dotted line A-A in FIG. 18. As illustrated in FIG. 19, in the semiconductor device 200, an n-type carrier storage layer 15 having a higher concentration of the n-type impurity than the n -- type drift layer 1 is disposed on the first principal plane 1 aside of the n -- type drift layer 1. The n-type carrier storage layer 15 is a semiconductor layer including, for example, arsenic or phosphorus as the n-type impurity. The concentration of the n-type impurity is 1.0×10 13 / cm 3 to 1.0×10 17 / cm 3. Note that the semiconductor device 200 may have a configuration in which the n-type carrier storage layer 15 is not provided and the n -- type drift layer 1 is also disposed in a region of the n-type carrier storage layer 15 illustrated in FIG. 19. By providing the n-type carrier storage layer 15, it is possible to reduce an excitation loss at the time when an electric current flows to the semiconductor device 200. The n-type carrier storage layer 15 and the n -- type drift layer 1 may be collectively referred to as a drift layer.A p-type base layer 22 is disposed as a first semiconductor layer on the first principal plane 1 aside of the n-type carrier storage layer 15. The p-type base layer 22 is a semiconductor layer including, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is 1.0×10 12 / cm 3 to 1.0×10 10 / cm 3. The p-type base layer 22 is in contact with the gate trench insulating films 12 bof the active trench gates 12. On the first principal plane 1 aside of the p-type base layer 22, n +- type source layers 25 are disposed in contact with the gate trench insulating films 12 bof the active trench gates 12. The p +- type contact layers 32 are disposed in the remaining region. The n +- type source layers and the p +- type contact layers 32 form the first principal plane 1 aof the semiconductor substrate. Note that the p +- type contact layers 32 are regions in which the concentration of the p-type impurity is higher than that in the p-type base layer 22. When it is necessary to distinguish between the p +- type contact layers 32 and the p type base layer 22, the p +- type contact layers 32 and the p type base layer 22 may be individually referred to, respectively. The p +- type contact layers 32 and the p type base layer 22 may be collectively referred to as a p type base layer. In the semiconductor device 200 in the second embodiment, the first semiconductor layer refers to the p-type base layer.In the semiconductor device 200, as in the semiconductor device 100 in the first embodiment, the first buffer layer 5 and the second buffer layer 4 are disposed on the second principal plane 1 bside of the n -- type drift layer 1. The configuration and a formation method of the first buffer layer 5 and the second buffer layer 4 are as explained in the first embodiment. The first buffer layer 5 contains the crystal defects 9 to serve as lifetime killers. Although not illustrated, the second buffer layer 4 also contains the crystal defects 9 to serve as the lifetime killers, and the n -- type drift layer 1 also contains the crystal defects 9 to serve as the lifetime killers. As explained in the first embodiment, the crystal defects 9 included in the semiconductor device 200 to serve as the lifetime killers are the CiOi, the CiCs, the ISi3, or the ISi4. The density of the CiOi of the first buffer layer 5, the second buffer layer 4, and the n +- type drift layer 1 is greater than the density of the CiCs of the layers.In the semiconductor device 200, a p-type collector layer 23 is disposed on the second principal plane 1 bside of the second buffer layer 4 as a second semiconductor layer. That is, the p-type collector layer 23 is disposed between the first buffer layer 5 and the second principal plane 1 b. The p-type collector layer 23 is a semiconductor layer containing boron or aluminum, for example, as a p-type impurity. The concentration of the p-type impurity is 1.0×10 5 / cm 3 to 1.0×10 20 / cm 3. The p-type collector layer 23 constitutes the second principal plane 1b of the semiconductor substrate.As illustrated in FIG. 19, in the semiconductor device 200, trenches are formed which pass through the p-type base layer 22 from the first principal plane 1 aof the semiconductor substrate and reach the n -- type drift layer 1. The gates 12 of active trenches are formed by disposing the electrodes 12 aof gate trenches in the trenches via the insulating films 12 bof gate trenches. The electrodes 12 aof gate trenches are opposed to the n -- type drift layer 1 via the gate trench insulating films 12 b. The gates 13 of dummy trenches are formed by disposing the electrodes 13 aof dummy trenches in the trenches via the insulating films 13 bof dummy trenches. The electrodes 13 aof dummy trenches are opposed to the n -- type drift layer 1 via the insulating films 13 bof dummy trenches. The gate trench insulating films 12 bof the active trench gates 12 are in contact with the p-type base layer 22 and the n +- type source layers 25. When a voltage for gate driving is applied to the electrodes 12 aof gate trenches, channels are formed in the p-type base layer 22 in contact with the insulating films 12 bof gate trenches of the gates 12 of active trenches.As illustrated in FIG. 19, interlayer insulating films 28 are disposed on the electrodes 12 aof gate trenches of the gates 12 of active trenches. A barrier metal 29 is formed on regions where the interlayer insulating films 28 are not arranged, the first principal plane 1 aof the semiconductor substrate, and on the interlayer insulating films 28. The barrier metal 29 may be, for example, a conductor containing titanium (Ti), may be, for example, titanium nitride, or may be TiSi obtained by alloying titanium and silicon (Si). As illustrated in FIG. 19, the barrier metal 29 is in ohmic contact with the n +- type source layers 25, the p +- type contact layers 32, and the electrodes 13 aof dummy trenches, and is electrically connected to the n +- type source layers 25, the p +- type contact layers 32, and the electrodes 13 aof dummy trenches.An emitter electrode 26 is disposed on the barrier metal 29. The emitter electrode 26 has the same configuration as the configuration of the anode electrode 6 of the semiconductor device 100 explained in the first embodiment. When there are fine regions between the interlayer insulating films 28 or the like adjacent to each other, the regions are not satisfactorily embedded by emitter electrode 26, tungsten having a better embedding property than emitter electrode 26 can be disposed in the fine regions, and emitter electrode 26 can be disposed on the tungsten. Note that the emitter electrode 26 may be disposed on the n +- type source layers 25, the p +- type contact layers 32, and the electrodes 13 aof dummy trenches without providing the barrier metal 29. The barrier metal 29 may be disposed only on n-type semiconductor layers such as the n +- type source layers 25. The barrier metal 29 and the emitter electrode 26 may be collectively referred to as an emitter electrode that is a first electrode.Note that in FIG. 19, the interlayer insulating films 28 are not disposed on the electrodes 13 aof dummy trenches of the gates 13 of dummy trenches. However, the interlayer insulating films 28 may be formed on the electrodes 13 aof dummy trenches of the gates 13 of dummy trenches. When the interlayer insulating films 28 are formed on the electrodes 13 aof dummy trenches of the gates 13 of dummy trenches, the emitter electrode 26 and the electrodes 13 aof dummy trenches need only be electrically connected at a different cross section.A collector electrode 27, which is a second electrode, is disposed on the second principal plane 1 bside of the p-type collector layer 23. The collector electrode 27 may have the same configuration as the configuration of the cathode electrode 7 of the semiconductor device 100 explained in the first embodiment. The collector electrode 27 is in ohmic contact with the p-type collector layer 23 and is electrically connected to the p-type collector layer 23.FIG. 20 is a sectional view of the semiconductor device 200 taken along a dotted line B-B in FIG. 18. The sectional view is different from the sectional view illustrated in FIG. 19 taken along the dotted line A-A in that the n +- type source layers 25 disposed on the first principal plane 1 aside of the semiconductor substrate in contact with the active trench gates 12 are not seen in a sectional view taken along the dotted line B-B in FIG. 20. That is, as illustrated in FIG. 18, the n +- type source layers 25 are selectively disposed on the first principal plane 1 aside of the p-type base layer 22. Note that the p-type base layer 22 and the p +- type contact layers 32 are collectively referred to as the p-type base layer.Also in the semiconductor device 200, a measurement result indicating a density change of the CiOi with respect to the depth from the second principal plane 1 bof the semiconductor device is obtained, as well as the measurement result illustrated in FIG. 4 from photoluminescence of a C-line due to the CiCs. A measurement result indicating a density change of the CiCs with respect to the depth from the second principal plane 1 bof the semiconductor device is obtained from photoluminescence of a G line due to the CiCs, in the same manner as the measurement result illustrated in FIG. 5.Like the semiconductor device 100 in the first embodiment, the semiconductor device 200 includes, in the semiconductor substrate, ISi 3 or ISi 4, which is a complex defect of interstitial silicon. Also in the semiconductor device 200, a measurement result indicating a density change of the ISi 3 with respect to the depth from the second principal plane 1 bof the semiconductor substrate is obtained, as well as the measurement result illustrated in FIG. 6 from photoluminescence of a W line due to the ISi 3. A measurement result indicating a density change of the ISi4with respect to the depth from the second principal plane 1 bof the semiconductor device is obtained from photoluminescence of an X line due to the ISi4, in the same manner as the measurement result illustrated in FIG. 7.Like the semiconductor device 100 in the first embodiment, the semiconductor device 200 includes more CiOi in the semiconductor substrate than the crystal defects 9 to serve as the lifetime killers compared to the CiCs. The semiconductor device 200 includes more CiOi in the n -- type drift layer 1 compared to the CiCs, and also includes more CiOi compared to the CiCs in the first buffer layer 5 and the second buffer layer 4. As a result, the semiconductor device 200 in the second embodiment achieves the same effects as the effects of the semiconductor device 100 in the first embodiment.Third EmbodimentFIG. 21 is a sectional view illustrating a semiconductor device in the third embodiment. In FIG. 21, components denoted by the same reference numerals and characters as the reference numerals and characters in FIG. 1, 19 or 20 are the same or corresponding components. Explanation of the components will be omitted. In the first embodiment, the semiconductor device 100 is a diode. In the second embodiment, the semiconductor device 200 is the IGBT. A semiconductor device 300 in the third embodiment is an RC-IGBT (Reverse Conduction IGBT) in which an IGBT region 40 and a diode region 41 are disposed in a semiconductor substrate.The semiconductor device 300 includes one or more IGBT regions 40 and one or more diode regions 41 in a semiconductor substrate (semiconductor chip), and has a configuration in which the IGBT regions 40 and the diode regions 41 are alternately arranged in a stripe shape, a configuration in which the IGBT regions 40 are arranged so as to surround the island-like dispersed diode regions 41, or a configuration in which the diode regions 41 are arranged so as to surround the island-like dispersed IGBT regions 40.The IGBT region 40 and the diode region 41 form a cell region. A terminal end region (terminal end region) is disposed between the cell region and the outer peripheral edge of the semiconductor substrate (semiconductor chip) so as to surround the cell region. The first buffer layer 5, the second buffer layer 4, and the n -- type drift layer 1 are also disposed in the termination end region. The first buffer layer 5, the second buffer layer 4, or the n -- type drift layer 1 in the termination end region may include the crystal defects 9 to serve as the lifetime killers.As illustrated in FIG. 21, the configuration of the IGBT region 40 of the semiconductor device 300 is the same as the configuration of the semiconductor device 200 explained in the second embodiment, which is the IGBT. The configuration of the diode region 41 of the semiconductor device 300 is the same as the configuration of the semiconductor device 100 that is the diode explained in the first embodiment, but is different in that the diode region 41 includes the n-type carrier storage layer 15 between the p-type anode layer 2 and the n -- type drift layer 1 and includes the p +- type contact layers 32 between the p-type anode layer 2 and the first main plane 1 a. The configuration of the diode region 41 is different in that the n +- type cathode layer 3 is not disposed and the p type collector layer 23 is disposed over a region of a distance U 1 from a boundary between the IGBT region 40 and the diode region 41 to the diode region 41 side. Note that the diode region 41 may have a configuration in which, unlike the semiconductor device 100 explained in the first embodiment, the n-type carrier storage layer 15 or the p +- type contact layers 32 are not provided, and the n +- type cathode layer 3 is also disposed in the region of the distance U 1 from the boundary between the IGBT region 40 and the diode region 41 to the diode region 41 side.In the semiconductor device 300 in the third embodiment, in the IGBT region 40, a first semiconductor layer is a p-type base layer obtained by combining the p-type base layer 22 and the p +- type contact layers 32, and in the diode region 41, the first semiconductor layer is an anode layer obtained by combining the p-type anode layer 2 and the p +- type contact layers 32. A second semiconductor layer is the p-type collector layer 23 in the IGBT region 40, and is the n +- type cathode layer 3 in the diode region 41.An anode electrode, which is a first electrode, of the diode region 41 of the semiconductor device 300 is integrally formed with the emitter electrode 26 of the IGBT region 40. A cathode electrode, which is a second electrode, of the diode region 41 is integrally formed with the collector electrode 27 of the IGBT region 40.As illustrated in FIG. 21, the semiconductor device 300 includes the crystal defects 9 to be used as the lifetime killers in the first buffer layer 5 of the IGBT region 40 and the first buffer layer 5 of the diode region 41. although not illustrated, the semiconductor device 300 also includes the crystal defects 9 to be used as the lifetime killers in the second buffer layer 4 of the IGBT region 40 and the second buffer layer 4 of the diode region 41, and also includes the crystal defects 9 to be used as the lifetime killers in the n -- type drift layer 1 of the IGBT region 40 and the n -- type drift layer 1 of the diode region 41, The crystal defects 9 included in the semiconductor device 300 to serve as the lifetime killers are the CiOi, the CiCs, the ISi3, or the ISi4. The density of the CiOi of the first buffer layer 5, the second buffer layer 4, and the n -- type drift layer 1 is greater than the density of the CiCs of the layers.Also in the semiconductor device 300, a measurement result indicating a density change of the CiOi with respect to the depth from the second principal plane 1 bof the semiconductor device is obtained, as well as the measurement result illustrated in FIG. 4 from photoluminescence of a C-line due to the CiOi. A measurement result indicating a density change of the CiCs with respect to the depth from the second principal plane 1 bof the semiconductor device is obtained from photoluminescence of a G line due to the CiCs, in the same manner as the measurement result illustrated in FIG. 5.Like the semiconductor device 100 in the first embodiment, the semiconductor device 300 includes, in the semiconductor substrate, ISi 3 or ISi 4, which is a complex defect of interstitial silicon. Also in the semiconductor device 300, a measurement result indicating a density change of the ISi 3 with respect to the depth from the second principal plane 1 bof the semiconductor device is obtained, as well as the measurement result illustrated in FIG. 6 from photoluminescence of a W line due to the ISi 3. A measurement result indicating a density change of the ISi4with respect to the depth from the second principal plane 1 bof the semiconductor device is obtained from photoluminescence of an X line due to the ISi4, in the same manner as the measurement result illustrated in FIG. 7.Like the semiconductor device 100 in the first embodiment, the semiconductor device 300 includes more CiOi in the semiconductor substrate than the crystal defects 9 to serve as the lifetime killers compared to the CiCs. The semiconductor device 300 includes more CiOi in the n -- type drift layer 1 as compared with the CiCs, and also includes more CiOi in the first buffer layer 5 and the second buffer layer 4 as compared with the CiCs. As a result, the semiconductor device 300 in the third embodiment achieves the same effects as the effects of the semiconductor device 100 in the first embodiment.

Claims

A semiconductor device (100, 200, 300) comprising: - a drift layer (1) of a first conductivity type disposed in a semiconductor substrate (1c) having a first principal plane (1a) and a second principal plane (1b) opposite to the first principal plane (1a); - a first semiconductor layer (2, 22, 32) of a second conductivity type disposed between the first principal plane (1a) of the semiconductor substrate (1c) and the drift layer (1) and having an impurity concentration higher than an impurity concentration of the drift layer (1); - a first buffer layer (5) of a first conductivity type disposed between the second principal plane (1b) of the semiconductor substrate (1c) and the drift layer (1) and having hydrogen-induced donors having an impurity concentration higher than an impurity concentration of the drift layer (1); and a second semiconductor layer (3, 23) of a first conductivity type or a second conductivity type, which is disposed between the second principal plane (1b) of the semiconductor substrate (1c) and the first buffer layer (5) and has an impurity concentration higher than an impurity concentration of the drift layer (1), wherein: the first buffer layer (5) has a complex defect (9, CiOi) of interstitial carbon and interstitial oxygen having a density decreasing from the second principal plane (1b) side toward the first principal plane (1a) side, and a density of the complex defect (9, CiOi) of interstitial carbon and interstitial oxygen in the first buffer layer (5) is greater than a density of a complex defect (9, CiOi), CiMn) is of interstitial carbon and lattice site carbon in the first buffer layer (5).The semiconductor device (100, 200, 300) according to claim 1, wherein the interstitial carbon-interstitial oxygen complex defect (9, CiOi) is a lifetime killer that reduces a recombination lifetime of a carrier.The semiconductor device (100, 200, 300) according to any one of the preceding claims, wherein: the first buffer layer (5) has an interstitial silicon complex defect (9, Isi3, Isi4) having a density decreasing from the second principal plane (1b) side toward the first principal plane (1a) side, and the first buffer layer (5) has a region in which a rate of decrease in density of the interstitial carbon interstitial oxygen complex defect (9, CiOi) increases and a rate of decrease in density of the interstitial silicon complex defect (9, Isi3, Isi4) decreases from the second principal plane (1b) side toward the first principal plane (1a) side.The semiconductor device (100, 200, 300) according to any one of the preceding claims, wherein: - the first buffer layer (5) has at least one concentration peak of the hydrogen-induced donors; and - the interstitial carbon-interstitial oxygen complex defect (9, CiOi) is present further on the first principal plane (1a) side than the concentration peak closest to the first principal plane (1a) among the concentration peaks of the hydrogen-induced donors.The semiconductor device (100, 200, 300) according to any one of the preceding claims, further comprising a second buffer layer (4) of a first conductivity type disposed between the second semiconductor layer (3, 23) and the first buffer layer (5), having phosphorus as impurities, and having an impurity concentration higher than an impurity concentration of the first buffer layer (5), wherein: - the second buffer layer (4) has the interstitial carbon-interstitial oxygen complex defect (9, CiOi), and - a density of the interstitial carbon-interstitial oxygen complex defect (9, CiOi) of the second buffer layer (4) is lower than a maximum density of the interstitial carbon-interstitial oxygen complex defect (9, CiOi) of the first buffer layer (5).The semiconductor device (100, 200, 300) according to any one of the preceding claims, wherein the second semiconductor layer (3, 23) is a collector layer (23) of a second conductivity type.The semiconductor device (100, 200, 300) according to any one of claims 1 to 5, wherein the second semiconductor layer (3, 23) is a cathode layer (3) of a first conductivity type.The semiconductor device (100, 200, 300) according to any one of claims 1 to 5, wherein the semiconductor substrate (1c) includes an IGBT region (40) in which the second semiconductor layer (3, 23) is a collector layer (23) of a second conductivity type and a diode region (41) in which the second semiconductor layer (3, 23) is a cathode layer (3) of a first conductivity type.A manufacturing method for a semiconductor device (100, 200, 300), the method comprising: preparing a first conductivity type semiconductor substrate (1c) having a first principal plane (1a) and a second principal plane (1b) opposite to the first principal plane (1a), and comprising carbon and oxygen; forming a second conductivity type first semiconductor layer (2, 22, 32) having an impurity concentration higher than an impurity concentration of the semiconductor substrate (1c) on the first principal plane (1a) side of the semiconductor substrate (1c); after forming the first semiconductor layer (2, 22, 32), grinding the semiconductor substrate (1c) from the second principal plane (1b) side; - after grinding the semiconductor substrate (1c), forming a second semiconductor layer (3, 23) of a first conductivity type or a second conductivity type having an impurity concentration higher than an impurity concentration of the semiconductor substrate (1c) on the second principal plane (1b) side of the semiconductor substrate (1c); - after grinding the semiconductor substrate (1c), injecting protons (10) from the second principal plane (1b) side; - a first heat treatment step to heat the semiconductor substrate (1c) at a first temperature, convert the protons (10) injected into the semiconductor substrate (1c) into hydrogen-induced donors, and form a first buffer layer (5) of a first conductivity type having an impurity concentration higher than the impurity concentration of the semiconductor substrate (1c); after the first heat treatment step, a charged particle irradiation step for irradiating the semiconductor substrate (1c) with charged particles and forming a complex defect (9, CiOi) of interstitial carbon and interstitial oxygen and a complex defect (9, CiMn) of interstitial carbon and lattice site carbon; and after the charged particle irradiation step, a second heat treatment step for heating the semiconductor substrate (1c) at a second temperature lower than the first temperature and extinguishing the complex defect (9, CiMn) of interstitial carbon and lattice site carbon.The manufacturing method according to claim 9, wherein in the second heat treatment step, the interstitial carbon-interstitial carbon complex defect (9, CiNb) is extinguished more than the interstitial carbon-interstitial oxygen complex defect (9, CiOi).The production method according to claim 9 or 10, wherein the charged particles are electrons or protons (10).The production method according to any one of claims 9 to 11, wherein the interstitial carbon-interstitial oxygen complex defect (9, CiOi) is a lifetime killer that reduces a recombination lifetime of a carrier.The manufacturing method according to any one of claims 9 to 12, wherein the complex defect (9, CiOi) of interstitial carbon and interstitial oxygen is formed in the first buffer layer (5).The production method according to any one of claims 9 to 13, wherein: - the first temperature is 380°C or higher and 525°C or lower, and - the second temperature is 250°C or higher and 350°C or lower.The manufacturing method according to any one of claims 9 to 14, wherein: - the step of forming the second semiconductor layer (3, 23) includes, after injecting a first conductivity type impurity or a second conductivity type impurity from the second principal plane (1b) side of the semiconductor substrate (1c), irradiating the second principal plane (1b) of the semiconductor substrate (1c) with a laser beam in air; and - the charged particle irradiation step is performed after forming the second semiconductor layer (3, 23).The manufacturing method according to any one of claims 9 to 15, further comprising forming a second buffer layer (4) of a first conductivity type that includes phosphorus as impurities and has an impurity concentration higher than an impurity concentration of the first buffer layer (5) between the second semiconductor layer (3, 23) and the first buffer layer (5), wherein the charged particle irradiation step is performed after forming the second buffer layer (4).The manufacturing method according to any one of claims 9 to 16, comprising a film forming step of forming a metal film on the second semiconductor layer (3, 23), and a sintering treatment step of heating the metal film, wherein: - the film forming step is performed between the first heat treatment step and the second heat treatment step, and - the sintering treatment step is performed by the second heat treatment step.The manufacturing method according to claim 17, wherein the film forming step includes a step of sputtering or vapor depositing a metal layer containing Al, Ti, Ni, Au, Ag and / or Cu on the second semiconductor layer (3, 23).

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