STORAGE DEVICE

Abstract

A memory device comprising: a memory cell region (CELL) comprising a first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901), gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) spaced apart from one another on the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) such that they are stacked in a first direction (Z) perpendicular to an upper surface of the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901), and channel structures (CH) connecting the gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) and are electrically connected to the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901); and a peripheral circuit region (PERI) containing a second semiconductor substrate (202; 302; 402; 502; 602; 702; 802;902) arranged below the memory cell region (CELL), an intermediate insulating layer, and a plurality of upper metal lines (LM2) arranged above the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) in the intermediate insulating layer at a first height such that they extend in a second direction (Y) parallel to an upper surface of the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902), wherein the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801;901) includes first regions having a first distance (H1) between a lower surface thereof and the first height, and second regions having a second distance (H2) between the lower surface thereof and the first height, the second distance (H2) being shorter than the first distance (H1), the second regions being formed on recessed portions of the interlayer insulating layer, and first upper metal lines of the plurality of upper metal lines (LM2) being arranged below the first regions, and at least one of the first upper metal lines being configured to transmit a reference voltage for operating the memory cell region (CELL) and the peripheral circuit region (PERI);

Description

BACKGROUNDThe present disclosure relates to a storage device.Recent memory devices have to have a high degree of integration and a high speed in order to be able to process more data in a short period of time. An increase in speed of a memory device can be achieved primarily by a reduction in resistance of a metal line. However, an RC delay caused by a parasitic capacitor may result in a limitation in increasing the speed of a memory device. Therefore, a method of reducing parasitic capacitance (or stray capacitance) using a decoupling capacitor has been proposed as a method of reducing coupling noise associated with RC delay. However, a structural problem makes it difficult to form a decoupling capacitor having a high capacitance. Therefore, there is a need for a basic solution to reduce coupling noise.From US 2019 / 0 067 308 A1 a nonvolatile memory device is known, which includes a first semiconductor layer including a peripheral region, wherein the peripheral region includes one or more peripheral transistors on a lower substrate. The nonvolatile memory device further includes a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate and including a memory cell array on the upper substrate.SUMMARYExample embodiments provide a memory device including a memory cell region in which a lower surface of a common source line opposing a lower metal line is non-planar. A coupling capacitance between the common source line and a metal line for transmitting a significant signal may be reduced with the memory device. Moreover, example embodiments provide a storage device with improved performance.According to an exemplary embodiment, a memory device includes: a memory cell region including a first semiconductor substrate, gate electrodes spaced apart from each other on the first semiconductor substrate so as to be stacked in a first direction perpendicular to an upper surface of the first semiconductor substrate, and channel structures penetrating the gate electrodes and electrically connected to the first semiconductor substrate; and a peripheral circuit region including a second semiconductor substrate disposed below the memory cell region, an interlayer insulating layer, and a plurality of upper metal lines disposed above the second semiconductor substrate in the interlayer insulating layer at a first height (or at a first level), respectively, so as to extend in a second direction parallel to an upper surface of the second semiconductor substrate. The first semiconductor substrate includes first regions having a first distance between a bottom surface thereof and a top surface of first upper metal lines of the plurality of upper metal lines, and second regions having a second distance between the bottom surface thereof and a top surface of second upper metal lines of the plurality of upper metal lines, the second distance being shorter than the first distance. The second regions are formed on recessed portions of the interlayer insulating layer. The first upper metal lines are disposed below the first regions and the second upper metal lines are disposed below the second regions, and at least one of the first upper metal lines is configured to transmit a reference voltage for operation of the memory cell region and the peripheral circuit region.According to an exemplary embodiment, a memory device includes: a memory cell region including a first semiconductor substrate; gate electrodes spaced apart from each other on the first semiconductor substrate so as to be stacked in a first direction perpendicular to an upper surface of the first semiconductor substrate; and channel structures penetrating the gate electrodes and disposed in a recessed portion of the first semiconductor substrate; and a peripheral circuit portion including a second semiconductor substrate disposed below the memory cell portion, an interlayer insulating film, a plurality of lower metal lines disposed above the second semiconductor substrate in the interlayer insulating film at a predetermined height so as to extend in a second direction parallel to an upper surface of the second semiconductor substrate, and a plurality of upper metal lines disposed between the plurality of lower metal lines and the first semiconductor substrate so as to extend in a third direction parallel to an upper surface of the second semiconductor substrate and perpendicular to the second direction. The first semiconductor substrate includes first regions having a first distance between a bottom surface thereof and a top surface of first upper metal lines of the plurality of upper metal lines, and second regions having a second distance between a bottom surface thereof and a top surface of second upper metal lines of the plurality of upper metal lines, the second distance being shorter than the first distance. The first upper metal lines and the second upper metal lines are at the same height with respect to a top surface of the second semiconductor substrate. The first regions and the second regions are arranged alternately in the third direction. The second regions are formed on recessed portions of the interlayer insulating layer.According to an exemplary embodiment, a memory device includes: a first semiconductor substrate including first regions having a first thickness and second regions having a second thickness larger than the first thickness; a second semiconductor substrate disposed below the first semiconductor substrate so as to overlap the first semiconductor substrate in a first direction that is perpendicular to a top surface of the first semiconductor substrate; an interlayer insulating layer disposed between the first semiconductor substrate and the second semiconductor substrate; a plurality of metal lines disposed in the interlayer insulating layer so as to extend in a direction parallel to a top surface of the second semiconductor substrate, and including first metal lines configured to transmit a band gap reference signal via the first metal lines; Gate electrodes spaced apart from each other on the first semiconductor substrate so as to be stacked in the first direction; insulating layers alternately stacked with the gate electrodes; and channel structures passing through the gate electrodes and the insulating layers and disposed in a recessed portion of the first semiconductor substrate. The first metal lines are arranged below the first region. The second regions are formed on recessed portions of the interlayer insulating layer.BRIEF DESCRIPTION OF THE DRAWINGSThe above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. FIG. 1 is a block diagram of a memory device according to an example embodiment. FIG. 2 is a view showing a 3D V NAND structure for a memory device according to an exemplary embodiment. FIG. 3 is a cross-sectional view of a memory device according to an example embodiment. FIGS. 4A to 4D are views illustrating a method for reducing coupling noise in a memory device according to an exemplary embodiment. FIG. 5 is a cross-sectional view of a memory device according to an example embodiment. FIG. 6 is a view illustrating a method of adjusting coupling capacitance in a memory device according to an exemplary embodiment. FIGS. 7 to 11 are cross-sectional views of memory devices according to an exemplary embodiment. FIGS. 12 and 13 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 11. FIG. 14 is a cross-sectional view of a memory device according to an example embodiment. FIGS. 15 and 16 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 14. FIG. 17 is a cross-sectional view of a memory device according to an example embodiment. FIGS. 18 and 19 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 17. FIGS. 20 and 21 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 17.DETAILED DESCRIPTIONHereinafter, exemplary embodiments will be described with reference to the accompanying drawings.FIG. 1 is a block diagram of a memory device according to an example embodiment.Referring to FIG. 1, a memory device 1 may include a control logic circuit 20, a memory cell array 30 (or a memory cell array), a page buffer unit 40, a voltage generator 50, and a row decoder 60. Although not illustrated in FIG. 1, the memory device 1 may also include a memory interface circuit, and column logic, a predecoder, a temperature sensor, a command decoder, an address decoder, and the like.The control logic circuit 20 can generally control various operations in the storage device 1. The control logic circuit 20 may output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit. For example, the control logic circuit 20 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.The memory cell array 30 may include a plurality of memory blocks BLK 1 to BLKz (where z is a positive integer). Each of the plurality of memory blocks BLK 1 to BLKz may include a plurality of memory cells. The memory cell array 30 may be connected to the page buffer unit 40 via bit lines BL, and to the row decoder 60 via word lines WL, string select line lines SSL, and ground select lines GSL.In an exemplary embodiment, the memory cell array 30 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of memory cell strings (or strings of memory cells). Each of the memory cell strings may include memory cells connected to word lines vertically stacked on a substrate, respectively. Patents U.S. Pat. No. 7,679,133 B2, U.S. Pat. No. 8,553,466 B2, U.S. Pat. No. 8,654,587 B2, U.S. Pat. No. 8,559,235 B2 and patent application US 2011 / 0 233 648 A1 are incorporated herein by reference. In an exemplary embodiment, the memory cell array 30 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of memory cell strings arranged in the row and column directions.Spatially relative terms such as "below", "below", "lower", "above", "higher", "vertical", "horizontal" and the like may be used herein to describe positional relationships for convenience of description. It should be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures.The page buffer unit 40 may include a plurality of page buffers PB 1 to PBn (where n is an integer of 3 or greater), and the plurality of page buffers PB 1 to PBn may be connected to the memory cells via a plurality of bit lines BL, respectively. The page buffer unit 40 may select at least one of the bit lines BL in response to the column address Y-ADDR. The page buffer unit 40 may function as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, page buffer unit 40 may apply a bit line voltage corresponding to data DATA to be programmed to a selected bit line. The page buffer unit 40 may sense a current or voltage on the selected bit line to sense data stored in a memory cell during a read operation.The voltage generator 50 may generate various voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. The voltage generator 50 may generate, for example, a program voltage, a read voltage, a program verification voltage, an erase voltage, or the like as a word line voltage VWL.The row decoder 60 may select one of the plurality of word lines WL and one of the plurality of string selection lines SSL in response to the row address X-ADDR. For example, row decoder 60 may apply a program voltage and a program test voltage to a selected word line during a program operation and apply a read voltage to a selected word line during a read operation.FIG. 2 is a view showing a 3D V NAND structure applicable to a memory device according to an exemplary embodiment.When a memory module of a memory device is implemented as a 3D-V-NAND flash memory, each of the plurality of memory blocks constituting the memory module may be represented by an equivalent circuit diagram as shown in FIG. 2.A memory block BLKi shown in FIG. 2 indicates a three-dimensional memory block having a three-dimensional structure formed on a substrate. For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.Referring to FIG. 2, a memory block BLKi may include a plurality of memory cell strings NS 11 to NS 33 connected between the bit lines BL 1, BL 2, and BL 3 and a common source line CSL. Each of the plurality of memory cell strings NS 11 to NS 33 may include a string selection transistor SST (string selection transistor), a plurality of memory cells MC 1, MC 2..., and MC 8, and a ground selection transistor GST. In FIG. 2, each of the plurality of memory cell strings NS 11 to NS 33 is illustrated as including eight memory cells MC 1, MC 2... and MC 8 connected in series, but the present disclosure is not limited thereto.The string selection transistor SST may be connected to corresponding string selection lines SSL 1, SSL 2, and SSL 3. The plurality of memory cells MC 1, MC 2... and MC 8 may be connected to corresponding gate lines GTL 1, GTL 2... and GTL 8, respectively. The gate lines GTL 1, GTL 2... and GTL 8 may correspond to word lines, and some of the gate lines GTL 1, GTL 2... and GTL 8 may correspond to dummy word lines (or dummy word lines). The ground selection transistor GST may be connected to corresponding ground selection lines GSL 1, GSL 2, and GSL 3. The string selection transistor SST may be connected to corresponding bit lines BL 1, BL 2, and BL 3, and the ground selection transistor GST may be connected to the common source line CSL. In the memory device according to an exemplary embodiment, the common source lines CSL may be connected to each other. Therefore, the common source line CSL may be formed in the shape of a plate below the memory block BLK. The common source line CSL may be, for example, a conductive pattern / layer and / or a semiconductor pattern / layer extending horizontally, for example, in X and Y directions, as illustrated in FIGS. 2 and 3. The common source line CSL may include or be, for example, a common source line plate PCSL.Gate lines (for example, GTL 1) having the same height may be commonly connected, and the ground selection lines GSL 1, GSL 2, and GSL 3 and the string selection lines SSL 1, SSL 2, and SSL 3 may be separated from each other. In FIG. 2, the memory block BLK is connected to eight gate lines GTL 1, GTL 2... and GTL 8 and three bit lines BL 1, BL 2, BL 3, but the present disclosure is not limited thereto.FIG. 3 is a cross-sectional view of a memory device according to an example embodiment.Referring to FIG. 3, a memory device 100 may include a memory cell area CELL in which data is stored, and a peripheral circuit area PERI disposed below the memory cell area CELL.In the device 100 illustrated in FIG. 3, the memory cell region CELL may include a first semiconductor substrate 101, a plurality of insulating layers 120, a plurality of gate electrodes 130, a first conductive layer 104, a second conductive layer 105, channel structures CH, and a separation region SR (or separation region).In an exemplary embodiment of the memory device 100, the first semiconductor substrate 101 may have a top surface extending in the X-axis and Y-axis directions. For example, a direction perpendicular to the top surface of the first semiconductor substrate 101 (e.g., a Z direction) may be defined as a first direction, and directions parallel to the top surface of the first semiconductor substrate 101 (e.g., Y and X directions) may be defined as second and third directions, respectively. The first semiconductor substrate 101 may include or be formed from a semiconductor material such as a group IV semiconductor, a group III-V semiconductor compound, or a group II-VI oxide semiconductor. The group IV semiconductor may include or consist of, for example, silicon, germanium or silicon germanium. However, the configuration of the first semiconductor substrate 101 is not limited thereto, and the first semiconductor substrate 101 may be provided as an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SEOI) layer.The memory device 100 according to an exemplary embodiment may include insulating layers 120 and gate electrodes 130 spaced apart from each other so as to be alternately stacked in the first direction (for example, a Z direction) perpendicular to the upper surface of the first semiconductor substrate 101. The insulating layers 120 may be vertically and / or horizontally spaced apart from each other, for example. The gate electrodes 130 may be vertically and / or horizontally spaced apart from each other. The insulating layers 120 and the gate electrodes 130 may be alternately stacked in the vertical direction. The insulating layers 120 may include or be formed from an insulating material such as a silicon oxide or a silicon nitride. Of the insulating layers 120, for example, the uppermost insulating layer may have a larger thickness than the other insulating layers 120. The gate electrodes 130 may extend over different lengths in at least one region of the first semiconductor substrate 101.In an exemplary embodiment of the memory device 100, the gate electrodes 130 may include at least one gate bottom electrode, at least one gate top electrode, and an intermediate gate electrode between the gate bottom electrodes and the gate top electrodes. Referring to the memory block BLKishown in FIG. 2 together with FIG. 3, the lower gate electrode may correspond to the ground selection lines GSL 1, GSL 2, and GSL 3, and the upper gate electrode may correspond to the string selection lines SSL 1, SSL 2, and SSL 3. For example, the ground selection lines GSL 1, GSL 2, GSL 3 may be connected to a gate electrode of the ground selection transistor GST, and the string selection lines SSL 1, SSL 2, SSL 3 may be connected to a gate electrode of the string selection transistor SST.At least some of the intermediate gate electrodes may correspond to the gate lines GTL 1, GTL 2..., and GTL 8 illustrated in FIG. 2. On the other hand, some of the intermediate gate electrodes may also be dummy gate electrodes (or dummy gate electrodes). According to an exemplary embodiment, the number of intermediate gate electrodes may be determined depending on a capacitance of the memory device 100, for example.Each of the gate electrodes 130 may include a first gate layer 130 aand a second gate layer 130 b. The first gate layer 130 amay include or be formed from, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. The second gate layer 130 bmay include or be formed from, for example, a metallic material such as tungsten (W). However, the configuration of the gate electrodes 130 is not limited thereto, and the gate electrodes 130 may include three or more layers and may include polycrystalline silicon or a metal silicide material.The first conductive layer 104 and the second conductive layer 105 may be sequentially stacked on the upper surface of the first semiconductor substrate 101. According to an exemplary embodiment, at least a portion of the first semiconductor substrate 101, the first conductive layer 104, and the second conductive layer 105 may function as a common source line in the memory device 100 and correspond to the common source line CSL illustrated in FIG. 2. As described above, the first conductive layer 104 and the second conductive layer 105 may be plate-shaped (e.g., horizontally and / or two-dimensionally extending) conductive layers and may be disposed between the insulating layers 120 and / or the gate electrodes 130 and the first semiconductor substrate 101. The first conductive layer 104 and the second conductive layer 105 may include or be formed from a semiconductor material. For example, the first conductive layer 104 and the second conductive layer 105 may include polycrystalline silicon. For example, at least the first conductive layer 104 may be doped with impurities (or impurities), and the second conductive layer 105 may be doped with impurities or contain impurities diffused from the first conductive layer 104. The first semiconductor substrate 101, the first conductive layer 104 and the second conductive layer 105 together may form a common source line. However, the configuration of the common source line is not limited to that illustrated in FIG. 3, and the memory cell region CELL may additionally include an insulating layer and / or an additional conductive layer adjacent to the common source line according to an exemplary embodiment.In an exemplary embodiment of the memory device 100, each of the channel structures CH may extend in the first direction and be disposed to penetrate the gate electrodes 130 and the insulating layers 120. However, this is only an example and is not limited to the illustration in FIG. 3, and the channel structures CH may be disposed to penetrate at least a portion of the first semiconductor substrate 101. The channel structures CH may be disposed at recessed portions of the first semiconductor substrate 101, for example. The channel patterns CH may be disposed on the first semiconductor substrate 101 so as to be spaced apart from each other in rows and columns in a direction horizontal to the upper surface of the first semiconductor substrate 101. Each of the channel structures CH may have a side surface that is perpendicular to the upper surface of the first semiconductor substrate 101 or may have a shape of a pillar having an inclined side tapering toward the first semiconductor substrate 101 depending on an aspect ratio.In an exemplary embodiment of the memory device 100, each of the channel structures CH may include a channel layer 145, a channel insulating layer 150, and a pad layer 155 (or pad layer). For example, each of the channel structures CH may further include a gate dielectric layer 140 including a plurality of layers disposed between the channel layer 145 and the gate electrodes 130 to trap electric charges. In the channel structures CH, the channel layer 145 may be formed to have an annular shape surrounding a channel insulating layer 150 disposed therein. However, according to an exemplary embodiment, the channel layer 145 may also have a columnar, for example cylindrical or prismatic shape without the channel insulating layer 150. A portion of the gate dielectric layer 140 may be removed at a lower end of each of the channel structures CH, and the channel layer 145 may be electrically connected to and / or contact the first conductive layer 104 in the region where the gate dielectric layer 140 is removed.When an element is referred to as being "connected" or "coupled" to or "on" another element, it may be directly connected or coupled to or on the other element or intervening elements may be present. On the other hand, when an element is referred to as being "directly connected" or "directly coupled" to another element or "contacting" or "in contact with" another element, there are no intervening elements at the contact location.In an exemplary embodiment of the memory device 100, the channel layer 145 may include a semiconductor material such as polycrystalline or single crystal silicon. The semiconductor material included in the channel layer 145 may not be doped with an impurity or may be doped with p-type impurities or n-type impurities. The channel layer 145 may be divided into a plurality of regions based on an impurity concentration and / or a manufacturing method. Referring to the memory block BLKishown in FIG. 2 together with FIG. 3, in the memory device 100, a single memory cell string NS 11, NS 12, or NS 13 may be formed / configured around the channel layer 145, and a plurality of memory cell strings NS 11 to NS 33 may be arranged in rows and columns in the X-axis and Y-axis directions.In an exemplary embodiment of the memory device 100, the separation region SR may extend in the first direction and penetrate the alternately stacked gate electrodes 130 and insulating layers 120. The separation region SR may extend in a second direction (for example, the Y direction) parallel to the upper surface of the first semiconductor substrate 101. The separation region SR may include or be formed from an insulating material. For example, the separation region SR may contain a silicon oxide or the like or be formed therefrom. The gate electrodes 130 may be arranged, for example, to be separated by the separation region SR in a third direction (for example, the X direction). The gate electrodes 130 disposed between the plurality of separation regions SR may form a single memory block. However, this is only an example, and the configuration of a memory block is not limited thereto.The memory cell region CELL of the memory device 100 may further include a first interlayer insulating layer 160, a second interlayer insulating layer 165, a contact plug 170 (or a contact plug) electrically connected to the channel structures CH, and a bit line 180 electrically connected to the contact plug 170. The first interlayer insulating layer 160 and the second interlayer insulating layer 165 may, for example, cover the insulating layers 120 and the gate electrodes 130, and include or be formed of an insulating material such as silicon oxide. The contact plug 170 may penetrate the first interlayer insulating layer 160 and the second interlayer insulating layer 165 to electrically connect the bit lines 180 disposed on the second interlayer insulating layer 165 and the channel structures CH to each other. The bit line 180 shown in FIG. 3 may correspond to the bit lines BL 1, BL 2, and BL 3 shown in the circuit diagram of FIG. 1.The memory device 100 according to an embodiment may be manufactured by forming the peripheral circuit region PERI and then forming the first semiconductor substrate 101 of the memory cell region CELL on the peripheral circuit region PERI. The first semiconductor substrate 101 may have the same size as the second semiconductor substrate 102 of the peripheral circuit region PERI or may be formed smaller than the second semiconductor substrate 102.The peripheral circuit region PERI may include a second semiconductor substrate 102, circuit elements driving a memory cell disposed on the second semiconductor substrate 102, circuit contact plugs, and a plurality of metal lines LM 1 and LM 2. The circuit elements included in the peripheral circuit area PERI may include, for example, planar transistors. Each of the circuit elements may include a dielectric layer, a spacer layer, and a gate electrode, and source / drain regions may be disposed in the second semiconductor substrate 102 on opposite sides adjacent to the gate electrode.In the memory device 100 according to the present disclosure, the plurality of metal lines LM 1 and LM 2 may include an upper metal line LM 2 and a lower metal line LM 1. The plurality of metal lines LM 1 and LM 2 are metal lines disposed below the memory cells, and may be different from the metal lines disposed above the memory cells. According to an exemplary embodiment, of the plurality of metal lines LM 1 and LM 2 disposed below the memory cells, metal lines disposed close to the memory cell may be defined as an upper metal line LM 2, and metal lines disposed farther from the memory cell may be defined as a lower metal line LM 1. For example, the upper metal line LM 2 may be disposed at a first height (or at a first level) above the second semiconductor substrate 102, and the lower metal line LM 1 may be disposed at a second height (or at a second level) above the second semiconductor substrate 102 that is lower than the first height. The upper metal line LM 2 and the lower metal line LM 1 may extend in directions perpendicular to each other. For example, at least some of the plurality of metal lines LM 1 and LM 2 may extend in a second direction that is parallel to the first and second semiconductor substrates 101 and 102. On the other hand, the rest of the plurality of metal lines LM 1 and LM 2 may extend in a third direction that is parallel to the first and second semiconductor substrates 101 and 102 and perpendicular to the second direction. However, this is only an example, and the arrangement and shape of the plurality of metal lines LM 1 and LM 2 is not limited to those described above and / or illustrated in FIG. 3. According to example embodiments, the plurality of metal lines LM 1 and LM 2 may include only lower metal line LM 1, or may further include another metal line disposed at a third height different from the first height and the second height. For example, the memory device 100 may include another metal line disposed at the third height lower than the second height, and the another metal line may include a metal pattern used as a pin (pin). The pin may be, for example, a terminal configured to be connected to an external device. The memory device 100 may further include a plurality of metal layers arranged at different heights. However, this is only an example, and a height at which the plurality of metal lines are arranged, and a structure of the plurality of metal lines are not limited to those described above or to those of the plurality of metal lines LM 1 and LM 2.The memory cell area CELL and the peripheral circuit area PERI may be connected to each other in an area not shown. According to an exemplary embodiment, in the memory device 100, the peripheral circuit region PERI may be electrically connected to the memory cell region CELL via a connection portion. According to an exemplary embodiment, the memory cell region CELL may be electrically connected to the circuit elements of the peripheral circuit region PERI via the connection portion and a plurality of metal lines. The connection portion may be, for example, a via (THV) (or via hole). The connection portion may extend, for example, in the first direction perpendicular to the first and second semiconductor substrates 101 and 102 through a space on / in a side surface of the first semiconductor substrate 101. However, this is only an example, and the present disclosure is not limited thereto. The length of the connection portion may vary depending on the height of the upper surface of the common source line including or formed from the first semiconductor substrate 101, the first conductive layer 104, and the second conductive layer 105. For example, as the height of the upper surface of the common source line increases, the length of the connection portion may be increased.FIGS. 4A to 4D are views illustrating a method for reducing coupling noise in a memory device according to an exemplary embodiment.FIG. 4A is a schematic enlarged view of the region 100A illustrated in FIG. 3, and FIGS. 4B to 4D may be views showing alternative structures of a portion of the storage device illustrated in FIG. 4A for reducing the coupling capacitance.Referring to FIG. 4A, a common source line CSL included in a memory cell region and a plurality of upper metal lines LM 2 included in a peripheral circuit region may include a conductive material. The common source line CSL may have the shape of a plate (for example, horizontally extending in the X and Y directions) covering the plurality of upper metal lines LM 2 everywhere. Therefore, a coupling capacitance may be formed between the common source line CSL and the plurality of upper metal lines LM 2. Thus, during operation of the memory device, when a high voltage is applied to the common source line CSL and signals are transmitted to the plurality of upper metal lines LM 2, the coupling capacitance may affect signals applied to the plurality of upper metal lines LM 2, thereby generating coupling noise. A semiconductor chip including a memory device may have difficulty in performing normal operation due to the coupling noise generated during operation of the memory device.A plurality of upper metal lines LM 2 illustrated in FIGS. 4A to 4D may be metal lines disposed on an uppermost layer among the layers including metal lines disposed below the memory cells. The plurality of upper metal lines LM 2 may be disposed at a first height above / on an upper surface of the second semiconductor substrate 102 included in the peripheral circuit region, for example. The plurality of lower metal lines LM 1 may be metal lines disposed at a second height lower than the first height at which the plurality of upper metal lines LM 2 are disposed.Referring to FIG. 4B, in order for the memory device according to an exemplary embodiment to reduce the coupling noise, the plurality of upper metal lines LM 2 may not be used for significant / sensitive signals because the upper metal lines LM 2 may be affected by the coupling capacitance. The significant / sensitive signals may be transmitted via the plurality of lower metal lines LM 1 and not via the plurality of upper metal lines LM 2, for example. Accordingly, a distance between the common source line CSL and the lower metal line LM 1 transmitting a significant / sensitive signal may be increased and the size of the coupling capacitance may be decreased. Therefore, the coupling noise can be reduced to improve the operational stability of the memory device.Signals applied to the plurality of metal lines LM 1 and LM 2 may include a first signal and a second signal different from the first signal. The first signal may be, for example, a significant / sensitive signal that is relatively more strongly affected by the coupling capacitance. According to an exemplary embodiment, the first signal may include a reference voltage for operation of the memory device. The reference voltage included in the first signal may include, for example, a band gap reference signal (BGR). The BGR signal may correspond to a first signal / operation of applying the reference voltage. Therefore, the coupling noise generated by the coupling capacitance in the first signal may be amplified by an amplifier and may be relatively more significant / sensitive than the coupling noise generated by the coupling capacitance in the second signal.However, when the problem of the coupling noise is addressed with the method illustrated in FIG. 4B, the plurality of upper metal lines LM 2 cannot be used. This can reduce the degree of freedom in layout.Referring to FIG. 4C, in order to reduce coupling noise in the memory device according to an exemplary embodiment, a common source line CSL and at least one of a plurality of upper metal lines LM 2 may be shifted such that a distance therebetween increases. In this way, the size of the coupling capacitance and the coupling noise may be reduced to improve the operational stability of the memory device.However, when the method illustrated in FIG. 4C is used, as the length of the connection portion THV increases, a resistance of the connection portion THV and a coupling resistance between opposing connection portions THV may increase, and a process for forming the connection portion THV may become more difficult.Referring to FIG. 4D, in order for the memory device according to an exemplary embodiment to reduce the coupling noise while solving a problem of increasing the length of the connection portion THV occurring in FIGS. 4B and 4C, a thickness of the common source line CSL may be reduced. Therefore, a distance between the common source line CSL and the plurality of upper metal lines LM 2 can be increased while maintaining the length of the connection portion THV, and the size of the coupling capacitance and the coupling noise can be reduced.However, when the method illustrated in FIG. 4D is used, the resistance of the common source line CSL may be increased because the thickness of the common source line CSL is decreased. However, the magnitude of the resistance of the common source line CSL may be directly related to the performance of a semiconductor chip including the memory device. Therefore, there may be a need for a method for reducing the amount of coupling capacitance and coupling noise while maintaining the amount of resistance of the common source line CSL.FIG. 5 is a cross-sectional view of a memory device according to an example embodiment.Referring to FIG. 5, a storage device 200 according to an exemplary embodiment may include components respectively corresponding to the components of the storage device 100 illustrated in FIG. 3. For example, a memory cell region CELL of the memory device 200 according to the exemplary embodiment may include a first semiconductor substrate 201, a plurality of insulating layers 220, a plurality of gate electrodes 230, a first conductive layer 204, a second conductive layer 205, channel structures CH, and a separation region SR. In addition, a peripheral circuit region PERI of the memory device 200 may include a second semiconductor substrate 202, circuit elements disposed on the second semiconductor substrate 202, circuit contact plugs, and a plurality of metal lines LM 1 and LM 2.In contrast to the memory device 100 illustrated in FIG. 3, the memory device 200 according to an exemplary embodiment may include a plate-shaped first semiconductor substrate 201 having a curved bottom surface or a protruding and recessed surface. The first semiconductor substrate 201 may function as a common source line together with the first conductive layer 204 and the second conductive layer 205, for example. Referring to FIG. 3 together with FIG. 5, a lower surface of the common source line in the memory device 100 may correspond to a reference line RL of the common source line in the memory device 200 illustrated in FIG. 5. As described above, the first semiconductor substrate 101, the first conductive layer 104, and the second conductive layer 105 may be defined as a common source line.The protruding and recessed bottom surface of the first semiconductor substrate 201 included in the memory device 200 may be formed of, for example, an interlayer insulating film in the peripheral circuit region PERI. For example, a thickness of the first semiconductor substrate 201 may be adjusted by etching a portion of the interlayer insulating film and forming the first semiconductor substrate 201 on the etched surface of the interlayer insulating film of the peripheral circuit region PERI. However, this is only an example, and the present disclosure is not limited thereto. For example, the first semiconductor substrate 201 may include first regions having a first thickness Z 1 in a first direction and second regions having a second thickness Z 2 larger than the first thickness Z 1.In an exemplary embodiment of the memory device 200, the first regions and the second regions may be alternately arranged in a third direction (e.g., an X direction) parallel to the first semiconductor substrate 201 and the second semiconductor substrate 202. In the first semiconductor substrate 201 including a plurality of regions having different thicknesses, the first regions may be provided to reduce coupling capacitance with a plurality of metal lines LM 1 and LM 2 disposed thereunder. On the other hand, the second regions may be provided to maintain the total resistance of the first semiconductor substrate 201. For example, thicknesses of the first regions and the second regions of the first semiconductor substrate 201 may be adjusted by a target resistance value of the first semiconductor substrate 201. For example, the target resistance value may be a resistance value of the first semiconductor substrate 101 in the memory device 100 illustrated in FIG. 3 when a lower surface of the first semiconductor substrate 101 is disposed on a reference line RL, which is an imaginary line. For example, in the memory device 200 according to an exemplary embodiment, the first semiconductor substrate 201 may include a lower surface having a plurality of regions each having a lower surface formed to be higher or lower than the virtual reference line RL.In the memory device 200 illustrated in FIG. 5, at least two upper metal lines LM 2 may be disposed below a first region and another first region adjacent to the first region. However, this is only an example, and the present disclosure is not limited thereto, and the first semiconductor substrate 201 and the plurality of upper metal lines LM 2 may be arranged in various ways according to exemplary embodiments.FIG. 6 is a view illustrating a method of adjusting a coupling capacitance in a memory device according to an example embodiment.FIG. 6 is a schematic enlarged view of the region 200A illustrated in FIG. 5. For example, the memory device 200 according to an exemplary embodiment may include a common source line CSL having a stepped / curved bottom surface. A curvature of the lower surface of the common source line CSL may be defined based on a reference line RL corresponding to the planar lower surface of the common source line CSL illustrated in FIG. 4A. The degree of curvature and / or the step depth of the lower surface of the common source line CSL may be determined depending on the coupling capacitance to be reduced. For example, a coupling capacitance formed between an upper metal line LM 2 over which a significant / sensitive signal is transmitted and the common source line CSL should be reduced by a certain value and / or held at this or less so that coupling noise for the significant / sensitive signal is held at a predetermined value or less. For example, a space between the upper metal line LM 2 and the common source line CSL needs to be further secured to significantly reduce the coupling capacitance, thereby increasing the degree of curvature (for example, a height of the protrusions or a depth of the recesses).In the enlarged region 200A of the memory device 200 illustrated in FIG. 6, based on a reference line RL, a thickness of the common source line CSL in the first regions a- a' and a thickness of the common source line CSL in the second regions a+a' may be. In a direction parallel to the reference line RL, a total width of the common source line CSL may be "l", and widths of the first region and the second region may be x×1 and (1-x)×l, respectively. In this case, distances between the first and second regions of the common source line CSL and the upper metal line LM 2 disposed below the common source line CSL may be H 1 and H 2, respectively. For example, as described above, the upper metal line LM 2 may be disposed at the first height above the second semiconductor substrate, such that a distance between a lower surface of the common source line CSL and an upper surface of the upper metal line LM 2 in the first region may have a first value H 1. On the other hand, a distance between a lower surface of the common source line CSL and an upper surface of the upper metal line LM 2 in the second region may have a second value H 2 that is smaller than the first value H 1. The upper metal line LM 2 in the first region and the upper metal line LM 2 in the second region may be located on the same plane extending in the horizontal direction. For example, the upper metal line LM 2 in the first region and the upper metal line LM 2 in the second region may be disposed at the same height with respect to a top surface of the second semiconductor substrate. As described above, the magnitude of the total resistance of the common source line CSL should be maintained at a certain level or below regardless of the first value H 1 and the second value H 2, so that the first value H 1 can be decreased as the second value H 2 is increased. In contrast, the first value H 1 may be increased as the second value H 2 is decreased. However, this is only an example, and the present disclosure is not limited thereto, and definitions of the thicknesses and widths of the common source line CSL in the first region and the second region may be changed.In an exemplary embodiment of the memory device 200, the upper metal line LM 2 over which a significant / sensitive signal is transmitted may be disposed below the first region at a relatively large distance from the common source line CSL. A coupling capacitance between the upper metal line LM 2 over which the significant / sensitive signal is transmitted and the first portion of the common source line CSL may be determined by a first value H 1, a distance therebetween. The first value H1 may be determined by a' representing the degree of curvature, and a' may be determined depending on the required amount of coupling capacitance. In order to maintain the performance of the memory device 200, the total resistance of the common source line CSL included in the memory device 200 may be less than or equal to the total resistance of the common source line CSL included in the memory device 100 illustrated in FIG. 4A, as can be seen from Equation 1.In a storage device 200 according to an exemplary embodiment, each of the values "a" and "l" may have a predetermined value. Thus, when a' is determined, "x" can be determined by deriving Equation 2 from Equation 1.For example, when the thickness "a" of the common source line CSL is decreased by about 10% in the first region, the first value H 1, i.e., the distance between the common source line CSL and the upper metal line LM 2, may be increased by about 11% compared to an existing value. In this way, coupling noise generated in a significant / sensitive signal by the common source line CSL may be reduced by about 11%. In this case, in order to prevent the performance of the memory device from being deteriorated by an increase in the total resistance of the common source line CSL, the thickness "a" of the common source line CSL in the second region may be increased by about 10%, and the second value H 2, i.e., the distance between the common source line CSL and the upper metal line LM 2, may also be increased. "x" may be, for example, 0.45. In this case, the common source line CSL may include a first region having a width of x×l corresponding to 45% of the total width "l", and a second region having a width of (1-x)×l corresponding to 55% of the total width "l".However, this is only an example, and the present disclosure is not limited thereto, and a change in the thickness of the common source line CSL and a width of each region may vary. In addition, a method for determining "x" according to the embodiments may vary. For example, when the degree of thickness decrease in the first range is different from the degree of thickness increase in the second range, the degree of thickness decrease in the first range may determine a relationship between the degree of thickness increase in the second range and "x", and "x" may be determined based on this relationship.FIGS. 7 to 11 are cross-sectional views of memory devices according to example embodiments.Referring to FIGS. 7 to 11, storage devices 300, 400,..., and 700 according to example embodiments may include components respectively corresponding to the components of the storage device 200 according to the example embodiment illustrated in FIG. 5. For example, the memory cell regions CELL of each of the memory devices 300, 400,..., and 700 according to an exemplary embodiment may include first semiconductor substrates 301, 401,..., and 701, a plurality of insulating layers 320, 420,..., and 720, a plurality of gate electrodes 330, 430,..., and 730, first conductive layers 304, 404,..., and 704, second conductive layers 305, 405,..., and 705, channel structures CH, and separation regions SR. Peripheral circuit regions PERI of the memory devices 300, 400..., and 700 according to the exemplary embodiments may include second semiconductor substrates 302, 402..., and 702, as well as circuit elements, circuit contact plugs, and a plurality of metal lines LM 1 and LM 2 disposed over the semiconductor substrates 302, 402..., and 702, respectively.Similar to the memory device 200 illustrated in FIG. 5, the memory devices 300, 400,..., and 700 according to the exemplary embodiments may include plate-shaped first semiconductor substrates 301, 401,..., and 701 each having curved lower surfaces. However, a shape of the curvature may be different for each example embodiment and may be determined considering the selection of a curvature and the degree of process difficulty and performance improvement overall. As described above, the first semiconductor substrates 301, 401..., and 701, the first conductive layers 304, 404..., and 704, and the second conductive layers 305, 405..., and 705 may be defined as a common source line. The first semiconductor substrates 301, 401..., and 701 may be defined with reference to an overall configuration disposed adjacent to the first semiconductor substrates 301, 401..., and 701 to function as a common source line.The memory devices 300, 400..., and 700 according to example embodiments may include a plurality of upper metal lines LM 2 extending in a second direction (a Y direction) parallel to the second semiconductor substrate 302, 402..., and 702, respectively. The plurality of upper metal lines LM 2 may be disposed at a first height above the second semiconductor substrates 302, 402..., and 702, and a plurality of lower metal lines LM 1 may be disposed at a second height lower than the first height. For example, a first signal may include a reference voltage for operation of the memory devices 300, 400..., and 700 according to example embodiments. The first signal may include, for example, a band gap reference signal.Each of the first semiconductor substrates 301, 401..., and 701 may include first regions in which a distance between a lower surface thereof and an upper surface of the plurality of upper metal lines LM 2 has a first value, and second regions having a second value (distance) less than the first value. For example, the thickness of the first regions may be less than the thickness of the second regions. The first regions and the second regions may be arranged alternately in a third direction.Of the plurality of upper metal lines LM 2, first metal lines through which the first signal is transmitted may be disposed below the first regions. A first coupling capacitance may be formed between the first semiconductor substrates 301, 401..., and 701 and the first metal lines, and a second coupling capacitance may be formed between the first semiconductor substrates 301, 401..., and 701 and the second metal lines. For example, the first coupling capacitance for the first metal lines arranged below the first regions may be lower than the second coupling capacitance for the second metal lines. However, this is only an example, and the present disclosure is not limited thereto, and second coupling capacitances smaller than the first coupling capacitances may also be formed.Referring to FIG. 7, in the memory device 300 according to an exemplary embodiment, a distance between a pair of first regions adjacent in a third direction from the first regions may be equal to a distance between a pair of upper metal lines adjacent in the third direction from the plurality of upper metal lines LM 2. For example, in each of the first regions arranged alternately with the second regions, a single upper metal line LM 2 may be arranged. Of all the upper metal lines LM 2, one or more upper metal lines LM 2 may be first metal lines through which the first signal is transmitted. Accordingly, a coupling capacitance for all the upper metal lines LM 2 can be reduced. However, the lower surface of the first semiconductor substrate 301 is not limited to the shape shown in FIG. 7, but may be formed in various shapes. For example, a pair of adjacent first regions of the first regions and a pair of adjacent second regions of the second regions may each have the same length in the third direction. For example, the plurality of first regions may be the same as the plurality of second regions. For example, the sum of the lengths of the plurality of first regions in the third direction may be equal to the sum of the lengths of the plurality of second regions in the third direction.Referring to FIG. 8, in the memory device 400 according to an exemplary embodiment, at least some of the first and second regions arranged alternately in a third direction (for example, an X direction) may have different lengths. For example, in a memory device 200 according to the embodiment illustrated in FIG. 5, at least two upper metal lines LM 2 may be disposed below a portion between a pair of first regions adjacent in the third direction among the first regions. For example, in an embodiment of the present disclosure, as illustrated in FIG. 5, a second region located between two adjacent first regions may vertically overlap two or more upper metal lines LM 2. In the memory device 400 according to an exemplary embodiment, the first regions arranged alternately with the second regions may have different lengths in the third direction. Similarly, the second regions may have different lengths from each other. For example, some of the first regions and the second regions may have a length X 1 in the third direction, and other regions of the first regions and the second regions may have a length X 2 in the third direction different from the length X 1. Accordingly, one of the plurality of upper metal lines LM 2 may be disposed below some of the first regions, and at least two upper metal lines LM 2 may be disposed below other regions. For example, some of the first regions may vertically overlap with one upper metal line LM 2, and some other of the first regions may vertically overlap with two upper metal lines LM 2. In the storage device 400 according to an exemplary embodiment illustrated in FIG. 8, at least one of the first regions may be adjacent to a second region having the same length on a first side in the third direction, and may be adjacent to a second region having a different length on a second side in the third direction. However, the present disclosure is not limited to the diagram in FIG. 8, and the first regions and the second regions may be formed in various combinations and methods based on the contents of the present specification.Referring to FIG. 9, in the storage device 500 according to an exemplary embodiment, a first region and a second region that are adjacent to each other may have different lengths in a third direction. For example, a thickness of the first regions may be decreased in a first direction with respect to the reference line RL, and a thickness of the second regions may be increased in the first direction with respect to the reference line RL. As illustrated in FIGS. 5 to 8, the thickness reduced in the first regions and the thickness increased in the second regions are illustrated as being the same, but the present disclosure is not limited thereto. For example, as described with reference to FIG. 6, the increased or decreased thickness in the first regions and the second regions and lengths of the first regions and the second regions in the third direction may be in a predetermined relationship to each other. For example, the first regions and the second regions may be formed such that the total resistance of the first semiconductor substrate 401 is less than or equal to a predetermined value.A first semiconductor substrate 501 included in the memory device 500 according to the exemplary embodiment of FIG. 9 may have a thickness that is a reference thickness (for example, an average thickness) "a" decreased by "a 1" in the first regions and is a reference thickness "a" increased by "a 2" in the second regions, and the thickness increase "a 2" may be larger than the thickness decrease "a 1." In a third direction, a length "b 1" of the first regions may be larger than a length "b 2" of the second regions. Therefore, the first regions and the second regions may have different shapes, but may be formed so that the magnitude of the total resistance of the first semiconductor substrate 501 remains less than or equal to an existing magnitude. However, the present disclosure is not limited to the illustration in FIG. 9, and the first regions and the second regions may be formed in various shapes.Referring to FIGS. 10 and 11, the memory devices 600 and 700 according to example embodiments may further include third regions in which a distance between a predetermined height at which a lower surface of the semiconductor substrates 601 and 701 is disposed and a first height above the second semiconductor substrates 602 and 702 has a third value between a first value and a second value. For example, a thickness of each of the first semiconductor substrates 601 and 701 in the third regions may have a value between the thickness of the first regions and the thickness of the second regions. The third regions may be formed such that the third value continuously changes in the third direction. For example, the thickness of the third regions of the first semiconductor substrates 601 and 701 may vary along the third direction. For example, the storage device 600 according to an exemplary embodiment of FIG. 10 may include third ranges in which the third value continuously changes based on a constant rate of change. Accordingly, the first semiconductor substrate 601 may have a lower surface inclined in the third regions. On the other hand, the storage device 700 according to the embodiment of FIG. 11 may include third regions in which the third value continuously varies in a wave shape. For example, the first semiconductor substrate 701 may have a curved (e.g. wave-shaped) lower surface in the third regions. However, this is only an example, and the present disclosure is not limited thereto, and the third regions may be formed in consideration of a process difficulty and a performance improvement of the storage device in general.FIGS. 12 and 13 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 11.FIG. 12 is a perspective view showing a common source line CSL included in the memory device 700 according to an exemplary embodiment illustrated in FIG. 11, and a plurality of upper metal lines 11, 12,..., and 18 disposed below the common source line CSL. FIG. 13 is a bottom view of the embodiment of FIG. 12 as viewed in the direction A.Referring to FIGS. 12 and 13, a plurality of upper metal lines l 1, l 2..., and l 8 may be disposed below first regions to secure a space as large as possible with the common source line CSL. As described above, the first metal lines, over which a first signal containing a significant / sensitive signal is transmitted, may be arranged below the first regions in order to significantly reduce the coupling noise for the first signal. Accordingly, at least one of the plurality of upper metal lines l 1, l 2..., and l 8 may include the first metal lines. The remaining ones of the plurality of upper metal lines 11, 12,..., and l8 may include a second metal line through which a second signal is transmitted. However, this is only an example, and the present disclosure is not limited thereto.FIG. 14 is a cross-sectional view of a memory device according to an example embodiment.Referring to FIG. 14, a storage device 800 according to an exemplary embodiment may include components respectively corresponding to the components of the storage device 700 according to an exemplary embodiment illustrated in FIG. 11. For example, a memory cell region CELL of the memory device 800 according to an example embodiment may include a first semiconductor substrate 801, a plurality of insulating layers 820, a plurality of gate electrodes 830, a first conductive layer 804, a second conductive layer 805, channel structures CH, and a separation region SR. A peripheral circuit region PERI of the memory device 800 according to an exemplary embodiment may include a second semiconductor substrate 802, and circuit elements, circuit contact plugs, and a plurality of metal lines LM 1 and LM 2 disposed over the second semiconductor substrate 802.Similar to the memory device 700 according to an exemplary embodiment illustrated in FIG. 11, the memory device 800 according to an exemplary embodiment may include a plate-shaped first semiconductor substrate 801 curved to have a continuously changed thickness. As described above, in the memory device 700, a distance between a first region and another first region adjacent to the first region may be equal to a distance between two adjacent upper metal lines LM 2 of a plurality of upper metal lines LM 2. Unlike the memory device 700, in the memory device 800 according to an exemplary embodiment illustrated in FIG. 14, at least two upper metal lines LM 2 may be disposed below a portion between a first region and another first region adjacent to the first region.FIGS. 15 and 16 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 14.FIG. 15 is a view showing a common source line CSL included in the memory device 800 according to an exemplary embodiment illustrated in FIG. 14, and a plurality of upper metal lines m 1, m 2..., and m 9 disposed below the common source line CSL. FIG. 16 is a bottom view of the embodiment of FIG. 15 as viewed in the direction A.Referring to FIGS. 15 and 16, the plurality of upper metal lines m 1, m 2..., and m 8 may be disposed below the common source line CSL. Unlike the memory device 700 according to an exemplary embodiment illustrated in FIG. 11, some of the plurality of upper metal lines m 1, m 2,..., and m 8 may be disposed below first regions, and the rest thereof may be disposed below second regions or third regions. For example, of the plurality of upper metal lines m 1, m 2..., and m 8, the metal lines m 3, m 6, and m 9 arranged below the first regions may be included in a first group. Of the plurality of upper metal lines m 1, m 2.., and m 8, the metal lines m 2, m 4, m 5, m 7, and m 8 disposed below the second regions may be included in a second group.First metal lines, via which a first signal containing a significant / sensitive signal is transmitted, may be arranged below the first areas in order to significantly reduce the coupling noise for the first signal. Accordingly, at least one of the metal lines m 3, m 6, and m 9 included in the first group may include or be the first metal lines. Of the metal lines m 3, m 6, and m 9 included in the first group, the rest may include a second metal line through which a second signal is transmitted. Moreover, at least one of the metal lines m 1, m 2, m 4, m 5, m 7, and m 8 included in the second group may include the second metal line. However, this is only an example and the present disclosure is not limited thereto, and according to certain embodiments, the first metal lines may be disposed in a portion of the third regions instead of the first regions. Moreover, the plurality of upper metal lines m 1, m 2..., and m 8 may not include the first metal lines.FIG. 17 is a cross-sectional view of a memory device according to an example embodiment.Referring to FIG. 17, a storage device 900 according to an exemplary embodiment may include components respectively corresponding to the components of the storage device 800 according to an exemplary embodiment illustrated in FIG. 14. For example, a cell region CELL of the memory device 900 according to an example embodiment may include a first semiconductor substrate 901, a plurality of insulating layers 920, a plurality of gate electrodes 930, a first conductive layer 904, a second conductive layer 905, a channel structure CH, and a separation region SR. In addition, a peripheral circuit region PERI of the memory device 900 according to an exemplary embodiment may include a second semiconductor substrate 902 and circuit elements, circuit contact plugs, and a plurality of metal lines LM 1 and LM 2 disposed over the second semiconductor substrate 902.Similar to the memory device 800 according to an exemplary embodiment illustrated in FIG. 14, the memory device 900 according to an exemplary embodiment may include a plate-shaped first semiconductor substrate 901 curved to have a continuously changed (e.g., varying) thickness. However, an extending direction of the plurality of metal lines LM 1 and LM 2 included in the memory device 800 according to the embodiment illustrated in FIG. 14 and an extending direction of the plurality of metal lines included in the memory device 900 according to the embodiment illustrated in FIG. 17 may be perpendicular to each other, for example, with respect to other elements / circuits formed in the memory devices 800 and 900. For example, in the memory device 800 according to an exemplary embodiment illustrated in FIG. 14, a plurality of upper metal lines LM 2 may extend in a second direction, and a plurality of lower metal lines LM 1 may extend in a third direction that is perpendicular to the second direction. On the other hand, in the memory device 900 according to an exemplary embodiment illustrated in FIG. 17, a plurality of upper metal lines LM 2 may extend in a third direction, and a plurality of lower metal lines LM 1 may extend in a second direction.Accordingly, according to an exemplary embodiment, unlike the memory device 800 in which at least two upper metal lines LM 2 may be disposed below a portion between mutually adjacent first regions, the memory device 900 may include at least two lower metal lines disposed below a portion between mutually adjacent first regions. However, this is only an example, and the present disclosure is not limited thereto. Moreover, the first metal lines through which a first signal including a significant / sensitive signal is transmitted may be included in at least one of the plurality of metal lines LM 1 and LM 2, but the present disclosure is not limited thereto.FIGS. 18 and 19 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 17.FIG. 18 may be a view showing a common source line CSL included in the memory device 900 according to an exemplary embodiment in FIG. 17 and a plurality of upper metal lines n1', n2' and n3' arranged below the common source line CSL. FIG. 19 may be a bottom view of the embodiment of FIG. 18 when viewed in the direction A.Referring to FIGS. 18 and 19, a plurality of upper metal lines n1', n2' and n3' may be disposed below the common source line CSL. However, unlike the memory devices 700 and 800 according to the embodiments of FIGS. 11 and 14, the plurality of upper metal lines n1', n2' and n3' may extend in a third direction in which first regions and second regions are alternately arranged. For example, the plurality of upper metal lines n1', n2' and n3' may be arranged to cross under the first regions, the second regions and the third regions. In this case, at least one of the plurality of upper metal lines n1', n2' and n3' may include a first metal line through which a first signal is transmitted, and the rest of the plurality of upper metal lines n1', n2' and n3' may include a second metal line through which a second signal is transmitted. However, this is only an example, and the present disclosure is not limited thereto, and the plurality of upper metal lines n1', n2' and n3' may not include the first metal line over which the first signal is transmitted. For example, the plurality of upper metal lines n1', n2' and n3' may all be second metal lines through which the second signal is transmitted.In order to significantly reduce coupling noise for the first signal including a significant / sensitive signal, the positions of the first metal lines over which the first signal is transmitted may be determined in consideration of a placement relationship of adjacent metal lines and elements. For example, a first coupling capacitance may be formed between the first metal lines and the first regions of the first semiconductor substrate 901, and a second coupling capacitance may be formed between the second metal lines and the second regions of the first semiconductor substrate 901. For example, the first coupling capacitance may be smaller than the second coupling capacitance. The memory device 900 according to an exemplary embodiment may reduce the first coupling capacitance to reduce the coupling noise for the first signal. Therefore, considering the placement relationship of adjacent metal lines and elements, one metal line among the plurality of upper metal lines n1', n2' and n3' capable of effectively reducing the first coupling capacitance can be used as the first metal line.FIGS. 20 and 21 are a schematic perspective view and a schematic bottom view, respectively, of the storage device according to an exemplary embodiment illustrated in FIG. 17.FIG. 20 shows a common source line CSL included in the memory device 900 according to an exemplary embodiment illustrated in FIG. 17, and a plurality of upper metal lines n1', n2' and n3' arranged below the common source line CSL, and a plurality of lower metal lines n1, n2,..., and n9 arranged below the plurality of upper metal lines n1', n2' and n3'. FIG. 21 may be a bottom view of the embodiment of FIG. 20 as viewed in direction A.Referring to FIGS. 20 and 21, a plurality of upper metal lines n1', n2' and n3' may be disposed below the common source line CSL and correspond to the plurality of upper metal lines n1', n2' and n3' shown in FIGS. 18 and 19, respectively. However, the memory device 900 according to an exemplary embodiment may also include a plurality of lower metal lines n 1, n 2,..., and n 9 arranged at a second height lower than a first height at which a plurality of upper metal lines n 1', n 2', and n 3' are arranged and extend in a second direction perpendicular to a direction in which the plurality of upper metal lines n 1', n 2', and n 3' extend. For example, in order to prevent an operation problem of a memory device from occurring due to coupling noise, the plurality of upper metal lines n1', n2' and n3' arranged to be near the common source line CSL may not include a first upper metal line over which a first signal including a significant / sensitive signal is transmitted. However, this is only an example, and at least one of the plurality of upper metal lines n1', n2' and n3' may include the first upper metal line.The plurality of lower metal lines n 1, n 2..., and n 9 may include a first lower metal line through which a first signal is transmitted and a second lower metal line through which a second signal is transmitted. For example, the first lower metal line may be arranged below the first regions and the second lower metal line may be arranged below the second regions or the third regions. Accordingly, at least one of the lower metal lines n 3, n 6, and n 9 included in a first group may include the first lower metal line. The remaining ones of the lower metal lines n 3, n 6, and n 9 included in a first group may include a second lower metal line through which the second signal is transmitted. Moreover, at least one of the lower metal lines m 1, m 2, m 4, m 5, m 7, and m 8 included in a second group may include a second lower metal line through which the second signal is transmitted. However, this is only an exemplary embodiment, and the present disclosure is not limited thereto. According to example embodiments, the first metal lines may be disposed in a portion of the third regions instead of the first regions.A first coupling capacitance formed between the common source line CSL and the first lower metal line may be less than a second coupling capacitance formed between the common source line CSL and the second lower metal line. A structure of the lower surface of the common source line CSL may not be limited to that illustrated in FIGS. 20 and 21. For example, at least some of the alternately arranged first and second regions may have different lengths in a third direction in which the plurality of upper metal lines n1', n2' and n3' extend.As described above, in a memory device according to an exemplary embodiment, the distance between a common source line and a metal line opposing the common source line may be adjusted based on a curvature of a bottom surface of the common source line. A placement of the metal line may vary depending on the meaning of a signal applied to the metal line. In this way, the effect of the coupling capacitance on a significant / sensitive signal from the common source line can be reduced.Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present inventive concept as defined by the appended claims.

Claims

A memory device comprising: a memory cell region (CELL) including a first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901), gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) spaced apart from each other on the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) such that they are stacked in a first direction (Z) perpendicular to an upper surface of the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901), and channel structures (CH) penetrating the gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) and electrically connected to the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901); and a peripheral circuit region (PERI) including a second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) disposed below the memory cell region (CELL), an interlayer insulating film, and a plurality of upper metal lines (LM2) disposed above the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) in the interlayer insulating film at a first height so as to extend in a second direction (Y) parallel to an upper surface of the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902), wherein the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) includes first regions having a first distance (H1) between a bottom surface thereof and the first height, and second regions having a second distance (H2) between the bottom surface thereof and the first height, wherein the second distance (H2) is shorter than the first distance (H1), wherein the second regions are formed on recessed portions of the interlayer insulating film, and wherein first upper metal lines of the plurality of upper metal lines (LM2) are disposed below the first regions, and at least one of the first upper metal lines is configured to transmit a reference voltage for driving the memory cell region (CELL) and the peripheral circuit region (PERI).The memory device of claim 1, wherein the reference voltage includes a band gap reference signal (BGR).The memory device according to claim 1 or 2, wherein the first regions and the second regions are laterally arranged in the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) and are alternately arranged in a third direction (X) perpendicular to the second direction (Y).The memory device according to claim 3, wherein at least two of the plurality of upper metal lines (LM2) are disposed below a portion between a pair of first regions among the first regions adjacent to each other in the third direction.The memory device according to claim 3 or 4, wherein at least some of the first regions and the second regions have different lengths in the third direction (X).The storage device according to any one of claims 1 to 5, wherein the number of the first areas is the same as the number of the second areas.The memory device according to any one of claims 1 to 6, wherein the first semiconductor substrate (601; 701) further includes third regions having a third distance between a bottom surface of the first semiconductor substrate and the first height, the third distance being between the first distance (H1) and the second distance (H2), and the first semiconductor substrate has an inclined bottom surface (601; 701) in the third regions.The memory device according to any one of claims 1 to 7, wherein a length of the first regions in a third direction (X) parallel to the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) and the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) and perpendicular to the second direction (Y) is determined based on the first distance (H1) and the second distance (H2).A memory device comprising: a memory cell region (CELL) including a first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901); gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) spaced apart from each other on the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) such that they are stacked in a first direction (Z) perpendicular to an upper surface of the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901); and channel structures (CH) penetrating the gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) and disposed in a recessed portion of the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901); and a peripheral circuit region (PERI) including a second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) disposed below the memory cell region (CELL), an interlayer insulating layer, a plurality of lower metal lines (LM1) disposed in the interlayer insulating layer above the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) at a predetermined height so as to be parallel to an upper surface of the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802) in a second direction (Y); 902), and a plurality of upper metal lines (LM2) arranged between the plurality of lower metal lines (LM1) and the first semiconductor substrate so as to extend in a third direction (X) parallel to an upper surface of the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) and perpendicular to the second direction (Y), wherein the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) includes first regions having a first distance (H1) between a lower surface thereof (201; 301; 401; 501; 601; 701; 801; 901; 901) and an upper surface of first upper metal lines of the plurality of upper metal lines (LM 2), and second regions having a second distance (H 2) between a lower surface thereof and an upper surface of second upper metal lines of the plurality of upper metal lines (LM 2), the second distance (H 2) being shorter than the first distance (H 1), the second regions being formed on recessed portions of the interlayer insulating layer, the first upper metal lines and the second upper metal lines being at the same height with respect to an upper surface of the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902), and the first regions and the second regions being alternately arranged in the third direction (X).A memory device comprising: a first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) including first regions having a first thickness and second regions having a second thickness larger than the first thickness; a second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902) disposed below the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) so as to overlap the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) in a first direction (Z) perpendicular to an upper surface of the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901); an interlayer insulating layer disposed between the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 801; 901) and the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902); a plurality of metal lines (LM1, LM2) arranged in the interlayer insulating film so as to extend in a direction (X, Y) parallel to an upper surface of the second semiconductor substrate (202; 302; 402; 502; 602; 702; 802; 902), and include first metal lines configured to transmit a band gap reference signal via the first metal lines; gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) spaced apart from each other on the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901) so as to be stacked in the first direction (Z); insulating films (220; 320; 830; 420; 520; 620; 720; 820; 920) alternately stacked with the gate electrodes (230; 330; 430; 530; 630; 730; 830; 930); and channel structures (CH) penetrating the gate electrodes (230; 330; 430; 530; 630; 730; 830; 930) and the insulating layers (220; 320; 420; 520; 620; 720; 820; 920) and arranged in a recessed portion of the first semiconductor substrate (201; 301; 401; 501; 601; 701; 801; 901), wherein the first metal lines are arranged below the first regions, and wherein the second regions are formed on recessed portions of the intermediate insulating layer.

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