Reverse conducting semiconductor device and method of manufacturing a reverse conducting semiconductor device

Abstract

Reverse conducting semiconductor device (100-109), which has: - a region (10) of an insulated gate bipolar transistor and a diode region (20), - a semiconductor substrate (50): - which is contained in the region (10) of an insulated gate bipolar transistor and the diode region (20) and - which has: - a first main surface (F1) and a second main surface (F2) opposite the first main surface, - a drift layer (1) extending over the insulated gate bipolar transistor region (10) and the diode region (20) and having a first conductivity type, - a base layer (15) arranged between the drift layer (1) and the first main surface (F1) in the region (10) of an insulated gate bipolar transistor, the base layer (15) having a second conductivity type different from the first conductivity type, - an emitter layer (13) arranged between the base layer (15) and the first main surface (F1) in the region (10) of an insulated gate bipolar transistor, the emitter layer (13) having the first conductivity type, - a base contact layer (14) arranged between the base layer (15) and the first main surface (F1) in the region (10) of an insulated gate bipolar transistor, the base contact layer (14) forming part of the first main surface (F1), the base contact layer (14) having the second conductivity type, - a collector layer (16) arranged between the drift layer (1) and the second main surface (F2) in the region (10) of an insulated gate bipolar transistor, the collector layer (16) having the second conductivity type, - an anode layer (25) arranged between the drift layer (1) and the first main surface (F1) in the diode region (20), the anode layer (25) having the second conductivity type, - an anode contact region (24) arranged between the anode layer (25) and the first main surface (F1) in the diode region (20), wherein the anode contact region (24) forms part of the first main surface (F1), the anode contact region (24) has a peak value of a concentration of impurities of the second conductivity type which is higher than that of the anode layer (25), the anode contact region (24) has the second conductivity type, and - a cathode layer (26) arranged between the drift layer (1) and the second main surface (F2) in the diode region (20), the cathode layer (26) having the first conductivity type; - an insulated gate structure (11) for forming a channel with the base layer (15) to control an electrical path between the emitter layer (13) and the drift layer (1); - a collector electrode (7) electrically connected to the collector layer (16) and the cathode layer (26); and - an emitter electrode (5) in contact with the base contact layer (14) and the anode contact region (24), where: - the anode contact region (24) contains a first anode contact layer (24b) which has a concentration of impurities of the first conductivity type and a concentration of impurities of the second conductivity type, - the concentration of impurities of the second conductivity type of the first anode contact layer (24b) is higher than the concentration of impurities of the first conductivity type of the first anode contact layer (24b), so that the first anode contact layer (24b) has the second conductivity type, - the concentration of impurities of the first conductivity type of the first anode contact layer (24b) is higher than that of the base contact layer (14) and - the first anode contact layer (24b) has a lower net concentration than that of the base contact layer (14).

Description

BACKGROUND OF THE INVENTIONField of the InventionThe present invention relates to a reverse conductive semiconductor device and a method of manufacturing the reverse conductive semiconductor device.Description of Background ArtFrom the viewpoint of energy saving, an insulated gate bipolar transistor (IGBT) and a free wheeling diode are used for a power module or the like that performs variable speed control of a three-phase motor in the fields of general-purpose inverters, AC servomotors, and the like. In this case, the use of a reverse conducting semiconductor device having an IGBT region and a diode region, that is, a reverse conducting IGBT (RC-IGBT), enables the area occupied by the IGBT and the diode in the power module to be reduced as compared with the use of both the semiconductor device and the IGBT and the semiconductor device as the free wheeling diode (diode for reverse conduction). Therefore, the size of the power module can be reduced.For example, WO 2014 / 097 454 A1 discloses a semiconductor device in which an IGBT region and a diode region are formed on the same semiconductor substrate. The IGBT region includes a collector layer, an IGBT drift layer, a gate electrode, an emitter layer, a body layer, and a high impurity concentration body contact layer. The diode region includes a trench electrode, a diode drift layer, a cathode layer, an anode layer, and a high impurity concentration anode contact layer. The diode region is divided into unit diode regions by a gate electrode or a trench electrode. In the unit diode region adjacent to the IGBT region, when the surface of the semiconductor device is viewed in plan view, the anode layer and the anode contact layer are mixedly arranged, and the anode contact layer is arranged at least at a position opposite to the emitter layer via the gate electrode. In this semiconductor device, in the unit diode region adjacent to the IGBT region, the anode contact layer is not entirely formed but partially formed. With such a configuration, the injection amount of holes from the anode contact layer to the diode drift layer during diode operation is reduced. Consequently, recovery loss in the diode region can be reduced.From the viewpoint of manufacturing efficiency of the semiconductor device, it is preferable to form the anode contact layer and the body contact layer together by a common ion implantation step. In this case, the anode contact layer and the body contact layer have substantially the same impurity concentration. As the impurity concentration is increased, the injection amount of holes increases from the anode contact layer to the diode drift layer, so that recovery loss in the diode region increases. Conversely, if the impurity concentration is made lower, the latch-up tolerance in the IGBT region tends to become insufficient. In order to improve this conflict of goals, it is expedient to set the impurity concentration of the anode contact layer lower than the impurity concentration of the body contact layer. On the other hand, in order to provide such a concentration difference, it is usually necessary to greatly complicate the step of impurity doping, and as a result, the manufacturing cost is greatly increased.JP 2013-048 230 A relates to semiconductor devices configured to reduce loss at the time of switching in a diode. A diode described therein includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a blocking region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a higher concentration than that of the drift region, and a pillar region formed to connect the blocking region to the anode electrode and made of a first conductivity type semiconductor having a higher concentration than that of the blocking region. The pillar region and the anode are connected via a Schottky junction.US 2014 / 0 070 270 A1 discloses an IGBT and a diode which can be formed on the same semiconductor substrate with improved electrical properties. An IGBT region and an FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals on the front side of an n-type semiconductor substrate and p-type channel regions at predetermined intervals in the longitudinal direction of the trench between adjacent trenches, thereby configuring a MOS gate. The p-type channel region and the n-type drift region are alternately arranged in the longitudinal direction of the trench in the IGBT region. The p-type channel region and a p-type spacer region are alternately arranged in the longitudinal direction of the trench in the FWD region. A longitudinal distance of the trench of the p-type channel region in the IGBT region is shorter than the longitudinal distance of the trench of the p-type channel region in the FWD region.WO 2020 / 012 605 A1 discloses a semiconductor component with a low turn-on voltage and low production costs. This known semiconductor device includes a semiconductor layer having a drift layer, a semiconductor region having a collector region disposed in a first direction in an IGBT region adjacent to the semiconductor layer, and a cathode region disposed in a first direction in an FWD region adjacent to the semiconductor layer. The collector region is an epitaxial growth layer. The thickness of the cathode region is greater than the thickness of the collector region.SUMMARYThe present invention has been made to solve the above problems, and an object of the present invention is to provide a reverse conductive semiconductor device having a high latch-up tolerance and a low recovery loss while avoiding a significant increase in manufacturing cost.The object on which the invention is based is achieved in a reverse-conducting semiconductor device according to the invention with the features of claim 1 and in a method for producing a reverse-conducting semiconductor device according to the invention with the features of claim 11. Advantageous refinements are the subject matter of the respective dependent claims.A reverse conducting semiconductor device comprising an insulated gate bipolar transistor region and a diode region according to the present invention comprises a semiconductor substrate, an insulated gate structure, a collector electrode and an emitter electrode. The semiconductor substrate is included in the insulated gate bipolar transistor region and the diode region and has a first main surface and a second main surface opposite the first main surface. The semiconductor substrate includes a drift layer having a first conductivity type, a base layer having a second conductivity type different from the first conductivity type, an emitter layer having the first conductivity type, a base contact layer having the second conductivity type, a collector layer having the second conductivity type, an anode layer having the second conductivity type, an anode contact region having the second conductivity type, and a cathode layer having the first conductivity type. The drift layer extends over the region of an insulated gate bipolar transistor and the diode region. The base layer is arranged between the drift layer and the first main surface in the region of an insulated gate bipolar transistor. The emitter layer is arranged between the base layer and the first main surface in the region of an insulated gate bipolar transistor. The base contact layer is arranged between the base layer and the first main surface in the region of an insulated gate bipolar transistor and forms part of the first main surface. The collector layer is arranged between the drift layer and the second main surface in the region of an insulated gate bipolar transistor. The anode layer is arranged between the drift layer and the first main surface in the diode region. The anode contact region is disposed between the anode layer and the first main surface in the drift region, forms a part of the first main surface, and has a peak value of a concentration of impurities of the second conductivity type higher than that of the anode layer. The cathode layer is arranged between the drift layer and the second main surface in the diode region. The insulated gate structure is formed to form a channel with the base layer to control an electrical path between the emitter layer and the drift layer. The collector electrode is electrically connected to the collector layer and the cathode layer. The emitter electrode is in contact with the base contact layer and the anode contact region.The anode contact region includes a first anode contact layer having a concentration of impurities of the first conductivity type and a concentration of impurities of the second conductivity type, wherein the concentration of impurities of the second conductivity type of the first anode contact layer is higher than the concentration of impurities of the first conductivity type of the first anode contact layer, such that the first anode contact layer has the second conductivity type. The concentration of impurities of the first conductivity type of the first anode contact layer is higher than that of the base contact layer. The first anode contact layer has a lower net concentration than that of the base contact layer.A method of manufacturing a reverse conductive semiconductor device to manufacture the reverse conductive semiconductor device described above includes: a step of performing doping of impurities of the first conductivity type of an emitter layer by ion implantation into a first main surface of a semiconductor substrate; and a step of performing doping of impurities of the first conductivity type of a first anode contact layer by ion implantation into the first main surface of the semiconductor substrate. The step of performing impurity doping of the first conductivity type of the emitter layer and the step of performing impurity doping of the first conductivity type of the first anode contact layer are simultaneously performed as a step of co-doping impurities of the first conductivity type.According to the reverse conducting semiconductor device of the present invention, it is possible to achieve high latch-up tolerance and low recovery loss while avoiding significant increase in manufacturing cost.These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a plan view schematically illustrating a configuration of a reverse conductive semiconductor device according to a first preferred embodiment. FIG. 2 is a partial plan view schematically illustrating a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate in a region II in FIG. 1 ; FIG. 3 is a partial cross-sectional view taken along a line III-III in FIG. 2 ; FIG. 4 is a partial cross-sectional view taken along a line IV-IV in FIG. 2 ; FIG. 5 is a partial cross-sectional view taken along a line V-V in FIG. 2 ; FIG. 6 is a partial cross-sectional view taken along a line VI-VI in FIG. 1 ; FIG. 7 is a partial cross-sectional view taken along a line VII-VII in FIG. 1 ; FIG. 8 is a flowchart schematically illustrating a method of manufacturing the reverse conductive semiconductor device in FIG. 1 ; FIG. 9 is a partial cross-sectional view schematically illustrating a step in the manufacturing method in FIG. 8 according to a cross section common to lines III-III, IV-IV, and V-V in FIG. 2 ; FIG. 10 is a partial cross-sectional view schematically illustrating a step in the manufacturing method in FIG. 8 according to a cross section common to lines III-III, IV-IV, and V-V in FIG. 2 ; FIG. 11 is a partial cross-sectional view schematically illustrating a step in the manufacturing method in FIG. 8 corresponding to a cross-section taken along line III-III in FIG. 2 ; FIG. 12 is a partial cross-sectional view schematically illustrating the step in FIG. 11 corresponding to the cross section common to the lines IV-IV and V-V in FIG. 2 ; FIG. 13 is a partial cross-sectional view schematically illustrating a step in the manufacturing method in FIG. 8 corresponding to a cross-section taken along line III-III in FIG. 2 ; FIG. 14 is a partial cross-sectional view schematically illustrating the step in FIG. 13 corresponding to a cross-section taken along the line IV-IV in FIG. 2 ; FIG. 15 is a partial cross-sectional view schematically illustrating the step in FIG. 13 corresponding to a cross-section taken along the line V-V in FIG. 2 ; FIG. 16 is a plan view illustrating a modified example of FIG. 1 ; FIG. 17 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to a second preferred embodiment; FIG. 18 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to a third preferred embodiment; FIG. 19 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to a fourth preferred embodiment; FIG. 20 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to a fifth preferred embodiment; FIG. 21 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to a sixth preferred embodiment; FIG. 22 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to a seventh preferred embodiment; FIG. 23 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to an eighth preferred embodiment; FIG. 24 is a partial plan view schematically illustrating, in a view similar to FIG. 2, a configuration of a reverse conductive semiconductor device along a first main surface of a semiconductor substrate according to a ninth preferred embodiment; FIG. 25 is a graph illustrating an example of a concentration profile of a semiconductor substrate included in a reverse conductive semiconductor device according to a tenth preferred embodiment in a depth range of an alternate long and short dash line DD in FIG. 3 ; FIG. 26 is a graph illustrating an example of a measurement result of a relationship between a net peak concentration of an anode layer and a controllable Vcc in a reverse conductive semiconductor device according to the tenth preferred embodiment; FIG. 27 is a graph illustrating an example of a measurement result of a relationship between a net peak concentration of a first anode contact layer and an on-voltage of a diode in a reverse conductive semiconductor device according to the tenth preferred embodiment; FIG. 28 is a graph illustrating an example of a concentration profile of a semiconductor substrate included in a reverse conductive semiconductor device according to an eleventh preferred embodiment in a depth range of an alternate long and short dash line in FIG. 2 ; FIG. 29 is a graph illustrating an example of a concentration profile of a semiconductor substrate included in a reverse conductive semiconductor device according to a twelfth preferred embodiment in a depth range of an alternate long and short dash line in FIG. 2 ; and FIG. 30 is a graph illustrating an example of a concentration profile of a semiconductor substrate included in a reverse conductive semiconductor device according to a thirteenth preferred embodiment in a depth range of an alternate long and short dash line in FIG. 2 ;DESCRIPTION OF THE PREFERRED EMBODIMENTSHereinafter, embodiments will be described with reference to the drawings. It should be noted that, in the following drawings, the same or corresponding parts are denoted by the same reference numerals and the description thereof is not repeated. In some figures, orthogonal xyz coordinate axes are shown for clarity of illustration. In the figure, with respect to the impurity concentration, n - indicates that the net concentration is lower than n + n ++ indicates that the net concentration is higher than n + p + indicates that the net concentration is higher than p, and p ++ indicates that the net concentration is higher than p +.Each of the following preferred embodiments will be described when the first conductivity type is an n-type and the second conductivity type is a p-type, in other words, when the impurities of the first conductivity type are donors and the impurities of the second conductivity type are acceptors. Such selection of the conductivity type is a typical selection to obtain satisfactory characteristics of the IGBT. However, as a variant, the first conductivity type may be a p-type and the second conductivity type may be an n-type, and in this variant, it should be understood that the donor and the acceptor are interchanged with each other in the present description.Moreover, in the present specification, the net concentration means the absolute value of the difference between the donor concentration and the acceptor concentration, and the net peak concentration means the peak value of the net concentration in the mentioned range. In addition, the numerical value of the concentration is represented by the number of atoms per unit volume.< Preferred Embodiment>(Outline of Configuration)FIG. 1 is a plan view schematically illustrating a configuration of an RC-IGBT 100 (reverse conductive semiconductor device) according to the present first preferred embodiment. The RC-IGBT 100 includes, as a planar layout (layout in the XY plane), an IGBT region 10, a diode region 20, a termination region 30, and a pad region 40. Collectively, the IGBT region 10 and the diode region 20 are referred to as a cell region. The pad region 40 is disposed adjacent to the cell region. The pad region 40 is provided with a control pad 41 for controlling the RC IGBT 100. A termination region 30 for holding the withstand voltage of the RC IGBT 100 is disposed around a region including the cell region and the pad region 40.FIG. 2 is a partial plan view schematically illustrating the configuration of the RC-IGBT 100 along the first main surface of the semiconductor substrate 50 in the region II in FIG. 1. FIGS. 3 to 5 are respective partial cross-sectional views taken along lines III-III, IV-IV and V-V in FIG. 2. It should be noted that in FIG. 2, a configuration above the first main surface is not illustrated to facilitate viewing of the image.The RC-IGBT 100 includes a semiconductor substrate 50, an active trench gate 11 (insulated gate structure), a collector electrode 7, and an emitter electrode 5. The semiconductor substrate 50 is included in the IGBT region 10 and the diode region 20, and has an upper surface F 1 (first main surface) and a lower surface F 2 (second main surface opposite to the first main surface). Both the upper surface F 1 and the lower surface F 2 span the IGBT region 10 and the diode region 20, in other words, each of the upper surface F 1 and the lower surface F 2 continuously extends between the IGBT region 10 and the diode region 20.The semiconductor substrate 50 includes an n -- drift layer 1 having an n-type conductivity, a p-type base layer 15, an n-type emitter layer 13, a p ++- base contact layer 14 having a p-type conductivity, a p-type collector layer 16, a p-type anode layer 25, a p-type anode contact region 24, and a cathode layer 26 having an n-type conductivity. The n -- drift layer 1 extends over the IGBT region 10 and the diode region 20.The p-type base layer 15 is disposed between the n -- drift layer 1 and the upper surface F 1 in the IGBT region 10. The n-type emitter layer 13 is disposed between the p-type base layer 15 and the upper surface F 1 in the IGBT region 10. The p ++- base contact layer 14 is disposed between the p-type base layer 15 and the upper surface F 1 in the IGBT region 10, and forms a part of the upper surface F 1. The p-type collector layer 16 is disposed between the n -- drift layer 1 and the lower surface F 2 in the IGBT region 10.The p-type anode layer 25 is disposed between the n -- drift layer 1 and the upper surface F 1 in the diode region 20. The net peak concentration of the p-type anode layer 25 is preferably 1×10 16 / cm 3 or more. In the present preferred embodiment, as illustrated in FIG. 5, the p-type anode layer 25 forms a part of the upper surface F 1. The cathode layer 26 is disposed between the n-type drift layer 1 and the lower surface F 2 in the diode region 20. The anode contact region 24 is disposed between the p-type anode layer 25 and the upper surface F 1 in the diode region 20, and forms a part of the upper surface F 1. The anode contact region 24 has a higher peak value of the acceptor concentration than the p-type anode layer 25.The p-type anode contact region 24 includes a p +- anode contact layer 24 b(first anode contact layer) and a p ++- anode contact layer 24 a(second anode contact layer). The p +- anode contact layer 24 bhas a lower net concentration and a higher donor concentration than the p ++- base contact layer 14. Moreover, the p +- anode contact layer 24 bhas a higher donor concentration than the p ++- anode contact layer 24 a. The net peak concentration of the p +- anode contact layer 24 bis 1×10 18 / cm 3 or more.The gate 11 of an active trench serves to form a channel with the p-type base layer 15 to control an electrical path between the n-type emitter layer 13 and the n -- drift layer 1. The potential of the gate 11 of an active trench is controlled by applying a potential to the gate pad 41 c.The collector electrode 7 is electrically connected to the p-type collector layer 16 and the cathode layer 26. The collector electrode 7 extends over the IGBT region 10 and the diode region 20. In other words, the collector electrode 7 extends continuously between the IGBT region 10 and the diode region 20. the emitter electrode 5 is in contact with the p ++- base contact layer 14 and the anode contact region 24. the emitter electrode 5 extends over the IGBT region 10 and the diode region 20.(Outline of Production Method)In the method of manufacturing the RC-IGBT 100 in the present preferred embodiment, a step of performing donor doping of the n-type emitter layer 13 and a step of performing donor doping of the p +- anode contact layer 24 bare simultaneously performed as a common donor doping step (which will be described below with reference to FIGS. 11 and 12 ). In addition, a step of performing acceptor doping of the p ++- base contact layer 14 and a step of performing acceptor doping of the p +- anode contact layer 24 bare simultaneously performed as a common acceptor doping step (described below with reference to FIGS. 13 to 15 ). The implantation amount of donor ions (impurity ions of the first conductivity type) per unit area in the common donor doping step is lower than the implantation amount of acceptor ions (impurity ions of the second conductivity type) per unit area in the common acceptor doping step. By the donor doping step, the n-type emitter layer 13 is formed, and at the same time, counter-doping is performed to lower the net concentration of the p +- anode contact layer 24b as compared with the net concentration of the p ++- base contact layer 14.(Details of Configuration)Hereinafter, details of the present first preferred embodiment will be described although there is a part overlapping with the description of an overview set forth above.Referring to FIG. 1, both the IGBT region 10 and the diode region 20 extend from one end side to the other end side of the RC IGBT 100, and the IGBT region 10 and the diode region 20 are alternately arranged in a stripe shape in a direction orthogonal to the extending direction. In FIG. 1, three IGBT regions 10 and two diode regions are illustrated, and all the diode regions 20 are sandwiched between the IGBT regions 10. It should be noted that the numbers of the IGBT regions 10 and the diode regions 20 are not limited thereto and are arbitrary. In addition, the arrangement of the IGBT regions 10 and the diode regions 20 in FIG. 1 can be interchanged with each other, and in this case, all the IGBT regions 10 are sandwiched between the diode regions 20. Alternatively, the number of the IGBT regions 10 and the number of the diode regions 20 may be the same, and the IGBT regions 10 and the diode regions 20 may be alternately arranged.In FIG. 1, a pad region 40 is disposed adjacent to the IGBT region 10 on the lower side of the drawing. The control pads 41 may be, for example, a current sensing pad 41 a, a Kelvin emitter pad 41 b, a gate pad 41 c, and pads 41 dand 41 efor a temperature sensing diode. The current detection pad 41 afunctions to detect a current flowing through a cell region of the RC IGBT 100. To this end, the current detection pad 41 ais electrically connected to IGBT cells or diode cells in a part of the cell area so that a current of a fraction up to several tens of thousands of the current flowing through the entire cell area of the RC-IGBT 100 flows. A voltage for gate driving to control on / off of the RC IGBT 100 is applied to the gate pad 41 c. The Kelvin emitter pad 41 bis electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41 cis electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41 bis electrically connected to the p-type base layer via a p-type contact layer. The pads 41 dand 41 efor a temperature sensing diode are electrically connected to an anode and a cathode of a temperature sensing diode disposed in the RC-IGBT 100. The temperature of the RC-IGBT 100 is measured by measuring a voltage between an anode and a cathode of a temperature sensing diode (not shown) disposed in the cell region.As the withstand voltage holding structure included in the termination region 30, for example, a field limiting ring (FLR) or a variation of lateral doping (VLD) is provided so as to surround the cell region on the upper surface F 1 side of the RC-IGBT 100. FLR consists of a ring-shaped p-type termination well layer, and VLD consists of a p-type well layer having a concentration gradient. The number of p-type termination well layers in the FLR and the concentration distribution in the VLD may be appropriately selected according to the withstand voltage design of the RC-IGBT 100. It should be noted that the withstand voltage class of the RC-IGBT is not particularly limited. In addition, a p-type termination well layer may be disposed over substantially the entire pad region 40, or at least one of an IGBT cell and a diode cell may be disposed in the pad region 40.Referring to FIG. 2, in the IGBT region 10, an active trench gate 11 including an active gate electrode 11 aand a gate insulating film 11 b, a dummy trench gate 12 including a dummy gate electrode 12 aand a dummy trench insulating film 12 b, an n-type emitter layer 13, and a p ++- base contact layer 14 are arranged. It should be noted that the gate 12 of a dummy trench may be omitted. A gate potential is applied to the active gate electrode 11 aof the active trench gate 11 by being electrically connected to the gate pad 41 c. The dummy gate electrode 12 aof the gate 12 of a dummy trench is electrically connected to the emitter electrode 5 through a wiring (not shown), thereby applying the emitter potential. The dummy gate electrode 12a faces the n -- drift layer 1 via the insulating film 12b of a dummy trench. On the sidewall of the gate 12 of a dummy trench, the n-type emitter layer 13 is not formed, and the p ++- base contact layer 14 is formed.In the diode region 20, a gate 21 of a diode trench including a diode trench electrode 21 aand an insulating film 21 of a diode trench, a p-type anode layer 25, a p ++- anode contact layer 24 a, and a p +- anode contact layer 24 bare disposed. In the present first preferred embodiment, the p ++- anode contact layer 24 ais arranged in a stripe shape while being orthogonal to the gate 21 of a diode trench. In addition, the p +- anode contact layer 24 bis arranged in a stripe shape so as to be separated from the p-type anode layer 25 by the p ++- anode contact layer 24 a. FIG. 2 shows a configuration including an active trench gate 11 and three dummy trench gates 12 disposed adjacent thereto, and although not illustrated in FIG. 2, the configuration repeats in the Y direction. It should be noted that in each of the above configurations, the number of active trench gates 11 is any number of one or more, and the number of dummy trench gates 12 is any number of 0 or more. Therefore, the gate 12 of a dummy trench may be omitted.Referring to FIG. 3 (a cross section taken along the line III-III in FIG. 2 ), the IGBT region 10 includes an n-type carrier accumulation layer 2 disposed between the n -- drift layer 1 and the upper surface F 1, a p-type base layer 15 disposed between the carrier accumulation layer 2 and the upper surface F 1, and an n-type emitter layer 13 and a p ++- base contact layer 14 disposed between the p-type base layer 15 and the upper surface F 1, respectively.The n-type carrier accumulation layer 2 is disposed on the upper surface (a surface opposite to the upper surface F 1) of the n -- drift layer 1 and has a higher donor concentration than the n -- drift layer 1. It should be noted that since the n-type carrier accumulation layer 2 and the n -- drift layer 1 n-type regions are in contact with each other, these two can be regarded as a drift layer. It should be noted that the n -- drift layer 1 may be omitted.The p-type base layer 15 is disposed between the n-type carrier accumulation layer 2 (n -- drift layer 1 when the n-type carrier accumulation layer 2 is omitted) and the upper surface F 1. The p-type base layer 15 is in contact with the gate insulating film 11 bof the gate 11 of an active trench.Each of the n-type emitter layer 13 and the p ++- base contact layer 14 is disposed on the p-type base layer 15 and partially forms the upper surface F 1. The n-type emitter layer 13 is in contact with the gate insulating film 11 bof the gate 11 of an active trench. The p ++- base contact layer 14 has a higher acceptor concentration than the p-type base layer 15.In the present preferred embodiment, the emitter electrode 5 includes an electrode layer 5 aand a barrier metal layer 5 bbetween the electrode layer 5 aand the upper surface F 1 of the semiconductor substrate 50. The material of the barrier metal layer 5b is preferably selected so as to obtain a satisfactory ohmic contact with the semiconductor substrate 50, and may be, for example, a titanium (Ti)-containing conductor, for example, titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). The electrode layer 5 ais, for example, an aluminum alloy layer such as an aluminum-silicon (Al-Si) alloy layer. At least one plating film may be formed on the aluminum alloy layer by an electroless plating method or an electrolytic plating method. The plating film is made of nickel (Ni), for example. When there is a region that is a fine region between adjacent interlayer insulating films 4 or the like and in which favorable embedding in the electrode layer 5 acannot be obtained, in order to favorably embed the region, a partial region made of tungsten that is a material having favorable embeddability can be formed, and then the partial region made of the above-described material can be formed.In addition, the IGBT region 10 includes an active trench gate 11 and a dummy trench gate 12 each of which penetrates from the upper surface F 1 through the n-type emitter layer 13, the p-type base layer 15, and the carrier accumulation layer 2 to reach the n-type drift layer 1. The gate 11 of an active trench and the gate 12 of a dummy trench are disposed in a trench formed in the semiconductor substrate 50. Specifically, the gate 11 of an active trench includes a gate insulating film 11 bformed on the inner wall of the trench and an active gate electrode 11 aformed in the trench via the gate insulating film 11 b. When a voltage for gate driving is applied to the active gate electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate insulating film 11b. The dummy trench gate 12 includes a dummy trench insulating film 12 bformed on the inner wall of the trench and a dummy gate electrode 12 aformed in the trench via the dummy trench insulating film 12 b. An interlayer insulating film 4 is disposed on the gate 11 of an active trench. The interlayer insulating film 4 is disposed between the gate 11 of an active trench and the barrier metal layer 5 bof the emitter electrode 5 to isolate the gate 11 of an active trench and the barrier metal layer 5 bfrom each other. The interlayer insulating film 4 on the gate 12 of a dummy trench may be omitted, and in this case, the dummy gate electrode 12 aand the emitter electrode 5 are in contact with each other.The IGBT region 10 includes an n-type buffer layer 3 disposed between the n -- drift layer 1 and the bottom surface F 2. The n-type buffer layer 3 has a higher donor concentration than the n -- drift layer 1. the n-type buffer layer 3 is arranged to suppress punch-through of a depletion layer extending from the p-type base layer 15 toward the lower surface F 2 when the RC IGBT 100 is in the off state. It should be noted that the buffer layer 3 may be omitted. It should be noted that, since the n-type buffer layer 3 and the n -- drift layer 1 n-type regions are in contact with each other, these two may be regarded as a drift layer.In addition, the IGBT region 10 includes a p-type collector layer 16 between the n-type buffer layer 3 (the n -- drift layer 1 when the n-type buffer layer 3 is omitted) and the lower surface F 2. The p-type collector layer 16 partially forms the lower surface F 2 and is ohmically connected to the collector electrode 7 by being in contact with the collector electrode 7. The collector electrode 7 may be made of Al, AlSi, Ni, Ti and / or Au. Similar to the emitter electrode 5, the collector electrode 7 may be made of an aluminum alloy or a laminate of an aluminum alloy and a plating film. The composition of the collector electrode 7 may be different from the composition of the emitter electrode 5.The n-type emitter layer 13 is disposed on both sides in the Y direction (width direction of the gate 11 of an active trench) so as to be in contact with the gate insulating film 11 b. The n-type emitter layer 13 and the p ++- base contact layer 14 are alternately arranged in the X direction (extension direction of the gate 11 of an active trench) in FIG. 2. The p ++- base contact layer 14 is also disposed between two adjacent gates 12 of dummy trenches.The active gate electrode 11a may be formed of, for example, polysilicon or a metal doped with phosphorus or the like. The electrode layer 5 aof the emitter electrode 5 may be formed of Al and / or AlSi. The barrier metal layer 5 bof the emitter electrode 5 is made of Ti, TiN, TiSi, CoSi, or the like, and may include a plug made of W or the like.By omitting the barrier metal layer 5 b, instead of the barrier metal layer 5 b, the electrode layer 5 amay be in contact with the semiconductor substrate 50. Alternatively, on the upper surface F 1, the barrier metal layer 5 bmay be provided only on an n-type portion, for example, the n-type emitter layer 13.Referring to FIG. 3 (a cross section taken along the line III-III in FIG. 2 ), the diode region 20 includes a p-type anode layer 25 disposed between the n -- drift layer 1 and the upper surface F 1, and a p +- anode contact layer 24 bdisposed between the p-type anode layer 25 and the upper surface F 1. In addition, the diode region 20 includes gates 21 of diode trenches each of which penetrates from the upper surface F 1 through the p-type anode layer 25 and the p +- anode contact layer 24 bto reach the n -- drift layer 1. The gate 21 of a diode trench is disposed in a trench formed in the semiconductor substrate 50. Specifically, the gate 21 of a diode trench includes a diode trench insulating film 21 bformed on the inner wall of the trench and a diode trench electrode 21 formed over the diode trench insulating film 21 b. Directly disposing the emitter electrode 5 on the gate 21 of a diode trench applies an emitter potential to the electrode 21 aof a diode trench. As a modified example, the interlayer insulating film 4 may be provided on the gate 21 of a diode trench, and in this case, the electrode 21 aof a diode trench of the gate 21 of a diode trench is electrically connected to the emitter electrode 5 through a wiring (not illustrated). The electrode 21 aof a diode trench is opposed to the n-type drift layer 1 via the diode trench insulating film 21 b.In addition, the diode region 20 includes an n-type buffer layer 3 disposed between the n-type drift layer 1 and the lower surface F 2, and an n-type cathode layer 26 disposed between the n-type buffer layer 3 and the lower surface F 2. The n-type cathode layer 26 partially forms the lower surface F 2 and is in contact with the collector electrode 7. It should be noted that the p-type anode layer 25 may be made of a structure similar to the laminated structure of the p-type base layer 15 and the carrier accumulation layer 2 in the IGBT region 10. In addition, as described above, omitting the barrier metal layer 5 ballows the electrode layer 5 ato be in contact with the semiconductor substrate 50 instead of the barrier metal layer 5 b.The donor concentration of the p +- anode contact layer 24 bis equal to or higher than the donor concentration of the n -- drift layer 1. The acceptor concentration of the p +- anode contact layer 24 bis equal to or higher than the donor concentration of the p +- anode contact layer 24 b. Moreover, the peak value of the acceptor concentration of the p +- anode contact layer 24 bis higher than the peak value of the acceptor concentration of the p-type anode layer 25, whereby the net doping concentration of the p +- anode contact layer 24 bis higher than the net doping concentration of the p-type anode layer 25.Referring to FIG. 4 (a cross section taken along the line IV-IV in FIG. 2 ), in contrast to FIG. 3, in this cross section, a p ++- anode contact layer 24 ais disposed in the diode region 20 instead of the p +- anode contact layer 24 b. The net doping concentration of the p ++- anode contact layer 24 ais higher than the net doping concentration of the p +- anode contact layer 24 b.Referring to FIG. 5 (a cross section taken along the line V-V in FIG. 2 ), unlike FIGS. 3 and 4, in this cross section, in the diode region 20, the p ++- anode contact layer 24 aand the p +- anode contact layer 24 bare not disposed, and thus the p-type anode layer 25 is in contact with the barrier metal layer 5 bof the emitter electrode 5.Referring to FIG. 2, between two adjacent gates 21 of diode trenches, the anode contact layer 24 and the p-type anode layer 25 are alternately arranged in the X direction (extending direction of the gate 21 of a diode trench). Moreover, in the present first preferred embodiment, in the X direction, the p ++- anode contact layer 24 ais disposed between the p-type anode layer 25 and the p +- anode contact layer 24 b.Although the IGBT region 10 and the diode region 20 are in contact with each other in the present preferred embodiment, another region may be interposed therebetween. In either case, the IGBT region 10 and the diode region 20 share a semiconductor substrate 50 In the former case, the end of the p-type collector layer 16 may be positioned at the boundary between the IGBT region 10 and the diode region 20, or may protrude into the diode region 20 by the distance U 1 (FIGS. 3 to 5 ). When U1>0, since the distance between the n-type cathode layer 26 and the gate 11 of an active trench can be increased, even when a voltage for gate driving is applied to the active gate electrode 11a during the operation of the free wheeling diode of the RC-IGBT 100, a current from a channel formed adjacent to the gate 11 of an active trench of the IGBT region 10 to the n-type cathode layer 26 can be suppressed. For this purpose, the distance U 1 is preferably, for example, about 100 μm. However, depending on the application of the RC-IGBT, the distance U 1 may preferably be 0 μm or more and less than 100 μm. As a modified example, furthermore, implanting acceptors into the lower surface F 2 may set a part of the region where the n-type cathode layer 26 is disposed in FIGS. 3 to 5 as a p-type region.The donor of the n -- drift layer 1 may be arsenic or phosphorus, and the donor concentration of the n-drift layer 1 is, for example, 1×10 12 / cm 3 or more and 1×10 15 / cm 3 or less. The donor of the n-type emitter layer 13 may be arsenic or phosphorus, and the donor concentration of the n-type emitter layer 13 is, for example, 1×10 17 / cm 3 or more and 1×10 20 / cm 3 or less. The donor of the n-type carrier accumulation layer 2 may be arsenic or phosphorus, and the donor concentration of the n-type carrier accumulation layer 2 is, for example, 1×10 13 / cm 3 or more and 1×10 17 / cm 3 or less. The donor of the n-type buffer layer 3 may be phosphorus (P) and / or protons (H +) and the donor concentration of the n-type buffer layer 3 is, for example, 1×10 12 / cm 3 or more and 1×10 10 / cm 3 or less. The donor of the n-type cathode layer 26 may be arsenic or phosphorus, and the donor concentration of the n +- type cathode layer 26 is, for example, 1×10 10 / cm 3 or more and 1×10 21 / cm 3 or less.The acceptor of the p-type anode contact region 24 may be boron or aluminum, and the acceptor concentration of the p-type anode contact region 24 is, for example, 1×10 15 / cm 3 or more and 1×10 20 / cm 3 or less. The acceptor of the p ++- base contact layer 14 may be boron or aluminum, and the acceptor concentration of the p ++- base contact layer 14 is, for example, 1×10 15 / cm 3 or more and 1×10 20 / cm 3 or less. The donor of the p-type base layer 15 may be boron or aluminum, and the donor concentration of the p-type base layer 15 is, for example, 1×10 12 / cm 3 or more and 1×10 10 / cm 3 or less. The acceptor of the p-type collector layer 16 may be boron or aluminum, and the acceptor concentration of the p-type collector layer 16 is, for example, 1×10 10 / cm 3 or more and 1×10 20 / cm 3 or less. The acceptor of the p-type anode layer 25 may be boron or aluminum, and the acceptor concentration of the p-type anode layer 25 is, for example, 1×10 12 / cm 3 or more and 1×10 10 / cm 3 or less.Next, a configuration of a termination region 30 will be described below. FIGS. 6 and 7 are schematic cross-sectional views taken along lines VI-VI and VII-VII, respectively, in FIG. 1.As described above, both the upper surface F 1 and the lower surface F 2 extend over not only the IGBT region 10 and the diode region 20 but also the termination region 30. in other words, each of the upper surface F 1 and the lower surface F 2 extends continuously between the IGBT region 10, the diode region 20, and the termination region 30. in addition, as described above, the n -- drift layer 1 extends not only over the IGBT region 10 and the diode region 20 but also over the termination region 30. in other words, the n -- drift layer 1 extends continuously between the IGBT region 10, the diode region 20, and the termination region 30.In the termination region 30, a plurality of p-type termination well layers 31 and an n +- type channel stop layer 32 are disposed on a surface of the n -- drift layer 1 opposite to the upper surface F 1. The acceptor of the p-type termination well layer 31 may be boron or aluminum, and the acceptor concentration of the p-type termination well layer 31 is, for example, 1×10 14 / cm 3 or more and 1×10 10 / cm 3 or less. The p-type termination well layer 31 surrounds a cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is arranged as a plurality of ring structures, and the number thereof is appropriately selected according to the withstand voltage design of the RC-IGBT 100. The n +- type channel stop layer 32 surrounds the p-type termination well layer 31.Between the n-type drift layer 1 and the lower surface F 2 of the semiconductor substrate 50, a p-type termination collector layer 16 ais disposed. The p-type termination collector layer 16a is formed integrally and continuously with the p-type collector layer 16 disposed in the cell region. Therefore, the termination p-type collector layer 16 aand the collector p-type layer 16 can be collectively referred to as a collector layer. The p-type termination collector layer 16 amay protrude into the diode region 20 by a distance U 2. When the diode region 20 is adjacent to the termination region 30 as illustrated in FIG. 1, maintaining U2>0 increases the distance between the n-type cathode layer 26 of the diode region 20 and the p-type termination well layer 31. This makes it possible to prevent the p-type termination well layer 31 from functioning as an anode of a diode. The distance U 2 is, for example, about 100 μm.As described above, the collector electrode 7 extends not only over the IGBT region 10 and the diode region 20, but also over the termination region 30.As described above, the emitter electrode 5 extends not only over the IGBT region 10 and the diode region 20, but also over a part of the termination region 30. in other words, the emitter electrode 5 extends continuously between the IGBT region 10, the diode region 20, and a part of the termination region 30. On the upper surface F 1 of the semiconductor substrate 50, the termination region 30 includes a termination electrode 6 separate from the emitter electrode 5. The termination electrode 6 is electrically connected to each of the p-type termination well layer 31 and the n +- type channel stop layer 32 via a contact hole formed in the interlayer insulating film 4 on the upper surface F 1. The emitter electrode 5 and the termination electrode 6 are electrically connected to each other via the semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film.The termination region 30 is provided with a termination protection film 34 covering the emitter electrode 5, the termination electrode 6, and the semi-insulating film 33. The termination protection film 34 is made of, for example, polyimide.(Details of Production Method)FIG. 8 is a flowchart schematically illustrating a method of manufacturing the RC-IGBT 100. FIGS. 9 to 15 are partial cross-sectional views schematically illustrating a step in the manufacturing method in FIG. 8. It should be noted that the cross section in FIG. 9 corresponds to the cross sections common to the line III-III, the line IV-IV and the line V-V in FIG. 2. The cross section in FIG. 10 also corresponds to the cross sections corresponding to the line III-III, the line IV-IV, and the line V-V in FIG. 2. FIGS. 11 and 12 show the same one step, the cross section in FIG. 11 corresponds to the cross section of the line III-III in FIG. 2, and the cross section in FIG. 12 corresponds to the cross sections common to the lines IV-IV and V-V in FIG. 2. Figs. 13 to 15 show the same one step, and the respective cross sections in Figs. 11 to 15 correspond to the cross sections of the lines III-III, IV-IV and V-V in Fig. 2.Referring to FIG. 9, the semiconductor substrate 50 is prepared in step ST 10 (FIG. 8 ). The semiconductor substrate 50 to be prepared is, for example, a wafer manufactured by a floating region (FZ) method, that is, an FZ wafer, a wafer manufactured by an applied magnetic field (MCZ) Czochralski method, that is, an MCZ wafer, or an epitaxial wafer. The semiconductor substrate 50 to be prepared includes a portion serving as the n -- drift layer 1 in the completed RC-IGBT 100 as it is, and the whole has an n-type conductivity. The donor concentration of the n -- drift layer 1 is appropriately selected according to the withstand voltage of the RC-IGBT 100, and when the withstand voltage is 1200 V, for example, the resistivity of the n -- drift layer 1 is set to about 40 to 120 Ω·cm. Performing ion implantation and subsequent heat treatment on the thus prepared semiconductor substrate 50 forms a desired layer (region) in the semiconductor substrate 50. During the heat treatment, the implanted ions are allowed to diffuse and are activated. Although the description of the heat treatment below is omitted, the heat treatment may be performed at an appropriate timing. The order of the ion implantation step may be interchanged. In addition, the order of other steps can be freely interchanged.In step ST 20, the termination region 30 (FIGS. 6 and 7 ) is formed by a well-known manufacturing method. In order to form an FLR including the termination well layer 51 as a withstand voltage holding structure of the termination region 30, acceptor ions are doped by ion implantation, for example. It should be noted that a part or all of the ion implantation for forming the termination region 30 may be performed simultaneously when the ion implantation is performed on the IGBT region 10 and the diode region 20 as described below.In steps ST 30 and ST 40, implanting acceptors such as boron (B) from the upper surface F 1 side of the semiconductor substrate 50 forms the p-type base layer 15 and the p-type anode layer 25. Since mask processing is performed on the upper surface F 1 of the semiconductor substrate 50, and then the donor and the acceptor are added by ion implantation, the donor and the acceptor are selectively formed on the upper surface F 1 of the semiconductor substrate 50. It should be noted that the mask processing refers to processing for forming a mask by applying a resist to the semiconductor substrate 50 and forming an opening in a predetermined region of the resist using a photoengraving technique. The use of this mask makes it possible to perform processing such as ion implantation or etching on a specific region of the semiconductor substrate 50. The p-type anode layer 25 and the p-type base layer 15 are formed by performing ion implantation of an acceptor simultaneously or individually. When they are formed individually, each composition can be independently adjusted. The p-type termination well layer 51 (FIGS. 6 and 7 ) may be formed simultaneously by ion implantation of an acceptor for forming the p-type anode layer 25. When they are formed individually, each composition can be independently adjusted. In addition, the p-type termination well layer 51, the p-type base layer 15, and the p-type anode layer 25 may be formed simultaneously.In step ST 50 (FIG. 8 ), the n-type carrier accumulation layer 2 is formed by implanting donors such as phosphorus (P) from the upper surface F 1 side of the semiconductor substrate 50.Referring to FIG. 10, in step ST 60 (FIG. 8 ), the gate 11 of an active trench, the gate 12 of a dummy trench, and the gate 21 of a diode trench are formed. Specifically, trenches for these are first formed by etching. The etching may be performed using, for example, a mask having an opening made of an oxide film (for example, an SiO 2- film). It should be mentioned in particular that in FIG. 10 the distances from center to center or pitches of the trenches are the same, but the pitches of the trenches may be the same. Next, heating the semiconductor substrate 50 in an atmosphere containing oxygen oxidizes the inner walls of the trenches. Thus, the gate insulating film 11 b, the dummy trench insulating film 12 b, and the diode trench insulating film 21 bare formed simultaneously. From the surface of the semiconductor substrate 50, an unnecessary portion oxidized by the oxidation is removed in a later step. Next, depositing doped polysilicon in the trench by chemical vapor deposition (CVD) or the like forms the active gate electrode 11 a, the dummy gate electrode 12 a, and the diode trench electrode 21 a.Referring to FIG. 11 (corresponding to the cross section taken along the line III-III in FIG. 2 ) and FIG. 12 (corresponding to the cross sections taken along the lines IV-IV and V-V in FIG. 2 ), in step ST 70 (FIG. 8 ), an implantation mask 61 is formed for the n-type emitter layer 13 and the p +- anode contact layer 24 b(first anode contact layer). The implantation mask 61 has an opening exposing a region where the n-type emitter layer 13 and the p +- anode contact layer 24 b(see FIG. 3 ) are to be formed. In step ST 80 (FIG. 8 ), by ion implantation onto the upper surface F 1 of the semiconductor substrate 50 using the implantation mask 61, a step of performing donor doping of the n-type emitter layer 13 and a step of performing donor doping of the p +- anode contact layer 24 b(see FIG. 3 ) as a common donor doping step are simultaneously performed. In FIG. 11, a region serving as a p +- anode contact layer 24 b(see FIG. 3 ) is a preliminary region 24 bD having an n-type conductivity instead of a p-type conductivity. Similar to the n-type emitter layer 13, the preliminary region 24 bD has an n-type conductivity by donors being doped. Thereafter, the implantation mask is removed.Referring to FIG. 13 (corresponding to the cross section taken along the line III-III in FIG. 2), FIG. 14 (corresponding to the cross sections taken along the lines IV-IV and V-V in FIG. 2 ), and FIG. 15 (corresponding to the cross section taken along the line V-V in FIG. 2 ), in step ST 90 (FIG. 8 ), an implantation mask 62 is formed for the p ++- base contact layer 14, the p +- anode contact layer 24 b(first anode contact layer), and the p ++- anode contact layer 24 a(second anode contact layer). The implantation mask 62 has an opening exposing a region where the p ++- base contact layer 14, the p +- anode contact layer 24 b, and the p ++- anode contact layer 24 aare to be formed. In step ST 100 (FIG. 8 ), by ion implantation onto the upper surface F 1 of the semiconductor substrate 50 using the implantation mask 62, a step of performing acceptor doping of the p ++- base contact layer 14, a step of performing acceptor doping of the p +- anode contact layer 24 b(FIG. 3 ), and a step of performing acceptor doping of the p ++- anode contact layer 24 aare performed as a step of common acceptor doping. The step of performing acceptor doping of the p +- anode contact layer 24 b(FIG. 3 ) causes the preliminary region 24 bD (FIG. 11 ) having n-type conductivity to become the p +- anode contact layer 24 bhaving p-type conductivity. In order to enable the conductivity type to be exchanged in this manner, the implantation amount of donor ions per unit area in the common donor doping step (FIGS. 13 to 15 ) is lower than the implantation amount of acceptor ions per unit area in the common acceptor doping step (FIGS. 11 and 12 ). Thereafter, the implantation mask 62 is removed.It should be noted that, as described above, the order of the ion implantation step may be interchanged. Therefore, the order of the donor doping step (FIGS. 13 to 15 ) and the acceptor doping step (FIGS. 11 and 12 ) may be interchanged. In this case, a high net concentration p-type region similar to the p ++- base contact layer 14 is formed in a region to be the p +- anode contact layer 24 bin place of the preliminary region 24 bD (FIG. 11 ) having an n-type conductivity at the time between both doping steps.In step ST 110 (FIG. 8 ), the interlayer insulating film 4 (see FIGS. 3 to 5 ) made of, for example, SiO 2 is formed. Thereafter, a contact hole is formed in the interlayer insulating film 4. This contact hole is formed on each of the n-type emitter layer 13, the p ++- base contact layer 14, the p +- anode contact layer 24b, the p ++- anode contact layer 24a, the dummy gate electrode 12a and the electrode 21a of a diode trench.In step ST 120 (FIG. 8 ), a barrier metal layer 5 band an electrode layer 5 aare formed as the emitter electrode 5 (see FIGS. 3 to 5 ). The barrier metal layer 5 bis formed by depositing titanium nitride by physical vapor deposition (PVD) or CVD. As the electrode layer 5 a, for example, an aluminum alloy layer such as an aluminum-silicon (Al-Si) alloy layer is formed by PVD such as sputtering or vapor deposition. At least one plating film may be formed on the aluminum alloy layer by an electroless plating method or an electrolytic plating method. The plating film is made of, for example, nickel (Ni) or an alloy thereof. Forming at least a part of the electrode layer 5 aby a plating method enables the thickness of the electrode layer 5 ato be easily secured. Increasing the thickness of the electrode layer 5 aincreases the heat capacity, thereby improving the heat resistance of the electrode layer 5 a.In step ST 130 (FIG. 8 ), a back surface pattern is formed. The structure of the back surface is formed, for example, as follows.First, grinding the bottom surface F 2 of the semiconductor substrate 50 reduces the thickness of the semiconductor substrate 50 to a predetermined design thickness. The design thickness is, for example, 80 μm to 200 μm.Next, implantation of donors into the lower surface F 2 of the semiconductor substrate 50 forms the n-type buffer layer 3. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30. Alternatively, the n-type buffer layer 3 may be formed only in the IGBT region 10 or the diode region 20. The donor implantation may be performed, for example, by means of an implantation of phosphorus (P) ions and / or an implantation of protons (H +). Protons may be implanted from the lower surface F 2 of the semiconductor substrate 50 to a deep position with relatively low acceleration energy. In addition, changing the acceleration energy enables the depth of proton implantation to be changed relatively easily. Therefore, when the n-type buffer layer 3 is to be formed with protons, when compared with a case where the n-type buffer layer 3 is to be formed with phosphorus, performing ion implantation multiple times while changing the acceleration energy makes it easy to sufficiently ensure the dimension of the n-type buffer layer 3 in the thickness direction (Z direction) of the semiconductor substrate 50. On the other hand, phosphorus has a higher activation rate than donor than protons. Therefore, forming the n-type buffer layer 3 with phosphorus enables an effect of more reliably suppressing punch-through of the depletion layer even in the thin semiconductor substrate 50. In order to further enhance the effect, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, and in this case, protons are implanted from the lower surface F 2 at a position deeper than phosphorus.In addition, implanting acceptors into the lower surface F 2 of the semiconductor substrate 50 forms the p-type collector layer 16. An acceptor implantation is carried out, for example, by means of an implantation of boron (B). When the p-type collector layer 16 is formed, the p-type termination collector layer 16 a(see FIGS. 6 and 7 ) may be formed in the termination region 30 at the same time.Next, the n-type cathode layer 26 (see FIGS. 3 to 5 ) is formed in the diode region 20 by, for example, implanting phosphorus (P). The implantation amount of the donors for forming the n-type cathode layer 26 is larger than the implantation amount of the acceptors for forming the p-type collector layer 16. It should be noted that in FIGS. 3 to 5, the depths of the p-type collector layer 16 and the n-type cathode layer 26 are shown to be the same from the lower surface F 2, but the depth of the n-type cathode layer 26 is preferably the same as the depth of the p-type collector layer 16 or greater. Since acceptors are also implanted in the region where the n-type cathode layer 26 is to be formed, more donors than the amount that balances the acceptors are implanted.The ions implanted into the lower surface F 2 side of the semiconductor substrate 50 may be activated by laser annealing in which the lower surface F 2 is irradiated with a laser beam. Laser annealing enables not only the p-type collector layer 16 but also the n-type buffer layer 3 positioned relatively flat from the lower surface F 2 to be activated at the same time. When protons are used for the n-type buffer layer 3, the heat treatment temperature suitable for activation is relatively low, about 380° C. to 450° C. Therefore, it is necessary to make sure that the temperature of the region where the protons are implanted is not higher than about 380° C. to 450° C. Since the laser annealing can heat the vicinity of the lower surface F 2 of the semiconductor substrate 50 to a high temperature, even after protons are implanted into the n-type buffer layer 3 separated from the lower surface F 2, appropriate setting of the conditions of laser irradiation enables the vicinity of the lower surface F 2 to be heated to a high temperature while not exceeding the above temperature range.Next, on the lower surface F 2 of the semiconductor substrate 50, the collector electrode 7 (FIGS. 3 to 5 ) is formed. The collector electrode 7 is formed to extend over the IGBT region 10, the diode region 20, and the termination region 30 on the lower surface F 2. The collector electrode 7 may be formed on the entire lower surface F 2. PVD such as sputtering or vapor deposition forms an aluminum alloy layer such as an aluminum-silicon (Al-Si) alloy layer or a titanium (Ti) layer as the collector electrode 7. In addition, at least one plating film may be formed on the metal film formed by PVD by an electroless plating method or an electrolytic plating method.It should be noted that step ST 130 may be performed at a timing between the formation of the aluminum alloy layer and the formation of at least one plating film in the above description with respect to step ST 120.After the above, the RC-IGBT 100 is manufactured. It should be noted that in mass production, at the time when the wafer-level step is completed, a plurality of RC-IGBTs 100 arranged in a matrix form are formed on one wafer. These are cut into individual RC-IGBTs 100 by laser dicing or dicing with a knife.(Effect)According to the present first preferred embodiment, first, the p +- anode contact layer 24 bof the diode region 20 has a lower net concentration than the p ++- base contact layer 14 of the IGBT region 10. This net concentration difference can achieve a high latch-up tolerance in the IGBT region 10 and a low recovery loss in the diode region 20. Second, the p +- anode contact layer 24 bhas a higher donor concentration than the p ++- base contact layer 14. utilization of this high donor concentration allows the process of adjusting the acceptor concentration to be simplified to avoid a significant increase in manufacturing cost when the above-described net concentration difference is obtained. According to the above, it is possible to achieve high latch-up tolerance and low recovery loss while avoiding significant increase in manufacturing cost.Specifically, the step of performing donor doping of the n-type emitter layer 13 and the step of performing donor doping of the p +- anode contact layer 24 bare simultaneously performed as the common donor doping step (FIGS. 11 and 12 ). Consequently, the manufacturing method is simplified compared with the case where the step of performing donor doping of the n-type emitter layer 13 and the step of performing donor doping of the p +- anode contact layer 24 bare individually performed. Therefore, the manufacturing cost can be reduced.In addition, a step of performing acceptor doping of the p ++- base contact layer 14 and a step of performing acceptor doping of the p +- anode contact layer 24 bare simultaneously performed as a step of common acceptor doping (FIGS. 13 to 15 ). Thus, the manufacturing method is simplified compared with the case where the step of performing acceptor doping of the p ++- base contact layer 14 and the step of performing acceptor doping of the p +- anode contact layer 24 bare performed individually. Therefore, the manufacturing cost can be reduced.The implantation amount of donor ions per unit area in the above-described donor common doping step is lower than the implantation amount of acceptor ions per unit area in the above-described acceptor common doping step. Thus, by a combination of the donor common doping step and the acceptor common doping step, a p-type conductivity can be associated with the p +- anode contact layer 24 b.The p +- anode contact layer 24 bhas a lower net concentration than the p ++- anode contact layer 24 a. Thus, adjusting the arrangement of the p ++- anode contact layer 24 aand the p +- anode contact layer 24 bin the diode region 20 enables the recovery loss of the diode region 20 to be further reduced.The p +- anode contact layer 24 bhas a higher donor concentration than the p ++- anode contact layer 24 a. Thus, the difference in the net concentration of the p +- anode contact layer 24b from the net concentration of the p ++- anode contact layer 24a can be adjusted by the difference in donor concentration.The upper surface F 1 does not have n-type conductivity in the diode region 20. Thus, it is possible to suppress a decrease in the safe operating range in the reverse recovery safe operating area (RRSOA) due to the formation of the parasitic npn transistor.The p-type anode layer 25 forms a part of the upper surface F 1. Thus, the hole injection efficiency is reduced. Therefore, the recovery loss of the diode region 20 can be reduced.The net peak concentration of the p-type anode layer 25 is 1×10 16 / cm 3 or more. Thus, it is possible to suppress a decrease in RRSOA.The net peak concentration of the p +- anode contact layer 24 bis 1×10 18 / cm 3 or more. Thus, the turn-on voltage of the diode region 20 can be kept low.(Modified Example)FIG. 16 is a plan view illustrating a modified example of FIG. 1. In the present modification, a plurality of diode regions 20 are arranged side by side in both the longitudinal direction and the lateral direction. The periphery of the diode region 20 is surrounded by the IGBT region 10. That is, the plurality of diode regions 20 are arranged in the island-shape in the IGBT region 10. In Fig. 16, the diode regions 20 are arranged in a matrix of four columns in the horizontal direction on the sheet and two rows in the vertical direction on the sheet. However, the number and arrangement of the diode regions 20 are not limited thereto, and a configuration in which the peripheries of one or more diode regions 20 are surrounded by the IGBT region 10 in the IGBT region 10 may be used.< Preferred Embodiment>FIG. 17 is a partial plan view in a view similar to FIG. 2, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 102 along an upper surface (first main surface) of a semiconductor substrate 50 according to a second preferred embodiment. In the present second preferred embodiment, unlike the first preferred embodiment (FIG. 2 ), the p +- anode contact layer 24 is disposed within the p ++- anode contact layer 24 ato be surrounded by the p ++- anode contact layer 24 a. It should be noted that, since the remaining configuration thereof is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals and the description of the elements will not be repeated.As in the first and second preferred embodiments, a p-type is counter-doped in the p +- anode contact layer 24b, in which acceptors are further doped into a donor doped region. Therefore, due to variations in the formation of an implantation mask for impurity doping, a portion of a region to be the p-type p +- anode contact layer 24 bmay have an n-type conductivity on the upper surface F 1. When the n-type region constitutes a parasitic npn transistor, the RRSOA decreases.According to the present second preferred embodiment (FIG. 17 ), compared with the first preferred embodiment (FIG. 2 ), the size of each of the p +- anode contact layers 24 bis small, and the dimensional variation of the p +- anode contact layer 24 bbased on the formation variation of the implantation mask is also small. Therefore, it is possible to suppress a decrease in RRSOA due to manufacturing variation.< Preferred Embodiment>FIG. 18 is a partial plan view in a view similar to FIG. 17, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 103 along an upper surface (first main surface) of a semiconductor substrate 50 according to a third preferred embodiment. In the present preferred embodiment, unlike the second preferred embodiment (FIG. 17 ), the p +- anode contact layer 24 bsursurrounded by the p ++- anode contact layer 24 ais arranged in a zigzag form. It should be noted that, since the remaining configuration thereof is substantially the same as the configuration of the second preferred embodiment described above, the same or corresponding elements are denoted by the same reference numerals and the description of the elements will not be repeated.According to the present third preferred embodiment (FIG. 18 ), the hole current density in the diode region 20 is more uniform as compared with the second preferred embodiment (FIG. 17 ). Thus, the heat dissipation of the diode region 20 can be increased.< Preferred Embodiment>FIG. 19 is a partial plan view in a view similar to FIG. 2, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 104 along an upper surface (first main surface) of a semiconductor substrate 50 according to a fourth preferred embodiment. In the present preferred embodiment, unlike the first preferred embodiment (FIG. 2 ), a p ++- anode contact layer 24 ais disposed so as to be separated from the p-type anode layer 25 by the p +- anode contact layer 24 b. It should be noted that, since the remaining configuration thereof is substantially the same as the configuration of the above-described first preferred embodiment, the same or corresponding elements are denoted by the same reference numerals and the description of the elements will not be repeated.According to the present fourth embodiment (FIG. 19 ), the density of holes injected into the p-type anode layer 25 is reduced as compared with the first preferred embodiment (FIG. 2 ). Thus, the recovery loss can be reduced.< Preferred Embodiment>FIG. 20 is a partial plan view in a view similar to FIG. 17, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 105 along an upper surface (first main surface) of a semiconductor substrate 50 according to a fifth preferred embodiment. In the present fifth preferred embodiment, unlike the second preferred embodiment (FIG. 17 ), the p ++- anode contact layer 24 ais disposed inside the p +- anode contact layer 24 bso as to be surrounded by the p +- anode contact layer 24 b. In other words, the arrangement of the p ++- anode contact layer 24 aand the p +- anode contact layer 24 bis interchanged. It should be noted that the remaining configuration is substantially the same as the configuration of the second preferred embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and the description of the elements is not repeated.According to the present preferred embodiment, the density of holes injected into the p-type anode layer 25 is reduced. Thus, the recovery loss can be reduced.< Preferred Embodiment>FIG. 21 is a partial plan view in a view similar to FIG. 2, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 106 along an upper surface (first main surface) of a semiconductor substrate 50 according to a sixth preferred embodiment. In the present preferred embodiment, unlike the fifth preferred embodiment (FIG. 20 ), the p ++- anode contact layer 24 asurrounded by the p +- anode contact layer 24 bis arranged in a zigzag form. It should be noted that, since the remaining configuration thereof is substantially the same as the configuration of the fifth preferred embodiment described above, the same or corresponding elements are denoted by the same reference numerals and the description of the elements will not be repeated.According to the present sixth preferred embodiment (FIG. 21 ), the hole current density in the diode region 20 is more uniform as compared with the fifth preferred embodiment (FIG. 20 ). Thus, the heat dissipation of the diode region 20 can be increased.< Preferred Embodiment>FIG. 22 is a partial plan view in a view similar to FIG. 2, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 107 along an upper surface (first main surface) of a semiconductor substrate 50 according to a seventh preferred embodiment. In the present seventh preferred embodiment, in contrast to the first preferred embodiment (FIG. 2 ), of a plurality of mesa regions of the semiconductor substrate 50 divided by the gates 21 of diode trenches, only the p-type anode layer 25 is disposed on the upper surface of some mesa regions, and the p ++- anode contact layer 24 aand the p +- anode contact layer 24 bare not disposed, and only the p ++- anode contact layer 24 aand the p +- anode contact layer 24 bare disposed on the upper surface of other mesa regions, and the p-type anode layer 25 is not disposed. It should be noted that the remaining configuration is substantially the same as the configuration of the above-described first preferred embodiment, the same or corresponding elements are denoted by the same reference numerals, and the description of the elements is not repeated.According to the present preferred embodiment, it is possible to reduce the influence of dimensional variation in the X direction (direction parallel to the direction of extension of the trench) of the p ++- anode contact layer 24 aand the p +- anode contact layer 24 b.< Preferred Embodiment>FIG. 23 is a partial plan view in a view similar to FIG. 2, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 108 along an upper surface (first main surface) of a semiconductor substrate 50 according to an eighth preferred embodiment. In the present eighth preferred embodiment, unlike the first preferred embodiment (FIG. 2 ), the p ++- anode contact layer 24 ais omitted. Thus, in each of the plurality of mesa regions of the semiconductor substrate 50 divided by the gates 21 of diode trenches, the p +- anode contact layer 24 band the p-type anode layer 25 are alternately arranged in contact with each other in the X direction (direction parallel to the extending direction of the trench). It should be noted that, since the remaining configuration thereof is the same as the configuration of the first preferred embodiment described above, the same or corresponding elements are denoted by the same reference numerals and the description of the elements will not be repeated.According to the present eighth preferred embodiment (FIG. 23 ), the density of holes injected into the p-type anode layer 25 is reduced. Thus, the recovery loss can be reduced.< Preferred Embodiment>FIG. 24 is a partial plan view in a view similar to FIG. 2, schematically illustrating a configuration of a reverse conducting semiconductor device (RC-IGBT) 109 along an upper surface (first main surface) of a semiconductor substrate 50 according to a ninth preferred embodiment. Also in the present ninth preferred embodiment, similarly to the eighth preferred embodiment (FIG. 23 ), the p ++- anode contact layer 24 a(see FIG. 2 ) is omitted. Then, in the present ninth preferred embodiment, in contrast to the eighth preferred embodiment, of a plurality of mesa regions of the semiconductor substrate 50 divided by the gates 21 of diode trenches, only the p-type anode layer 25 is disposed on the upper surface of some mesa regions, and the p +- anode contact layer 24 bis not disposed, and only the p +- anode contact layer 24 bis disposed on the upper surface of other mesa regions, and the p-type anode layer 25 is not disposed. It should be noted that, since the remaining configuration thereof is substantially the same as the configuration of the above-described first preferred embodiment, the same or corresponding elements are denoted by the same reference numerals and the description of the elements will not be repeated.According to the present preferred embodiment, it is possible to reduce the influence of dimensional variation in the X direction (direction parallel to the direction of extension of the trench) of the p +- anode contact layer 24 b.< Preferred Embodiment>In the present tenth preferred embodiment, the dopant concentration profile of the semiconductor substrate 50 included in the RC-IGBT 100 described in the first preferred embodiment will be described in more detail.FIG. 25 is a graph illustrating, in a depth range of an alternate long and short dash line DD (FIG. 3 ), an example of a concentration profile of the semiconductor substrate 50 included in the RC-IGBT 100 according to the present tenth preferred embodiment. In this graph, concentration Na1represents an acceptor implantation profile for forming the p-type anode layer 25. Concentration Na1+concentration Na2represents an acceptor implantation profile for forming the p +- anode contact layer 24 b. Concentration Nd2represents a donor implant profile for forming the p +- anode contact layer 24 b. The net concentration Nn represents a net concentration obtained from the acceptor concentration Na1+concentration Na2and the donor concentration Nd2.The peak concentration of the net concentration Nn of the p-type anode layer 25 (range in which the depth position is about 2 μm or more) is 1×10 16 / cm 3 or more. The peak concentration of the net concentration Nn of the p +- anode contact layer 24 b(region where the depth position is about 2 μm or less) is 1×10 10 / cm 3 or more.FIG. 26 is a graph illustrating the relationship between the net peak concentration of the p-type anode layer 25 and the controllable Vcc measured in the RRSOA test in the RC-IGBT 100 according to the present tenth preferred embodiment. It should be noted that Vcc is a voltage of the DC power supply applied between the collector and the emitter, and the controllable Vcc is the maximum Vcc at which no device breakdown occurred in the RRSOA test. The plotted values of the net peak concentration ( / cm 3) were 2.5×10 15, 5,0×10 15, 1,2×10 16, 2,0×10 16, 2,5×10 16 and 5.0×10 16. From this result, it is found that setting the net peak concentration of the p-type anode layer 25 to 1.2×10 10 / cm 3 or more enables the decrease in RRSOA to be suppressed. In addition, it can be considered from the general tendency of the illustration that setting the net peak concentration of the p-type anode layer 25 to about 1×10 10 / cm 3 or more enables the decrease in the RRSOA to be suppressed.FIG. 27 is a graph illustrating an example of a measurement result of a relationship between the net peak concentration of the p +- anode contact layer 24 b(first anode contact layer) and the turn-on voltage of the diode formed by the diode region 20 in the RC-IGBT 100 according to the present tenth preferred embodiment. The plotted values of the net peak concentration were 1.0×10 17, 3,5×10 18, 5,0×10 18, 1,0×10 19 and 2.0×10 19. This result shows that setting the net peak concentration of the p +- anode contact layer 24 bto 3.5×10 18 or more enables the turn-on voltage of the diode to be remarkably reduced. From the general trend of the illustration, it can be considered that setting the net peak concentration of the p +- anode contact layer 24 bto about 1×10 18 / cm 3 or more allows the turn-on voltage of the diode to be reduced. It can be considered that the reduction of the turn-on voltage is due to the reduction of the contact resistance between the emitter electrode 5 and the p +- anode contact layer 24 b.< Preferred Embodiment>FIG. 28 is a modified example of FIG. 25 (tenth preferred embodiment) and illustrates an impurity concentration profile of the semiconductor substrate 50 in the present eleventh preferred embodiment. In the present eleventh preferred embodiment, in the diode region 20, the semiconductor substrate 50 has the minimum value of the profile of the net concentration Nn in the thickness direction at the depth position between the p +- anode contact layer 24 b(left region in the illustration) and the p-type anode layer 25 (right region in the illustration). Thus, the hole injection efficiency in the diode region 20 is reduced. Therefore, the recovery loss of the diode region 20 can be reduced.< Preferred Embodiment>FIG. 29 is a modified example of FIG. 25 (tenth preferred embodiment) and illustrates an impurity concentration profile of the semiconductor substrate 50 in the present twelfth preferred embodiment. In the present twelfth preferred embodiment, the p +- anode contact layer 24 b(left region in the figure) has a peak value of the profile of the net concentration Nn in the thickness direction at a depth position away from the upper surface (depth position 0). Thus, the hole injection efficiency in the diode region 20 is reduced. Therefore, the recovery loss of the diode region 20 can be reduced.< Preferred Embodiment>FIG. 30 is a modified example of FIG. 25 (tenth preferred embodiment) and illustrates an impurity concentration profile of the semiconductor substrate 50 in the present thirteenth preferred embodiment. In the present thirteenth preferred embodiment, the semiconductor substrate 50 includes the intermediate n-type conductivity layer 29 between the p +- anode contact layer 24 band the p-type anode layer 25 in the thickness direction in the diode region 20. The recovery loss of the diode region 20 can therefore be reduced.It should be noted that each preferred embodiment can be freely combined and each preferred embodiment can be appropriately modified or omitted. In addition, a certain preferred embodiment may also be partially used for another preferred embodiment.

Claims

A reverse conducting semiconductor device (100-109) comprising: - an insulated gate bipolar transistor region (10) and a diode region (20), - a semiconductor substrate (50): - comprised in the insulated gate bipolar transistor region (10) and the diode region (20), and - comprising: - a first main surface (F1) and a second main surface (F2) opposite the first main surface, - a drift layer (1) extending over the insulated gate bipolar transistor region (10) and the diode region (20) and having a first conductivity type, - a base layer (15) arranged between the drift layer (1) and the first main surface (F1) in the insulated gate bipolar transistor region (10), wherein the base layer (15) has a second conductivity type different from the first conductivity type, - an emitter layer (13) arranged between the base layer (15) and the first main surface (F1) in the region (10) of an insulated gate bipolar transistor, wherein the emitter layer (13) has the first conductivity type, - a base contact layer (14) arranged between the base layer (15) and the first main surface (F1) in the region (10) of an insulated gate bipolar transistor, wherein the base contact layer (14) forms part of the first main surface (F1), wherein the base contact layer (14) has the second conductivity type, - a collector layer (16) arranged between the drift layer (1) and the second main surface (F2) in the region (10) of an insulated gate bipolar transistor, wherein the collector layer (16) has the second conductivity type, an anode layer (25) disposed between the drift layer (1) and the first main surface (F1) in the diode region (20), the anode layer (25) having the second conductivity type, an anode contact region (24) disposed between the anode layer (25) and the first main surface (F1) in the diode region (20), the anode contact region (24) forming a part of the first main surface (F1), the anode contact region (24) having a peak value of a concentration of impurities of the second conductivity type higher than that of the anode layer (25), the anode contact region (24) having the second conductivity type, and a cathode layer (26), which is arranged between the drift layer (1) and the second main surface (F2) in the diode region (20), wherein the cathode layer (26) has the first conductivity type; - an insulated gate structure (11) for forming a channel with the base layer (15) in order to control an electrical path between the emitter layer (13) and the drift layer (1); - a collector electrode (7) electrically connected to the collector layer (16) and the cathode layer (26); and - an emitter electrode (5) in contact with the base contact layer (14) and the anode contact region (24), wherein: - the anode contact region (24) contains a first anode contact layer (24b) which has a concentration of impurities of the first conductivity type and a concentration of impurities of the second conductivity type, the concentration of impurities of the second conductivity type of the first anode contact layer (24b) is higher than the concentration of impurities of the first conductivity type of the first anode contact layer (24b), so that the first anode contact layer (24b) has the second conductivity type, the concentration of impurities of the first conductivity type of the first anode contact layer (24b) is higher than that of the base contact layer (14), and the first anode contact layer (24b) has a lower net concentration than that of the base contact layer (14).The reverse conducting semiconductor device (100-109) of claim 1, wherein: - the anode contact region (24) includes a second anode contact layer (24a), and - the first anode contact layer (24b) has a lower net concentration than the second anode contact layer (24a).The reverse conducting semiconductor device (100-109) according to claim 2, wherein the first anode contact layer (24b) has a higher concentration of impurities of the first conductivity type than the second anode contact layer (24a).The reverse conducting semiconductor device (100-109) according to any of the preceding claims, wherein the first main surface (F1) does not have the first conductivity type in the diode region (20).The reverse conducting semiconductor device (100-109) according to any of the preceding claims, wherein the anode layer (25) forms a part of the first main surface (F1).The reverse conducting semiconductor device (100-109) according to any one of the preceding claims, wherein a net peak concentration of the anode layer (25) is 1 × 10 10 / cm 3 or more.The reverse conducting semiconductor device (100-109) according to any one of the preceding claims, wherein a net peak concentration of the first anode contact layer (24b) is 1 × 10 18 / cm 3 or more.The reverse conducting semiconductor device (100-109) according to any one of the preceding claims, wherein in the diode region (20), the semiconductor substrate (50) has a minimum value of a net concentration profile in a thickness direction at a depth position between the first anode contact layer (24b) and the anode layer (25).The reverse conducting semiconductor device (100-109) according to any one of the preceding claims, wherein the first anode contact layer (24b) has a peak value of a net concentration profile in a thickness direction at a depth position away from the first main surface (F1).The reverse conducting semiconductor device (100-109) according to any of the preceding claims, wherein the semiconductor substrate (50) in the diode region (20) comprises an intermediate layer (29) having a first conductivity type in a thickness direction between the first anode contact layer (24b) and the anode layer (25).A method of manufacturing a reverse conducting semiconductor device (100-109), wherein: - the reverse conducting semiconductor device (100-109) is formed according to any of the preceding claims, and - the method comprises: - performing doping of impurities of the first conductivity type of the emitter layer (13) by ion implantation into the first main surface (F1) of the semiconductor substrate (50); and - performing doping of impurities of the first conductivity type of the first anode contact layer (24b) by ion implantation into the first main surface (F1) of the semiconductor substrate (50), and - the doping of impurities of the first conductivity type of the emitter layer (13) and the doping of impurities of the first conductivity type of the first anode contact layer (24b) as a common doping of impurities of the first conductivity type are performed simultaneously.The method of claim 11, further comprising: - performing doping of second conductivity type impurities of the base contact layer (14) by ion implantation into the first main surface (F1) of the semiconductor substrate (50); and - performing doping of second conductivity type impurities of the first anode contact layer (24b) by ion implantation into the first main surface (F1) of the semiconductor substrate (50), wherein the doping of second conductivity type impurities of the base contact layer (14) and the doping of second conductivity type impurities of the first anode contact layer (24b) are simultaneously performed as a common doping of second conductivity type impurities.The method according to claim 12, wherein an implantation amount of impurity ions of the first conductivity type per unit area in the joint doping of impurities of the first conductivity type is less than an implantation amount of impurity ions of the second conductivity type per unit area in the joint doping of impurities of the second conductivity type.

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