Structure of a multilevel cell configuration for a non-volatile memory element in a bit cell and method of manufacturing the same

Abstract

Structure (10), comprising: a first non-volatile memory element (14) having a first electrode (42), a second electrode (38) and a switching layer (40) between the first electrode (42) and the second electrode (38); a second non-volatile memory element (12) comprising a first electrode (42), a second electrode (38), and a switching layer (40) between the first electrode (42) and the second electrode (38); a third non-volatile memory element (13) having a first electrode (42), a second electrode (38) and a switching layer (40) between the first electrode (42) and the second electrode (38); a first bit line (60) connected to the first electrode (42) of the first non-volatile memory element (14) and to the first electrode (42) of the second non-volatile memory element (12); and a second bit line (62) connected to the first electrode (42) of the third non-volatile memory element (13), the second bit line (62) being aligned transversely to the first bit line (60).

Description

background

[0001] The present invention relates to integrated circuits and the fabrication of semiconductor devices, and more particularly to structures having non-volatile memory elements and methods of fabricating a structure having non-volatile memory elements.

[0002] Resistive random-access memory (ReRAM, or RRAM) is a type of embedded non-volatile memory technology. Because the storage elements are non-volatile, the stored data in resistive random-access memory is retained even when the storage elements are not supplied with power. The non-volatility of resistive random-access memory contrasts with volatile memory technologies such as dynamic random-access memory (DRAM), which loses stored data unless it is regularly refreshed, or static random-access memory (SRAM), which eventually loses stored data if it is not supplied with power.

[0003] Data is stored in a storage element of each bit cell of a resistive random access memory by changing the resistance across a switching layer to create different resistance states, namely a high resistance state and a low resistance state. The switching layer can be written to the low resistance state by applying a bias voltage sufficient to form one or more filaments that define conductive paths spanning the thickness of the switching layer. The filaments can also be destroyed by applying a bias voltage to the switching layer to write to the high resistance state.

[0004] US 10 700 277 B1 discloses a memory device comprising a bottom electrode, a first switching element, and a second switching element arranged above the bottom electrode, a first top electrode arranged above the first switching element, the first top electrode comprising a first contact surface in contact with the first switching element, and a second top electrode arranged above the second switching element, the second top electrode comprising a second contact surface in contact with the second switching element. The first switching element comprises a resistor configured to switch between a first resistance value and a second resistance value in response to a change in the voltage applied between the first top electrode and the bottom electrode.The second switching element has a resistor configured to switch between a third resistance value and a fourth resistance value in response to a change in the voltage applied between the second upper electrode and the lower electrode. The lower electrode comprises at least one conductive layer having a third contact surface in contact with the first switching element and a fourth contact surface in contact with the second switching element. An area of ​​the first contact surface is larger than an area of ​​the third contact surface, and an area of ​​the second contact surface is larger than an area of ​​the fourth contact surface.

[0005] From the document 2015 / 0 357 376 A1 a semiconductor memory device is known, comprising a first bit line located at a first height above a semiconductor substrate, a second bit line located at a second height above the semiconductor substrate, wherein the second height differs from the first height, a first memory element with variable resistance, which is connected to the first bit line and is located at a third height above the semiconductor substrate, and a second memory element with variable resistance, which is connected to the second bit line and is located substantially at the third height.

[0006] The document DE 11 2017 006 212 T5 describes a resistive random access memory cell comprising a first resistive random access memory device having an ion source layer and a solid electrolyte layer, a second resistive random access memory device having an ion source layer and a solid electrolyte layer connected in series with the first resistive random access memory device such that either both ion source layers or both solid electrolyte layers are adjacent to one another, and a third resistive random access memory device having an ion source layer and a solid electrolyte layer connected in series with the first and second resistive random access memory devices.

[0007] The document US 2020 / 0 321 396 A1 discloses an integrated circuit with a memory cell, wherein the memory cell comprises a transistor with a source and a drain, a first resistance unit in electrical connection with the source, and a second resistance unit in electrical connection with the drain. The first resistance unit comprises a first lower electrode, a first upper electrode, and a first resistance element positioned between the first lower electrode and the first upper electrode. The second resistance unit comprises a second lower electrode, a second upper electrode, and a second resistance element positioned between the second lower electrode and the second upper electrode.

[0008] The object is to provide improved structures with non-volatile memory elements and improved methods for producing a structure with non-volatile memory elements.

[0009] The object is achieved by a structure according to patent claim 1 and a method according to patent claim 14. Further embodiments emerge from the dependent patent claims. Summary

[0010] According to one embodiment of the invention, a structure comprises a first non-volatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, a second non-volatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, and a third non-volatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is connected to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is connected to the first electrode of the third non-volatile memory element, the second bit line being aligned transversely to the first bit line.

[0011] According to another embodiment of the invention, a method comprises forming a first non-volatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, forming a second non-volatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode, and forming a third non-volatile memory element having a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode.The method further comprises forming a first bit line connected to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element, and forming a second bit line connected to the first electrode of the third non-volatile memory element, the second bit line being aligned transversely to the first bit line. Short description of the drawings

[0012] The accompanying drawings illustrate various embodiments of the invention and, together with the general description of the invention above and the detailed description of the embodiments below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features throughout the different views. Fig. 1 is a schematic top view of a structure for a multi-bit multi-level bit cell according to embodiments of the invention. Fig. Figure 2 is a cross-sectional view taken generally along line 2-2 in Fig. 1 runs. Fig. 3 is a cross-sectional view taken generally along line 3-3 in Fig. 1 runs. Fig. Figure 4 is a cross-sectional view taken generally along line 4-4 in Fig. 1 runs. Detailed description

[0013] With reference to Figures 1-4, and in accordance with embodiments of the invention, a structure 10 for a multi-bit, multi-level bit cell includes a non-volatile memory element 12, a non-volatile memory element 13, a non-volatile memory element 14, and a field-effect transistor 16. The field-effect transistor 16 may be fabricated by CMOS processing using a substrate 18 comprising a semiconductor material such as single-crystal silicon. The structure 10 may be part of a memory array comprising multiple bit cells substantially similar or identical to the structure 10.

[0014] The field-effect transistor 16 may include a gate electrode 22, a gate dielectric layer 24, a source region 26, and a drain region 28. The gate electrode 22 may be formed from heavily doped polysilicon deposited as a flat layer over the substrate 18 and patterned using lithography and etching techniques. The gate dielectric layer 24 may be formed from silicon dioxide, which is deposited and patterned when the gate electrode 22 is patterned. Alternatively, the gate electrode 22 may be a metal gate formed by a gate-first process or a replacement gate process, and the gate dielectric layer 24 may be formed from a high-k dielectric material. The gate electrode 22 may have multiple fingers connected together at one end. The source region 26 and the drain region 28 may represent doped portions of the substrate 18.The source region 26 and the drain region 28 may be doped with an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type electrical conductivity, or alternatively, the source region 26 and the drain region 28 may be doped with a p-type dopant (e.g., boron) that provides p-type electrical conductivity.

[0015] An interconnect structure 30 may be formed by middle-of-line processing and back-end-of-line processing over the field-effect transistor 16 and the substrate 18. The interconnect structure 30 includes metallization levels with interlayer dielectric layers 31 and metal features disposed in the interlayer dielectric layers 31. The interlayer dielectric layers 31 may be formed from a dielectric material, e.g., carbon-doped silicon dioxide. Conductive features in the various interlayer dielectric layers 31 of the interconnect structure 30 connect the field-effect transistor 16 to the non-volatile memory element 14 and provide the connections for the lines used to read data from and write data to the structure 10.

[0016] The non-volatile memory elements 12, 13, 14 are arranged in a plane of the structure 10 located between a metallization plane 80 and one or more metallization planes 82 of the interconnect structure 30. The non-volatile memory elements 12, 14 are arranged next to one another in a horizontal direction within the plane, and the non-volatile memory elements 12, 13 are also arranged next to one another in a different horizontal direction within the plane. The non-volatile memory elements 12, 13, 14 are not stacked vertically within different planes in the interconnect structure 30.

[0017] In one embodiment, the non-volatile memory elements 12, 13, 14 may be constructed as resistive memory elements comprising a lower electrode 38, a switching layer 40 arranged on the lower electrode 38, and an upper electrode 42 arranged on the switching layer 40. The switching layer 40 is arranged vertically between the lower electrode 38 and the upper electrode 42. The lower electrode 38 may be formed from a metal, e.g., ruthenium, platinum, titanium nitride, or tantalum nitride. The switching layer 40 may be formed from a dielectric material, e.g., silicon dioxide, silicon nitride, or a metal oxide (e.g., magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, or aluminum oxide). The upper electrode 42 may be formed from a metal such as tantalum, hafnium, titanium, copper, silver, cobalt, or tungsten.The lower electrode 38, the switching layer 40 and the upper electrode 42 of each of the non-volatile memory elements 12, 13, 14 can be formed simultaneously by common lithography and etching processes that form a deposited layer stack of the materials forming them.

[0018] Data is stored in the structure 10 by varying the individual electrical resistances of the switching layers 40 of the non-volatile memory elements 12, 13, 14 by applying bias voltages to create different overall resistance levels. The electrical resistance of the switching layer 40 can be reduced by applying a bias voltage to the switching layer 40 to create one or more filaments or conductive paths that bridge between the electrodes 38, 42. The electrical resistance of the dielectric material can be increased by applying a bias voltage to the switching layer 40 to destroy the filaments. In this context, filaments are created to write the low-resistance state of each of the non-volatile memory elements 12, 13, 14, and filaments are destroyed to write the high-resistance state of each of the non-volatile memory elements 12, 13, 14.

[0019] In combination, the low resistance and high resistance states of the non-volatile memory elements 12, 13, 14 can be used to store data in multiple levels (e.g., eight state combinations). In one embodiment, the non-volatile memory elements 12, 13, 14 can have nominally equal sizes such that their resistance values ​​in the high resistance state are approximately the same and their resistance values ​​in the low resistance state are approximately the same. In one embodiment, at least two of the non-volatile memory elements 12, 13, 14 can have different sizes such that their resistance values ​​in the high resistance state and their resistance values ​​in the low resistance state are different, which can increase the number of state combinations available as levels for the structure 10.

[0020] The interconnect structure 30 includes a select line 44 that is physically and electrically connected (i.e., coupled) to the source region 26 of the field-effect transistor 16 via one or more source contacts 46. The interconnect structure 30 also includes one or more drain contacts 48, metal islands, and one or more vias 50 that physically and electrically connect (i.e., couple) the drain region 28 of the field-effect transistor 16 to the bottom electrode 38 of the non-volatile memory element 12. A word line 52 is connected to the gate electrode 22 of the field-effect transistor 16 via one or more vias (not shown).

[0021] A bitline stripe 54 is physically and electrically connected (i.e., coupled) to the top electrode 42 of the non-volatile memory element 12 and also physically and electrically connected (i.e., coupled) to the top electrode 42 of the non-volatile memory element 14. The bitline stripe 54 is physically and electrically connected (i.e., coupled) to a bitline 60 via one or more vias 56. In this way, the bitline stripe 54 commonly connects the bitline 60 to the top electrode 42 of the non-volatile memory element 12 and the top electrode 42 of the non-volatile memory element 14.

[0022] A bit line 58 is physically and electrically connected (i.e., coupled) to the bottom electrode 38 of the non-volatile memory element 13 and also to the bottom electrode 38 of the non-volatile memory element 14. In one embodiment, the bit line 58 may be directly coupled to the bottom electrode 38 of the non-volatile memory element 13 and directly to the bottom electrode 38 of the non-volatile memory element 14. A bit line 62 is physically and electrically connected (i.e., coupled) to the top electrode 42 of the non-volatile memory element 13. In one embodiment, the bit line 62 may be directly connected to the top electrode 42 of the non-volatile memory element 13.

[0023] Bit line 58 and bit line 62 control access to non-volatile memory element 13, and bit line 58 and bit line 60 control access to non-volatile memory elements 12, 14. Bit line 58 is arranged vertically below non-volatile memory elements 12, 13, 14, and bit line stripe 54 and bit lines 60, 62 are arranged vertically above non-volatile memory elements 12, 13, 14. Bit line 60 is aligned parallel or substantially parallel to bit line 58, and bit line 60 is arranged vertically above bit line 58 and above bit line 62. Non-volatile memory element 12 overlaps with a portion of bit line 58. However, non-volatile memory element 14 is laterally (i.e., horizontally) offset from bit line 58.The bit line 62, which is arranged vertically between the bit line 58 and the bit line 60, is connected only to the upper electrode 42 of the non-volatile memory element 13 and not to any of the non-volatile memory elements 12, 14. The bit line 62 is arranged in the same metallization level 82 as the bit line stripe 54, but laterally offset (i.e., horizontally offset) from the bit line stripe 54. The horizontal direction of the offset of the bit line 62 relative to the bit line stripe 54 may be transverse to the horizontal direction of the offset of the non-volatile memory element 14 relative to the bit line 58. The non-volatile memory elements 12, 13, 14, the bit line stripe 54, and the bit line 62 are arranged in a vertical direction between the bit line 58 and the bit line 60. The non-volatile memory element 13 is arranged in the vertical direction between the bit line 60 and the bit line 62.

[0024] A portion of the bit line 62 overlaps with the non-volatile memory element 13, and the non-volatile memory element 13 overlaps with a portion of the bit line 58. The bit line 58 is located below the bit line 62 and is aligned transversely to the bit line 62. In the latter respect, the bit line 58 includes a longitudinal axis 70 and the bit line 62 includes a longitudinal axis 72 that is aligned transversely to the longitudinal axis 70. The non-volatile memory elements 12, 14 are spaced along the longitudinal axis 70 of the bit line 58. The bit line 60 is located above the bit line 62 and is aligned transversely to the bit line 62. In the latter respect, the bit line 60 includes a longitudinal axis 68 that is aligned transversely to the longitudinal axis 72 of the bit line 62.

[0025] The source contacts 46 and the drain contacts 48 may be formed in contact openings defined by lithography and etching in one or more of the interlayer dielectrics 31. The source contacts 46 and the drain contacts 48 may include a lower portion comprising a metal silicide, such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide, formed by silicidation, and an upper portion comprising a metal, such as tungsten, deposited and planarized by chemical vapor deposition. The select line 44, the vias 50, the word line 52, the bit line stripe 54, the bit lines 58, 60, 62, and the metal islands may be formed by a damascene process in which trenches are patterned in one or more of the interlayer dielectrics 31 and the trenches are filled with a conductor, e.g., copper.

[0026] In use, the non-volatile memory elements 12, 14 may be transitioned from a high resistance state to a low resistance state by a commit operation in a first step of a two-step process. One, both, or neither of the non-volatile memory elements 12, 14 may then be written from the low resistance state to a high resistance state by a reset operation to provide multiple levels with different state combinations. In a subsequent step of the two-step process, the non-volatile memory element 13 may then be read and, if necessary, separately switched by commit and reset operations to write either a high resistance state or a low resistance state, providing a mechanism for providing additional multiple levels with different state combinations.In an alternative sequence for the two-stage process, the non-volatile memory element 13 can be read and, if necessary, written, followed by a subsequent step of writing the non-volatile memory elements 12, 14. The combination of the non-volatile memory elements 12, 13, 14 can be placed in multiple levels characterized by different state combinations in which the non-volatile memory elements 12, 13, 14 have different combinations of low resistance and high resistance states. The structure 10 can therefore be programmed to any of these multiple levels. The bit lines 60, 62 provide additional biasing mechanisms for controlling the two-stage process that provides the different state combinations of the multiple levels.

[0027] In an alternative embodiment, the non-volatile memory elements 12, 13, 14 may be phase-change material (PCM) memory elements, in which the switching layer 40 may be a phase-change material such as a chalcogenide glass (e.g., Ge 2 Sb 2 The 5). The phase change material can be heated above a transition temperature and cooled to form either an amorphous phase or a crystalline phase, which define the high-resistance and low-resistance states, respectively. More specifically, the phase change material can be heated by applying an electric current sufficient to raise the temperature of the switching layer 40 above the transition temperature and then cooled to a temperature below the transition temperature to cause a change of state. The change of state of the phase change material to the amorphous phase or the crystalline phase can depend, for example, on the cooling rate.

[0028] In an alternative embodiment, the non-volatile memory elements 12, 13, 14 may be ferroelectric memory elements comprising a ferroelectric material as the switching layer 40. The ferroelectric material of the switching layer 40 may comprise, for example, lead zirconate titanate (PZT).

[0029] In an alternative embodiment, the non-volatile memory elements 12, 13, 14 may be magnetic tunnel junction memory elements. In this regard, each of the non-volatile memory elements 12, 13, 14 may comprise a fixed layer, a tunnel barrier layer, and a free layer arranged in a layer stack between the lower and upper electrodes 38, 42. The fixed layer may comprise one or more layers, such as a reference layer and a hard layer, formed from a magnetic material, such as a cobalt-platinum alloy or a cobalt-iron-boron alloy. The tunnel barrier layer may be formed from a non-magnetic dielectric material, such as magnesium oxide or aluminum oxide. The free layer forming the switching layer 40 may comprise one or more layers of a magnetic alloy, such as a cobalt-iron-boron alloy.The magnetization of the reference layer of the fixed layer is fixed so that the magnetization vector cannot reverse (i.e., rotate) under the influence of a programming current. The magnetization of the free layer is not pinned, so the magnetization vector can flip (i.e., rotate) under the influence of a programming current.

[0030] The field-effect transistor 16 and the non-volatile memory elements 12, 13, 14 have a 1T3R (single-transistor, three-resistor) multi-level cell (MLC) configuration, capable of storing multiple bits in a single bit cell, which can lead to improved density and reduced cost per bit compared to conventional non-volatile memory bit cells. The non-volatile memory elements 12, 13, 14 can be formed using the same lithography and etching processes, promoting efficient manufacturing.

[0031] The processes described above are used in the manufacture of integrated circuits. The resulting integrated circuit chips can be distributed by the manufacturer in the form of unprocessed wafers (e.g., a single wafer containing multiple unpackaged chips), as a bare chip, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product containing integrated circuit chips, such as computer products with a central processor or smartphones.

[0032] Reference in this document to terms modified by imprecise terms such as "approximately," "about," and "substantially" is not intended to be limited to the exact value. The imprecise term may correspond to the accuracy of an instrument used to measure the value and, unless otherwise dependent upon the instrument's accuracy, may mean + / - 10% of the stated value(s).

[0033] Reference to terms such as "vertical," "horizontal," etc., is used herein only by way of example and not as a limitation, to provide a frame of reference. As used herein, "horizontal" is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the just-defined horizontal. The term "lateral" refers to a direction within the horizontal plane.

[0034] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present instead. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if there is at least one intervening feature. A feature that is "on" or "in contact" with another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present instead. A feature may be "directly on" or in "direct contact" with another feature if there are no intervening features.A feature can be “indirectly on” another feature or in “indirect contact” with it if at least one intervening feature is present.

Claims

[1] Structure (10), comprising: a first non-volatile memory element (14) having a first electrode (42), a second electrode (38) and a switching layer (40) between the first electrode (42) and the second electrode (38); a second non-volatile memory element (12) comprising a first electrode (42), a second electrode (38), and a switching layer (40) between the first electrode (42) and the second electrode (38); a third non-volatile memory element (13) having a first electrode (42), a second electrode (38) and a switching layer (40) between the first electrode (42) and the second electrode (38); a first bit line (60) connected to the first electrode (42) of the first non-volatile memory element (14) and to the first electrode (42) of the second non-volatile memory element (12); and a second bit line (62) connected to the first electrode (42) of the third non-volatile memory element (13), the second bit line (62) being aligned transversely to the first bit line (60). [2] Structure (10) according to claim 1, further comprising: a third bit line (58) connected to the second electrode (38) of the first non-volatile memory element (14) and to the second electrode (38) of the third non-volatile memory element (13). [3] The structure (10) of claim 2, wherein the third bit line (58) is aligned parallel to the first bit line (60). [4] The structure (10) of claim 2, wherein the third non-volatile memory element (13) is arranged vertically between the second bit line (62) and the third bit line (58). [5] The structure (10) of claim 4, wherein the first non-volatile memory element (14) is arranged between the first bit line (60) and the third bit line (58) in the vertical direction. [6] Structure (10) according to claim 5, further comprising: a bit line strip (54) connected to the first electrode (42) of the first non-volatile memory element (14) and the first electrode (42) of the second non-volatile memory element (12), wherein the first bit line (60) is connected by the bit line strip (54) to the first electrode (42) of the first non-volatile memory element (14) and the first electrode (42) of the second non-volatile memory element (12). [7] Structure (10) according to claim 2, further comprising: a field effect transistor (16) with a drain (28), wherein the drain (28) of the field effect transistor (16) is coupled to the second electrode (38) of the second non-volatile memory element (12). [8] The structure (10) of claim 2, wherein the first non-volatile memory element (14) and the third non-volatile memory element (13) are arranged side by side above the third bit line (58), and wherein the first non-volatile memory element (14) is arranged with a lateral offset relative to the second bit line (62). [9] The structure (10) of claim 2, wherein the third bit line (58) is directly coupled to the second electrode (38) of the first non-volatile memory element (14) and to the second electrode (38) of the third non-volatile memory element (13). [10] The structure (10) of claim 2, wherein the first non-volatile memory element (14) and the third non-volatile memory element (13) are spaced along a longitudinal axis (70) of the third bit line (58). [11] The structure (10) of claim 1, wherein the switching layer (40) of the first non-volatile memory element (14) and the switching layer (40) of the second non-volatile memory element (12) each comprise a dielectric material. [12] The structure (10) of claim 1, wherein the switching layer (40) of the first non-volatile memory element (14) and the switching layer (40) of the second non-volatile memory element (12) each comprise a phase change material. [13] The structure (10) of claim 1, wherein the switching layer (40) of the first non-volatile memory element (14) and the switching layer (40) of the second non-volatile memory element (12) each comprise a ferroelectric material. [14] Method comprising: forming a first non-volatile memory element (14) having a first electrode (42), a second electrode (38), and a switching layer (40) between the first electrode (42) and the second electrode (38); forming a second non-volatile memory element (12) having a first electrode (42), a second electrode (38) and a switching layer (40) between the first electrode (42) and the second electrode (38); forming a third non-volatile memory element (13) having a first electrode (42), a second electrode (38) and a switching layer (40) between the first electrode (42) and the second electrode (38); forming a first bit line (60) coupled to the first electrode (42) of the first non-volatile memory element (14) and to the first electrode (42) of the second non-volatile memory element (12); and forming a second bit line (62) coupled to the first electrode (42) of the third non-volatile memory element (13), the second bit line (62) being aligned transversely to the first bit line (60). [15] The method of claim 14, wherein the first non-volatile memory element (14), the second non-volatile memory element (12) and the third non-volatile memory element (13) are formed simultaneously by lithography and etching processes. [16] The method of claim 14, further comprising: forming a third bit line (58) connected to the second electrode (38) of the first non-volatile memory element (14) and to the second electrode (38) of the third non-volatile memory element (13). [17] The method of claim 16, wherein the third bit line (58) is aligned parallel to the first bit line (60). [18] The method of claim 16, wherein the third non-volatile memory element (13) is arranged in a vertical direction between the second bit line (62) and the third bit line (58) and the first non-volatile memory element (14) is arranged in the vertical direction between the first bit line (60) and the third bit line (58).

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