Control circuit and method for controlling a data input / output

Abstract

Control circuit (200) for controlling a data input / output, comprising: • a plurality of control stages comprising at least a first control stage and a last control stage, each of the control stages comprising at least one control element (224); • wherein a number of control elements (224) of the last control stage is greater than a number of control elements of the first control stage; • wherein each of the control elements (224) is configured to receive a first control signal and a second control signal and to control a current for the data input / output in dependence on the first control signal and the second control signal; • wherein the control circuit (200) is configured to provide the first control signal to the respective control elements (224) in a sequence beginning at the first control stage and ending at the last control stage, and then additionally provide the second control signal to the control stages at least of the last control stage in a reverse sequence, wherein a current intensity of the current for the data input / output is increased by providing the second control signal.

Description

The invention relates to a control circuit and a method for controlling data input / output.In the case of data input / output, a signal is typically switched between (at least) two states, for example between a low voltage (low level potential) and a high voltage (high level potential), for example by means of transistors. Such a data signal can be provided, for example, at a data input / output pad or a contactless data input / output element.FIG. 1A shows two ideal profiles of such a data signal.The dashed line represents a square-wave signal 102 which switches between a low voltage (low level potential) and a high voltage (high level potential) without delay and, after the switching, keeps the voltage constant over a current intensity variance (low level output current and high level output current). This allows instant switching between the two states. After the charge reversal of the network node (line transmitter to receiver), the current for defining the logic level drops to the current intensity which is necessary for maintaining the level (leakage current of the transmitter and receiver and / or weak pull-up / down current for defining the receiver input voltage level for the case of transmitter in tristate mode). The abrupt current change, which precedes a voltage potential change of the network node (line transmitter to receiver, capacitive network node), leads to a strong (undesired) electromagnetic emission (EME), which in-coupled fashion (galvanically on the power supply of the transmitter and receiver or field-coupled via the conductor loop on the printed circuit board) will generate a noise signal (interference power). Such electromagnetic emission occurs in principle during transistor switching operations and depends on an internal interconnection (process energy), a driver strength (i.e. a current strength which is provided), a switching frequency and the load pick-up (capacitive, resistive, inductive).Solid line 104 represents a sinusoidal switching characteristic of signal 102 between the low voltage and the high voltage. The smooth continuous current waveform (current differential, current rate of change per time) of switching the voltage level reduces electromagnetic emissions because a sinusoidal waveform does not generate frequency harmonics (only the fundamental wave). However, after a switching command, the target state (e.g. reaching the maximum or minimum voltage) is only reached with a time delay here, which is typically likewise undesirable, since in general it is desirable to provide as short switching times as possible (quickly reaching the new level state (high data rates / frequencies).In FIG. 1B, a real switching current signal 106 is shown, which occurs when a data input / output is switched from a low voltage level to a high voltage level.As can be seen from a comparison of the real signal 106 from FIG. 1B with the ideal signals from FIG. 1A, the real signal 106 represents an averaging between the two ideal signals, in particular in the increase: the increase does not run as abruptly as in the case of the square-wave signal 102, but also not as smoothly as in the case of the sinusoidal signal 104. The real signal 106 thus represents a compromise between a (as low as possible) switching speed and an (likewise as low as possible) electromagnetic emission.According to the latest designs, however, such high switching frequencies with such high power consumption are required during the data input / output that the electromagnetic emission can be above acceptable limits, e.g. above limits specified by customers or e.g. above legally prescribed limit values for electromagnetic compatibility (EMC).There is thus a need to provide a data input / output with switching times that are as short as possible while maintaining limit values for electromagnetic emission (e.g. EMC limits).DE 10 2014 118 156 A1 discloses a bus driver circuit. The driver circuit includes first and second circuit nodes, the first node being operatively coupled to a bus line that causes bus capacitance between the first and second circuit nodes. A switching circuit is coupled to the first circuit node and is configured to apply an output voltage between the first and second circuit nodes. In this case, the bus capacitance is charged if a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and second circuit nodes and is configured to enable the bus capacitance to be discharged across the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide, in addition to the discharge circuit, a temporary current path for discharging the bus capacitance during a transition time period from a dominant state to a recessive state.DE 699 27 911 T2 discloses a low noise CMOS circuit for providing a current profile for a constant impedance load and a linear-ramp current profile at the circuit output upon receipt of an input signal at a circuit input.A control circuit according to claim 1 and a method of controlling data input / output according to claim 17 are provided. Further embodiments are described in the dependent claims.In various embodiments, a control circuit and a method for controlling a data input / output are provided, which make it possible to minimize electromagnetic emission caused by the switching operation despite short switching times.In various embodiments, when switching a current for data input / output (also referred to as driving current or driven current) from a minimum value to a maximum value, the current change may be smaller near the minimum (start of level change) and maximum value (66% value of level end value), respectively, than in the prior art, and may be stronger near an average value between the minimum and maximum values (50% value of level change, steepest current rise to change voltage level) than in the prior art.In various exemplary embodiments, the control circuit can be configured to realize a gradual increase in the current intensity at the beginning (only a few parts of the switching stage active), a steep, rapid current rise ("boost") in the middle (all parts of the switching stage active) and a gradual flattening of the current rise towards the end of a switching process (asymptotic approach of the level in the case of capacitive loads causes reducing charging currents) from a low-current data signal to a high-current data signal.For this purpose, according to various exemplary embodiments, a stepwise connection of control elements, for example current control elements (for example divided transistors, so-called transistor fingers), which are connected in some parallel can be used.The control elements can be provided, for example--described clearly--in a firtree-like configuration, according to which, starting at the tree tip (e.g. one or two transistor fingers of the main transistor), an increasing number of parallel-connected control elements (transistor fingers of the main transistor) is partially connected in successive switching steps. This switching behavior of one / two transistor fingers of the main transistor over the parasitic gate resistances and gate capacitances with a time delay to the next instance (doubling of the number of transistor fingers of the main transistor) and the further interconnection (usually always a further doubling) of the instances up to the depth of 4 instances produces a controlled, avalanche-like increase in the switching current.In the case of a transition from a partial switching state to a complete switching state, the control elements (transistor fingers of the main transistor) are also switched on from the opposite side-illustratively from the firtree base to the firtree tip.This double side switching of the transistor finger gates of the main transistor achieves a more stable and faster turn-on state than the turn-on definition from the firtree tip.The firtree base terminal has the more direct transistor finger gate drive of the main transistor (less gate voltage drop by paralleling the transistor finger elements).Accordingly, directly after the control stage is partially switched with the most numerous control elements connected in parallel (at the firtree base), the complete switching of these most numerous control elements takes place. This corresponds to a boost mode in which the current intensity rises sharply within a short time, whereas the partial activation of fewer control elements at the beginning and at the end of the switching operation can realize the gradual increase of the current.Thus, the capacitive load may be recharged in approximation to a sine / cosine function of the switching current and thus harmonic harmonic oscillations may be reduced, which would lead to electromagnetic emission, which may be radiated and / or fed as noise / interference power to the control circuit, the data input / output pad (e.g. a high-speed data interface port) or the like.By means of the low-emission profile of the driver current curve realized on the basis of a control characteristic of the control elements, it is possible to dispense with additional circuit elements such as, for example, RC elements or to reduce their number and / or to avoid the control elements (e.g. standardized transistor finger elements) being affected by strong electromagnetic emission. Even in the case of additional circuits which can be located on a printed circuit board (PCB), for example, together with the control circuit, a need for filtering out the electromagnetic emission possibly received can be reduced, so that components and therefore chip area and weight can be saved.Exemplary embodiments of the invention are illustrated in the figures and are explained in more detail below.They show FIG. 1A shows ideal cases of two types of data signals; FIG. 1B shows an example of a real data signal according to a prior art; FIG. 2 shows a schematic illustration of a control circuit according to various embodiments; FIGS. 3A and 3B each show a schematic illustration of a control circuit according to various exemplary embodiments; FIG. 4 shows a schematic illustration of control element arrangements according to various exemplary embodiments; FIG. 5 shows a schematic illustration of a control circuit according to various embodiments; FIG. 6 shows a representation of simulation results for streams for data input / output according to various exemplary embodiments in comparison with a prior art; and FIG. 7 shows a flow chart of a method for controlling data input / output according to various exemplary embodiments.In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.As explained above, switching a current for data input / output typically leads to electromagnetic emission, in particular during generation of a (possibly steep) current edge and possibly at other points of the current curve.In Figure 1, such points are numbered in the current curve.Turning on (marked 1) may possibly have the greatest effect on emission. Particularly in the case of a rapid switch-on, an emission potential can be enormous (harmonic oscillations with respect to the fundamental frequency), because a capacitive load at the data input can behave like a short circuit at the driver transistor (wherein a switch-on resistor R DSon between source and drain of the transistor can limit a peak current when switch-on).Ideal turn-on behavior (with regard to emissions) would result in a sine- or cosine-shaped signal. In that case, the on-resistance of the transistor would accordingly be changed from the initial state (1 in FIG. 1B ; the desired optimum profile is not realized in FIG. 1B, which shows a real current profile according to a prior art, the comparison with FIG. 1B and the markings 1 to 4 used there merely serve for better understanding and the orientation along the current profile curve) to a state with a low resistance (marked with 2 in FIG. 1B ). In the vicinity of the region marked with 2, a current change rate can reach its maximum value (similar to that in the case of a sine / cosine signal).At the point marked 3, the maximum current can be provided and the on-resistance R DSon is minimized.In the case of a transition from the region marked with 3 to the region marked with 4, a current change rate can be limited by saturation of the capacitive load.The above-described configuration of a control circuit with staggered partial activation and subsequent full activation of groups of control elements connected in parallel ("firtree concept") has been developed with a view to generating a smooth activation behavior (capacitive short circuit, therefore minimum transistor finger number of the main transistor active) in the phase marked 1, and to generating a sufficiently strong signal sufficiently quickly in phase 3 (boost of the base of the firtree of the transistor fingers of the main transistor) in order on the one hand to provide a fast switching behavior and on the other hand to generate a signal insensitive to noise / interference power (so that the logic value associated with the current signal value is stable).In various embodiments, a high switching frequency with low electromagnetic emission can thus be provided for data input / output by means of a special intelligent switching sequence of the control elements of the control circuit.Once again, in other words, neither all control elements are switched simultaneously nor all control elements are switched one after the other, but a switching sequence is realized in which, in a first control stage, first a small number of control elements (e.g. a single one) is switched at least partially to be transmissive for a driven current, and then, in a second control stage, simultaneously a larger number (i.e. greater than in the first control stage) of control elements (e.g. at least two) is switched partially to be transmissive. In other words, a simultaneously connected number of control elements is increased in a time sequence, for example in a cascade or avalanche manner.In various exemplary embodiments, more than two control stages can be provided, for example at least three control stages, for example four or five control stages.In a reverse switching sequence, the control elements of the control stages can subsequently be switched in such a way that their current permeability is further increased, for example to a maximum possible permeability to them.In other words, a resistance of the control elements in the "forward" switching operation (as the number of control elements per control stage increases) can be decreased, and in the reverse "reverse" switching operation, the resistance (Rdson of the main driving transistor) can be decreased even further, respectively.In various exemplary embodiments, providing a first control signal to the control elements of the last control stage in a first direction (the forward direction) can trigger providing a second control signal to the control elements of the last control stage (and optionally of the further control stages up to the first control stage) in a second direction (the reverse direction).In various exemplary embodiments, the control elements can be constructed in the same way, for example as (for example standardized or standardized similar) transistor fingers.FIGS. 2, 3A and 3B each show a schematic representation of a control circuit 200 according to various embodiments, FIG. 4 shows a schematic representation of control element arrangements 224 which may be part of a control circuit 200 according to various embodiments, and FIG. 5 shows a schematic representation of a control circuit 200 according to various embodiments. In this case, it facilitates understanding if some of the figures are used together, because parts are shown in a highly schematic manner for the sake of better clarity.The control circuit 200 may be provided for controlling a data input / output, for example by means of a data input / output pad or by means of a contactless data input / output element.The control circuit 200 may include a plurality m of control stages including at least a first control stage (m=1) and a last control stage (index m). Typically, more than two control stages may be provided, for example three, four or five control stages.Each of the control stages may include at least one control element 224.In FIGS. 2, 3A and 3B, the control elements 224 are each shown in a highly schematic manner (as rectangles with two connections). In FIG. 3A at the top right and in FIG. 3B at the bottom left (there with additional reference numerals), insertions to be understood as legend are illustrated symbolically, as in the exemplary embodiments from FIGS. 2, 3A and 3B the schematic representation is to be understood: each rectangle represents a gate (a transistor finger of the main driver transistor) of a transistor, wherein the gate has two terminals 224A 1, 224A 2. A channel connecting a source terminal 224S and a drain terminal 224D is controlled by the gate. These are symbolized in the legend as a light gray region or as bars orthogonal to the gate and have been completely omitted in the "pine-tree" illustration.In FIG. 4, a circuit diagram is selected for the individual control elements 224. There, each of the twelve control elements 224 shown is of the same construction, so that, for the sake of clarity, designations of the connections have been distributed to a plurality of individual control elements 224.In the figures, the control elements 224 (for clarity only partially, e.g. in FIGS. 2 and 3A ) are provided with indices indicating the control stage m and ordinal number within the control stage n according to the scheme 224_mn, for example for the first control element of the fifth control stage 224_ 51.A number of control elements 224 may increase or remain the same, for example, from control stage to control stage. To achieve a particular current profile, it may also be possible to reduce a number n of control elements 224 from one control stage to the next, provided that it is ensured that a number n(m) of control elements 224 of the last (m-th) control stage 224_m is greater than a number n(1) of control elements 224_ 1 of the first control stage.Three example control element arrangements are shown in FIG. 4, which are referred to as first instance 224_Inst 1 (bottom down), second instance 224_Inst 2 (middle) and third instance 224_Inst 3 (top).The instances 224_addInst 1 to 224_Inst 3 may be used as main driver transistors for data input / output. Accordingly, the control circuit 200 according to various embodiments, which uses the control element arrangements of the instances 224_Inst 1 to 224_Inst 3, may also be referred to as a data input / output unit.The control element arrangement of the first instance 224_Inst 1 includes a control element 224 in each of the first three control stages and 24 control elements 224 in the fourth and last control stages, and thus a total of 27 double-finger transistors. This provides a strong driver (i.e. a high DC current (in the exemplary embodiment approximately 31 mA) is made possible) with a steep / fast current rise edge for high data frequencies.The control element arrangement of the second instance 224_Inst 2 includes a control element 224 in each of the first two control stages, two control elements 224 in the third control stage and five control elements 224 in the fourth and last control stages, and thus altogether nine double finger transistors. This provides a medium-strength driver (i.e. a medium DC current (in the exemplary embodiment about 6 mA) is made possible) with a medium-speed current rise for low data frequencies.The control element arrangement of the third instance 223_Inst 3 includes a control element 224 in the first control stage, two control elements 224 in the second control stage, five control elements 224 in the third control stage and ten control elements 224 in the fourth and last control stage, and thus a total of 18 double finger transistors. This provides a strong driver (i.e. a high DC current (in the exemplary embodiment about 17 mA) is made possible) with a medium-average current rise edge for medium data frequencies.In Figure 4, the N and P inputs are shown to the left, which form the top of the "firtree", the outputs are shown to the right, and the booster input is shown below it (which form the base of the "firtree").Each of the control elements 224 may be configured to receive a first control signal and a second control signal and, depending on the first control signal and the second control signal, control a current for data input / output, which flows between the source 224S and the drain 224D.In FIGS. 3A and 3B, the example transistors of the control elements 224 are each provided with a first gate terminal 224A 1 and a second gate terminal 224A 2. The first gate terminals 224A 1 may each be disposed on a first side of a channel connected by the gate, and the second gate terminals 224A 2 may each be disposed on a second side of the channel opposite to the first side.Herein, the first control signal may be provided at the first gate terminal 224A 1 of a respective gate, and the second control signal may be provided at a second gate terminal 224A 2 of the same gate, respectively.As clearly described above, the control circuit 200 may be configured to provide the first control signal to the respective control elements (i.e. first to the control elements 224_ 1 and last to the control elements 224_m) in an order starting at the first control stage and ending at the last control stage, and then to provide the second control signal to the control stages at least to the last control stage in a reverse order (i.e. first to the control elements 224_m of the last control stage and then optionally to the control elements 224 in decreasing control stage order up to the first control stage).In various exemplary embodiments, the provision can be effected automatically or passively, for example by means of a capacitive coupling, i.e. the second gate terminal 2242of a preceding gate can be electrically conductively connected to the first gate terminal 224A1of a subsequent gate in order to provide the first control signal. Furthermore, by means of a signal at the second gate terminal 224A 2 of the control elements 224_m of the last control stage, a (stronger) control signal can be directly switched, which is supplied to these second gate terminals 224A 2 of the control elements 224_m of the last control stage than the second control signal.According to an alternative embodiment, the control elements can be switched indirectly or actively, for example by supplying a respective signal at one of the gate outputs to a controller which supplies the first control signal to the subsequent gate, and likewise vice versa for the second control signal.According to a further exemplary embodiment, an active and a passive provision of the control signal can be combined, for example by passively activating the control stages in the forward direction, then actively providing a control signal for switching to the reverse direction, and finally passively activating the control stages in the reverse direction, or for example by actively activating the control stages in the forward direction, then passively providing a control signal for switching to the reverse direction, and finally actively activating the control stages in the reverse direction.For the data input / output, a current intensity of the current can be increased by means of the provision of the second control signal.In other words, the control elements 224 may not be switched to be completely transmissive for the current for the data input / output by means of the first control signal, in particular in the higher control stages, but rather may be switched to be only partially transmissive. For example, a portion of the maximum drivable current provided after providing only the first control signal may be between 30% and 80%. In this case, the highest proportion can be achievable at the lowest control stage, the lowest proportion at the highest control stage.One cause for this can be parasitic capacitances which can attenuate the first control signal which is transmitted in each case from control elements 224 of a control stage to the control elements 224 of the subsequent control stage, such that the first control signal can be too weak, for example, already after the first control stage, in order to switch the control elements 224 of the subsequent control stage into a state of minimally achievable resistance.For switching the control elements 224 (at least for the at least one control element 224_ 1 of the first control stage in the first direction and the control elements 224_m of the last control stage in the reverse direction - the subsequent control elements 224 can be switched by the control elements 224 of the preceding control stages respectively) at least one pre-circuit 222 can be provided as part of the control circuit 200. This can have an A part 222A for switching the control elements 224 in the forward direction and a B part 222B for switching the control elements 224 in the reverse direction.In Fig. 5, the ballast circuit is shown in more detail. For each of the three instances shown there (which in various exemplary embodiments can be constructed as CMOS, i.e. a control element arrangement 224P based on PMOS transistors and an additional control element arrangement 224N based on NMOS transistors, see also FIGS. 3A and 3B in this respect), in each case two ballast circuit parts 222A / B can be provided, namely a ballast circuit part 222A / B for the NMOS control element arrangement 224N and an additional ballast circuit part 222A / B for the PMOS control element arrangement 224P, such that the ballast circuit 222 can have a total of six (two times three) of the ballast circuit parts 222A / B shown below in FIG. 5.In another number of instances or providing only as a PMOS or only as an NMOS circuit, the number of ballast circuit portions 222A / B may be changed accordingly.A first control signal provided after the last control stage may still be sufficiently strong despite the parasitic capacitances to make the second control signal available, for example to switch it by means of an additional transistor and to make it supply it to the control elements 224_m of the last control stage.When switching the control elements 224 in the control stages sequentially, the second control signal can also be attenuated due to parasitic capacitances. In various exemplary embodiments, however, the first switching signal and the second switching signal can be configured such that a state of minimally achievable resistance can be switched on a control element 224 by means of the combination of first switching signal and second switching signal.Since a comparatively small number of control elements 224_ 1 is switched with the first control stage and a comparatively large number of control elements 224_m is switched with the last control stage, and the large number is switched first to maximum permeability during the "reverse pass", and only then optionally the small number is switched with the first control stage, the slow, uniform increase of the provided current at the beginning and shortly before reaching the maximum current can thus be achieved in conjunction with a current which increases in a boost-like manner, i.e. rapidly and strongly, approximately centrally between the extreme values.As further illustrated in FIG. 5, the control circuit 200 may include a plurality of control element arrangements (instances). The instances may have different properties, as illustrated in FIG. 4 and illustrated in FIG. 6 on the basis of a simulation, as regards how the controlled current is driven, for example in terms of a speed and in terms of a maximum current achieved, which can be achieved in that the number of control elements 224 differs in each case in at least one control stage in comparison with one instance with another instance.The control circuit 200 may be configured to individually switch each of the instances. This means that, for example, all instances can be connected together in parallel, only one of the instances or a subset of the instances.For a maximum current, i.e. the fastest switching, all instances can be activated together. In the exemplary embodiment, the maximum current can form the sum of the maximum currents of the individual instances 1 to 3, i.e. in the exemplary embodiment illustrated in FIG. 4, a maximum current of 31 mA+17 mA+6 mA=54 mA can be provided.The summed signal according to a simulation of the exemplary embodiment from FIG. 4 is shown in FIG. 6 together with the individual signals. For comparison, a signal according to a prior art is also shown there, once slightly offset horizontally. The time offset results for the same switching time (at about 101.5 ns) in the control circuit 200 and the control circuit according to the prior art, because by interconnecting the double finger transistors of the three main driver transistors of a data input / output unit (see FIG. 4 ), the control circuit 200 generates a time delay (in the present example of about 500 ps). For better comparison, the prior art signal is once again shown with the same base point as the sum signal according to the exemplary embodiment explained in connection with FIG. 4, so that it can be seen that the summed signal initially rises more slowly than the signal according to the prior art, but both reach their maximum approximately simultaneously, which is achieved in various exemplary embodiments by means of the boost approximately in the middle between the minimum current and the maximum current.The comparison in FIG. 6 between the "adapted" current signal curve (at t=0, here t=101.5 ns) according to the prior art (dashed) and the cumulative curve of the instances 1 to 3 (solid) illustrates that a delay (of approximately 300 ps in this case) arises upon switching on, but is completely recovered again with the switching on of the booster. In addition, the maximum current value of circuit 200 remains about 10% below the value of the prior art according to various embodiments.The specific current setting during the changeover (sine rise) does not result in any disadvantage in the changeover delay. The switching time no longer becomes (ratio of switching time to high / low bit time), there is only a shift by 500 ps, which is not critical in the data protocol, since the entire period shifts.Furthermore, in various exemplary embodiments, for example depending on an application for which the data input / output is used, one or more of the instances can be switched, while other instances remain unused. This allows great flexibility with respect to the data signal to be generated.In various embodiments, the control circuit 200 may be provided with only one control element arrangement 224 (or also with two) with less flexibility.Illustratively described, controlling a data input / output by means of a control circuit 200, as is exemplarily illustrated in FIG. 3A and FIG. 3B, respectively (i.e. with a single control element in the first control stage 224_ 1, two control elements in the second control stage 224_ 2, four control elements in the third control stage 224_ 3, eight control elements in the fourth control stage 224_ 4 and sixteen control elements in the fifth control stage 224_ 5) may proceed as explained below.In this case, the gates that are parts of the transistors forming the control elements 224 may be used as RC elements (i.e. the gate resistance and the gate capacitance in combination with source-drain) in order to map a slow start for providing the current for the data input / output (by means of the single transistor 224_ 11 in the first control stage) and a subsequent avalanche-like increased speed (by means of the sixteen transistors connected in parallel in the fifth control stage).In this case, R DSon( or its reciprocal value) is designed by means of the number of transistor fingers that are switched on per unit time.When turned on, the "firtree" is turned on at the narrow end (i.e., the gate on the single transistor of the first control stage), while the wide end of the "firtree" (i.e., the sixteen transistors of the fifth switching stage) may be in a tristate state (e.g., not connected to any potential).After the gate potential slowly passes through the driver gates of the 32 transistors in the five control stages and, by providing the gate control signal at respective gate inputs of the transistors, has switched the respective channels controlled by the gates partially to the conducting state, the gates of the transistors in the fifth control stage are finally switched to the same potential as the gate of the transistor in the first control stage, namely by additionally providing a second control signal at a second gate input of the respective gates.In other words, the "firtree" is additionally connected from the broad end. This may occur at point 3 illustrated in FIG. 1B. In this case, the additional switching can be effected from the broad end delayed by: 1. a time constant (with respect to the transistor model used) (delay control) 2. or by means of an output level voltage return circuit (which measures an output voltage saturation point of the load capacitor), in this case the output voltage value is read between 50 and 66% and at this point the second side of the firtree (broad basis of the firtree structure of the single finger transistors of the haup transistor) is switched on in addition to the top of the firtree.The partially charged load capacitance is now recharged more rapidly in order now to recover the charge reversal delay upon switching on. The total switching times of the load capacitance are thus compensated by this boost circuit and no longer.FIG. 7 shows a flow chart of a method for controlling data input / output according to various embodiments.The method may include controlling data input / output using a plurality of control stages including at least a first control stage and a last control stage, each of the control stages including at least one control element, a number of control elements of the last control stage being greater than a number of control elements of the first control stage, the method including providing a first control signal to the respective control elements in an order starting at the first control stage and ending at the last control stage, for providing a current to the data input / output (710), and subsequently providing a second control signal to the control elements of at least the last control stage in a reverse order, wherein a current intensity of the current provided for the data input / output is increased (720) using the provision of the additional control signal.Some exemplary embodiments are given in summary below.Embodiment 1 is a control circuit for controlling data input / output. The control circuit may include a plurality of control stages including at least a first control stage and a last control stage, each of the control stages including at least one control element, a number of control elements of the last control stage being greater than a number of control elements of the first control stage, each of the control elements being configured to receive a first control signal and a second control signal and to control a current for data input / output depending on the first control signal and the second control signal, and wherein the control circuit is configured to provide the first control signal to the respective control elements in an order starting from the first control stage and ending at the last control stage, and thereafter to provide the second control signal to the control stages in a reverse order, wherein a current intensity of the current for the data input / output is increased by means of the provision of the second control signal.Embodiment 2 is a control circuit according to Embodiment 1, wherein each of the control elements includes at least one transistor.Embodiment 3 is a control circuit according to Embodiment 1 or 2, wherein the first control signal is provided at a first gate terminal of a respective gate.Embodiment 4 is a control circuit according to Embodiment 3, wherein the second control signal is provided to a second gate terminal of the same gate, respectively.Embodiment 5 is a control circuit according to Embodiment 4, wherein the first gate terminals are each disposed on a first side of a channel connected by the gate, and the second gate terminals are each disposed on a second side of the channel opposite to the first side.Embodiment 6 is a control circuit according to any one of Embodiments 1 to 5, wherein each of the control elements is formed as a CMOS element.Exemplary embodiment 7 is a control circuit according to one of exemplary embodiments 1 to 6, which is furthermore configured to switch the second control signal by means of the first control enable signal at the control elements of the last control stage.Embodiment 8 is a control circuit according to embodiment 7, further comprising at least one additional transistor configured to switch the second control signal.Exemplary embodiment 9 is a control circuit according to one of exemplary embodiments 1 to 8, wherein each of the control elements is configured to provide only a part of the maximum current which can be provided by the control element for the data input / output when only the first control signal is provided.Embodiment 10 is a control circuit according to Embodiment 9, wherein the part is between 30% and 80%.Embodiment 11 is a control circuit according to Embodiment 9 or 10, wherein the part decreases in the order of the control stages.Exemplary embodiment 12 is a control circuit according to one of exemplary embodiments 1 to 11, wherein each of the control elements is configured to provide the maximum current which can be provided by the control element for the data input / output when both the first control signal and the second control signal are provided to the control element.Embodiment 13 is a control circuit according to any one of Embodiments 1 to 12, further comprising an additional plurality of control stages formed like the plurality of control stages except that the number of control elements in at least one control stage of the plurality of control stages is different from the number of control elements in the corresponding control stage of the additional plurality of control stages, the additional plurality of control stages being connected in parallel to the plurality of control stages.Exemplary embodiment 14 is a control circuit according to exemplary embodiment 13, which further comprises a pre-driver circuit which is configured to switch the plurality of control stages and / or the additional plurality of control stages into a switchable state.Embodiment 15 is a control circuit according to any of embodiments 1 to 14, further comprising a data input / output pad or a contactless data input / output element to which the current is provided.Embodiment 16 is a method for controlling data input / output by means of a plurality of control stages comprising at least a first control stage and a last control stage, each of the control stages comprising at least one control element, wherein a number of control elements of the last control stage is greater than a number of control elements of the first control stage, wherein the method comprises providing a first control signal to the respective control elements in an order starting at the first control stage and ending at the last control stage, for providing a current for the data input / output, and subsequently providing a second control signal to the control elements of at least the last control stage in a reverse order, wherein a current intensity of the current provided for the data input / output is increased by means of providing the additional control signal.Embodiment 17 is a method according to embodiment 16, wherein each of the control elements comprises at least one transistor.Embodiment 18 is a method according to embodiment 16 or 17, wherein the first control signal is provided at a first gate terminal of a respective gate.Embodiment 19 is a method according to embodiment 18, wherein the second control signal is provided at a second gate terminal of the same gate, respectively.Embodiment 20 is a method according to embodiment 19, wherein the first gate terminals are each arranged on a first side of a channel connected by the gate and the second gate terminals are each arranged on a second side of the channel, which is opposite the first side.Embodiment 21 is a method according to any one of Embodiments 16 to 20, wherein each of the control elements is formed as a CMOS element.Exemplary embodiment 22 is a method according to one of exemplary embodiments 16 to 21, further comprising:switching the second control signal by means of the first control signal provided at the control elements of the last control stage.Embodiment 23 is a method according to embodiment 22, wherein the control circuit further comprises at least one additional transistor, the method comprising:switching the second control signal by means of the transistor.Exemplary embodiment 24 is a method according to one of exemplary embodiments 16 to 23, which furthermore has provision of only a part of the maximum current which can be provided by the control element for the data input / output when only the first control signal is provided.Embodiment 25 is a method according to Embodiment 24, wherein the portion is between 30% and 80%.Embodiment 26 is a method according to Embodiment 24 or 25, wherein the part decreases in the order of the control stages.Exemplary embodiment 27 is a method according to one of exemplary embodiments 16 to 26, which furthermore has a provision of the maximum current which can be provided by the control element for the data input / output when both the first control signal and the second control signal are provided at the control element.Embodiment 28 is a method according to any one of Embodiments 16 to 27, wherein the control circuit further comprises an additional plurality of control stages formed like the plurality of control stages, except that the number of control elements in at least one control stage of the plurality of control stages is different from the number of control elements in the corresponding control stage of the additional plurality of control stages, the additional plurality of control stages being connected in parallel to the plurality of control stages.Exemplary embodiment 29 is a method according to exemplary embodiment 28, which further comprises switching the plurality of control stages and / or the additional plurality of control stages into a switchable state.Further advantageous embodiments of the device are evident from the description of the method and vice versa.

Claims

A control circuit (200) for controlling data input / output, comprising: • a plurality of control stages comprising at least a first control stage and a last control stage, each of the control stages comprising at least one control element (224); • wherein a number of control elements (224) of the last control stage is greater than a number of control elements of the first control stage; • wherein each of the control elements (224) is configured to receive a first control signal and a second control signal and to control a current for the data input / output in dependence on the first control signal and the second control signal; • wherein the control circuit (200) is configured to provide the first control signal to the respective control elements (224) in an order starting from the first control stage and ending at the last control stage, and subsequently additionally provide the second control signal to the control stages at least to the last control stage in a reverse order, wherein a current intensity of the current for the data input / output is increased by means of the provision of the second control signal.The control circuit (200) of claim 1, wherein each of the control elements (224) comprises at least one transistor.The control circuit (200) according to claim 1 or 2, wherein the first control signal is provided at a first gate terminal (224A1) of a respective gate.The control circuit (200) according to claim 3, wherein the second control signal is provided at a second gate terminal (224A2) of the same gate, respectively.The control circuit (200) of claim 4, wherein the first gate terminals (224A1) are each disposed on a first side of a channel connected by the gate, and the second gate terminals (224A2) are each disposed on a second side of the channel opposite to the first side.The control circuit (200) according to any one of claims 1 to 5, wherein each of the control elements (224) is formed as a CMOS element.Control circuit (200) according to one of claims 1 to 6, further configured to switch the second control signal by means of the first control signal at the control elements (224) of the last control stage.The control circuit (200) according to claim 7, further comprising: at least one additional transistor configured to switch the second control signal.Control circuit (200) according to one of claims 1 to 8, wherein each of the control elements (224) is configured to provide only a part of the maximum current that can be provided by the control element (224) for the data input / output when only the first control signal is provided.The control circuit (200) of claim 9, wherein the portion is between 30% and 80%.The control circuit (200) according to claim 9 or 10, wherein the part decreases in the order of the control stages.Control circuit (200) according to one of claims 1 to 11, wherein each of the control elements (224) is configured to provide the maximum current which can be provided by the control element (224) for the data input / output when both the first control signal and the second control signal are provided to the control element (224).The control circuit (200) according to any one of claims 1 to 12, further comprising: an additional plurality of control stages formed like the plurality of control stages except that the number of control elements (224) in at least one control stage of the plurality of control stages is different from the number of control elements (224) in the corresponding control stage of the additional plurality of control stages, wherein the additional plurality of control stages is connected in parallel to the plurality of control stages.The control circuit (200) according to claim 13, further comprising: a pre-driver circuit configured to switch the plurality of control stages and / or the additional plurality of control stages into a switchable state.The control circuit (200) according to any one of claims 1 to 14, further comprising: a data input / output pad or a contactless data input / output element to which the power is provided.Control circuit (200) according to one of claims 1 to 15, wherein the provision of the first control signal is effected by means of capacitive coupling.A method for controlling data input / output by means of a plurality of control stages comprising at least a first control stage and a last control stage, each of the control stages comprising at least one control element, wherein a number of control elements of the last control stage is greater than a number of control elements of the first control stage, the method comprising: • providing a first control signal to the respective control elements in an order starting at the first control stage and ending at the last control stage, for providing a current for the data input / output (710); and • subsequently additionally providing a second control signal to the control elements of at least the last control stage in a reverse order, wherein a current intensity of the current provided for the data input / output is increased (720) by means of providing the additional control signal.The method of claim 17, wherein each of the control elements comprises at least one transistor.The method of claim 17 or 18, wherein the first control signal is provided at a first gate terminal of a respective gate.The method of claim 19, wherein the second control signal is provided at a second gate terminal of the same gate, respectively.The method of claim 20, wherein the first gate terminals are each disposed on a first side of a channel connected by the gate and the second gate terminals are each disposed on a second side of the channel opposite the first side.The method according to any one of claims 17 to 21, wherein each of the control elements is formed as a CMOS element.Method according to one of claims 17 to 21, further comprising: switching the second control signal by means of the first control signal provided at the control elements of the last control stage.The method of claim 23, wherein the control circuit further comprises at least one additional transistor, the method comprising: switching the second control signal using the transistor.Method according to one of Claims 17 to 24, further comprising: providing only a part of the maximum current which can be provided by the control element for the data input / output when only the first control signal is provided.The method of claim 25, wherein the portion is between 30% and 80%.A method according to claim 25 or 26, wherein said portion decreases in the order of said control stages.Method according to one of Claims 17 to 27, further comprising: providing the maximum current which can be provided by the control element for the data input / output when both the first control signal and the second control signal are provided at the control element.The method according to any one of claims 17 to 28, wherein the control circuit further comprises an additional plurality of control stages formed like the plurality of control stages, except that the number of control elements in at least one control stage of the plurality of control stages is different from the number of control elements in the corresponding control stage of the additional plurality of control stages, the additional plurality of control stages being connected in parallel to the plurality of control stages.The method of claim 29, further comprising: switching the plurality of control stages and / or the additional plurality of control stages to a switchable state.Method according to one of Claims 17 to 30, wherein the first control signal is provided by means of capacitive coupling.

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