Semiconductor packages

Abstract

Semiconductor packages, comprising: - a plurality of die contact points (3a-3d); - a plurality of semiconductor chips (1a-1f, 2a-2f) each provided on the plurality of die contact points (3a-3d); - a plurality of conductor connections (6a-6f), each connected to a plurality of semiconductor chips (1a-1f, 2a-2f); and - a housing (7) that seals the majority of die contact points (3a-3d), the majority of semiconductor chips (1a-1f, 2a-2f) and the majority of conductor terminals (6a-6f), where: - the majority of die contact points (3a-3d) and the majority of conductor terminals (6a-6f) are exposed from a lower surface of the housing (7), - the majority of Die contact points (3a-3d) have a first Die contact point and a second Die contact point, - has the majority of semiconductor chips (1a-1f, 2a-2f): - a first semiconductor chip which is provided on the first die contact point and which has a lower electrode which is connected to the first die contact point, and - a second semiconductor chip, which is provided on the second die contact point and which has a lower electrode which is connected to the second die contact point, - has the majority of conductor connections (6a-6f): - a first conductor connection, which is formed in one piece with the first die contact point, - a second conductor connection, which is formed integrally with the second die contact point, and - a third conductor connection, which is wired to an upper surface electrode, and - recesses (8) are provided on the lower surface of the housing (7): - between a pair of the first die contact point and the first conductor terminal and a pair of the second die contact point and the second conductor terminal that are adjacent to each other, and - between a pair of the first die contact point and the first conductor terminal and the third conductor terminal that are adjacent to each other.

Description

Background of the invention: Area

[0001] The present invention relates to a semiconductor package. background

[0002] A non-insulating surface mounting module has been used in which a die contact point, on which a semiconductor chip is provided, is exposed on a lower housing surface (see, for example, the published Japanese patent JP H11-103 003 A). Summary

[0003] In the housing of this prior art, an inner end portion of a conductor termination is not exposed from the lower housing surface to ensure an insulation distance between the conductor termination and the die contact point. Therefore, the conductor termination is not in contact with a heat sink. Heat generated in the conductor termination when an electric current is applied is radiated into the air. Consequently, if the electric current is increased, the temperature of the conductor termination exceeds an acceptable value, making it difficult to increase the current density in the module. If multiple adjacent conductor terminations are exposed on the lower housing surface, an insulation distance between the exposed conductor terminations cannot be guaranteed.In a 6-in-1 package with multiple die contact points, an insulation distance between the exposed die contact points cannot be guaranteed. Consequently, the necessary insulation resistance cannot be ensured.

[0004] Publication US 6,818,973 B1 shows a QFP package with exposed pads, which, in addition to the gullwing connectors protruding from the sides of the package, also has exposed connectors on the underside of the package body. These exposed connectors on the underside of the package body are created by using a standard leadframe with additional connection elements, which are electrically insulated after a forming process using a partial sawing process.

[0005] Document US 2010 / 0001382A1 describes an integrated circuit package consisting of a terminal frame, an integrated circuit mounted on it, and a shunt resistor coupled to the terminal frame and the integrated circuit. The shunt resistor has a lower temperature coefficient than the terminal frame, and the terminal frame has a lower resistivity than the shunt resistor. The shunt resistor is coupled with low resistance to external terminals of the terminal frame or has its own integrated external terminals.

[0006] The present invention has been designed to solve the problems described above, and one object of the present invention is to obtain a semiconductor package which can ensure insulation resistance while improving heat dissipation.

[0007] The problem underlying the invention is solved according to the invention in a semiconductor package by the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0008] A semiconductor package according to the present invention comprises: a plurality of die contact points; a plurality of semiconductor chips, each provided on the plurality of die contact points; a plurality of conductor terminals, each connected to the plurality of semiconductor chips; and a package that seals the plurality of die contact points, the plurality of semiconductor chips, and the plurality of conductor terminals, wherein, among other things, the plurality of die contact points and the plurality of conductor terminals are exposed from a lower surface of the package, and recesses are provided on the lower surface of the package between the die contact points that are adjacent to each other and between the conductor terminals that are adjacent to each other.

[0009] In the present invention, not only the majority of the die contact points but also the majority of the conductor connections are exposed from the lower surface of the housing. This improves heat dissipation. Recesses are provided on the lower surface of the housing between adjacent die contact points and between adjacent conductor connections. This ensures a sufficient tracking distance between the exposed die contact points and between the exposed conductor connections. Consequently, the necessary insulation resistance can be guaranteed.

[0010] Other and further tasks, features and advantages of the invention will become more apparent from the following description. Brief description of the drawings Fig. Figure 1 is a top view showing the inside of a semiconductor package according to a first embodiment. Fig. Figure 2 is a sectional view showing the semiconductor package according to the first embodiment. Fig. Figure 3 is a sectional view showing the semiconductor package according to the first embodiment. Fig. Figure 4 is a bottom view showing the semiconductor package according to the first embodiment. Fig. Figure 5 is a sectional view showing a semiconductor package according to a second embodiment. Fig. Figure 6 is a sectional view showing a semiconductor package according to a second embodiment. Fig. Figure 7 is a top view showing the inside of a semiconductor package according to a third embodiment. Fig. Figure 8 is a sectional view showing the semiconductor package according to the third embodiment. Fig. Figure 9 is a sectional view showing a semiconductor package according to a fourth embodiment. Fig. Figure 10 is a sectional view showing a semiconductor package according to a fourth embodiment. Fig. Figure 11 is a sectional view showing a semiconductor package according to a fifth embodiment. Fig. Figure 12 is a sectional view showing a semiconductor package according to a fifth embodiment. Fig. Figure 13 is a bottom view showing the semiconductor package according to the fifth embodiment. Fig. Figure 14 is a sectional view showing a semiconductor package according to a sixth embodiment. Fig. Figure 15 is a bottom view showing the semiconductor package according to the sixth embodiment. Description of embodiments

[0011] A semiconductor package according to the embodiments of the present invention is described with reference to the drawings. The same components are identified by the same reference numerals, and the repeated description thereof may be omitted. First embodiment

[0012] Fig. Figure 1 is a top view showing the inside of a semiconductor package according to a first embodiment. Fig. 2 and Fig. Figure 3 shows sectional views of the semiconductor package according to the first embodiment. Fig. Figure 4 is a bottom view showing the semiconductor package according to the first embodiment. Fig. 2 is a sectional view, taken along I-II in Fig. 1. Fig. 3 is a sectional view, taken along III-IV in Fig. 1. The semiconductor package is a 6-in-1 Intelligent Power Module (IPM).

[0013] Semiconductor chips 1a to 1f are insulated-gate bipolar transistors (IGBTs) that perform ON / OFF switching of a main current. Semiconductor chips 2a to 2f are freewheeling diodes (FWDs) that supply a reverse current for a switching interruption time.

[0014] Semiconductor chips 1a and 2a are located at die contact point 3a. Semiconductor chips 1b and 2b are located at die contact point 3b. Semiconductor chips 1c and 2c are located at die contact point 3c. Semiconductor chips 1d to 1f and 2d to 2f are located at die contact point 3d.

[0015] The upper surface electrodes of semiconductor chips 1a to 1f are wired to the respective upper surface electrodes of semiconductor chips 2a to 2f. The lower surface electrodes of semiconductor chips 1a and 2a are connected to the die contact point 3a. The lower surface electrodes of semiconductor chips 1b and 2b are connected to the die contact point 3b. The lower surface electrodes of semiconductor chips 1c and 2c are connected to the die contact point 3c. The lower surface electrodes of semiconductor chips 1d to 1f and 2d to 2f are connected to the die contact point 3d. A bonding material, such as a solder, is used to connect the lower surface electrodes of semiconductor chips 1a to 1f and 2a to 2f to the die contact points 3a to 3d.

[0016] Control chips 4a and 4b are mounted on a circuit board 5. Control electrodes of semiconductor chips 1a to 1c are wired to control chip 4a. Control electrodes of semiconductor chips 1d to 1f are wired to control chip 4b. Control chip 4a controls semiconductor chips 1a to 1c. Control chip 4b controls semiconductor chips 1d to 1f.

[0017] A plurality of conductor terminals 6a to 6f are wired to the respective upper surface electrodes of the plurality of semiconductor chips 2a to 2f. The conductor terminals 6d to 6f are each connected to the die contact points 3a to 3c. The die contact points 3a to 3d, the conductor frame 5, and the conductor terminals 6a to 6f are obtained by machining a thin metal plate into a wire form.

[0018] A housing 7 made of epoxy resin or the like seals the semiconductor chips 1a to 1f and 2a to 2f, the die contacts 3a to 3d, the conductor frame 5, the conductor terminals 6a to 6f, wires, and the like. The lower surfaces of the die contacts 3a to 3d, the conductor frame 5, and the conductor terminals 6a to 6f are exposed from the lower surface of the housing 7 and act as heat-dissipating surfaces, radiating heat away. Recesses 8 are provided on the lower surface of the housing 7 between adjacent die contacts 3a to 3d and between adjacent conductor terminals 6a to 6f.

[0019] The semiconductor package, which has the configuration described above, is mounted on a substrate 9. When the semiconductor package is mounted on the substrate 9, the conductor frame 5 and the conductor terminals 6a to 6f, which project from one side of the package 7, are each bent downwards and connected to the electrodes of the substrate 9.

[0020] In this embodiment, not only the die contact points 3a to 3d but also the conductor connections 6a to 6f are exposed from the lower surface of the housing 7. This improves heat dissipation. Recesses 8 are provided on the lower surface of the housing 7 between the adjacent die contact points 3a to 3d and between the adjacent conductor connections 6a to 6f.

[0021] Accordingly, a creepage current distance between the exposed die contact points 3a to 3d and a creepage current distance between the exposed conductor terminals 6a to 6f can be ensured. Consequently, the necessary insulation resistance can be guaranteed. Second embodiment

[0022] Fig. 5 and Fig. Figure 6 shows sectional views of a semiconductor package according to a second embodiment. Cross-sections of Fig. 5 and Fig. 6 each correspond to cross-sections of Fig. 2 and Fig. 3 in the first embodiment. In this embodiment, an insulating material 10 adheres to the lower surface of the housing 7 and penetrates the recesses 8. The insulating material 10 has a higher thermal conductivity than the material of the housing 7 and is, for example, urethane, which has a Young's modulus of 500 MPa or less.

[0023] Spatial distances can be ensured because the insulating material 10 penetrates the recesses 8 between the die contact points 3a to 3d and between the conductor connections 6a to 6f. Therefore, the insulation resistance can be further improved. Heat from the die contact points 3a to 3d and the conductor connections 6a to 6f is not only radiated into the air but also transferred to the substrate 9 via the insulating material 10. Therefore, heat dissipation is improved. The other components and effects are the same as in the first embodiment. Third embodiment

[0024] Fig. Figure 7 is a top view showing the inside of a semiconductor package according to a third embodiment. Fig. Figure 8 is a sectional view showing the semiconductor package according to the third embodiment. Fig. 8 is a sectional view, taken along I-II in Fig. 7. In this embodiment, a shunt resistor 11 is provided on the conductor terminals 6a to 6c. One terminal of the shunt resistor 11 is connected to the conductor terminals 6a to 6c. The other terminal is connected to ground via an emitter terminal (not shown). The shunt resistor 11 is used to detect an electric current for short-circuit protection.

[0025] By integrating the shunt resistor 11 into the housing 7, the substrate mounting process and costs for attaching the shunt resistor 11 can be reduced. Since the conductor terminals 6a to 6c, on which the shunt resistor 11 is located, are exposed from the lower surface of the housing 7 and adhere to the insulating material 10, the heat dissipation of the shunt resistor 11 is improved. Fourth embodiment

[0026] Fig. 9 and Fig. Figure 10 shows sectional views of a semiconductor package according to a fourth embodiment. Cross-sections of Fig. 9 and Fig. 10 each correspond to the cross-sections of Fig. 2 and Fig. 3 in the first embodiment. In this embodiment, a metal structure 12, made of copper or the like, is provided on the lower surface of the insulating material 10. Since heat radiation from the externally mounted metal structure 12 is enabled, the heat radiation from the die contact points 3a to 3d and the conductor terminals 6a to 6f is further improved. The other components and effects are the same as those in the third embodiment. Fifth embodiment

[0027] Fig. 11 and Fig. Figure 12 shows sectional views of a semiconductor package according to a fifth embodiment. Fig. Figure 13 is a bottom view showing the semiconductor package according to the fifth embodiment. Cross-sections of Fig. 11 and Fig. 12 each correspond to the cross-sections of Fig. 2 and Fig. 3 in the first embodiment. In this embodiment, the insulating material 10 is sealed by a resin 13, such as an epoxy resin. The lower surface of the metal structure 12 is exposed by the resin 13. The other components are the same as those in the fourth embodiment.

[0028] The housing 7 and the resin 13 form a housing. By inserting the insulating material 10 into the housing in this way, the substrate assembly process and substrate assembly costs for attaching the semiconductor housing to the substrate 9 can be reduced. The other effects are the same as those in the fourth embodiment. It should be noted that even if the insulating material 10 is sealed by the resin 13, it is necessary to provide the recesses 8 and ensure that the insulating material 10 penetrates the recesses 8 in order to maintain spatial distances between the die contact points 3a to 3d and between the conductor terminals 6a to 6f. Sixth embodiment

[0029] Fig. Figure 14 is a sectional view showing a semiconductor package according to a sixth embodiment. Fig.Figure 15 is a bottom view showing the semiconductor package according to the sixth embodiment. In this embodiment, the conductor frame 5, on which the control chips 4a and 4b, which have a low thermal input, are provided, is not exposed from the lower surface of the package 7. That is, only the die contact points 3a to 3d, on which the semiconductor chips 1a to 1f and 2a to 2f, which are the main heat-generating sources, are provided, and the majority of conductor connections 6a to 6f are exposed from the lower surface of the package 7. The other components are the same as those in the second embodiment. In this case, heat dissipation can be improved, as in the second embodiment.

[0030] Semiconductor chips 1a to 1f and 2a to 2f are not limited to silicon-based semiconductors but can instead be made from a wide-bandgap semiconductor with a bandgap wider than that of silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, and diamond. A semiconductor chip made from such a wide-bandgap semiconductor exhibits high voltage withstand capability and high permissible current density, allowing for miniaturization. The use of such a miniaturized semiconductor chip enables the miniaturization and high integration of the semiconductor package in which the chip is housed.Furthermore, because the semiconductor chip has high heat resistance, the heat sink's heat sink fins can be reduced in size, and a water-cooled component can be air-cooled, leading to a further reduction in the size of the semiconductor package. Additionally, because the semiconductor chip has low energy loss and high efficiency, a highly efficient semiconductor package can be achieved.

[0031] In light of the foregoing teachings, it is evident that many modifications and variations of the present invention are possible. It is therefore understood that, within the scope of protection of the appended claims, the invention may be implemented differently than expressly described.

Claims

[1] Semiconductor packages comprising: - a plurality of die contact points (3a-3d); - a plurality of semiconductor chips (1a-1f, 2a-2f) each provided on the plurality of die contact points (3a-3d); - a plurality of conductor connections (6a-6f), each connected to a plurality of semiconductor chips (1a-1f, 2a-2f); and - a housing (7) that seals the majority of die contact points (3a-3d), the majority of semiconductor chips (1a-1f, 2a-2f) and the majority of conductor terminals (6a-6f), where: - the majority of die contact points (3a-3d) and the majority of conductor terminals (6a-6f) are exposed from a lower surface of the housing (7), - the majority of Die contact points (3a-3d) have a first Die contact point and a second Die contact point, - has the majority of semiconductor chips (1a-1f, 2a-2f): - a first semiconductor chip which is provided on the first die contact point and which has a lower electrode which is connected to the first die contact point, and - a second semiconductor chip, which is provided on the second die contact point and which has a lower electrode which is connected to the second die contact point, - has the majority of conductor connections (6a-6f): - a first conductor connection, which is formed in one piece with the first die contact point, - a second conductor connection, which is formed integrally with the second die contact point, and - a third conductor connection, which is wired to an upper surface electrode, and - recesses (8) are provided on the lower surface of the housing (7): - between a pair of the first die contact point and the first conductor terminal and a pair of the second die contact point and the second conductor terminal that are adjacent to each other, and - between a pair of the first die contact point and the first conductor terminal and the third conductor terminal that are adjacent to each other. [2] Semiconductor package according to claim 1, wherein the plurality of die contact points (3a-3d) and the plurality of conductor terminals (6a-6f) are aligned with each other on the lower surface of the package (7). [3] Semiconductor housing according to claim 1 or 2, further comprising an insulating material (10) which adheres to the lower surface of the housing (7), penetrates into the recesses (8) and has a higher thermal conductivity than the housing (7). [4] Semiconductor package according to any one of the preceding claims 1 to 3, further comprising a shunt resistor (11), wherein: - the majority of conductor connections (6a-6f) have a fourth conductor connection which is wired to an upper surface electrode of the second semiconductor chip, - one end of the shunt resistor (11) is connected to the adjacent third conductor terminal and fourth conductor terminal and - the other end of the shunt resistor (11) is grounded. [5] Semiconductor housing according to claim 3, further comprising a metal structure (12) provided on a lower surface of the insulating material (10). [6] Semiconductor housing according to claim 3 or 5, further comprising a resin (13) that seals the insulating material (10). [7] Semiconductor package according to any one of claims 1 to 6, further showing: - a ladder frame (5); and - a control chip (4a, 4b) provided on the conductor frame (5) which controls the majority of semiconductor chips (1a-1f, 2a-2f), wherein the conductor frame (5) is not exposed from the lower surface of the housing (7). [8] Semiconductor package according to any of the preceding claims, wherein the plurality of semiconductor chips (1a-1f, 2a-2f) consists of a wide bandgap semiconductor.

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