semiconductor device

Abstract

Semiconductor device (100, 200, 300, 400), comprising: - a semiconductor substrate having a drift layer (12) of a first conductivity type between a first main surface (S1) and a second main surface (S2) opposite the first main surface (S1); - a diode region (2) comprising: - an anode layer (11) of a second conductivity type arranged in a surface layer of the semiconductor substrate on the side of the first main surface (S1), and - a cathode layer (15) of the first conductivity type arranged in a surface layer of the semiconductor substrate on the side of the second main surface (S2); - an insulated gate bipolar transistor region (1, 20, 30, 40) arranged in a line with the diode region (2) along the first main surface (S1) of the semiconductor substrate in a first direction, comprising: - a base layer (9) of the second conductivity type arranged in the surface layer of the semiconductor substrate on the side of the first main surface (S1), - an emitter layer (8) of the first conductivity type, which has a higher impurity concentration than that of the drift layer (12) and which is selectively arranged in a surface layer of the base layer (9) on the side of the first main surface (S1), - a plurality of gate electrodes (7a) arranged side by side in the first direction and facing the emitter layer (8), the base layer (9) and the drift layer (12) via gate insulating films (6a), - a counter-doped layer (10, 21, 31, 41) arranged in a surface layer of the base layer (9), having a higher concentration of impurities of the second conductivity type than that of the base layer (9) and a higher concentration of impurities of the first conductivity type than that of the drift layer (12), and - a collector layer (13) of the second conductivity type arranged in the surface layer of the semiconductor substrate on the side of the second main surface (S2), wherein: - the insulated gate bipolar transistor region (40) has a third region (40a) in which the counterdoped layer (41) is arranged between the adjacent gate electrodes (7a) of the third region (40a), and a fourth region (40b) in which the counterdoped layer (41) is not arranged between the adjacent gate electrodes (7a) of the fourth region (40b), and - the third region (40a) is closer to the diode region (2) than the fourth region (40b).

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present invention relates to a semiconductor device. Description of the background technology

[0002] From the perspective of energy conservation, inverter devices are used in a variety of fields, such as household appliances, electric vehicles, and railways. Most inverter devices are configured using an insulated-gate bipolar transistor (IGBT) and a reverse flow diode. The insulated-gate bipolar transistor and the diode are connected by wiring such as a wire inside the inverter device.

[0003] In order to reduce the size of the inverter device, a semiconductor device in which an insulated gate bipolar transistor and a diode are formed on a semiconductor substrate has been proposed (for example, Japanese Patent Application Laid-Open No. 2008-103590 A).

[0004] DE 11 2017 000 727 T5 relates to an RC-IGBT with a transistor section and a diode section. The RC-IGBT is formed with a transistor section and a diode section and includes a semiconductor substrate, a drift region of the first conductivity type on the upper surface side of the semiconductor substrate, a base region of the second conductivity type above the drift region, a source region of the first conductivity type above the base region, and two or more trench sections penetrating the source region and the base region from the upper end side of the source region. The diode section includes a source region, a contact trench between two adjacent trench sections of the two or more trench sections on the upper surface side of the semiconductor substrate, and a contact layer of the second conductivity type below the contact trench, the concentration of which is higher than a concentration of the base region.

[0005] DE 11 2012 003 111 T5 discloses a semiconductor device in which loss in a diode is reduced at the time of switching. The diode includes a cathode electrode, a cathode region composed of a semiconductor of a first conductivity type, a drift region composed of a semiconductor of the first conductivity type with a low concentration, an anode region composed of a semiconductor of a second conductivity type, an anode electrode composed of metal, a barrier region formed between the drift region and the anode region and composed of a semiconductor of the first conductivity type with a higher concentration than that of the drift region, and a pillar region formed to connect the barrier region to the anode electrode and composed of a semiconductor of the first conductivity type with a higher concentration than that of the barrier region.The column region and the anode are connected via a Schottky junction. SUMMARY

[0006] However, in a semiconductor device in which an insulated-gate bipolar transistor and a diode are formed on a semiconductor substrate as described above, there has been a problem in that the recovery current during a recovery operation becomes larger than when the insulated-gate bipolar transistor and the diode, which are separate components, are connected in parallel. This is because holes constituting a small number of carriers flow from the insulated-gate bipolar transistor region to the diode region, resulting in a reduction in the fracture resistance of the diode. A semiconductor device having a diode region with a high breakdown resistance during a recovery operation is needed.

[0007] An object of the present invention is to provide a semiconductor device having improved breakdown resistance during recovery operation.

[0008] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0009] The semiconductor device according to the present invention comprises a semiconductor substrate, a diode region, and an insulated-gate bipolar transistor region. The semiconductor substrate has a drift layer of a first conductivity type between a first main surface and a second main surface opposite the first main surface. The diode region has an anode layer of a second conductivity type and a cathode layer of the first conductivity type. The anode layer of the second conductivity type is disposed in a surface layer of the semiconductor substrate on the first main surface side. The cathode layer of the first conductivity type is disposed in a surface layer of the semiconductor substrate on the second main surface side.The insulated-gate bipolar transistor region is arranged in line with the diode region in a first direction along the first main surface of the semiconductor substrate. The insulated-gate bipolar transistor region includes a second conductivity-type base layer, a first conductivity-type emitter layer, gate electrodes, a counter-doped layer, and a second conductivity-type collector layer. The second conductivity-type base layer is arranged in the surface layer of the semiconductor substrate on the first main surface side. The first conductivity-type emitter layer has a higher impurity concentration than that of the drift layer and is selectively arranged in the surface layer of the first main surface side base layer.A plurality of gate electrodes are arranged adjacent to each other in the first direction and opposite the emitter layer, the base layer, and the drift layer via gate insulating films. The counter-doped layer is arranged in the surface layer of the base layer, has a higher concentration of second conductivity type impurities than that of the base layer and a higher concentration of first conductivity type impurities than that of the drift layer. The second conductivity type collector layer is arranged in the surface layer of the semiconductor substrate on the second main surface side.The insulated gate bipolar transistor region has a third region in which the counterdoped layer is disposed between the adjacent gate electrodes of the third region and a fourth region in which the counterdoped layer is not disposed between the adjacent gate electrodes of the fourth region, the third region being closer to the diode region than the fourth region.

[0010] The provision of the counter-doped layer in the insulated gate bipolar transistor region suppresses holes from flowing into the diode region and ensures improvement of the breakdown resistance during recovery operation.

[0011] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view illustrating a semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 2 is a plan view illustrating the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 3 is a cross-sectional view illustrating the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 4 is a cross-sectional view illustrating the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 5 is a cross-sectional view illustrating the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 6 is a flowchart for manufacturing the semiconductor device according to Embodiment 1 of the technical background of the present invention; Fig. 7A to 7C are diagrams illustrating manufacturing processes for the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 8A to 8C are diagrams illustrating manufacturing processes for the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 9 is a diagram illustrating a manufacturing process for the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 10A and Fig. 10B are diagrams illustrating manufacturing processes for the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 11 is a schematic diagram illustrating the movement of holes during a diode operation of the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 12 is a schematic diagram illustrating the movement of holes during a recovery operation of the semiconductor device according to Embodiment 1 of the background art of the present invention; Fig. 13 is a plan view illustrating a semiconductor device according to Embodiment 2 of the background art of the present invention; Fig. 14 is a plan view illustrating the semiconductor device according to Embodiment 2 of the background art of the present invention; Fig. 15 is a plan view illustrating a semiconductor device according to Embodiment 3 of the background art of the present invention; Fig. 16 is a plan view illustrating the semiconductor device according to Embodiment 3 of the background art of the present invention; Fig. 17 is a plan view illustrating a semiconductor device according to Embodiment 4 of the present invention; and Fig. 18 is a plan view illustrating the semiconductor device according to Embodiment 4 of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present invention and the technical background of the present invention will be described with reference to the drawings. The drawings are schematically illustrated; therefore, the interrelationships of size and position of components may vary. In the following description, the same or corresponding components may be given the same reference numerals, and repeated descriptions may be omitted.

[0013] Although terms specifying certain positions and directions such as "top", "bottom", "left", "right", "side" and the like are used in the description described below, these terms are used for convenience in order to facilitate understanding of the contents of the embodiment, and the positions and directions in an actual implementation are not limited thereby.

[0014] Regarding the conductivity type of the semiconductor, in the description, an n-type represents the first conductivity type and a p-type represents the second conductivity type. Conversely, however, a p-type may represent the first conductivity type and an n-type may represent the second conductivity type. n + -type means that the donor concentration is higher than that of an n-type, and n - -type means that the donor concentration is lower than that of the n-type. Similarly, p + -type that the acceptor concentration is higher than that of the p-type, and p - -Type means that the acceptor concentration is lower than that of a p-type. <Ausführungsform 1 zum technischen Hintergrund der vorliegenden Erfindung>

[0015] The configuration of the semiconductor device according to Embodiment 1 of the technical background of the present invention will be described with reference to Fig. 1 to 5. Fig. 1 and Fig. 2 are plan views illustrating a semiconductor device according to Embodiment 1 of the background art of the present invention. Fig. 2 is an enlarged plan view of a Fig. 1 and is a plan view illustrating the structure of a semiconductor substrate on one side of the first main surface. In Fig. 2, the illustration of electrodes and the like arranged above the first main surface of the semiconductor substrate is omitted. Fig. 3 to 5 are cross-sectional views of the semiconductor device according to Embodiment 1 of the technical background of the present invention. Fig. 3 is one along the Fig. 2 illustrated line BB taken in cross-sectional view. Fig. 4 is one along the Fig. 2 illustrated line CC taken cross-sectional view. Fig. 5 is one along the Fig. 2 illustrated line DD. For a convenient description, the Fig. 1 to 5 also illustrate the orthogonal XYZ coordinate axes that indicate directions.

[0016] As in Fig. 1, in a semiconductor device 100, insulated-gate bipolar transistor regions 1 in which an insulated-gate bipolar transistor is formed and diode regions 2 in which a diode is formed are arranged adjacent to each other on a semiconductor substrate. The insulated-gate bipolar transistor regions 1 and the diode regions 2 are striped regions having a longitudinal direction in the Y direction of the semiconductor device 100, and the insulated-gate bipolar transistor regions 1 and the diode regions 2 are arranged adjacent to each other in the X direction of the semiconductor device 100. The insulated-gate bipolar transistor regions 1 and the diode regions 2 are active regions of the semiconductor device 100, and the insulated-gate bipolar transistor regions 1 and the diode regions 2 are arranged at the center of the semiconductor device 100 in plan view.

[0017] The semiconductor device 100 is provided with a gate signal receiving region 3. The gate signal receiving region 3 is a region for receiving an external electrical signal. The insulated-gate bipolar transistor region 1 switches between an energized state and a de-energized state in response to the electrical signal received in the gate signal receiving region 3. The gate signal receiving region 3 is arranged near the insulated-gate bipolar transistor regions 1. By disposing the gate signal receiving region 3 near the insulated-gate bipolar transistor regions 1, noise is prevented from being mixed into the electrical signal and malfunction of the insulated-gate bipolar transistor regions 1 is prevented. Wiring for receiving an external electrical signal is connected to the gate signal receiving region 3.For wiring, for example, a wire, a lead wire or the like can be used.

[0018] In Fig. 1, the gate signal receiving region 3 is rectangular, and although three sides thereof are adjacent to the insulated-gate bipolar transistor regions 1 and the diode region 2, the arrangement of the gate signal receiving region 3 is not limited to this. The gate signal receiving region 3 only needs to be arranged near an insulated-gate bipolar transistor region 1 and a diode region 2, which are active regions. The gate signal receiving region 3 may also be arranged in a center of the active region so that all its four sides are adjacent to an insulated-gate bipolar transistor region 1 and a diode region 2, or may also be arranged at a corner of the active region so that two of its four sides are adjacent to an insulated-gate bipolar transistor region 1 and a diode region 2.Furthermore, the arrangement of the gate signal receiving region 3 is not limited thereto, and the gate signal receiving region 3 only needs to be arranged in the region surrounded by a termination region 4 surrounding the active region in plan view, and the shape of the gate signal receiving region 3 is not necessarily rectangular.

[0019] In plan view, the termination region 4 is arranged to surround the insulated gate bipolar transistor regions 1, the diode regions 2, and the gate signal receiving region 3. To maintain the withstand voltage of the semiconductor device 100, the termination region 4 is provided with a withstand voltage holding structure such as a field limiting ring (FLR) or a reduced surface field (REduced SURface Field (RESURF)).

[0020] As in Fig. As illustrated in FIG. 2, a plurality of trenches 5a are arranged on the surface side of the insulated gate bipolar transistor region 1, a trench 5c is arranged at the boundary between the insulated gate bipolar transistor region 1 and the diode region 2, and a plurality of trenches 5b are arranged on the surface side of the diode region 2. The trenches 5a, 5b, and 5c are recesses formed on the first main surface side of the semiconductor substrate by means of etching technology or the like. A plurality of trenches 5a, 5b, and 5c are arranged adjacent to each other in the X direction, which is the first direction, and have a longitudinal direction in the Y direction, which is the second direction orthogonal to the first direction. A gate insulating film 6a is arranged on the sidewall of a trench 5a. A gate insulating film 6b is arranged on the sidewall of a trench 5b and the trench 5c.A conductive gate electrode 7a is disposed within a gate insulating film 6a of a trench 5a, and a conductive gate electrode 7b is disposed within the gate insulating films 6b of a trench 5b and a trench 5c. The gate electrodes 7a and the gate electrodes 7b have a longitudinal direction in the Y direction, and a plurality of the gate electrodes 7a and the gate electrodes 7b are arranged adjacent to each other in the X direction.

[0021] In the surface layer of the semiconductor substrate between the adjacent trenches 5a and in the surface layer of the semiconductor substrate between the adjacent trenches 5a and 5c in the insulated gate bipolar transistor region 1, an n-type emitter layer 8 in which a donor concentration is higher than a donor concentration of the (in Fig. 2) drift layer, a p-type base layer containing acceptor atoms, a p-type base contact layer 16 having a higher acceptor concentration than the acceptor concentration of the base layer 9, and a counterdoped layer 10 having a higher donor concentration than that of the drift layer and a higher acceptor concentration than that of the base layer 9. The counterdoped layer 10 is a semiconductor layer having both a high concentration of donors and a high concentration of acceptor atoms. In the counterdoped layer 10, in the surface layer of the semiconductor substrate, the donor concentration is higher than the acceptor concentration. The net doping concentration is equivalent to an n-type semiconductor layer.The net doping concentration is the concentration obtained by comparing the donor concentration and the acceptor concentration and subtracting the concentration on the low-concentration side from the concentration on the high-concentration side when both donor and acceptor atoms are present. Their conductivity becomes n-type when the concentration of donors is higher, and becomes p-type when the concentration of acceptor atoms is higher.

[0022] The emitter layer 8 is in contact with the gate insulating film 6a in the X direction. Meanwhile, the counter-doped layer 10 is disposed between the base layers 9, between the adjacent gate electrodes 7a, and between the adjacent gate electrodes 7a and 7b in the X direction, and is also disposed between the base contact layers 16; therefore, the counter-doped layer 10 is not in contact with the gate insulating films 6a. The emitter layer 8 has a longitudinal direction in the X direction and a lateral direction in the Y direction. The counter-doped layer 10 has a longitudinal direction in the Y direction and a lateral direction in the X direction. Furthermore, the counter-doped layer 10 is arranged to be located between the emitter layers 8 in the Y direction.

[0023] In plan view, the width of the counter-doped layer 10 in the lateral direction, that is, the width W2 of the counter-doped layer 10 in the X direction, is desirably equal to or less than the width of the emitter layer 8 in the lateral direction, that is, the width W1 of the emitter layer 8 in the Y direction.The provision of the counter-doped layer 10 raises concerns that a latch-up effect may occur directly under the counter-doped layer 10, reducing the current cutoff capability when the insulated gate bipolar transistor region 1 switches from the excited state to the de-excited state; however, if the width of both the counter-doped layer 10 and the emitter layer 8 in the lateral direction is set to the width satisfying the above relationship, the risk of a latch-up effect occurring directly under the counter-doped layer 10 can be suppressed to be equal to or lower than the level of the risk of a latch-up effect occurring directly under the emitter layer 8.

[0024] A p-type anode layer 11 is arranged in the diode region 2 in the surface layer of the semiconductor substrate between the adjacent trenches 5c and 5b and the surface layer of the semiconductor substrate between the adjacent trenches 5b.

[0025] As in Fig. 3, the insulated-gate bipolar transistor region 1 and the diode region 2 are arranged on a common semiconductor substrate. The semiconductor substrate is, for example, a substrate made of silicon. The semiconductor substrate has a first main surface S1 on the positive side in the Z direction and has a second main surface S2 opposite to the first main surface S1 on the negative side in the Z direction. The X and Y directions are directions extending along the first main surface, and the Z direction is a direction orthogonal to the first main surface S1. The semiconductor substrate has a drift layer 12 between the first main surface S1 and the second main surface S2. The drift layer 12 is arranged over both the insulated-gate bipolar transistor region 1 and the diode region 2.The drift layer 12 is a semiconductor layer having as its donors, for example, arsenic or phosphorus, and its donor concentration is 1.0E+12 / cm. 3 up to 1.0E+16 / cm 3 .

[0026] In the insulated-gate bipolar transistor region 1, the base layer 9 is disposed on the side of the first main surface S1 of the semiconductor substrate. The emitter layer 8 is disposed in the surface layer of the base layer 9. The emitter layer 8 is a semiconductor layer containing, for example, arsenic or phosphorus as its donors, and its donor concentration is 1.0E+17 / cm 3 up to 1.0E+20 / cm 3 . The base layer 9 is a semiconductor layer having as its acceptor atoms, for example, boron, aluminum or the like, and whose acceptor concentration is 1.0E+15 / cm 3 up to 1.0E+18 / cm 3 .

[0027] The trenches 5a are arranged on the first main surface S1 side of the insulated-gate bipolar transistor region 1 so as to extend through the emitter layer 8 and the base layer 9 and reach the drift layer 12. The gate electrode 7a faces the emitter layer 8, the base layer 9, and the drift layer 12 via the gate insulating film 6a. A first electrode 18 is arranged on the positive side of the gate electrode 7a in the Z direction via an interlayer insulating film 17. The gate electrode 7a is electrically insulated from the first electrode 18 by the interlayer insulating film 17. The gate electrode 7a is connected to the Fig. 1, receives an electrical signal via the gate signal receiving portion 3, and is controlled to increase and decrease its voltage in response to the electrical signal. The gate electrode 7a is an electrode also referred to as a so-called active gate electrode or the like.

[0028] When a positive voltage is applied to the gate electrode 7a, an n-type channel (not shown) is formed at a position in contact with the gate insulating film 6a of the base layer 9. The emitter layer 8 is in contact with the gate insulating film 6a; therefore, the emitter layer 8 and the drift layer 12 are connected through the n-type channel, and the insulated gate bipolar transistor region 1 is switched to the excited state. When no positive voltage is applied to the gate electrode 7a, no n-type channel is formed in the base layer 9, so the insulated gate bipolar transistor region 1 is switched to the de-excited state. The gate electrode 7a and the gate signal receiving region 3 are electrically connected by wiring (not shown) made of aluminum or the like on the first main surface S1 side in a different cross section.

[0029] The first electrode 18 is made of, for example, aluminum or an aluminum alloy. The first electrode 18 is arranged on the positive side in the Z direction of the emitter layer 8 and is electrically connected to the emitter layer 8. Aluminum and an aluminum alloy are metals that have low contact resistance with the p-type semiconductor layer and high contact resistance with the n-type semiconductor layer. Therefore, when the first electrode 18 is made of aluminum or an aluminum alloy, titanium, which has low contact resistance with the n-type semiconductor layer, can be in contact with the emitter layer 8 without directly connecting the first electrode 18 to the n-type emitter layer 8, to electrically connect the emitter layer 8 and the first electrode 18 via titanium.

[0030] In the insulated-gate bipolar transistor region 1, a p-type collector layer 13 with a higher acceptor concentration than that of the base layer 9 is disposed on the side of the second main surface S2 of the semiconductor substrate. The collector layer 13 is a semiconductor layer having, for example, boron, aluminum, or the like as its acceptor atoms, and its acceptor concentration is 1.0E+16 / cm 3 up to 1.0E+20 / cm 3 . A second electrode 19 is arranged on the negative side of the collector layer 13 in the Z direction, and the collector layer 13 and the second electrode 19 are electrically connected.

[0031] In the diode region 2, an anode layer 11 is arranged on the side of the first main surface S1 of the semiconductor substrate. The anode layer 11 is a semiconductor layer having, for example, boron, aluminum, or the like as its acceptor atoms, and its acceptor concentration is 1.0E+15 / cm3 up to 1.0E+18 / cm 3 .

[0032] The trenches 5b are arranged on the first main surface S1 side of the diode region 2. The trenches 5b are arranged to extend through the anode layer 11 and reach the drift layer 12. The gate electrode 7b faces the anode layer 11 and the drift layer 12 via the gate insulating film 6b. The first electrode 18 is arranged on the positive side of the gate electrode 7b in the Z direction. The gate electrode 7b and the first electrode 18 are electrically connected. Unlike the gate electrode 7a, the voltage of the gate electrode 7b does not rise and fall by a signal from the gate signal receiving region 3. The first electrode 18 is arranged on the positive side in the Z direction of the anode layer 11 and is electrically connected to the anode layer 11. The gate electrode 7b is an electrode which is also referred to as a so-called dummy gate electrode or the like.

[0033] In the diode region 2, an n-type cathode layer 15 with a higher donor concentration than that of the drift layer 12 is arranged on the side of the second main surface S2 of the semiconductor substrate. The cathode layer 15 is a semiconductor layer containing, for example, arsenic or phosphorus as its donors, and its donor concentration is 1.0E+16 / cm 3 up to 1.0E+20 / cm 3 The second electrode 19 is arranged on the negative side of the cathode layer 15 in the Z direction. The second electrode 19 is electrically connected to the cathode layer 15.

[0034] The trench 5c is arranged on the first main surface S1 side of the boundary between the insulated gate bipolar transistor region 1 and the diode region 2. The trench 5c is arranged to extend through the anode layer 11 and the base layer 9 and reach the drift layer 12. The gate electrode 7b faces the emitter layer 8, the base layer 9, and the drift layer 12 via the gate insulating film 6b. The first electrode 18 is arranged on the positive side of the gate electrode 7b in the Z direction, and the gate electrode 7b and the first electrode 18 are electrically connected.

[0035] As in Fig. As illustrated in Figure 4, in the insulated gate bipolar transistor region 1, the counterdoped layer 10 and the base contact layer 16 are arranged in the surface layer of the base layer 9. The counterdoped layer 10 is a semiconductor layer having, for example, arsenic or phosphorus as its donors, and its donor concentration is 1.0E+17 / cm 3 up to 1.0E+20 / cm 3 . The counter-doped layer 10 is a semiconductor layer having as its acceptor atoms, for example, boron, aluminum or the like, and its acceptor concentration is 1.0E+15 / cm 3 up to 1.0E+20 / cm 3 . The base contact layer 16 is a semiconductor layer having as its acceptor atoms, for example, boron, aluminum or the like, and its acceptor concentration is 1.0E+15 / cm 3 up to 1.0E+20 / cm 3 .

[0036] The counter-doped layer 10 is disposed between the base layers 9, between the adjacent gate electrodes 7a, and between the adjacent gate electrodes 7a and 7b in the X direction, and is not in contact with the gate insulating films 6a. Therefore, even when a positive voltage is applied to the gate electrode 7a, the counter-doped layer 10 and the drift layer 12 are not connected through the n-type channel. That is, the counter-doped layer 10 is a semiconductor layer that does not participate in switching between the excited state and the de-excited state of the insulated-gate bipolar transistor region 1.

[0037] As in Fig. 5, in the insulated gate bipolar transistor region 1, the emitter layer 8, the counter-doped layer 10 and the base contact layer 16 are each selectively arranged in the surface layer of the base layer 9.

[0038] Next, a manufacturing method of the semiconductor device according to Embodiment 1 will be described. Fig. 6 is a flowchart for manufacturing the semiconductor device according to Embodiment 1. The manufacturing method will be described following the order of the manufacturing flowchart. The manufacturing method of the active region will be described in the following description of the manufacturing method, and the manufacturing method of the termination region 4 and the gate signal receiving region 3 formed in an arbitrary structure will be omitted.

[0039] As in Fig. As illustrated in Figure 6, the semiconductor device according to Embodiment 1 is manufactured through a step (S100) of forming a semiconductor layer on the first main surface side, a step (S200) of forming a gate electrode, a step (S300) of forming a first electrode, a step (S400) of forming a semiconductor layer on the second main surface side, and a step (S500) of forming a second electrode. The step (S100) of forming a semiconductor layer on the first main surface side is divided into a step of preparing a semiconductor substrate, a step of forming a p-type semiconductor layer on the first main surface side, and a step of forming an n-type semiconductor layer on the first main surface side.The gate electrode forming step (S200) is divided into a trench forming step, a gate electrode depositing step, and an interlayer insulating film depositing step. The second main surface forming step (S400) is divided into a p-type semiconductor layer forming step on the second main surface side and an n-type semiconductor layer forming step on the second main surface side.

[0040] Fig. 7A to 10B are diagrams illustrating the manufacturing processes of the semiconductor device according to Embodiment 1. Fig. 7A to 10B are along the Fig. 2 illustrates cross-sectional views taken along line CC.

[0041] Fig. 7A to 7C are diagrams illustrating the manufacturing processes of the step of forming a semiconductor layer on the first main surface side. Fig. 7A is a diagram illustrating a state where the semiconductor substrate preparation step is completed. The semiconductor substrate preparation step is a step in which an n-type semiconductor substrate with a low donor concentration is prepared. The donor concentration of the drift layer 12 represents the donor concentration of the semiconductor substrate per se; the semiconductor substrate is prepared according to the donor concentration of the drift layer 12. When the semiconductor substrate preparation step is completed, the insulated-gate bipolar transistor region 1 and the diode region 2 have only the drift layer 12.

[0042] Fig. 7B is a diagram illustrating a manufacturing process of the step of forming a p-type semiconductor layer on the first main surface side. The step of forming a p-type semiconductor layer on the first main surface side is a step in which the base layer 9, the base contact layer 16, and the anode layer 11 are formed. The base layer 9 is formed by implanting acceptor atoms A1 into the insulated gate bipolar transistor region 1 from the first main surface S1 side. The base contact layer 16 is formed by implanting acceptor atoms A3 into the insulated gate bipolar transistor region 1 from the first main surface S1 side. The anode layer 11 is formed by implanting acceptor atoms A2 into the diode region 2 from the first main surface S1 side.For example, boron, aluminum, or the like are used as the acceptor atoms A1, A2, and A3. The acceptor atoms A1, A2, and A3 can be the same, and if the acceptor atoms A1, A2, and A3 are the same, the exchange of acceptor atoms is eliminated.

[0043] If a single ingredient is used for acceptor atoms A1 and A2, and the same implantation amount is set for acceptor atoms A1 and A2, simultaneous implantation of acceptor atoms A1 and A2 is feasible. Acceptor atoms A3 are selectively implanted. For selective implantation, acceptor atoms A3 only need to be implanted in a state where a mask is provided to prevent implantation in locations where implantation is not required. For example, a resist mask can be used as the mask. Even if acceptor atoms A1 and A2 are implanted separately, they can be selectively implanted using the mask. The implanted acceptor atoms A1, acceptor atoms A2 and acceptor atoms A3 are diffused by heating to form the base layer 9, the anode layer 11 and the base contact layer 16.

[0044] Fig. 7C is a diagram illustrating a manufacturing process of the step of forming an n-type semiconductor layer on the first main surface side. The step of forming an n-type semiconductor layer on the first main surface side is a step of forming the counter-doped layer 10. The counter-doped layer 10 is formed by implanting donors A1 into the base contact layer 16 in the insulated gate bipolar transistor region 1 from the first main surface S1 side. Arsenic, phosphorus, or the like is used as the donors D1.

[0045] The counterdoped layer 10 is formed by selectively implanting the donors D1 into the base contact layer 16. That is, the base contact layer 16 and the counterdoped layer 10 have the same acceptor atoms, and the region into which the donors D1 are implanted in the base contact layer 16 ultimately becomes the counterdoped layer 10, and the region into which the donors D1 are not implanted ultimately becomes the base contact layer 16.

[0046] To selectively form the counterdoped layer 10, the donors D1 can be selectively implanted using a donor implantation mask M1 on the first main surface side. The donor implantation mask M1 on the first main surface side is, for example, a resist mask formed by applying a resist to the first main surface S1 to prevent the penetration of donors. The donor implantation mask M1 on the first main surface side is arranged at locations where the donors D1 are not implanted and is removed after the donors D1 are implanted.

[0047] The implanted donors D1 are diffused by heating to form the counterdoped layer 10. Although the base layer 9, the anode layer 11, the base contact layer 16, and the counterdoped layer 10 are formed by implanting and diffusing the acceptor atoms A1, the acceptor atoms A2, and the acceptor atoms A3, and then implanting and diffusing the donors D1, the formation method of each semiconductor layer is not limited thereto. For example, one can implant the donors D1 and then implant the acceptor atoms A1, the acceptor atoms A2 and the acceptor atoms A3 and allow them to diffuse, or the donors D1 can be implanted after the acceptor atoms A1 and the acceptor atoms A2 have been implanted and the acceptor atoms A3 have been implanted, and then simultaneous heating can be carried out to allow them to diffuse.Post-implantation heating can be performed after each implantation individually or can be performed after implanting a plurality of types of acceptor atoms and donors simultaneously.

[0048] In the step of forming a semiconductor layer on the first main surface side, the Fig. 5 illustrated emitter layer 8 in a different from that in Fig. 7A to 7C. The emitter layer 8 is formed by selectively implanting donors into the surface layer of the base layer 9, similar to the counterdoped layer 10. If the donors used to form the emitter layer 8 and the donors D1 used to form the counterdoped layer 10 are the same, and further, their donor concentrations are the same, simultaneous donor implantation of the emitter layer 8 and the counterdoped layer 10 can be performed, simplifying the manufacturing process.

[0049] If different donors are used for the emitter layer 8 and the counterdoped layer 10, or if different donor concentrations are to be set, the implantation of the donors for the emitter layer 8 and the implantation of the donors D1 of the counterdoped layer 10 can be performed separately. In this case, the donor implantation mask can be formed twice on the first main surface side, and the donors can be selectively implanted into the partial region corresponding to each semiconductor layer.

[0050] Fig. 8A to 8C are diagrams illustrating the manufacturing processes of the gate electrode forming step.

[0051] Fig. 8A is a diagram illustrating a manufacturing process of the trench forming step. The trench forming step is a step of forming trenches 5a, 5b, and 5c on the first main surface S1 side by etching. Before etching, a trench mask M2 is previously formed at locations where the trenches 5a, 5b, and 5c are not formed. The trench mask M2 is, for example, a mask made of an oxide film formed by heating on the first main surface S1 side, and is to be removed after the trench is formed.

[0052] Fig. 8B is a diagram illustrating a manufacturing process of the gate electrode deposition step. The gate electrode deposition step is a step in which the gate electrodes 7a are deposited in the trenches 5a and the gate electrodes 7b are deposited in the trenches 5b and the trench 5c. First, an oxide film is formed on the front surface of the semiconductor substrate including the sidewalls of the trenches 5a, 5b, and 5c by heating. After forming the oxide film, the gate electrodes 7a and the gate electrodes 7b are deposited from the first main surface S1 side. The gate electrodes 7a and the gate electrodes 7b are formed by depositing the same conductive material. The gate electrodes 7a and the gate electrodes 7b are formed by depositing, for example, polysilicon.After the polysilicon is deposited on the entire surface of the first main surface S1, unnecessary polysilicon is removed by etching. The polysilicon remaining inside the trenches 5a becomes the gate electrodes 7a, and the polysilicon remaining inside the trenches 5b and the trench 5c becomes the gate electrodes 7b. Furthermore, the oxide films remaining inside the trenches 5a after the unnecessary oxide film is removed become the gate insulating film 6a, and the oxide films remaining inside the trenches 5b and the trench 5c become the gate insulating films 6b.

[0053] Fig. 8C is a diagram illustrating a state where the interlayer insulating film depositing step is completed. The interlayer insulating film forming step is a step in which the interlayer insulating films 17, which are insulators, are formed on the gate electrodes 7a. The interlayer insulating films 17 are oxide films formed by, for example, a chemical vapor deposition (CVD) method. The oxide film formed adjacent to the gate electrodes 7a on the first main surface S1 is removed by, for example, etching.

[0054] Fig. 9 is a diagram illustrating a state where the first electrode forming step is completed. The first electrode forming step is a step in which the first electrode 18 is formed. The first electrode 18 is formed by sputtering a metal from, for example, the first main surface S1 side. For example, aluminum is used as the metal. By sputtering, the first electrode 18 covering the interlayer insulating film 17 and the first main surface S1 is formed.

[0055] Fig. 10A and Fig. 10B are diagrams illustrating the manufacturing processes of the step of forming a semiconductor layer on the second main surface side.

[0056] Fig. 10A is a diagram illustrating a manufacturing process of the step of forming a p-type semiconductor layer on the second main surface side. The step of forming a p-type semiconductor layer on the second main surface side is a step in which the collector layer 13 is formed. The collector layer 13 is formed by implanting acceptor atoms A4 from the second main surface S2 side. For example, boron, aluminum, or the like is used as the acceptor atoms A4. The acceptor atoms A4 of the collector layer 13 may be the same as one or more of the acceptor atoms A1 of the base layer 9, the acceptor atoms A2 of the anode layer 11, and the acceptor atoms A3 of the base contact layer 16. If the acceptor atoms are the same, the work for changing the acceptor atoms can be reduced.A mask M3 for implanting the acceptor atoms on the second main surface side may be used on the second main surface S2 of the diode region 2 in which the acceptor A4 is not implanted. The mask M3 for implanting the acceptor atoms on the second main surface side is formed, for example, by applying a resist to the second main surface S2 and is removed after implanting the acceptor atoms A4. The implanted acceptor atoms A4 are diffused by heating to form the collector layer 13.

[0057] Fig. 10B is a diagram illustrating a manufacturing process of the step of forming an n-type semiconductor layer on the second main surface side. The step of forming an n-type semiconductor layer on the second main surface side is a step in which the cathode layer 15 is formed. The cathode layer 15 is formed by implanting donors D2 from the second main surface S2 side. Arsenic, phosphorus, or the like is used as the donors D2. The donors D2 of the cathode layer 15 may be the same as one or both of the donors of the emitter layer 8 and the donors of the counter-doped layer 10, and if the donors are the same, the labor for changing the donors can be reduced.

[0058] A mask M4 for implanting donors on the second main surface side may be used on the second main surface S2 side of the insulated gate bipolar transistor region 1 in which donors D2 are not implanted. The mask M4 for implanting donors on the second main surface side is formed, for example, by forming a resist on the second main surface S2 and is removed after implanting donors D2. The implanted donors D2 are diffused by heating to form the cathode layer 15. Although the cathode layer 15 is formed after the collector layer 13 is formed, the formation order is not limited thereto. The collector layer 13 may be formed after the cathode layer 15 is formed. Furthermore, the acceptor atoms A3 and the donors D2 may be heated and diffused simultaneously.

[0059] The second electrode forming step (not illustrated) is a step in which the second electrode 19 is formed. The second electrode 19 is formed by sputtering a metal from, for example, the second main surface S2 side. Aluminum, for example, is used as the metal. By sputtering, the second electrode 19 covering the second main surface S2 is formed. Through the above steps, the second electrode 19 shown in Fig. 1 illustrated semiconductor device 100 is obtained.

[0060] The diode operation of the semiconductor device according to Embodiment 1 of the technical background of the present invention will be described. Fig. 11 is a schematic diagram illustrating the movement of holes during a diode operation of the semiconductor device according to Embodiment 1 of the background art of the present invention. Fig. Figure 11 is a diagram showing the movement of holes during diode operation along the line CC in Fig. 2. During diode operation, a positive voltage is applied to the first electrode 18 compared to that applied to the second electrode 19. When a positive voltage is applied, holes h from the anode layer 11, the base layer 9, and the base contact layer 16, which are p-type semiconductor layers, are implanted into the drift layer 12, and the implanted holes h migrate toward the cathode layer 15. In the diode region 2 near the boundary with the insulated-gate bipolar transistor region 1, the density of holes h is higher than that of the diode region 2 remote from the insulated-gate bipolar transistor region 1 because, in addition to the holes h from the anode layer 11, holes h from the insulated-gate bipolar transistor region 1 migrate there.During diode operation, a return current flows in the direction from the first electrode 18 to the second electrode 19.

[0061] The recovery operation of the semiconductor device according to Embodiment 1 of the technical background of the present invention will be described. Fig. 12 is a schematic diagram illustrating the movement of holes during a recovery operation of the semiconductor device according to Embodiment 1 of the background art of the present invention. Fig. Figure 12 is a diagram showing the movement of holes during a recreation operation along the line CC in Fig. 2. During the recovery operation, a negative voltage is applied to the first electrode 18 compared to that applied to the second electrode 19. The holes h migrating toward the cathode layer 15 during the diode operation change the direction of movement and migrate toward the anode layer 11. During the recovery operation, the holes h flow out of the semiconductor device via the anode layer 11 and the first electrode 18.

[0062] In the anode layer 11 in the diode region 2 near the boundary with the insulated-gate bipolar transistor region 1 having a high density of holes h during diode operation, more holes h pass therethrough than pass through the anode layer 11 in the diode region 2 remote from the insulated-gate bipolar transistor region 1. Furthermore, some of the holes h present in the insulated-gate bipolar transistor region 1 flow out of the semiconductor device via the base layer 9, the base contact layer 16, and the first electrode 18. During recovery operation, a recovery current flows in the direction from the second electrode 19 toward the first electrode 18.

[0063] The effect of suppressing hole implantation in the semiconductor device according to Embodiment 1 will be described with reference to Fig. 11 described.

[0064] The semiconductor device according to Embodiment 1 suppresses the holes h from flowing from the insulated gate bipolar transistor region 1 to the diode region 2. As shown in Fig. 11, the holes h from the p-type base layer 9 and the p-type base layer 16 are implanted into the drift layer 12 in the diode region 2 during diode operation. On the other hand, the holes h from the n-type counterdoped layer 10 are not implanted into the drift layer 12 in the diode region 2. Therefore, when the counterdoped layer 10 is disposed, the implantation of the holes h from the insulated gate bipolar transistor region 1 to the diode region 2 during diode operation is suppressed more than in the case where no counterdoped layer 10 is disposed.

[0065] Therefore, by selectively disposing the counterdoped layer 10 in the surface layer of the base layer 9, an improvement in the breakdown resistance during recovery operation is ensured while suppressing the recovery current. Furthermore, the concentration of acceptor impurities in the surface layer of the counterdoped layer 10 is higher than that of the base layer 9. Accordingly, the electrical contact resistance between the first electrode 18 and the counterdoped layer 10 can be made lower than the electrical contact resistance between the first electrode 18 and the base layer 9.

[0066] Furthermore, in the semiconductor device according to Embodiment 1, as shown in Fig. 2, the width W2 of the counterdoped layer 10 in the X direction is narrower than the width W1 of the emitter layer 8 in the Y direction. By adjusting the width W2 of the counterdoped layer 10 as described, the voltage drop occurring at the interface between the counterdoped layer 10 and the base layer 9 can be made smaller than or equal to the voltage drop occurring at the interface between the emitter layer 8 and the base layer 9, and the latch-up resistance at the junction between the counterdoped layer 10 and the base layer 9 can be made higher than the latch-up resistance at the junction between the emitter layer 8 and the base layer 9.

[0067] Although the structure in which the gate electrodes 7a are arranged in all the trenches 5a is illustrated in Embodiment 1, the gate electrodes 7a are not necessarily arranged in all the trenches 5a of the insulated-gate bipolar transistor region 1 if the amount of heat generated per unit area of ​​the insulated-gate bipolar transistor region 1 when it is energized is large. Also, a structure referred to as a so-called thinning structure or the like may be adopted in which the gate electrodes 7b electrically connected to the first electrode 18 are arranged in some of the trenches of the plurality of trenches arranged in the insulated-gate bipolar transistor region 1.

[0068] Although the structure in which the gate electrode 7b is arranged in the trench 5c located at the boundary between the insulated gate bipolar transistor region 1 and the diode region 2 is illustrated, a structure in which the gate electrode 7a electrically connected to the gate signal receiving region 3 is arranged in the trench 5c may also be adopted. <Ausführungsform 2 zum technischen Hintergrund der vorliegenden Erfindung >

[0069] The configuration of the semiconductor device according to Embodiment 2 of the technical background of the present invention will be described with reference to Fig. 13 and Fig. 14 described. Fig. 13 and Fig. 14 are plan views illustrating the semiconductor device according to Embodiment 2 of the background art of the present invention. Fig. 14 is an enlarged view of the Fig. 13 and is a plan view illustrating the structure of the semiconductor device on the first main surface side. In Fig. 14, the description of electrodes and the like arranged above the first main surface of the semiconductor device is omitted. For the sake of convenience of description, Fig. 13 and Fig. 14 orthogonal XYZ coordinate axes indicating directions are illustrated. In Embodiment 2 of the background art of the present invention, the same components as those described in Embodiment 1 of the background art of the present invention are denoted by the same reference numerals, and their descriptions are omitted.

[0070] As in Fig. 13, in a semiconductor device 200 according to Embodiment 2 of the background art of the present invention, insulated gate bipolar transistor regions 20 and the diode regions 2 are repeatedly arranged in the X direction of the semiconductor device 200.

[0071] As in Fig. As illustrated in Fig. 14, in the semiconductor device according to Embodiment 2 of the background art of the present invention, a structure is adopted in which the ratio of the areas where the counter-doped layers 21 are disposed between the adjacent gate electrodes 7a or the areas where the counter-doped layers 21 are disposed between an adjacent gate electrode 7a and the gate electrode 7b becomes larger in plan view as one gets closer to the diode region 2. Further, the base contact layer 16 is disposed in the surface layer of the semiconductor substrate so that the base layer is not exposed.

[0072] In Fig. 14, each of the entire plurality of counterdoped layers 21 has the same area. In plan view, in the insulated gate bipolar transistor region 20, when comparing the ratio of the areas in which the counterdoped layers 21 are disposed between adjacent gate electrodes 7a or the ratio of the areas in which the counterdoped layers 21 are disposed between the gate electrode 7a and the gate electrode 7b, the ratio of the areas in which the counterdoped layers 21 are disposed between the gate electrode 7a and the gate electrode 7b closest to the diode region 2 is twice the ratio of the areas of the counterdoped layers 21 between the adjacent gate electrodes 7a.

[0073] The closer one gets to the diode region, the more holes typically flow from the insulated gate bipolar transistor region into the diode region during recovery operation.

[0074] In the semiconductor device according to Embodiment 2 of the background art of the present invention, by making the ratio of the areas in which the counter-doped layers 21 are disposed between the adjacent gate electrodes 7a or the ratio of the areas in which the counter-doped layers 21 are disposed between the gate electrode 7a and the gate electrode 7b higher the closer to the diode region 2, more efficient hole suppression from the insulated-gate bipolar transistor region 20 toward the diode region 2 and improvement of the breakdown resistance during recovery operation are ensured. Meanwhile, in the insulated-gate bipolar transistor region 20 remote from the diode region 2, the risk of a latch-up phenomenon occurring directly under the counter-doped layer 21 when it is switched to the de-energized state can be suppressed.

[0075] Furthermore, the counter-doped layer 21 is disposed between the base contact layers 16 and is not in contact with the gate insulating film 6a. The counter-doped layer 21 is a semiconductor layer that does not participate in switching between the excited state and the de-excited state of the insulated-gate bipolar transistor region 20. Therefore, by adopting the structure in which the ratio of the areas where the counter-doped layers 21 are disposed between the adjacent gate electrodes 7a or the areas where the counter-doped layers 21 are disposed between an adjacent gate electrode 7a and the gate electrode 7b becomes larger in plan view as one approaches the diode region 2, a current balance in the insulated-gate bipolar transistor region 20 is prevented from deteriorating.

[0076] In Embodiment 2 of the technical background of the present invention, an example was described in which it is assumed that each of the plurality of counter-doped layers 21 has the same area, the number of counter-doped layers 21 arranged between adjacent gate electrodes 7a or between the gate electrode 7a and the gate electrode 7b is increased as one gets closer to the diode region 2, so as to increase the ratio of the areas in which the counter-doped layers 21 are arranged between adjacent gate electrodes 7a or between the gate electrode 7a and the gate electrode 7b as one gets closer to the diode region 2.However, a structure may also be adopted in which the numbers of the counter-doped layers 21 between the adjacent gate electrodes 7a or between the gate electrode 7a and the gate electrode 7b are set to be the same and the areas of the counter-doped layers 21 are increased as one gets closer to the diode region 2, whereby the ratio of the area where the counter-doped layers 21 are arranged between the adjacent gate electrodes 7a or between the gate electrode 7a and the gate electrode 7b is increased as one gets closer to the diode region 2.

[0077] Furthermore, in Embodiment 2 of the technical background of the present invention, the base contact layer 16 is disposed in the surface layer of the semiconductor substrate, and the base layer is not exposed. To construct such a structure, the base contact layer 16 can be disposed by implanting acceptor atoms into a portion where the base layer is exposed. The base contact layer 16 is a semiconductor layer that has a higher acceptor concentration than that of the base layer, and from which more holes are implanted into the diode region 2, while the electrical contact resistance with the emitter electrode is lower than that of the base layer.Since both the counter-doped layer 21 and the base contact layer 16 are a semiconductor layer having a low electrical contact resistance with the emitter electrode, the semiconductor device of Embodiment 2 of the background art of the present invention is a semiconductor device in which the electrical contact resistance between the emitter electrode and the semiconductor substrate in the insulated gate bipolar transistor region can be further reduced than that in the semiconductor device of Embodiment 1 of the background art of the present invention. <Ausführungsform 3 zum technischen Hintergrund der vorliegenden Erfindung>

[0078] The configuration of the semiconductor device according to Embodiment 3 of the technical background of the present invention will be described with reference to Fig. 15 and Fig. 16 described. Fig. 15 and Fig. 16 are plan views illustrating the semiconductor device according to Embodiment 3 of the background art of the present invention. Fig. 16 is an enlarged view of the Fig. 15 and is a plan view illustrating the structure of the semiconductor device on the first main surface side. In Fig. 16, the illustration of electrodes and the like arranged above the first main surface of the semiconductor substrate is omitted. For the sake of convenience of description, Fig. 15 and Fig. 16 orthogonal XYZ coordinate axes indicating directions are illustrated. In Embodiment 3 of the background art of the present invention, the same components as those described in Embodiments 1 and 2 of the background art of the present invention are denoted by the same reference numerals, and their descriptions are omitted.

[0079] As in Fig. 15, in a semiconductor device 300 according to Embodiment 3 of the background art of the present invention, insulated gate bipolar transistor regions 30 and the diode regions 2 are repeatedly arranged in the X direction of the semiconductor device 300.

[0080] As in Fig. As illustrated in FIG. 16, the semiconductor device according to Embodiment 3 is a semiconductor layer in which a net doping concentration of the surface layer of the counter-doped layer 31 is p-type. To make the net doping concentration of the surface layer of the counter-doped layer 31 p-type, it is only necessary to implant impurities such that the concentration of acceptor impurities of the surface layer of the counter-doped layer 31 is higher than the concentration of donor impurities.

[0081] In the semiconductor device according to Embodiment 3, suppression of the occurrence of the risk of a latch-up phenomenon in the insulated gate bipolar transistor region 30 is ensured.

[0082] Furthermore, the counterdoped layer 31 is a p-type, whose net doping concentration is lower than that of the base layer 16, which is also a p-type. Therefore, fewer holes are implanted into the diode region 2 from the counterdoped layer 31 than from the base contact layer 16.

[0083] In Embodiment 3, by making the ratio of the areas in which the counter-doped layers 31 are arranged between adjacent gate electrodes 7a or the ratio of the areas in which the counter-doped layer 31 is arranged between the gate electrode 7a and the gate electrode 7b higher as one gets closer to the diode region 2, more efficient suppression of the holes from the insulated gate bipolar transistor region 30 toward the diode region 2 and improvement of the latch-up resistance of the insulated gate bipolar transistor region are ensured. <Erfindungsgemäße Ausführungsform 4>

[0084] The configuration of the semiconductor device according to Embodiment 4 of the present invention will be described with reference to Fig. 17 and Fig. 18 described. Fig. 17 and Fig. 18 are plan views illustrating the semiconductor device according to Embodiment 4 of the present invention. Fig. 18 is an enlarged view of the Fig. 17 and is a plan view illustrating the structure of the semiconductor substrate on the first main surface side. In Fig. 18, the illustration of electrodes and the like arranged above the first main surface of the semiconductor substrate is omitted. For the sake of convenience of description, Fig. 17 and Fig. 18 orthogonal XYZ coordinate axes indicating directions are illustrated. In Embodiment 4 of the present invention, the same components as those described in Embodiments 1 to 3 of the background art of the present invention are denoted by the same reference numerals, and their descriptions are omitted.

[0085] As in Fig. 17, in a semiconductor device 400 according to Embodiment 4 of the present invention, insulated gate bipolar transistor regions 40 and the diode regions 2 are repeatedly arranged in the X direction of the semiconductor device 400.

[0086] As in Fig.As illustrated in FIG. 18, the semiconductor device 400 according to Embodiment 4 of the present invention includes an insulated-gate bipolar transistor region 40. The insulated-gate bipolar transistor region 40 includes a first region 40a in which counter-doped layers 41 are disposed between the adjacent gate electrodes 7a or the adjacent gate electrodes 7a and 7b, and a second region 40b in which no counter-doped layer 41 is disposed between the adjacent gate electrodes 7a or the adjacent gate electrodes 7a and 7b. The first region 40a is located closer to the diode region 2 than the second region 40b.

[0087] In the semiconductor device according to Embodiment 4 of the present invention, the first region 40a in which the counter-doped layers 41 are disposed is arranged closer to the diode region 2 than the second region 40b in which no counter-doped layer 41 is arranged, thereby ensuring more efficient suppression of holes from the insulated-gate bipolar transistor region toward the diode region 2 and improving the breakdown resistance during a recovery operation. Meanwhile, in the insulated-gate bipolar transistor region 40, the second region 40b is arranged farther away from the first region 40a, and no counter-doped layer 41 is arranged in the second region 40b, whereby the risk of a latch-up phenomenon occurring when the insulated-gate bipolar transistor region 40 is switched to the de-energized state can be suppressed.

[0088] Furthermore, the counter-doped layer 41 is in contact with the emitter layer 8 in the Y direction. Such a structure makes it possible to increase the areas of the counter-doped layers 41 and suppress holes from flowing into the diode region 2, which improves the breakdown resistance during the recovery operation.

[0089] The semiconductor device according to Embodiment 4 of the present invention has a structure in which, unlike the semiconductor devices of Embodiments 1 to 3 of the background art of the present invention, no base contact layer is disposed in the surface layer on the first main surface side of the semiconductor substrate. To construct such a structure, only the implantation area of ​​the donor layer constituting the counter-doped layer needs to be wider than the implantation area for the acceptor atoms constituting the base contact layer, or respective impurities need only be implanted into the areas of the same size.When the implantation area of ​​the donor layer forming the counterdoped layer is wider than the implantation area of ​​the acceptor atoms forming the base contact layer, a structure to be adopted is one in which the counterdoped layer is covered with the n-type semiconductor layer in plan view. By adopting a structure in which the n-type semiconductor layer does not contact the gate insulating film of the active gate electrode, deterioration of the current balance in the insulated-gate bipolar transistor region is suppressed. Adopting the structure in which no base contact layer is disposed in the surface layer on the first main surface side of the semiconductor substrate ensures further suppression of the inflow of holes into the diode region.

[0090] Although the structure in which the anode layer is a single layer is illustrated in Embodiments 1 to 4, the structure is not limited thereto, and a structure in which the anode layer may comprise two layers made of the same conductivity type may also be adopted.For example, when the contact resistance at the contact portion between the anode layer and the first electrode is high, the contact resistance at the contact portion between the anode layer and the first electrode can be reduced by adopting a double-layer structure in which a high-concentration anode layer having a high impurity concentration is disposed on the first main surface side and a low-concentration anode layer having a lower impurity concentration than that of the high-concentration anode layer is disposed on the second main surface side closer than the high-concentration anode layer.

[0091] Although embodiments of the present invention have been described, they are presented as examples. Various omissions, substitutions, and changes may be made. Each embodiment may also be combined.

Claims

[1] A semiconductor device (100, 200, 300, 400), comprising: - a semiconductor substrate having a drift layer (12) of a first conductivity type between a first main surface (S1) and a second main surface (S2) opposite the first main surface (S1); - a diode region (2) comprising: - an anode layer (11) of a second conductivity type arranged in a surface layer of the semiconductor substrate on the side of the first main surface (S1), and - a cathode layer (15) of the first conductivity type arranged in a surface layer of the semiconductor substrate on the side of the second main surface (S2); - an insulated gate bipolar transistor region (1, 20, 30, 40) arranged in a line with the diode region (2) along the first main surface (S1) of the semiconductor substrate in a first direction, comprising: - a base layer (9) of the second conductivity type arranged in the surface layer of the semiconductor substrate on the side of the first main surface (S1), - an emitter layer (8) of the first conductivity type, which has a higher impurity concentration than that of the drift layer (12) and which is selectively arranged in a surface layer of the base layer (9) on the side of the first main surface (S1), - a plurality of gate electrodes (7a) arranged side by side in the first direction and facing the emitter layer (8), the base layer (9) and the drift layer (12) via gate insulating films (6a), - a counter-doped layer (10, 21, 31, 41) arranged in a surface layer of the base layer (9), having a higher concentration of impurities of the second conductivity type than that of the base layer (9) and a higher concentration of impurities of the first conductivity type than that of the drift layer (12), and - a collector layer (13) of the second conductivity type arranged in the surface layer of the semiconductor substrate on the side of the second main surface (S2), wherein: - the insulated gate bipolar transistor region (40) comprises a third region (40a) in which the counterdoped layer (41) is disposed between the adjacent gate electrodes (7a) of the third region (40a), and a fourth region (40b) in which the counterdoped layer (41) is not disposed between the adjacent gate electrodes (7a) of the fourth region (40b), and - the third region (40a) is closer to the diode region (2) than the fourth region (40b). [2] The semiconductor device (100, 200, 300, 400) according to claim 1, wherein the counter-doped layer (10, 41) is disposed between regions of the base layer (9) located between the adjacent gate electrodes (7a) in the first direction. [3] Semiconductor device (100, 200, 300, 400) according to claim 1 or 2, - further comprising a base contact layer (16) of the second conductivity type, which is arranged in the surface layer of the base layer (9) and has a higher impurity concentration than that of the base layer (9), - wherein the counter-doped layer (10, 21, 31) is arranged between regions of the base contact layer (16) between the adjacent gate electrodes (7a) in the first direction. [4] The semiconductor device (100, 200, 300, 400) according to claim 3, wherein impurities for the second conductivity type of the counter-doped layer (10, 21, 31, 41) are the same as impurities of the second conductivity type of the base contact layer (16). [5] Semiconductor device (100, 200, 300, 400) according to one of the preceding claims, wherein impurities for the first conductivity type of the counter-doped layer (10, 21, 31, 41) are the same as impurities of the first conductivity type of the emitter layer (8). [6] A semiconductor device (100, 200, 300, 400) according to any one of the preceding claims, wherein a concentration of impurities of the first conductivity type in the counter-doped layer (10, 21, 41) is higher than a concentration of impurities of the second conductivity type in the counter-doped layer (10, 21, 41). [7] The semiconductor device (100, 200, 300, 400) according to any one of claims 1 to 5, wherein a concentration of impurities of the first conductivity type in the counter-doped layer (31) is lower than a concentration of impurities of the second conductivity type in the counter-doped layer (31). [8] Semiconductor device (100, 200, 300, 400) according to one of the preceding claims, wherein the counter-doped layer (41) is in contact with the emitter layer (8) in the second direction orthogonal to the first direction along the first main surface (S1). [9] A semiconductor device (100, 200, 300, 400) according to any one of the preceding claims, wherein: - each of the counter-doped layer (10, 21, 31, 41) and the emitter layer (8) has, in plan view, a longitudinal direction and a lateral direction orthogonal to the longitudinal direction, and - a width (W2) of the lateral direction of the counter-doped layer (10, 21, 31, 41) is narrower than a width (W1) of the lateral direction of the emitter layer (8). [10] Semiconductor device (100, 200, 300, 400) according to one of the preceding claims, wherein the anode layer (11) in the diode region (2) comprises: - an anode layer with a high impurity concentration arranged in the surface layer on the first main surface (S1), and - a low impurity concentration anode layer arranged closer to the second main surface (S2) side than the high impurity concentration anode layer and having a lower impurity concentration than that of the high concentration anode layer.

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