Data storage device and method for writing information to a data storage device

Abstract

A data storage device that has the following features: a plurality of storage elements (12; 28), each storage element being configured to store one piece of information; wherein the plurality of storage elements (12; 28) can be accessed as a plurality of word sets (14), wherein each word set (14) has a set of storage elements, and as a plurality of piece sets (16), wherein each piece set (16) has a set of storage elements and wherein each storage element is part of a word set (14) and part of a piece set (16); a control unit (18) configured to receive word information (22) and piece information (24) different from the word information and to perform a write operation to write the word information (22) into a word set (14) of the plurality of word sets (14) and in parallel to write the piece information (24) into a piece set (16) of the plurality of piece sets (16), wherein the word set (14) and the piece set (16) share a common memory element (12) 3,4 ) exhibiting, which is defined by an overlap of the word set (14) and the piece set (16) in a layout of the plurality of storage elements (12; 28).

Description

[0001] The present disclosure relates to a data storage device and to a method for writing information to a data storage device. The present disclosure further relates to a memory with simultaneous orthogonal read and write access.

[0002] A data storage device can have multiple storage elements that can hold information. Some data storage devices can be accessed via a write operation to write or store information in one or more storage elements. Some data storage devices can be accessed via a read operation to retrieve or read information stored in storage elements.

[0003] US 5,959,911 describes a test of a memory device in which common memory addresses of a bank to be activated are selected. For this purpose, a plurality of memory banks are selected for testing, and a common memory address corresponding to a memory cell of each activated bank is chosen.

[0004] US 2011 / 0043507 A1 describes a synchronous semiconductor device, in particular a memory for fast operation.

[0005] There is a need for the efficient execution of secure write operations in data storage devices.

[0006] According to one embodiment, a data storage device comprises a plurality of storage elements, each storage element being configured to store information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements, and as a plurality of piece sets, each piece set comprising a set of storage elements, each storage element being a part of a word set and a part of a piece set. The data storage device includes a control unit configured to receive word information and piece information and to perform a write operation to write the word information to a word set of the plurality of word sets and, in parallel, to write the piece information to a piece set of the plurality of piece sets.The word set and the piece set have a common storage element, which is defined by an overlap of the word set and the piece set in a layout of the plurality of storage elements.

[0007] According to one embodiment, a method for writing information to a data storage device comprising a plurality of storage elements, each storage element being configured to store information, the plurality of storage elements being accessible as a plurality of word sets, each word set comprising a set of storage elements, and as a plurality of piece sets, each piece set comprising a set of storage elements, and each storage element being a part of a word set and a part of a piece set, comprises the following steps: obtaining word information and piece information, and performing a write operation to write the write information to a word set of the plurality of word sets and, in parallel, to write the piece information to a piece set of the plurality of piece sets, such that the word set and the piece set share a common storage element.which is defined by an overlap of the word set and the piece set in a layout of the plurality of storage elements.

[0008] Further embodiments are defined in the dependent claims.

[0009] Preferred embodiments according to the present disclosure are described below with reference to the accompanying drawings. Fig. Figure 1 shows a schematic block diagram of a data storage device according to an exemplary embodiment; Fig. Figure 2a shows a schematic block diagram of a data storage device according to an embodiment in which word information is prioritized over piece information in order to be written in parallel; Fig. Figure 2b shows a schematic block diagram of the data storage device and a configuration in which the piece information is prioritized over the word information according to an embodiment; Fig. Figure 3 shows a schematic block diagram of a circuit arrangement according to an embodiment, which includes a data storage element to enable the data storage element to be described with word information or piece information; Fig. Figure 4 shows a schematic block diagram of a data storage device according to an embodiment, wherein the data storage device includes additional data storage elements for storing parity information; and Fig. Figure 5 shows a schematic flowchart of a process according to an exemplary embodiment.

[0010] Identical or equivalent elements, or elements with the same or equivalent functionality, are designated by the same or equivalent reference symbols in the following description, even if the same elements appear in different figures.

[0011] The following description includes numerous details to provide a more thorough explanation of the embodiments of the present invention. However, it is clear to those skilled in the art that embodiments of the present invention can be implemented without these specific details. In other cases, well-known structures and devices are shown in block diagram form rather than in detail to avoid hindering embodiments of the present invention. Furthermore, features of the different embodiments described herein can be combined unless specifically noted otherwise.

[0012] Embodiments of the present disclosure relate to memory elements. Memory elements can be adapted to store information. For example, such information can comprise one or more bits. For example, a memory element can comprise a resistive random-access memory (RAM) cell, a magnetoresistive RAM (MRAM) cell, or any other type of volatile or non-volatile memory cell.

[0013] A data storage device according to the exemplary embodiments can have a plurality of storage elements, for example, at least 5, at least 10, at least 100, at least 1000, or even more, e.g., several thousand, several million, or even several billion memory cells. Each memory cell can be adapted to store information, e.g., one or a greater number of bits.

[0014] Fig. Figure 1 shows a schematic block diagram of a data storage device 10 according to an exemplary embodiment. The data storage device 10 can have a plurality of storage elements 12, which are represented as a plurality of word sets (words) 141 to 141. N and a plurality of slice sets 161 to 16 M data storage elements can be addressed for a read and / or write operation.

[0015] The data storage elements 12 1,1 up to 12 N,M They can be arranged in a corresponding matrix configuration, but they don't have to be. Even if they are arranged differently, the majority of storage elements can be 12. 1,1 up to 12 N,M be interconnected according to a matrix configuration in which the majority of word sets are 141 to 14 N are arranged parallel to each other along a first direction, and in which the majority of sets are 161 to 16 Mare arranged parallel to each other along a second perpendicular direction. Sets of data storage elements along a specific direction can be accessed collectively to read and / or write combined information, e.g., a data word or a data piece, from and / or to them. According to one embodiment, the control unit 18 can be configured to write word information 22 along a first direction, e.g., along a word set, and piece information 24 along an orthogonal second direction, e.g., along a piece set, to the plurality of storage elements according to the matrix configuration of the plurality of data storage elements.

[0016] The number of storage elements 12 in a word set 14 can be less than, equal to, or greater than the number of storage elements that make up a piece set 16. That is, a control unit of a data storage device according to exemplary embodiments can receive the word information 22 with a first data length and the piece information with a second, different data length. Different word sets can have the same number of data storage elements 12, but exemplary embodiments are not limited to this. Similarly, different piece sets can have the same number of data storage elements 12, but exemplary embodiments are not limited to this.

[0017] For example, when a write operation to add or replace information is performed in the data storage device 10, a control unit 18 of the data storage device 10 can generate information for a word set and for a piece set, both of which are to be written to the plurality of memory elements, memory elements of a word set 14 and a piece set 16, respectively. However, such a write operation is not limited to writing only one word set 14 and only one piece set 16. During a write operation, a higher number of word sets, e.g., at least 2, at least 3, or at least 4, or even a greater number, can also be written, along with at least 1, at least 2, at least 3, or at least 4, or a greater number of piece sets. Alternatively or additionally, a number of more than one piece set can be written along with at least one word set.In exemplary embodiments, the number of word sets and the number of piece sets to be written during a single write operation are equal and have a value of at least 1. For example, the control unit 18 can be configured to write a plurality of word information to a corresponding plurality of word sets and an associated plurality of piece information to a corresponding plurality of piece sets in parallel. Each word set can share a common memory element with the corresponding piece set. The control unit can be configured to resolve a corresponding plurality of competing pieces of information at a location corresponding to the respective common memory element.

[0018] As is indicated for the word set 143, which is to be written in parallel with the piece set 164, the word set 143 and the piece set 164 have a common storage element 12. 3,4, which is defined by an overlap of the word set 143 and the piece set 164. Each of the storage elements arranged in the plurality of word sets 14 and the plurality of piece sets 16 can be part of a word set and part of a piece set.

[0019] The control unit 18 can be configured to receive word information 22 and piece information 24, e.g., a sequence of information and / or bits. Such information can be obtained from any source and, in one embodiment, is obtained based on a bit transformation.

[0020] The control unit 18 can perform a write operation to write the word information 22 into a word set, e.g., word set 143, and the piece information 24 in parallel into a piece set, e.g., piece set 164. To write the word information 22 and the piece information 24 in parallel, the saving of the information into word set 143 and into piece set 164 can be performed at least partially during the same time. That is, the control unit 18 can be configured to write the word information 22 during one word-write time interval and to write the piece information 24 during another piece-write time interval. The control unit 18 can be configured to write the word information and the piece information such that the word-write time interval partially or completely overlaps with the piece-write time interval.The word-writing time interval and the piece-writing time interval can have the same or different lengths. The starting and ending times of the word-writing and piece-writing time intervals can also be the same or different.

[0021] Based on the parallel write operation, it is evident that for the information stored in the shared memory element 12 3,4 A conflict can arise when the information to be stored, which is defined as the overlap of the word set 143 and the piece set 164, is to be stored. Such a conflict can arise if the information to be stored for the word information 22 differs from the information to be stored for the piece information 24 at the position assigned to the common storage element 12. 3,4is assigned. The control unit 18 can implement one or more concepts described herein for resolving such conflicts.

[0022] Such a conflict can arise from competing information between the word information 22 and the piece information 24 for the common storage element 12. 3,4 refer to. That is, the word information can provide initial information for the shared memory element 12. 3,4 exhibit or display, while the piece information 24 contains a different second piece of information for the same data storage element 12. 3,4 contain or display. Resolving the conflicting information may involve data storage element 12. 3,4 to describe it once with the corresponding part of the word information 22 and at another time, that is, earlier or later, with the corresponding part of the piece information 24.

[0023] This can be described as prioritizing word information over piece information, or alternatively as prioritizing piece information over word information in at least the shared memory element 12. 3,4 The prioritized information will later be stored in memory element 12. 3,4 written when compared with the information against which it was prioritized.

[0024] According to one embodiment, the control unit 18 can be configured to write a single data element to the common memory element 12. 3,4 , which can only be considered a single write operation if the word information 22 and the piece information 24 are written. Therefore, either part of the word information 22 or part of the piece information 24 can be stored in the common memory element 12. 3,4 be saved.

[0025] According to one embodiment, the control unit 18 can be configured for the write operation to replace a portion of the piece information 24 belonging to the common storage element 12. 3,4 corresponds to a corresponding part of the word information 22, where the corresponding part corresponds to the common storage element 12 3,4 This corresponds to the possibility that the piece information may become corrupted or prone to errors, but this can be corrected, for example, by using error detection codes and / or error correction codes. Alternatively, the control unit 18 can also be configured to replace part of the word information 22 that corresponds to the common memory element 12. 3,4 corresponds to a corresponding part of the piece information 24, wherein the corresponding part corresponds to the common storage element 12 3,4This corresponds to the fact that instead of falsifying the piece information, the word information can also be falsified or adapted.

[0026] Fig. Figure 2a shows a schematic block diagram of a data storage device 20 according to an exemplary embodiment. The data storage device 20 can have the same data storage elements 12 as the data storage device 10. The control unit 18 can be configured to replace part of the piece information 24 with information 12. x , to obtain modified piece information 24'. For example, by using one or more circuit elements, such as multiplexers 26, a bit x can be combined with the piece information 24 at any selected bit position, i.e., the position of the common memory element 12. 3,4 in the piece information 24. This allows the word information 22 to be prioritized over the piece information 24.

[0027] In other words, Fig. Figure 2a shows a memory with N words and M pieces. A conflict can occur at an overlapping bit at position (x, y). This can be resolved by transferring a single bit with priority and / or by using a gate bit with or without priority. In this example, the word information has priority and is real information, while the piece information is dummy information.

[0028] Fig. Figure 2b shows a schematic block diagram of the data storage device 20 and a configuration in which the piece information 24 is prioritized over the word information 22. A piece x of the piece information 24 can be inserted into the word information 22 to obtain modified word information 22'.

[0029] Unlike Fig. 2a. The piece information is prioritized over the word information, and the word information is pseudo-information, while the piece information is real information.

[0030] In the embodiments described herein, data from different data paths, i.e., word information and piece information, are written in parallel. This can lead to asymmetric information being written orthogonally into memory. For example, data values ​​and data pieces may have different bit sizes. This can result in a large number of conflicts; for instance, almost every write operation can cause a conflict. The embodiments provide a solution that allows both data elements to be written in a single cycle, i.e., in parallel. For example, when two elements, i.e., the word information and the piece information, are written to memory, one data element has priority. For an overlapping bit, the prioritized bit is selected, which may be a different single bit for a different word / piece combination.All bits of both data elements can be written to memory; at a position of the overlapping bit of the shared memory element, the same data for both the word and the piece can be written to that element. This solution also works for multiple bits, for example, if pipeline stages are used. (With reference to...) Fig. 2a and / or Fig. 2b, for example, multiple bits can be copied from one data element to another.

[0031] Both configurations of the data storage device 20 in Fig. 2a and Fig. 2b allows the number of write operations to the shared data storage element 12 to be increased. 3,4to reduce to a single write operation. The configuration that prioritizes information over other information can be fixed or variable. For example, it can vary with regard to the reliability or usability of the information to be written. For instance, control unit 18 performs several iterations to write information to word set 143 and piece set 164. During one or more of these iterations, dummy information can form piece information 24 or word information 22. For example, one set of information, word information 22 or piece information 24, might be real information that needs to be protected by using dummy operations, and the other set of information might contain such dummy information. In such a case, the real information can be prioritized over the dummy information.

[0032] Such real information can be considered secret information, written alongside dummy information to conceal a write operation of the secret information to be secured. For example, control unit 18 can be configured to write secret information in parallel to a word set and dummy information to an associated piece set, e.g., in the configuration of Fig. 2a. Alternatively, the control unit can write dummy information into the word set and secret information into the assigned piece set, as described in the configuration of Fig. 2b is shown.

[0033] For example, during a first iteration, control unit 18 can write initial secret information to word set 143 and simultaneously write initial dummy information to the associated piece set 164, and during a second iteration, write second dummy information to word set 143 and simultaneously write second secret information to the associated piece set 164. Between iterations, the configuration between Fig. 2a and Fig. 2b can be changed, e.g. using a control signal from control unit 18.

[0034] If, for example, the real secret word information 22 is denoted by a capital letter W and the real secret piece information 24 by a capital letter S, while the respective dummy information is denoted by the corresponding lowercase letters w and s, respectively, and by displaying a cycle / iteration separator with “-” , which separates the rounds [ ], and by displaying a hiding parameter (#dummy rounds / cycle) with h, and if costs are calculated relative to a round by the parameter c, a calculation can only be performed on words, in an example with w−w−w−w−W−W−W−W.

[0035] By extending this example to writing words and pieces, as implemented in the embodiment examples, a single round of such operations without hiding can be expressed by W−W−W−W−S−S−S−S.

[0036] Hiding, i.e., using fake information to conceal the use of real information at the turn level, can be done in known concepts, for example by performing... [w−w−w−w−s−s−s−s]−[w−w−w−w−s−s−s−s]−[W−W−W−W−S−S−S−S_]−[w−w−w−w−s−s−s−s]−[w−w−w−w−s−s−s−s] [wwwwsss] and [WWWWSSSS] each denote a round or iteration and can be used to write four word and four piece information operations to the data storage device. Writing can be performed on different word and piece sets to avoid overwriting real information with fake information. Using a final write operation to write real information can be a vulnerable concept if an attacker gains knowledge of such a structure.

[0037] The given example yields 5 rounds instead of one by using 4 fake rounds, thus costing 5 times as much, i.e., c = 5.

[0038] Another example can be expressed as: [w−w−w−w−s−s−s−s]−[w−w−w−w−s−s−s−s]−[w−w−w−w−s−s−s−s]−[w−w−w−w−s−s−s−s]−[w−w−w−w− s−s−s−s]−[w−w−w−w−s−s−s−s]−[W−W−W−W−S−S−S−S_]−[w−w−w−w−s−s−s−s]−[w−w−w−w−s−s−s−s] with 8 mock rounds and one real iteration, thus costing 9 times as much.

[0039] According to examples, words and pieces can be nested, e.g., according to: [w−s]−[w−s]−[w−s]−[w−s]−[W−s]−[W−s]−[W−s]−[W−s]−[w−S]−[w−S]−[w−S]−[w−S]

[0040] Such a concept mixes the writing of fake information and real information within a round and for one or more rounds, e.g., when [Ws] or [wS] is written. In the given example, 12 rounds are planned with 4 fake rounds, resulting in 3 times the cost compared to writing words and pieces without hiding information.

[0041] In another example, the rounds can be organized as follows: [w−s]−[w−s]−[w−s]−[w−s]−[w−s]−[w−s]−[w−s]−[w−s]−[W−s]−[W−s]−[W−s]−[W−s]−[w−S]−[w−S]−[w−S]−[w−S]

[0042] With 8 mock rounds and 4 times the cost compared to writing words and pieces without hiding, when 16 words and 16 pieces are written.

[0043] As can be seen from the [Ws] and [wS] operations, a cycle can be performed by writing both dummy information and real information, or by writing only dummy information. When only dummy information is written, indicated by [ws], prioritization can be performed in either direction and / or omitted.

[0044] According to the exemplary implementations, the writing is carried out in such a way that the word and the piece are calculated in the same cycle, e.g. according to [ws]−[ws]−[ws]−[ws]−[Ws]−[Ws]−[Ws]−[Ws]−[wS]−[wS]−[wS]−[wS] with 4 mock rounds, but only 1.5 times the cost compared to a scenario without hiding or [ws]−[ws]−[ws]−[ws]−[Ws]−[Ws]−[Ws]−[Ws]−[wS]−[wS]−[wS]−[wS]−[ws]−[ws]−[ws]−[ws] with 8 mock rounds, but only 2 times the cost compared to a scenario without hiding.

[0045] In the given exemplary embodiments, the cycle operator “-” can be placed outside the iterations, since within an iteration the word information and the piece information are written in parallel.

[0046] This can be implemented through hardware and / or software, along with a solution to fix overlapping bits, for example, by writing the prioritized bit last or by replacing information. This can be used to resolve the need to write both the word and the piece in the same cycle and to address the overlapping bit, e.g., data storage element 12. 3,4 , in which a word (e.g. a line) and a piece (e.g. a column) might not match.

[0047] Implementation examples create a special memory that performs simultaneous read and write operations for orthogonal words and pieces. This can be done indistinguishably, regardless of whether a word or a piece is being accessed, for example, by hiding such details. According to one aspect, a word and its associated piece are always written together. This allows for hiding at a cycle level whether real or sham information is being written at a cycle level instead of a round level. An overlapping bit can be corrected at a changing bit position (x, y) for a piece x and a word y. This enables high efficiency, for example, for strong customer authentication (SCA) and the secure implementation of cryptographic algorithms, such as those that use the shuffling of orthogonal data.

[0048] Fig. Figure 3 shows a schematic block diagram of a circuit arrangement 30 that includes a data storage element 28 to allow the data storage element 28 to be written with word information 22 or piece information 24. For example, the circuit arrangement 30 shown can be implemented for each data storage element of a memory array. The data storage element 28 can, for example, be a data storage element 12 of Fig. 1, Fig. 2a and / or Fig. 2b. That is, one or more of the data storage elements 12 can be configured as a data storage element 28. The information input 34 can be configured to receive information to be written, e.g., information relating to word information or piece information. The control input 32 can be configured to receive a control signal, e.g., a signal such as "activate" or the like. The control input 32 can be connected to a control circuit 38, which may, for example, include an OR gate or the like.

[0049] It is clear that similar behavior to that described below can be obtained with other gates and / or a different circuit arrangement. For example, control circuit 38 can include a NOR gate as an alternative to, or in addition to, the OR gate shown.

[0050] Control circuit 38 can be configured to receive a control signal 421 indicating that word information should be written, e.g., word information 22. Furthermore, control circuit 38 can be configured to receive a control signal 422 indicating that piece information should be written, e.g., piece information 24. Control circuit 38 can be configured to activate a write operation in response to at least one of the control signals 421 and 422.

[0051] The data storage element 28 can have a control input 32, an information input 34, and an information output 36. The data storage element 28 can have a single data cell or multiple data cells, e.g., for storing several bits.

[0052] Alternatively or additionally, the information input 34 can be connected to a selection circuit 44, which may, for example, include a multiplex element. The selection circuit 44 can be configured to receive an information signal 461 containing at least part of the word information 22, and to receive an information signal 462 containing at least part of the piece information 24. The selection circuit 44 can be configured to select one of the information signals 461 and 462 to be forwarded to the data storage element 28.

[0053] The information output 36 can be connected to a circuit arrangement 48 configured to provide the stored information. The information output 38 can be connected to one or more multiplexers 521 and / or 522, which can be connected to further data storage elements 28 of the same piece and / or word, so that the data storage element 28 can be read when the word set or piece set to which the data storage element 28 belongs is read.

[0054] Fig. Figure 4 shows a schematic block diagram of a data storage device 40 according to an exemplary embodiment. Compared to the data storage devices 10 and / or 20, the data storage device 40 may have additional data storage elements 54 configured to store parity information. Although the structure and / or function of the data storage element itself may be the same as that of the data storage element 12 and / or 28, a circuit arrangement associated with the data storage element 54 may be simpler than that of the data storage element 28. In particular, the data storage elements 54 may not be considered part of a word or piece, but rather, for example, as an extension of a word or piece.

[0055] The control unit 18 can be configured to write the word information 22 and associated word parity information 56 in parallel. The word parity information 56 can, for example, be stored in a data storage element 54. w.3 be stored. The word set can overlap with a plurality of overlapping clauses, e.g., all clauses 161 to 16. M By writing down the word information, all the information contained in pieces 161 to 16 can be obtained. M are included, may be changed or modified. Parity information for at least one, for several, or even for all of these overlapping sets 161 to 16 M can be updated in conjunction with writing the word information 22. Alternatively or additionally, the control unit 18 can write the piece information 24 into the piece record 164 and thereby also update each of the word records 141 to 14. NThe control unit can update word parity information for one, several, or even all overlapping word sets and can also transfer piece parity information 58 to a corresponding data storage element 54. s,4 It must be verified that the second part refers to writing the piece information. Although the word parity information 56 and the piece parity information 58 are described as being written to a single data storage element 54, parity information can also be stored in a plurality of data storage elements, e.g., if they contain more than a single bit.

[0056] Parity information can also enable error detection and / or correction, for example, using error detection codes (EDC) and / or error correction codes (ECC). This can allow for improvement in using the information even after the word or piece information in the common data storage element of a word and piece set has been modified. For example, memory extension can be used to add an error detection code to words and pieces using one or more parity bits for each word and one or more parity bits for each piece. The parity bit can be written and updated along with the word / piece write operation. This can enable error detection of the stored data similar to EDC with a minimum spacing of three, meaning any three errors in the memory can be detected.

[0057] The control unit 18, according to the exemplary embodiments, can be configured to obtain the word information 22 based on at least one bit transformation and to obtain the bit information 24 based on at least one other bit transformation. For example, the data storage can be used in conjunction with SHA-3 transformations. For example, an RHO transformation can be used on words. A THETA transformation, a Pi transformation, and / or a CHI transformation can be used on a bit bit.

[0058] For example, according to one embodiment, a control unit can read one or more words from a corresponding number of word sets, calculate the RHO transformation, and write the resulting word information. In parallel, the control unit can read fragments and calculate the THETA transformation, the PI transformation, the CHI transformation, and / or the IOTA transformation, and write the fragment information. For example, to use the RHO transformation, 25 words of an exemplary length of 64 bits can be read and / or written. A corresponding number of 64 25-bit fragments can be read and / or written.

[0059] Examples of implementation create a memory with simultaneous orthogonal read and write access.

[0060] Fig.Figure 5 shows a schematic flowchart of a method 500 according to an embodiment. The method 500 can be used to write information to a data storage device, e.g., data storage device 10, 20, and / or 40. The data storage device in conjunction with the method 500 has a plurality of storage elements, each storage element being configured to store information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements. Furthermore, the plurality of storage elements is accessible as a plurality of piece sets, each piece set comprising a set of storage elements. Each storage element is part of a word set and part of a piece set. At Figure 510, word information and piece information are obtained.At 520, a write operation is performed to write the word information in parallel to a word set of the plurality of word sets and the piece information to a piece set of the plurality of piece sets, such that the word set and the piece set have a common memory element defined by an overlap of the word set and the piece set in a layout of the plurality of memory elements.

[0061] Although some aspects have been described in connection with a device, it is understood that these aspects also constitute a description of the corresponding process, so that a block or component of a device can also be understood as a corresponding process step or as a feature of a process step. Similarly, aspects described in connection with or as a process step also constitute a description of a corresponding block, detail, or feature of a corresponding device.

[0062] Depending on specific implementation requirements, embodiments of the invention can be implemented in hardware or in software. The implementation can be carried out using a digital storage medium, for example a floppy disk, DVD, Blu-ray disc, CD, ROM, PROM, EPROM, EEPROM or FLASH memory, hard disk or other magnetic or optical storage medium, on which electronically readable control signals are stored that can interact with, or interact with, a programmable computer system in such a way that the respective method is carried out.

[0063] Some embodiments according to the invention therefore include a data carrier which has electronically readable control signals which are able to interact with a programmable computer system in such a way that one of the methods described herein is carried out.

[0064] In general, embodiments of the present invention can be implemented as a computer program product with program code, wherein the program code is effective in carrying out one of the methods when the computer program product runs on a computer. The program code can, for example, also be stored on a machine-readable medium.

[0065] Other embodiments include the computer program for carrying out one of the methods described herein, wherein the computer program is stored on a machine-readable medium.

[0066] In other words, an embodiment of the method according to the invention is thus a computer program that includes program code for carrying out one of the methods described herein when the computer program runs on a computer.

[0067] Another embodiment of the methods according to the invention is therefore a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for carrying out one of the methods described herein is recorded.

[0068] Another embodiment of the method according to the invention is thus a data stream or a sequence of signals that represents the computer program for carrying out one of the methods described herein. The data stream or sequence of signals can be configured, for example, to be transmitted via a data communication connection, such as the Internet.

[0069] Another embodiment comprises a processing device, for example a computer, a security processor, a security module, a smart card, a Trusted Platform Module (TPM), a secure root of trust, or a programmable logic device, configured or adapted to perform one of the procedures described herein.

[0070] Another embodiment comprises a computer on which the computer program for performing one of the procedures described herein is installed.

[0071] In some embodiments, a programmable logic device (for example, a field-programmable gate array, an FPGA) can be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field-programmable gate array can interact with a microprocessor to perform one of the methods described herein. Generally, the methods are preferably performed by any hardware device.

[0072] The embodiments described above are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein will be obvious to other people skilled in the art. Therefore, it is intended that the invention be limited only by the scope of protection set forth in the following claims and not by the specific details presented herein by way of description and explanation of the embodiments.

Claims

[1] A data storage device which has the following features: a plurality of storage elements (12; 28), each storage element being configured to store one piece of information; wherein the plurality of storage elements (12; 28) can be accessed as a plurality of word sets (14), wherein each word set (14) has a set of storage elements, and as a plurality of piece sets (16), wherein each piece set (16) has a set of storage elements and wherein each storage element is part of a word set (14) and part of a piece set (16); a control unit (18) configured to receive word information (22) and piece information (24) different from the word information and to perform a write operation to write the word information (22) into a word set (14) of the plurality of word sets (14) and in parallel to write the piece information (24) into a piece set (16) of the plurality of piece sets (16), wherein the word set (14) and the piece set (16) share a common memory element (12) 3,4 ) exhibiting, which is defined by an overlap of the word set (14) and the piece set (16) in a layout of the plurality of storage elements (12; 28). [2] The data storage device according to claim 1, wherein the plurality of storage elements (12; 28) are connected to each other according to a matrix configuration, wherein the plurality of word sets (14) are arranged parallel to each other along a first direction and wherein the plurality of piece sets (16) are arranged parallel to each other along a second perpendicular direction. [3] The data storage device according to claim 2, wherein the control unit (18) is configured to write the word information (22) along a first direction and the piece information (24) along an orthogonal second direction to the plurality of storage elements (12; 28) according to the matrix configuration. [4] The data storage device according to the preceding claims, wherein the control unit (18) is configured to resolve a conflict of information between the word information (22) and the piece information (24) for the common storage element (12) 3,4 ). [5] The data storage device according to one of the preceding claims, wherein the control unit (18) is configured to write a single data element to the common storage element (12) 3,4 ), to store either part of the word information (22) or part of the piece information (24) in the common storage element (12 3,4 ) to save. [6] The data storage device according to one of the preceding claims, wherein for the write operation the control unit (18) is configured to replace a part of the piece information (24) that is in the common storage element (12) 3,4 ) corresponds, by a corresponding part (22 x) of the word information (22), wherein the corresponding part (22 x ) the common storage element (12 3,4 ) corresponds; or wherein the control unit (18) is configured to replace a portion of the word information (22) corresponding to the common memory element (12) 3,4 ) corresponds, by a corresponding part (24 x ) of the piece information (24), wherein the corresponding part (24 x ) the common storage element (12 3,4 ) corresponds. [7] The data storage device according to one of the preceding claims, wherein the control unit (18) is configured to prioritize the word information (22) over the piece information (24) or to prioritize the piece information (24) over the word information (22) in at least one common storage element (12) 3,4 ), which is assigned to the word set (14) and the piece set (16). [8] The data storage device according to one of the preceding claims, wherein the control unit (18) is configured to write a plurality of word information (22) in parallel to a corresponding plurality of word sets (14) and an associated plurality of piece information (24) to a corresponding plurality of piece sets (16), wherein each word set (14) has a common storage element (12) 3,4 ) with the corresponding set of components (16), wherein the control unit (18) is configured to resolve a corresponding plurality of competing pieces of information at a position corresponding to the respective common storage element (12) 3,4 ) corresponds. [9] The data storage device according to one of the preceding claims, wherein a storage element (28) of the plurality of storage elements has an information input (34) for receiving information to be written, and a control input (32) for receiving a control signal (421, 422) and an information output (36), wherein the control input (32) is connected to a control circuit (38) configured to receive a first control signal (421) indicating to write word information (22), and to receive a second control signal (422) indicating to write piece information (24), wherein the control circuit (38) is configured to activate a write operation responding to at least one of the first control signal (421) and the second control signal (422). [10] The data storage device according to one of the preceding claims, wherein a storage element (28) of the plurality of storage elements has an information input (34) for receiving information to be written, a control input (32) for receiving a control signal, and an information output (36), wherein the information input (34) is connected to a selection circuit (44) configured to receive a first information signal (461) comprising at least a part of the word information (22), and to receive a second information signal (462) comprising at least a part of the piece information (24), wherein the selection circuit (44) is configured to select one of the first information signal (461) and the second information signal (462) to be forwarded. [11] The data storage device according to any one of the preceding claims, wherein the control unit (18) is configured to write the word information (22) to the word set (14), wherein the word set (14) overlaps with a plurality of overlapping piece sets (16), and to update piece parity information (58) for an overlapping piece set (16) and to write word parity information associated with the word information (22); and / or wherein the control unit (18) is configured to write the piece information (24) to the piece set (16), wherein the piece set (16) overlaps with a plurality of overlapping word sets (14), and to update word parity information (56) for an overlapping word set (14) and to write piece parity information associated with the piece information (24). [12] The data storage device according to one of the preceding claims, wherein the control unit (18) is configured to obtain the word information (22) based on at least one bit transformation and to obtain the piece information (24) based on at least one other bit transformation. [13] The data storage device according to one of the preceding claims, wherein the control unit (18) is configured to write secret information in parallel to a word set (14) and dummy information to an associated piece set (16) or to write dummy information in parallel to the word set (14) and secret information to an associated piece set (16). [14] The data storage device according to claim 13, wherein the control unit (18) is configured to write first secret information to a word set (14) and first fake information to an associated piece set (16) in parallel during a first iteration, and to write second fake information to the second word set (14) and second secret information to the associated piece set (16) in parallel during a second iteration. [15] The data storage device according to one of the preceding claims, wherein the control unit (18) is configured to write the word information (22) during a word-write time interval and to write the piece information (24) during a piece-write time interval, wherein the control unit (18) is configured to write the word information (22) and the piece information (24) such that the word-write time interval overlaps with the piece-write time interval for parallel execution of writing the word information (22) and writing the piece information (24). [16] The data storage device according to one of the preceding claims, wherein the control unit (18) is configured to receive the word information with a first data length and the piece information (24) with a second, different data length. [17] A method for writing information to a data storage device comprising a plurality of storage elements, wherein each storage element is configured to store information, wherein the plurality of storage elements is accessible as a plurality of word sets (14), each word set (14) comprising a set of storage elements, and as a plurality of piece sets (16), each piece set (16) comprising a set of storage elements, and wherein each storage element is part of a word set (14) and part of a piece set (16), wherein the method comprises the following steps: Received (510) word information and piece information different from the word information; and Performing (520) a write operation to write the word information into a word set (14) of the plurality of word sets (14) and to write the piece information into a piece set (16) of the plurality of piece sets (16) such that the word set (14) and the piece set (16) have a common memory element defined by an overlap of the word set (14) and the piece set (16) in a layout of the plurality of memory elements. [18] The method according to claim 17, wherein during writing the word information is written along a first direction and the piece information (24) is written along an orthogonal second direction into the plurality of memory elements (12; 28) according to the matrix configuration. [19] The method according to claim 17 or 18, comprising the following step: Resolving a conflict of information between the word information (22) and the piece information (24) for the common storage element (12) 3,4 ). [20] The method according to any one of claims 17 to 19, comprising the following step: Writing a single data element to the shared memory element (12 3,4 ) to store either part of the word information (22) or part of the piece information (24) in the common storage element (12) 3,4 ). [21] The method according to any one of claims 17 to 20, comprising the following steps for the writing operation: Replacing part of the piece information (24) that belongs to the common memory element (12) 3,4 ) corresponds to a corresponding part of the word information (22), where the corresponding part corresponds to the common storage element (12) 3,4 ) corresponds; or Replacing part of the word information (22) that belongs to the common memory element (12) 3,4 ) corresponds to a corresponding part of the piece information (24), where the corresponding part corresponds to the common storage element (12) 3,4 ) corresponds. [22] The method according to any one of claims 17 to 21, comprising the following step: Prioritizing the word information (22) over the piece information (24) or prioritizing the piece information (24) over the word information (22) in at least one common storage element (12) 3,4 ), which is assigned to the word set (14) and the piece set (16). [23] The method according to any one of claims 17 to 22, comprising the following steps: parallel writing of a plurality of word information (22) into a corresponding plurality of word sentences (14) and an associated plurality of piece information (24) into a corresponding plurality of piece sentences (16), wherein each word sentence (14) has a common storage element (12) 3,4 ) with the corresponding set of pieces (16); and Resolving a corresponding plurality of competing pieces of information at a position corresponding to the respective common storage element (12 3,4 ) corresponds. [24] The method according to any one of claims 17 to 23, wherein a storage element (28) of the plurality of storage elements has an information input (34) for receiving information to be written, a control input (32) for receiving a control signal and an information output (36), the method comprising the following steps: Receiving, with a control circuit (38) connected to the control input (32), a first control signal (421) indicating to write word information (22), and receiving a second control signal (422) indicating to write piece information (24); and Activating a write operation in response to at least one of the first control signal (421) and the second control signal (422). [25] The method according to any one of claims 17 to 24, wherein a storage element of the plurality of storage elements (28) has an information input (34) for receiving information to be written, a control input (32) for receiving a control signal and an information output (36), the method comprising the following steps: Receiving, with a selection circuit (44) connected to the information input (34), a first information signal which contains at least part of the word information (22), and receiving a second information signal which contains at least part of the piece information (24) and Selecting one of the first information signals and the second information signal to be forwarded. [26] The method according to any one of claims 17 to 25, comprising the following steps: Writing the word information (22) to the word set (14), wherein the word set (14) overlaps with a plurality of overlapping piece sets (16), and updating piece parity information for an overlapping piece set (16) and writing word parity information associated with the word information (22); and / or Writing the piece information (24) to the piece set (16), wherein the piece set (16) overlaps with a plurality of overlapping word sets (14), and updating word parity information for an overlapping word set (14) and writing piece parity information associated with the piece information (24). [27] The method according to any one of claims 17 to 26, comprising the following steps: obtaining the word information (22) based on at least one bit transformation and obtaining the piece information (24) based on at least one other bit transformation. [28] The method according to any one of claims 17 to 27, comprising the following steps: parallel writing of secret information into a word sentence (14) and of pseudo-information into an associated fragmentary sentence (16); or parallel writing of pseudo-information into the word sentence (14) and of secret information into an associated piece sentence (16). [29] The method according to claim 28, comprising the following step: parallel writing of first information into a word sentence (14) and of first pseudo-information into an associated piece sentence (16) during a first iteration, and parallel writing of second pseudo-information into the word sentence (14) and of second secret information into the associated piece sentence (16) during a second iteration. [30] The method according to any one of claims 17 to 29, comprising the following steps: Writing the word information (22) during a word-writing time interval and writing the piece information (24) during a piece-writing time interval, so that the word-writing time interval overlaps with the piece-writing time interval to perform the writing of the word information (22) and the writing of the piece information (24) in parallel. [31] The method according to any one of claims 17 to 30, comprising the following step: Retrieval of the word information (22) with a first data length and the piece information (24) with a second, different data length. [32] A non-volatile storage medium on which a computer program is stored, with program code for carrying out, when the same is running on a computer, a method according to any one of claims 17 to 31.

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