Power module

Abstract

Power module (100), comprising: two semiconductor components (3), each having an electrode (6) on a one-sided surface and an other-sided surface of the semiconductor component (3); a flat plate-shaped first electrically conductive metal pattern connected to the electrode (6) on the one-sided surface of each of the two semiconductor devices (3) arranged in a same plane; a flat-plate-shaped second electrically conductive metal pattern connected to the electrode (6) on the other surface of each of the two semiconductor devices (3); and a capacitive element (4) arranged between the first electrically conductive metal pattern and the second electrically conductive metal pattern and forming a capacitance between the first electrically conductive metal pattern and the second electrically conductive metal pattern, wherein the two semiconductor components (3) and the capacitive element (4) are arranged at the apices of a triangle in the same plane, the first electrically conductive metal pattern and the second electrically conductive metal pattern are each formed to have a flat plate shape with a contour within which the three vertices and three sides of the triangle are encompassed, assumed that a shortest connection length path between the two semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern is defined as a first shortest path, and a shorter path and a longer path from two shortest connection length paths between the capacitive element (4) and the two respective semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern are defined as a second shortest path and a third shortest path, respectively, (first shortest path)≥(second shortest path) and ((first shortest path) 2 +(second shortest path) 2 )≥(third shortest path) 2 are fulfilled, assumed that a resonance frequency defined as a first resonance frequency from two capacitances interfering between the one-sided surfaces and the other-sided surfaces of the two semiconductor components (3) and two inductances generated between the one-sided surfaces and between the other-sided surfaces of the two semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, a resonant frequency defined as a second resonant frequency from a capacitance generated by the capacitive element (4) and a capacitance acting interferingly between the one-sided surface and the other-sided surface of one of the two semiconductor components (3), and two inductances generated between the capacitive element (4) and the one-sided surface of one of the semiconductor components (3) and between the capacitive element (4) and the other-sided surface of one of the semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, and a resonant frequency resulting from a capacitance generated by the capacitive element (4) and a capacitance interfering between the one-sided surface and the other-sided surface of another of the two semiconductor components (3), and two inductances generated between the capacitive element (4) and the one-sided surface of the other of the semiconductor components (3) and between the capacitive element (4) and the other-sided surface of the other of the semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern is defined as a third resonant frequency, the first electrically conductive metal pattern and the second electrically conductive metal pattern each have a thickness equal to or greater than twice a skin depth through which current flows due to the skin effect generated by the first resonant frequency, the second resonant frequency, and the third resonant frequency of current paths, and the first electrically conductive metal pattern, the second electrically conductive metal pattern and the capacitive element (4) reduce vibrations caused by any one of the first resonance frequency, the second resonance frequency and the third resonance frequency of the current paths, each of which is present between two elements arbitrarily selected from the two semiconductor devices (3) and the capacitive element (4).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention

[0001] The present disclosure relates to a power module. 2. Description of the state of the art

[0002] Power modules obtained by integrating and modularizing power semiconductor components can be used for power conversion devices and the like. The power semiconductor components include MOSFETs (metal oxide semiconductor field-effect transistors), IGBTs (insulated gate bipolar transistors), diodes, and the like. Oscillations are known to occur when two or more power semiconductor components are connected and operated in parallel.The phenomena associated with the oscillations include: phenomena caused by LC resonance due to the spurious inductance and spurious capacitance of a gate signal line or an emitter signal line; phenomena caused by the difference between switching times at the time of on / off based on the difference in gate threshold voltage between the elements driven in parallel; phenomena caused by a difference in current based on a busbar layout between the elements or a variation between the elements; and the like.

[0003] In addition, phenomena that cause oscillation at a frequency higher than the frequencies of these oscillations include PETT (Plasma Extraction Transit Time Oscillation) and IMPATT (Impact Ionization Avalanche Transit Time Oscillation) (see, for example, Non-Patent Document 1). Fig. Figure 12 is a diagram showing an example of PETT frequency distributions with respect to operating voltage for a bipolar power semiconductor device, where temperature is a parameter based on the expression shown in the figure. The bipolar power semiconductor device refers to an IGBT, a pn junction diode, a reverse conducting IGBT, or the like. Fig. Figure 13 is a diagram showing an example of the distribution of IMPATT frequencies with respect to the operating voltage for a power semiconductor device, where temperature is a parameter based on the expression shown in the figure. The power semiconductor device refers to an IGBT, a MOSFET, a pn junction diode, a Schottky junction diode, a reverse-conducting IGBT, or the like. In the expressions in Fig. 12 and Fig. 13, each numerator indicates a saturation velocity, which depends on the temperatures, types, and physical properties of the semiconductor's charge carriers, and each denominator indicates a depletion layer thickness, which depends on an impurity concentration, voltage, and permittivity of the physical property. In an application with a wide operating voltage and a wide operating temperature range, the frequencies of PETT and IMPATT are widely distributed with respect to the operating voltage and temperature. Fig. 12 and Fig. 13 each show an example indicating the possibility of oscillations occurring. In a case where a power module is formed by coupling an IGBT and a pn junction diode, the frequency distributions of PETT and IMPATT are different from those shown in Fig. 12 and Fig. 13, the distributions are shifted, and the frequencies are more widely distributed because there is a difference in the impurity concentration between the IGBT and the diode. A prerequisite for the occurrence of a local breakdown-limit electric field (local avalanche) in a depletion layer is associated with IMPATT. However, even when the voltage is low, IMPATT falls within an occurrence condition region when the current is high. Meanwhile, even when the current is low, IMPATT falls within the occurrence condition region when the voltage is high. Therefore, the frequencies can still be said to be distributed over a wide range.

[0004] The occurrence of strong vibrations due to PETT and IMPATT may include: a malfunction of a drive circuit due to the transmission of vibrations to a gate signal line or a ground line; destruction of a power semiconductor device due to the induction of vibrations to a gate signal; an LSI malfunction in low-voltage operation that occurs when the vibrations are radiated to be transmitted through a space to a control board equipped with a microcomputer, a power supply IC, a drive circuit for a power semiconductor device, and the like, so that the vibrations are superimposed on a signal or the ground line; or the like. Therefore, in recent years, the demand for suppressing the occurrence of PETT and IMPATT in power modules has increased.In view of this, a method has been disclosed in which PETT is suppressed by correcting layouts of a leadframe and a wire bond so that an LC resonance frequency determined according to the parasitic capacitance of a power semiconductor device and the parasitic inductances of the leadframe and the wire bond does not coincide with a frequency determined according to a time required for holes (positive holes, minority carriers) to pass through a depletion layer when an IGBT or a pn junction diode is turned off (see, for example, Patent Document 1). Fig. Figure 14 is a graph showing an example of the distributions of PETT and LC resonance frequencies in upper-bound and lower-bound designs for a spurious inductor in a case where the leadframe design is corrected.

[0005] Patent document 1: JP 2013- 229 383 A

[0006] Non-Patent Document 1: J. Lutz et al., Semiconductor Power Device, DOI 10.1007 / 978-3-642-11125-9_13, pages 475 to 495

[0007] In Patent Document 1 described above, PETT can only be suppressed within a range based on a partially limited condition as shown in Fig. 14. However, the following problem arises. Although the parasitic capacitance takes a number determined by the specification of a semiconductor device, suppression of vibrations caused by PETT and IMPATT in a design of a module arranged with a power semiconductor device deviating from the frequency distributions of PETT and IMPATT is difficult to solve only by correcting the layouts of the leadframe and wire bonding with respect to the arrangement and configuration of a power semiconductor device determined according to the heat dissipation performance and insulation performance. SUMMARY OF THE INVENTION

[0008] In view of the above, it is an object of the present disclosure to provide a power module in which the vibrations caused by PETT and IMPATT are suppressed.

[0009] A power module according to the present disclosure is a power module comprising: two semiconductor devices, each having an electrode on a one-sided surface and an other-sided surface of the semiconductor device; a flat plate-shaped first electrically conductive metal pattern connected to the electrode on the one-sided surface of each of the two semiconductor devices arranged on a same plane; a flat plate-shaped second electrically conductive metal pattern connected to the electrode on the other surface of each of the two semiconductor devices; and a capacitive element arranged on the same plane between the first electrically conductive metal pattern and the second electrically conductive metal pattern and forming a capacitance between the first electrically conductive metal pattern and the second electrically conductive metal pattern.

[0010] The two semiconductor devices and the capacitive element are located at the vertices of a triangle in the same plane. The first and second electrically conductive metal patterns are each characterized by a flat plate shape with a contour encompassing the three vertices and three sides of the triangle.

[0011] If a shortest connection length path between the two semiconductor devices on the first electrically conductive metal pattern and the second electrically conductive metal pattern is defined as a first shortest path, and a shorter path and a longer path of two shortest connection length paths between the capacitive element and the two respective semiconductor devices on the first electrically conductive metal pattern and the second electrically conductive metal pattern are defined as a second shortest path and a third shortest path, respectively, ((first shortest path)≥(second shortest path) and ((first shortest path) 2 +(second shortest path) 2 )≥(third shortest path) 2 fulfilled.

[0012] If a resonant frequency consisting of two capacitances interfering between the one-sided surfaces and the other-sided surfaces of the two semiconductor components and two inductances generated between the one-sided surfaces and between the other-sided surfaces of the two semiconductor components on the first electrically conductive metal structure and the second electrically conductive metal structure is defined as the first resonant frequency, wherein a resonant frequency consisting of a capacitance generated by the capacitive element and a capacitance interfering between the one-sided surface and the other-sided surface of one of the two semiconductor components and two inductances,which are generated between the capacitive element and the one-sided surface of one of the semiconductor components and between the capacitive element and the other-sided surface of one of the semiconductor components on the first electrically conductive metal pattern and the second electrically conductive metal pattern, is defined as a second resonant frequency, and wherein a resonant frequency which is composed of a capacitance generated by the capacitive element and a capacitance acting interferingly between the one-sided surface and the other-sided surface of another of the two semiconductor components, and two inductances which are generated between the capacitive element and the one-sided surface of the other of the semiconductor components and between the capacitive element and the other-sided surface of the other of the semiconductor components on the first electrically conductive metal pattern and the second electrically conductive metal pattern,is defined as a third resonance frequency, wherein the first electrically conductive metal pattern and the second electrically conductive metal pattern each have a thickness equal to or greater than twice a skin depth through which current flows due to the skin effect generated by the first resonance frequency, the second resonance frequency, and the third resonance frequency of current paths, and wherein the first electrically conductive metal pattern, the second electrically conductive metal pattern, and the capacitive element reduce vibrations caused by any one of the first resonance frequency, the second resonance frequency, and the third resonance frequency of the current paths, each of which is present between two elements arbitrarily selected from the two semiconductor devices and the capacitive element.

[0013] The power module according to the present disclosure is as follows. The two semiconductor devices and the capacitive element are located at the vertices of the triangle between the flat-plate-shaped first electrically conductive metal pattern and the flat-plate-shaped second electrically conductive metal pattern. The electrically conductive metal patterns are shaped to encompass the triangle within their contours.If a shortest connection length path between the two semiconductor devices on the first electrically conductive metal pattern and the second electrically conductive metal pattern is defined as a first shortest path, and a shorter path and a longer path out of two shortest connection length paths between the capacitive element and the two respective semiconductor devices on the first electrically conductive metal pattern and the second electrically conductive metal pattern are respectively defined as a second shortest path and a third shortest path, (first shortest path)≥(second shortest path) and ((first shortest path). 2 +(second shortest path) 2 )≥(third shortest path) 2are met. The first electrically conductive metal pattern and the second electrically conductive metal pattern each have a thickness equal to or greater than twice the skin depth, through which current flows due to the skin effect generated according to the frequency characteristics of the current paths having the first resonant frequency, the second resonant frequency, and the third resonant frequency, respectively obtained from the capacitance(s) and the inductance(s). The capacitance(s) are mutually formed between two elements selected from the three elements that are the capacitive element and the spurious capacitances between the one-side electrodes and the other-side electrodes of the two semiconductor devices. The inductances are derived between the electrodes of the currently selected two elements. The elements are selected in three ways.That is, from the three elements, two elements are selected that are connected to one of the first to third shortest paths. Accordingly, the following advantageous effect is achieved with respect to current vibrations that occur when the semiconductor devices are turned on or off. With respect to vibrations caused by one of the first, second, and third resonant frequencies of the current paths, each of which exists between two elements arbitrarily selected from the two semiconductor devices and the capacitive element, the first electrically conductive metal pattern, the second electrically conductive metal pattern, and the capacitive element prevent the current of the vibrations from being concentrated on a part of the paths on a leadframe 1 and a leadframe 2. Furthermore, the following advantageous effect is achieved with respect to vibration currents caused by PETT and IMPATT, which fall within the same frequency range.For example, the vibration currents are prevented from concentrating on part of the paths at any of the first, second, and third resonance frequencies, which can suppress vibrations caused by PETT and IMPATT. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view schematically showing main parts of a power module according to a first embodiment; Fig. 2 is a perspective view schematically showing main parts of another power module according to the first embodiment; Fig. 3 is a diagram showing an example of the distributions of the frequencies of LC resonance and PETT with respect to the operating voltage in the power module according to the first embodiment; Fig. 4 is a diagram showing an example of the distributions of the frequencies of LC resonance and PETT with respect to the operating voltage in the other power module according to the first embodiment; Fig. 5 is a perspective view schematically showing main parts of a power module according to a third embodiment; Fig. 6A is a perspective view schematically showing main parts of a power module according to a fourth embodiment; Fig. 6B illustrates a radiation frequency; Fig. 7 is a plan view schematically showing main parts of a power module according to a fifth embodiment; Fig. 8 is a plan view schematically showing main parts of a power module according to a sixth embodiment; Fig. 9 is a plan view schematically showing main parts of a power module according to a seventh embodiment; Fig. 10A is a perspective view schematically showing main parts of the power module of a comparative example; Fig. Figure 10B is a diagram showing a circuit consisting of two semiconductor devices in Fig. 10A exists; Fig. 11A is a perspective view schematically showing main parts of the other power module of a comparative example; Fig. 11B is a diagram showing a circuit in Fig. 11A shows; Fig. 12 is a diagram showing an example of distributions of frequencies of PETT with respect to the operating voltage; Fig. 13 is a diagram showing an example of the distribution of frequencies of IMPATT with respect to the operating voltage; and Fig. Figure 14 is a diagram showing an example of distributions of frequencies of LC resonance and PETT at an upper limit and a lower limit of a spurious inductance. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

[0014] Hereinafter, power modules according to embodiments of the present disclosure will be described with reference to the drawings. The description is made by designating the same or corresponding elements and parts in the drawings with the same reference numerals. FIRST EMBODIMENT

[0015] Fig. 1 is a perspective view schematically showing main parts of a power module 100 according to a first embodiment. Fig. 2 is a perspective view schematically showing main parts of another power module 100. Fig. 3 is a graph showing an example of the distributions of the frequencies of LC resonance and PETT with respect to the operating voltage in the power module 100. Fig. 4 is a diagram illustrating an example of the distribution of frequencies of LC resonance and PETT with respect to the operating voltage in another power module 100. Fig. 1 and Fig. 2 are views of the power modules 100 from which the insulating fillers enclosing the semiconductor devices 3 and the like inside have been removed. Each insulating filler is, for example, a mold resin and may be a gel. The gel is arranged around the semiconductor devices and between the devices. The resin is arranged on the outermost side. Each power module 100 is a module that is mounted with two semiconductor devices 3 and constitutes, for example, an inverter circuit in an inverter device. <Leistungsmodul 100>

[0016] As in Fig. 1, the power module 100 includes the two semiconductor devices 3, two capacitive elements 4, a leadframe 1 constituting a first electrically conductive metal pattern, a leadframe 2 constituting a second electrically conductive metal pattern, and leadframes 5. Each semiconductor device 3 has an electrode 6 on one side and an other side surface. The electrode 6 on the one side surface is an upper surface electrode and an N electrode, and the electrode on the other side surface (not shown) is a lower surface electrode and a P electrode. The number of electrodes 6 on each surface is not limited to one, and one electrode 6 may be divided. In the present first embodiment, each electrode 6 is divided into two electrodes 6a and 6b. The two semiconductor devices 3 and the two capacitive elements 4 are arranged on the same plane.The leadframe 1 is in the shape of a flat plate and is connected to the upper surface electrode of each of the two semiconductor devices 3. The leadframe 1 includes terminal areas 1a that are connected to another circuit (not shown). The leadframe 2 is in the shape of a flat plate and is connected to the lower surface electrode of each of the two semiconductor devices 3. The leadframe 1 and the leadframe 2 are made of copper, for example. The leadframe 2 is arranged on a DBC (Direct Bonded Copper) substrate or an insulating resin, which are not shown.

[0017] The two capacitive elements 4 are arranged between leadframe 1 and leadframe 2 and form capacitances between leadframe 1 and leadframe 2. The two semiconductor components 3 and the two capacitive elements 4 are connected in parallel between leadframe 1 and leadframe 2. The two semiconductor components 3 and the two capacitive elements 4 are connected to leadframe 1 and leadframe 2 by solder, an electrically conductive paste, or an electrically conductive adhesive material. Leadframe 1 and leadframe 2 are each connected to the two semiconductor components 3 and the two capacitive elements 4 at the same potential. The leadframes 5 are connected to the semiconductor components 3 via bonding wires (not shown). Each leadframe 5 is a terminal that is connected to the other circuit (not shown) and is supported by the insulation filling.The other circuit connected to the terminal sections 1a and the leadframes 5 is, for example, a drive circuit for controlling the power module 100.

[0018] The two semiconductor components 3 and one or the other of the two capacitive elements 4 are located at the vertices of a triangle in the same plane. When the two semiconductor components 3 are connected and operated in parallel, oscillations occur due to resonances caused by parasitic inductances and parasitic capacitances between the two semiconductor components 3. If the two semiconductor components 3 are of the same type, size, and characteristics, stronger oscillations occur. To suppress the oscillations, the capacitive elements 4 are arranged so that the two semiconductor components 3 and each capacitive element 4 are located at the vertices of a triangle. In the following, the sides on which the two semiconductor components 3 are located are considered to be the sources of the vibrations.However, the side where the capacitive element 4 is present can be considered as a source of vibrations.

[0019] The positions of the vertices of the triangle are arranged as follows. That is, if a shortest connection length path between the two semiconductor devices 3 on the leadframe 1 and the leadframe 2 is defined as a first shortest path, and a shorter path and a longer path of two shortest connection length paths between the capacitive element 4 and the two respective semiconductor devices 3 on the leadframe 1 and the leadframe 2 are defined as a second shortest path and a third shortest path, respectively, the relationships of (first shortest path)≥(second shortest path) and ((first shortest path) 2 +(second shortest path) 2 )≥(third shortest path) 2The first of the expressions is defined as the first expression and the second of the expressions is defined as the second expression. If the two shortest connection length paths between the capacitive element 4 and the two associated semiconductor devices 3 are of equal length, one of the two shortest connection length paths can be defined as the second shortest path or the third shortest path. The distance between the centers of the electrodes on the top or bottom surfaces of two elements is defined as the distance between the elements. If dividing electrodes are present, the center of an electrode resulting from the combination of the dividing electrodes is defined as the center of the electrodes. The intersection points of the dashed lines in Fig. 1 and Fig. 2 are located at the centers of the electrodes. If the shape of an electrode is different between the top and bottom, the distance between the top and bottom is different. In this case, too, the relationships of the first expression and the second expression must be satisfied at both the top and bottom surfaces. If the sides where the semiconductor components 3 are located in Fig. 1 are defined as sources of vibrations, the first expression is (first shortest path 81)≥(second shortest path 91) and the second expression is ((first shortest path 81) 2 +(second shortest path 91) 2 )≥(third shortest path 92) 2 If the sides where the capacitive elements 4 are Fig. 1 are defined as sources of vibrations, the first expression is (first shortest path 82)≥(second shortest path 91) and the second expression is ((first shortest path 82) 2 +(second shortest path 91) 2 )≥(third shortest path 93) 2 If the sides where the semiconductor components 3 are Fig. 2 are present, as the sources of vibrations are defined, the first expression (first shortest path 81)≥(second shortest path 91) and the second expression ((first shortest path 81) 2 +(second shortest path 91) 2 )≥(third shortest path 92) 2 .

[0020] An example in which two capacitive elements 4 are provided is shown in Fig. 1. As shown in Fig. 2, the number of capacitive elements 4 can also be one. In this case, the two semiconductor components 3 and the one capacitive element 4 are located at the vertices of a triangle in the same plane. Each semiconductor component 3 is a power semiconductor component such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The two semiconductor components 3 can be IGBTs or bipolar transistors, and the capacitive elements 4 can be pn junction diodes or Schottky junction diodes. In Fig. 1 and Fig. 2, the semiconductor components 3 are IGBTs and the capacitive elements 4 are pn junction diodes.

[0021] PETT and IMPATT are phenomena in which oscillations occur at relatively high frequencies. PETT and IMPATT also occur in a single power semiconductor device, and when several devices with the same size and characteristics are connected and operated in parallel, particularly strong oscillations can occur due to a slight difference between the switching timings, which is due to a variation in, for example, device thresholds such as gate thresholds Vth. The strong oscillation phenomenon occurs by: the onset of the occurrence of PETT or IMPATT frequencies a shift in the PETT or IMPATT frequency distributions inherent in semiconductor devices and in Fig. 12 or Fig. 13 to cause a phase shift of the same frequency so that an oscillation current inherent in the parallel-connected elements is generated between the elements; and an LC resonance frequency approximating or matching the oscillation current, the LC resonance frequency being due to parasitic inductance on a path through which the oscillation current flows and parasitic capacitances of the parallel-connected elements. The following describes a case where PETT occurs when an IGBT is turned off. The same description may also apply to: a case where PETT occurs at the time of recovery of a pn junction diode; a case where IMPATT occurs when a MOSFET or an IGBT is turned off; and a case where PETT occurs at the time of recovery of a pn junction diode or a Schottky junction diode. <vergleichsbeispiel>

[0022] A comparative example is given with reference to Fig. 10 and Fig. 11 before describing leadframes 1 and 2, which are essential parts of the present disclosure. Fig. 10 shows a power module 200 of a comparative example, Fig. 10A is a perspective view schematically showing main parts of the power module 200, and Fig. 10B is a diagram showing a circuit consisting of two semiconductor devices 3 in Fig. 10A exists. Fig. 11 shows another power module 300 of the comparative example, Fig. 11A is a perspective view schematically showing main parts of the further power module 300, and Fig. 11B is a diagram showing a circuit in Fig. 11A shows. As in Fig. As shown in Figure 10A, a leadframe 201 of the power module 200 is not in the shape of a flat plate, and the connections between the two semiconductor devices 3 and between two capacitive devices 4 are made by bridging portions 202 that have been machined to be thin. There is no direct connection between the semiconductor devices 3 and the capacitive elements 4, which are separated from each other in diagonal directions. As shown in Fig. As shown in Figure 11A, a leadframe 301 of the power module 300 is not in the shape of a flat plate, and a connection between two semiconductor devices 3 is made by a bridging portion 302 that has been processed to be thin. In Fig. 10 and Fig. 11, the semiconductor components 3 are IGBTs, and the capacitive elements 4 are pn junction diodes.

[0023] PETT is considered in terms of the operating range required for products and the wide operating voltage and temperature range. Even if an upper- or lower-boundary design constraint is applied to the leadframe design, it is normal for one or more PETT and IMPATT frequencies intersecting with an LC resonance frequency range from the entire range resulting from the parasitic capacitance and parasitic inductance of a semiconductor device to inevitably exist under a certain voltage and temperature condition. Therefore, the occurrence of PETT and IMPATT cannot be suppressed. Fig. Figure 14 is a graph showing an example of the distribution of PETT and LC resonance frequencies in upper- and lower-boundary boundary designs for spurious inductance in a case where the leadframe design is corrected. Even if both the upper- and lower-boundary boundary designs for spurious inductance are applied to the leadframe design, the occurrence of PETT and IMPATT cannot be suppressed, as shown in Fig. 14 shown.

[0024] In Fig. 10 A, the shortest path of the oscillation current between the parallel-arranged IGBTs is the bridging section 202, which connects the IGBTs to each other. Noise inductances on the leadframe 201 between the parallel-arranged IGBTs are considered based on two paths, namely the bridging section 202 and a path extending across each diode. The noise inductance value is 8.4 nH between the IGBTs alone on the path extending across the diode, and 2.4 nH alone between the IGBTs on the bridging section 202. A noise inductance value between the IGBTs resulting from the combination of the values ​​at the two paths is 1.9 nH, which is approximately the same as the value at the bridging section 202 alone. Strong oscillations occur on a path extending in Fig. 10 is indicated by an arrow, due to a resonance frequency based on the value of the parasitic inductance between the IGBTs, obtained by combining the values ​​on the two paths, and the parasitic capacitances of the IGBTs arranged in parallel. Fig. Figure 3 shows the distribution of LC resonances between the two IGBTs and the distribution of LC resonances between an IGBT and a diode in the comparative example. Strong vibrations occur under the power module condition at the locations where the PETT frequency distributions with respect to the operating voltage and the LC resonance distribution between the IGBTs with respect to the operating voltage overlap. The actual vibration measurements were performed using a near-field probe at the locations indicated by circles in the figure. The observed amplitudes are plotted in the figure so that the actual measured amplitudes are proportional to the diameter of the corresponding circle. No strong vibrations occurred at the locations where the PETT frequency distributions and the LC resonance distribution between the IGBT and the diode intersect.This is because the locations of the intersection points exist in a PETT boundary region of an operating region obtained in a case where the sides where the IGBTs are present are defined as the sources of vibrations.

[0025] In Fig. 11A, the shortest path of the oscillation current between the parallel-arranged IGBTs is the bridging section 302, which connects the IGBTs. Noise inductances on the leadframe 301 between the parallel-arranged IGBTs are considered based on two paths: the bridging section 302 and a path that passes through the diode. The noise inductance between the IGBTs alone on the path through the diode is 4.3 nH, and between the IGBTs alone on the bridging section 302 is 3.0 nH. These values ​​are approximately equal. A noise inductance value between the IGBTs, which is obtained by combining the values ​​of the two paths, is 1.8 nH. A large part of the oscillation current is distributed to the path that passes through the diode, and thus a large part of the oscillation current flows through the shortest path that passes through the diode between the two IGBTs.Strong oscillations occur on paths indicated by dashed arrows in . Fig. 11, due to resonance frequencies based on the value of the parasitic inductance achieved via the diode between the two IGBTs, and parasitic capacitances of the diode and the IGBTs on the shortest paths, which are not between the two IGBTs, but between the diode and the IGBTs. In addition, strong oscillations occur along a path indicated by a solid-line arrow in Fig. 11 due to a resonance frequency based on the value of the parasitic inductance between the parallel IGBTs and the parasitic capacitances of the parallel IGBTs. Fig. Figure 4 shows the distribution of LC resonances between the two IGBTs and the distribution of LC resonances between an IGBT and the diode in the comparative example. Strong vibrations occur under the power module condition at the points where the distributions of the PETT frequencies with respect to the operating voltage and the distribution of LC resonances between the IGBTs with respect to the operating voltage intersect. The actual vibration measurements were performed using a near-field magnetic field probe at the locations indicated by circles in the figure. The observed intensities are plotted in the figure so that the magnitude of each of the actually measured amplitudes is proportional to the diameter of the corresponding circle.

[0026] The possibility of strong oscillations occurring is considered based on two frequencies, namely: a resonant frequency based on a parasitic inductance value on a leadframe between an IGBT and a diode and a parasitic capacitance generated by the diode and the parasitic capacitance of the IGBT; and a resonant frequency based on a parasitic inductance value on the leadframe between the two IGBTs and parasitic capacitances of the two IGBTs. In the Fig. In the comparative example shown in Figure 10, strong oscillations occur due to the resonance between the two IGBTs, as shown in Fig. 3. In the Fig. In the comparative example shown in Figure 11, strong oscillations occur due to the resonance between the IGBT and the diode, as shown in Fig. 4 shown.

[0027] In the Fig. In the comparative example shown in Figure 10A, the bridging portion 202, which is the connecting portion between the IGBTs, is thin, and the current concentrates on the path indicated by the arrow, so that a magnetic dipole is easily formed. In the example shown in Fig. In the comparative example shown in Fig. 11A, the bridging portion 302, which is the connecting portion between the IGBTs, is thin in the same way as in Fig. 10A. The shortest path extending between the IGBTs across the diode appears to have a width. However, in terms of the shortest distance, one side along the outer circumference of a hole formed in the lead frame 301 is the path where the oscillation current is concentrated. Since a concentrated current loop has a certain area, a magnetic dipole is easily formed. When a magnetic dipole is formed, oscillation and strong radiation occur at a resonance point. <Leadframes 1 und 2>

[0028] A power module characterized as follows is obtained. Leadframe 1 and leadframe 2 each have a thickness equal to or greater than twice the skin depth, through which the current flows due to the skin effect generated according to the frequency characteristics of one of the first, second, and third resonant frequencies of the current paths. The first resonant frequency results from the LC series connection between: two capacitances interfering between the one-sided surfaces and the other-sided surfaces of the two semiconductor devices 3; and two inductances generated between the one-sided surfaces and the other-sided surfaces of the two semiconductor devices 3 on leadframe 1 and leadframe 2.The second resonant frequency results from the LC series connection between: a capacitance generated by each capacitive element 4 and a capacitance interfering between the one-sided surface and the other-sided surface of one of the two semiconductor components 3; and two inductances generated between the capacitive element 4 and the one-sided surface of one of the semiconductor components 3 and between the capacitive element 4 and the other-sided surface of one of the semiconductor components 3 on the leadframe 1 and the leadframe 2.The third resonant frequency results from the LC series connection between: a capacitance generated by the capacitive element 4 and a capacitance interfering between the one-sided surface and the other-sided surface of the other of the two semiconductor components 3; and two inductances generated between the capacitive element 4 and the one-sided surface of the other of the semiconductor components 3 and between the capacitive element 4 and the other-sided surface of the other of the semiconductor components 3 on the leadframe 1 and the leadframe 2. In this way, a high-frequency current flow through the leadframe 1 and the leadframe 2 can be easily induced.In addition, the leadframe 1, the leadframe 2, and the capacitive element 4 suppress vibrations caused by one of the first, second, and third resonant frequencies of the current paths, each of which is present between two elements arbitrarily selected from the two semiconductor devices 3 and the capacitive element 4. In a case where the leadframe 1 and the leadframe 2 are made of copper and the current flowing through the leadframe 1 and the leadframe 2 is assumed to be a current with a high frequency of 150 MHz, the leadframe 1 and the leadframe 2 each have a thickness of, for example, 32 µm. This value can be realized, for example, by using a tape made of copper with a thickness of 35 µm for the leadframe 1 or the leadframe 2; or by ensuring a copper pattern with a thickness of 35 µm on a printed circuit board as the leadframe 2.

[0029] In a case where the IGBTs, which are semiconductor devices 3, and the diodes, which are capacitive elements 4, are connected to each other by the flat-plate leadframe 1 and the flat-plate leadframe 2, the inductances can be reduced. However, since there are areas where the frequency distributions of the PETT and LC resonances between the elements overlap when analyzing the spurious inductance, there is a possibility that oscillation phenomena may occur, especially in the overlapping areas. Fig. 3 shows the distribution of the LC resonances between the two IGBTs in the Fig. 1 shown power module 100. Fig. 4 shows the distribution of the LC resonances between the two IGBTs and the distribution of the LC resonances between the IGBT and the diode in the other power module 100 of Fig. 2. Each LC resonance overlaps with the frequency distributions of the PETTs, and thus there is a possibility of oscillations occurring.

[0030] If the vibrations in the inductance values ​​are considered with respect to the entire set of paths, the oscillation current paths are scattered from the shortest path between the IGBTs to the path extending across each diode. Consequently, a dynamic distribution in terms of current density results, and oscillation currents between the IGBTs and oscillation currents between the IGBTs and the diode coexist. Vibrations between the IGBTs are exerted in a direction in which the vibrations are absorbed by the parasitic capacitance of the diode. Meanwhile, vibrations between an IGBT and the diode are exerted in a direction in which the vibrations are absorbed on one side, where the parasitic capacitance of the other IGBT is formed. Thus, the vibrations are suppressed.Furthermore, when a voltage difference exists between the electrodes of each of the designated elements, the current flows along the shortest path and is directed in directions that cancel the vibrations. Consequently, the current is directed in directions that suppress both the vibrations between the IGBTs and the vibrations between the IGBTs and the diode. If the value of the parasitic inductance between the IGBTs and the value of the parasitic inductance between each IGBT and the diode are caused to approach each other, the oscillation current between the IGBT and the diode and the oscillation current between IGBTs with different resonance points will interfere with each other, thereby suppressing vibrations.

[0031] If leadframe 1 and leadframe 2 are in the form of flat plates, and the shortest path between the IGBTs and the shortest paths extending between the IGBTs via the diodes are embedded in the flat plates, a parasitic inductance value between the IGBTs and parasitic inductance values ​​arising between the IGBTs via the diodes can be made to approach each other. A first condition is that: the IGBTs and each diode are arranged at the vertices of a triangle such that no diode is included on the shortest path between the IGBTs; and a parasitic inductance between one of the IGBTs and one of the diodes, or between another of the IGBTs and the one of the diodes on the path extending between the IGBTs via the diode, is equal to or lower than a parasitic inductance on the shortest path between the IGBTs.A second condition is that in each of the shortest paths between the IGBTs and the path extending between the IGBTs via the diode, there is no point where the oscillation current is concentrated when the oscillation current flows through the shortest path. If these conditions are met, the vibrations caused by PETT and IMPATT can be suppressed.

[0032] In the Fig. In the comparative example shown in Figure 10, the value of the noise inductance between the IGBTs on the path extending across each diode is 8.4 nH and between the IGBTs at the bypass section 202 is 2.4 nH. In the power module 100 in Fig. 1, the parasitic inductance value is reduced to 3.1 nH between the IGBTs on the path extending across each diode and to 1.4 nH between the IGBTs. By reducing the parasitic inductance values, the difference in inductance value between the paths is reduced and the oscillation current is dissipated. If, with respect to one of the IGBTs, there is an inductance on the shortest path to another of the IGBTs and an inductance on the path extending across each diode, and the inductance value between the IGBT and the diode is equal to or less than the inductance value on the path to the other of the IGBTs, the oscillation current is dissipated to the path extending across the diode while the first condition is satisfied.Furthermore, if leadframe 1 and leadframe 2 are in the form of flat plates and the IGBTs and diodes are connected together, there is no point where the oscillation current is locally concentrated. Consequently, the oscillation current between the IGBTs and the oscillation current between the IGBTs and the diodes interfere with each other and are dissipated, while the second condition is met. Thus, oscillations at both LC resonance frequencies are suppressed.

[0033] To avoid resonance, it is desirable that the capacitances of the diodes be separated from the parasitic capacitances of the IGBTs. However, even if the capacitances of the diodes and the parasitic capacitances of the IGBTs are not separated from each other, the present disclosure can be implemented unless these elements are of the same type and have the same characteristics. The reason for this is as follows. That is, the parasitic capacitances change depending on the voltage and temperature, and there is also a manufacturing variation. Thus, if the diodes operated in parallel are not of the same type with the same characteristics, the diodes do not have the same characteristics as those of the IGBTs when the voltage or temperature changes, resulting in a mismatch between the characteristics of the IGBTs and the diodes.

[0034] The first condition that causes the noise inductance value between the IGBTs and the noise inductance value between each IGBT and each diode to approach each other has been described. If the IGBTs and the diode are located at the vertices of the triangle, and the shortest path between the IGBTs and the shortest path between the IGBT and the diode are embedded in the flat-plate-shaped leadframe 1 and leadframe 2, the first condition regarding noise inductances can be reformulated as a magnitude relationship between three distances, which are: the shortest distance between the centers of the electrodes of the IGBTs; the shortest distance between the centers of one of the IGBTs and the diode; and the shortest distance between the centers of another of the IGBTs and the diode. The magnitude relationship corresponds to the relationships of the first expression and the second expression described above.

[0035] If the distance relationship expressed by the first expression is satisfied, it can be said that the parasitic inductance between the diode and an IGBT defined as closer to the diode is smaller than the parasitic inductance at the shortest distance between the IGBTs. If the first expression is satisfied, the oscillation current is easily dissipated and flows easily.If the distance relationships expressed by the first expression and the second expression are satisfied, a smaller one of the angles formed at the intersection point between a line segment formed by the shortest path between one of the IGBTs and the diode and a line segment formed by the shortest path between the IGBTs is equal to or less than 90 degrees, and a smaller one of the angles formed at the intersection point between a line segment formed by the shortest path between another of the IGBTs and the diode and the line segment formed by the shortest path between the IGBTs is also equal to or less than 90 degrees.If the first and second expressions are satisfied, a path of the oscillation current from each IGBT toward the diode side experiences a stress in such a direction upon a dynamic voltage change from the IGBT to the diode that the oscillation current flows toward the diode from one of the IGBTs, but strays toward another of the IGBTs along the way. This better disperses the path of the oscillation current. The angle of 90 degrees is obtained from the comparative example. If the shortest paths are considered to be lines connecting the centers of the electrodes defined above, there may be a case where an angle formed by two line segments may exceed 90 degrees due to a design limitation for thermal bonding and wire bonding depending on the size of an IGBT chip or the size of a diode.However, when extension lines are drawn from the outermost sides of a chip end and a device end, the resulting angle only needs to be within 90 degrees in the mutual arrangement relationship between the elements.

[0036] In the Fig. In the comparative example shown in Figure 10, the noise inductance value is 1.9 nH between the IGBTs, and if the paths through the diodes are considered individually, it is 0.7 nH between each IGBT and each diode. In an analysis in which the bridging section 202, which represents the shortest path between the IGBTs, is eliminated, the inductance created across the diode between the IGBTs is 8.4 nH. Meanwhile, the noise inductance value in the power module 100 in Fig. 1 between the IGBTs is 1.2 nH if the values ​​along all paths are combined. However, if we mentally take only the shortest path between the IGBTs given the size and width of each of the IGBT electrodes and cut the path apart on the diode side, the noise inductance value is 1.4 nH along the path between the IGBTs that has been cut out and made into a flat plate. The noise inductance value between one of the IGBTs and a closer diode is 0.7 nH, and the noise inductance value between one of the IGBTs and a more distant diode is 2.3 nH. Since the two paths are formed relative to the closer and more distant diodes, adding the values ​​along both paths results in a noise inductance value of 3.0 nH. An actual parasitic inductance without the shortest path between the IGBTs is 3.1 nH, and thus it is known that the number of bypass paths is not one, but two.

[0037] In the Fig. In the comparative example shown in Figure 11, in which the number of diodes is one, the noise inductance value is 1.8 nH between the IGBTs, 0.9 nH between one of the IGBTs and the diode, and 0.9 nH between another of the IGBTs and the diode. The noise inductance value is 0.9 nH between one of the IGBTs and the diode, ie, equal distribution is performed. In the other power module 100 in Fig. 2, the noise inductance value is 1.1 nH between the IGBTs, 0.8 nH between one of the IGBTs and the diode, and 0.8 nH between another of the IGBTs and the diode. The noise inductance value resulting from the combination of both values ​​between the IGBTs and the diode is 1.6 nH, which is approximately equivalent to 1.1 nH between the IGBTs. Since the flat-plate leadframe 1 is provided and the path where the oscillation current is concentrated is eliminated, oscillations are suppressed.

[0038] The configuration of the power module 100 described above achieves the following advantageous effects. Since the inductance between one of the IGBTs and each diode is smaller than the inductance at the shortest path between the IGBTs, operation occurs in which approximately half of an oscillating current between the IGBTs flows into a path between the one of the IGBTs and the diode. The current flows across the diode and then branches along two types of paths into a current flowing to the side where another of the IGBTs is located and a current returning to the side where the one of the IGBTs is located. There is a first shortest path between the IGBTs and a second shortest path, which extends across the diode, between the IGBTs.Even if the oscillation current between the IGBTs amplifies the vibrations along with LC resonance caused by parasitic inductances and capacitances between the IGBTs, a larger difference between the IGBT electrode voltages and the diode electrode voltage will result in more current flowing to the diode side. Furthermore, since the IGBTs and the diode are connected by the flat-plate leadframes 1 and 2, current flow is ensured from the surfaces of the leadframes, except for the areas between the electrodes. This can suppress the flow of resonance current.

[0039] The above-described beneficial effects are described using numerical values ​​of interference inductances. In the Fig. In the comparative example shown in Figure 10A, the noise inductance value between each IGBT and each diode is 0.7 nH, which is smaller than 1.9 nH between the IGBTs. However, a continuity through the path of the bridging section 202 between the diodes must be made to form a second path. Therefore, a noise inductance value obtained across each diode between the IGBTs is as large as 8.4 nH, and a noise inductance value obtained by summing the values ​​at the two paths is 3.7 nH. The oscillation current concentrates on the bridging section 202, which is the shortest between the IGBTs, to cause oscillation, forming a current loop and causing radiation. In the power module 100 in Fig. 1, the noise inductance between the IGBTs is 1.2 nH, the total value resulting from adding a noise inductance between the IGBTs across one of the diodes is 3.0 nH, and the total value resulting from adding a noise inductance between the IGBTs across another of the diodes is 3.0 nH. Since the paths extending across the two diodes are formed, vibrations can be suppressed without causing oscillation current to concentrate.

[0040] In the Fig. In the comparative example shown in FIG. 11A, the bridging portion 302 between the IGBTs is slightly shifted from the centers of the electrodes. Thus, in an analysis with only the bridging portion 302, the noise inductance value between the IGBTs is 3.0 nH, and in a case where the bridging portion 302 between the IGBTs is eliminated, the noise inductance value obtained via the diode is 4.3 nH. In this way, both noise inductance values ​​approach each other. Thus, the oscillation current is distributed to both paths. In addition, the current is concentrated on the thin bridging portion 302 between the IGBTs, and on the side where the path extends via the diode, the innermost peripheral side of a central part of the lead frame 301 has the shortest distance, so the oscillation current is concentrated on the innermost peripheral side.A noise inductance value obtained by combining the values ​​on all paths between the IGBTs is 1.8 nH, and the noise inductance value between each IGBT and the diode is 0.9 nH, and oscillations occur on both paths. For the other power module 100 in . Fig. 2, the noise inductance value between the IGBTs is 1.1 nH and between each IGBT and the diode is 0.8 nH. In this way, both values ​​approach each other. As a result, the oscillation current branches off; there is no path for the oscillation current to concentrate, and a current with a voltage difference flows between the electrodes of the diode and the two IGBTs, which can suppress oscillations. In the sense of evenly dividing an inductance into values ​​and approximating the values ​​to each other, there is no significant difference between the Fig. 11 and the other power module 100. However, the bridging portion 302, on which the oscillation current is concentrated and which exists between the IGBTs, and the shortest path, on which the oscillation current is concentrated, which exists on one side along the outer circumference of the hole formed in the lead frame 301, are eliminated from the comparative example by closing the hole in the lead frame 301, and the current can flow through each path upon a voltage change between each IGBT and the diode. As a result, the oscillation current is more widely distributed, and vibration can be suppressed.

[0041] In Fig. 3, the distribution of the LC resonances between the two IGBTs in the power module 100 overlaps with the frequency distributions of the PETT. In Fig. 4, the distribution of LC resonances between the two IGBTs and the distribution of LC resonances between the IGBT and the diode in the other power module 100 intersect with the PETT frequency distributions. Although the possibility of oscillations occurring at the intersection points was predicted, no oscillations detectable with a near-field magnetic field probe occurred at the intersection points. This is because the oscillation current is not concentrated in both power modules 100, thus suppressing oscillations.

[0042] In the above description, the two IGBTs were considered as the sources of the vibrations. However, the same description can also apply in the case where the parallel-connected sources of the vibrations are instead on the diode side. In the Fig. In the comparative example shown in Figure 10A, the noise inductance value between the diodes is 2.9 nH, and the noise inductance value resulting between the diodes across each IGBT when the bypass portion 202 is eliminated is 8.6 nH. Since there is a difference between the two noise inductance values, an oscillation current flows to the bypass portion 202 between the diodes, and oscillation occurs at the time of the diode regenerative operations. In the power module 100 in Fig. 1, the noise inductance between the diodes is 2.3 nH, and the noise inductance between the diodes across each IGBT is 3.7 nH. As the difference between the two noise inductances decreases, and the noise inductance between each IGBT and each diode is only 0.7 nH, the oscillation current flows between the diodes across the IGBT, which can also suppress oscillations on the diode side.

[0043] The leadframe 1 is designed in the form of a flat plate. As shown in Fig. 1 and Fig. As shown in Figure 2, the lead frame 1 has through holes 1b at locations corresponding to the locations between the IGBTs and the diodes. Each power module 100 includes an insulating filler, such as a gel or a mold resin, that encloses the semiconductor devices 3 and the like inside the power module 100 to ensure the insulating performance of the power module 100. Depending on the viscosity of the insulating filler at the time of filling, a portion between the lead frame 1 and the lead frame 2 may not be filled with the insulating filler, and large and small voids may be formed, thereby failing to achieve the insulating performance of the power module 100. By forming the through holes 1b in the lead frame 1 according to the viscosity of the insulating filler at the time of filling, the portion between the lead frame 1 and the lead frame 2 can be filled with the insulating filler up to every corner.

[0044] As described above, in each power module 100 according to the first embodiment, the two semiconductor components 3 and each capacitive element 4 are located at the vertices of a triangle between the flat-plate-shaped leadframe 1 and the flat-plate-shaped leadframe 2. If a shortest connection length path between the two semiconductor components 3 on the leadframe 1 and the leadframe 2 is defined as a first shortest path, and a shorter path and a longer path of two shortest connection length paths between the capacitive element 4 and the two respective semiconductor components 3 on the leadframe 1 and the leadframe 2 are defined as a second shortest path and a third shortest path, respectively, (first shortest path)≥(second shortest path) and ((first shortest path) 2 +(second shortest path) 2 )≥(third shortest path) 2 are met. The leadframe 1 and the leadframe 2 each have a thickness equal to or greater than twice the skin depth through which the current flows due to the skin effect, according to the frequency characteristics of the current paths with: the first resonant frequency resulting from capacitances and inductances between the two semiconductor devices 3; the second resonant frequency resulting from a capacitance and inductances between one of the two semiconductor devices 3 and one of the capacitive elements 4; and the third resonant frequency resulting from a capacitance and inductances between another of the two semiconductor devices 3 and the one of the capacitive elements 4. Accordingly, oscillation currents caused by PETT and IMPATT are prevented from being concentrated on part of the paths on the leadframe 1 and the leadframe 2, whereby vibrations caused by PETT and IMPATT can be suppressed.

[0045] Furthermore, since vibrations caused by PETT and IMPATT are suppressed, malfunction of the drive circuit for driving the power module 100 and breakage of the semiconductor devices 3 due to the induction of gate vibrations can be prevented. Even in a case where IGBTs or bipolar transistors are used as the two semiconductor devices 3 and pn junction diodes or Schottky junction diodes are used as the capacitive elements 4, oscillation currents caused by PETT and IMPATT are not concentrated on part of the paths on the lead frame 1 and the lead frame 2, thereby suppressing vibrations caused by PETT and IMPATT. SECOND EMBODIMENT

[0046] A power module 100 according to a second embodiment is described. The power module 100 according to the second embodiment comprises power semiconductor components 3, each of which has a depletion layer formed therein.

[0047] The two in Fig. 1 or Fig. The power semiconductor components 3 of the power module 100 shown in FIG. 2 are configured as two power semiconductor components 3, each of which has a depletion layer formed at the time of turn-off or at the time of switching from forward bias to reverse bias. A frequency determined according to a movement and discharge time required for majority-side charge carriers to traverse the depletion layer inside each power semiconductor component due to the occurrence of a local breakdown-limit electric field inside the power semiconductor component at the time of turn-off or at the time of switching off is defined as a first natural frequency.A frequency determined according to a movement and discharge time required for minority carriers to pass through the depletion layer within the power semiconductor device of a bipolar type at the time of turn-off or at the time of turn-off is defined as a second natural frequency.

[0048] Each of the two power semiconductor devices connected in parallel is a power semiconductor device exhibiting only the first natural frequency, or a power semiconductor device exhibiting both the first natural frequency and the second natural frequency. When the two power semiconductor devices are driven, the frequencies of the first natural frequency and the second natural frequency are distributed over a wide range depending on the voltage and temperature conditions.In a case where the first natural frequency of vibration includes a frequency that matches any one of the first resonance frequency, the second resonance frequency, and the third resonance frequency described in the first embodiment, or in a case where the second natural frequency of vibration includes a frequency that matches any one of the first resonance frequency, the second resonance frequency, and the third resonance frequency described in the first embodiment, if the power module 100 has the configuration described in the first embodiment, oscillation currents caused by PETT and IMPATT are prevented from being concentrated on a part of the paths on the leadframe 1 and the leadframe 2, whereby oscillations caused by PETT and IMPATT can be suppressed.That is, with the two power semiconductor devices each having the depletion layer formed therein, vibrations caused by PETT and IMPATT can be suppressed even if the first resonance frequency, the second resonance frequency, and the third resonance frequency are included in a frequency range in which the first natural vibration number and the second natural vibration number are distributed.

[0049] As described above, the power module 100 according to the second embodiment includes the two power semiconductor devices 3 each having the depletion layer formed therein. Each of the two power semiconductor devices is a power semiconductor device having only the first natural frequency or a power semiconductor device having both the first natural frequency and the second natural frequency. The first resonance frequency, the second resonance frequency, and the third resonance frequency are included in the frequency range in which the first natural frequency and the second natural frequency are distributed. Thus, vibrations caused by PETT and IMPATT can be suppressed even in the two power semiconductor devices 3 each having the depletion layer formed therein. THIRD EMBODIMENT

[0050] A power module 100 according to a third embodiment is described. Fig. 5 is a perspective view schematically showing essential parts of the power module 100 according to the third embodiment. The power module 100 according to the third embodiment includes semiconductor devices 3 and capacitive elements 4 that are different from those described in the first embodiment.

[0051] In Fig. 5, each of the two semiconductor components 3 is a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor in reverse bias. Each capacitive element 4 is a capacitor arranged between the plate-shaped leadframe 1 and the plate-shaped leadframe 2 and formed from an insulating filler. The insulating filler can be an air space, a resin material, or a gel material, as long as the insulating filler has a uniform permittivity.

[0052] An example in which two capacitive elements 4 are provided is shown in Fig. 5. However, the number of capacitive elements 4 may also be one or three or more. In either case, the two semiconductor devices 3 and one capacitive element 4 are located at the vertices of a triangle in the same plane. The leadframe 1 has an area of ​​l×w, where "l" represents a lateral width and "w" represents a longitudinal width. The leadframe 1 is arranged to cover the centers of the semiconductor devices 3 and the capacitive elements 4. The centers of the semiconductor devices 3 and the capacitive elements 4 are located at the intersection points of the dashed lines shown in the drawing. Each of the one-sided surfaces and the other-sided surfaces of the semiconductor devices 3 and the capacitive elements 4 includes an electrode (not shown).

[0053] The distances between the centers of the elements are described as follows. As in Fig. As shown in Figure 5, the distance between the semiconductor components 3 is denoted by (le11-12), the distance between one of the semiconductor components 3 and one of the capacitive elements 4 is denoted by (le11-21), the distance between one of the semiconductor components 3 and another of the capacitive elements 4 is denoted by (le11-22), the distance between another of the semiconductor components 3 and one of the capacitive elements 4 is denoted by (le12-21), and the distance between the other of the semiconductor components 3 and the other of the capacitive elements 4 is denoted by (le12-22). If the distances (le11-12)≥(le11-21) and ((le11-12) 2 +(le11-21) 2 )≥(le12-21) 2 satisfy or (le11-12)≥(le12-22) and ((le11-12) 2 +(le12-22) 2 )≥(le11-22) 2 vibrations caused by PETT and IMPATT can be suppressed.

[0054] As described above, in the power module 100 according to the third embodiment, each of the two semiconductor devices 3 is a metal oxide semiconductor field-effect transistor or an insulated gate bipolar transistor in reverse bias, and each capacitive element 4 is a capacitor arranged between the lead frame 1 and the lead frame 2 and formed of the insulation filler. In this case, too, oscillation currents caused by PETT and IMPATT are prevented from concentrating on a part of the paths on the lead frame 1 and the lead frame 2, thereby suppressing vibrations caused by PETT and IMPATT. FOURTH EMBODIMENT

[0055] A power module 100 according to a fourth embodiment is described. Fig. 6A is a perspective view schematically showing essential parts of the power module 100 according to the fourth embodiment. In the power module 100 according to the fourth embodiment, the lead frame 1 functions as a flat plate antenna.

[0056] The leadframe 1 has the function of a flat antenna 11, with the leadframe 2 acting as a ground when the voltage of each of the two semiconductor components 3 or the capacitive element 4 of the power module 100 changes. Fig. Figure 6A shows the power module 100, in which an insulating dielectric 13 corresponding to the capacitive element 4 is arranged between the flat antenna 11 corresponding to the leadframe 1 and a ground 12 corresponding to the leadframe 2. A feed point for the flat antenna 11 is located, for example, at the Fig. The black circle shown in Figure 6A. Fig. 6B shows a radiation frequency from a patch antenna which is the flat antenna 11. Regarding the radiation frequency of a radio wave radiated from the patch antenna, which is determined by the Fig. 6B show a voltage distribution and a current distribution respectively indicated by a solid line and a dashed line in Fig. 6B, fundamental waves. In this expression, c0 represents the speed of light, ε r for the dielectric constant and L e for the length of one long side of the patch antenna. In Fig. 6B, the ground circuit board corresponds to the leadframe 2 in Fig. 6A, and the radiating element corresponds to the leadframe 1 in Fig. 6A. If the radiation frequency, expressed by the Fig. 6B is higher than the first resonance frequency, the second resonance frequency, and the third resonance frequency described in the first embodiment, that is, if the radiation frequency is high without overlapping with the distributions of the frequencies of PETT and IMPATT, resonance between the leadframe 1 and the radiation frequency can be avoided.

[0057] As described above, in the power module 100 according to the fourth embodiment, the leadframe 1 functions as a flat antenna 11, with the leadframe 2 functioning as a ground, upon a change in the voltage of each of the two semiconductor devices 3 or the capacitive element 4 of the power module 100. The radiation frequency of the radio wave generated by the Fig. 6B and characteristic of the flat antenna 11 is higher than the first resonance frequency, the second resonance frequency, and the third resonance frequency. Thus, it is possible to avoid resonance between the lead frame 1 and the radiation frequency and suppress energy radiation to the radiation side as the flat antenna 11. FIFTH EMBODIMENT

[0058] A power module 100 according to a fifth embodiment is described. Fig. 7 is a plan view schematically showing essential parts of the power module 100 according to the fifth embodiment. The power module 100 according to the fifth embodiment includes three semiconductor devices 3.

[0059] As in Fig. 7, the power module 100 includes three semiconductor devices 3a, 3b, and 3c, a capacitive element 4, the flat-plate-shaped leadframe 1, and the flat-plate-shaped leadframe 2. Regarding the leadframe 1, only its outline is indicated by a dashed line. Although three semiconductor devices 3a, 3b, and 3c are provided here, their number is not limited to three, and n (where "n" represents an integer not less than 3) semiconductor devices 3 may be provided. The capacitive element 4 and two adjacent semiconductor devices 3 selected from the three semiconductor devices 3 are located at the vertices of a triangle on the same plane.

[0060] The positions of the vertices of the triangle are arranged as follows. That is, if a shortest connection length path between the two adjacent semiconductor devices 3 on the leadframe 1 and the leadframe 2 is defined as a first shortest path, and a shorter path and a longer path consisting of two shortest connection length paths between the capacitive element 4 and the two adjacent semiconductor devices 3 on the leadframe 1 and the leadframe 2 are defined as a second shortest path and a third shortest path, respectively, the relationships of (first shortest path)≥(second shortest path) and ((first shortest path) 2 +(second shortest path) 2 )≥(third shortest path) 2 The first of the expressions is defined as the first expression and the second of the expressions is defined as the second expression. If the two adjacent semiconductor devices 3 in Fig. 7 are defined as semiconductor devices 3a and 3b, the first expression is (first shortest path 81)≥(second shortest path 91), and the second expression is ((first shortest path 81) 2 +(second shortest path 91) 2 )≥(third shortest path 92) 2 .

[0061] The leadframe 1 and the leadframe 2 each have a thickness equal to or greater than twice the skin depth through which current flows due to the skin effect generated according to the frequency characteristics of current paths including: a first resonant frequency obtained from capacitances and inductances between the two adjacent semiconductor devices 3; a second resonant frequency obtained from a capacitance and inductances between the capacitive element 4 and one of the two adjacent semiconductor devices 3; and a third resonant frequency obtained from a capacitance and inductances between the capacitive element 4 and another of the two adjacent semiconductor devices 3.

[0062] As described above, in the power module 100 according to the fifth embodiment, the capacitive element 4 and two adjacent semiconductor devices 3 selected from the three semiconductor devices 3 are located at the vertices of the triangle between the flat-plate-shaped leadframe 1 and the flat-plate-shaped leadframe 2. The relationships of the first expression and the second expression are satisfied. The leadframe 1 and the leadframe 2 each have a thickness equal to or greater than twice the skin depth through which current flows due to the skin effect. With these features, oscillation currents caused by PETT and IMPATT are prevented from being concentrated on part of the paths on the leadframe 1 and the leadframe 2, thereby making it possible to suppress vibrations caused by PETT and IMPATT. SIXTH EMBODIMENT

[0063] A power module 100 according to a sixth embodiment is described. Fig. 8 is a plan view schematically showing essential parts of the power module 100 according to the sixth embodiment. In the power module 100 according to the sixth embodiment, one or both of the plate-shaped lead frames 1 and 2 each have through holes 7.

[0064] Two semiconductor devices 3 and a capacitive element 4 are arranged at the apices of a triangle on the same plane. As shown in Fig. 8, both the leadframe 1 and the leadframe 2 each have two or more through-holes 7 on a downward perpendicular 14 to a shortest path 15, which represents the shortest connection path between the two semiconductor components 3, from the point at which the capacitive element 4 is connected to the leadframe 1 or the leadframe 2. Fig. 8 shows an example in which the leadframe 1 has two through-holes 7. By forming the two through-holes 7, a bypass path 17 is created. Thus, the paths of the oscillation current flowing between the semiconductor devices 3 are not limited to two paths, including a first path, which is the shortest path 15 between the semiconductor devices 3, and a second path, which is a via-capacitance path 16 passing through the capacitive element 4. Through the bypass path 17, the oscillation current is dispersed without being concentrated on the first path or the second path. The vibration suppression effect can be improved by increasing the number of through-holes 7 or by reducing the areas of the through-holes 7.It should be noted that if an insulating filling is provided, the through holes 7 also serve to fill the section between the leadframe 1 and the leadframe 2 with the insulating filling.

[0065] As described above, in the power module 100 according to the sixth embodiment, the leadframe 1 and the leadframe 2, or both of them, each have the two or more through-holes 7 on the perpendicular 14 drawn downward from the point where the capacitive element 4 is connected to the leadframe 1 or the leadframe 2 to the shortest path between two semiconductor devices 3. Thus, the bypass path 17 to the leadframes with the through-holes 7 is provided. Consequently, oscillation currents caused by PETT and IMPATT are prevented from being concentrated on a part of the paths on the leadframes with the through-holes 7, whereby vibrations caused by PETT and IMPATT can be suppressed. SEVENTH EMBODIMENT

[0066] A power module 100 according to a seventh embodiment is described. Fig. 9 is a plan view schematically showing essential parts of the power module 100 according to the seventh embodiment. The power module 100 according to the seventh embodiment includes a through hole 8 having a specific size.

[0067] Each of the two semiconductor components 3 and the capacitive element 4, which are arranged at the vertices of a triangle, has a rectangular shape. The capacitive element 4 is arranged such that one long side thereof is opposite a long side of each of the two semiconductor components 3. Both the leadframe 1 and the leadframe 2 each have the through-hole 8 between the capacitive element 4 and the two semiconductor components 3. Fig. 9 shows an example in which the leadframe 1 has the through hole 8.

[0068] A value obtained by subtracting a hole width 26 from a bypass path width 23 is equal to or greater than 1 / 2 the length of a short side of the capacitive element 4, where: the bypass path width 23 is the length of a portion of a perpendicular 22 from an outer periphery of the capacitive element 4 to a line segment 21 connecting a corner of a semiconductor device 3a closest to the capacitive element 4 of the two semiconductor devices 3 to a corner that is one end of a long side facing the capacitive element 4 of another semiconductor device 3b farther from the capacitive element 4, the perpendicular 22 being drawn downward onto the line segment 21 from the center of the point where the capacitive element 4 is connected to the leadframe 1 or the leadframe 2;and the hole width 26 is the distance between two perpendiculars 24 and 25 drawn downwards to the perpendicular 22 from circumferential portions of the through-hole 8 which are furthest apart from each other in a direction of the perpendicular;

[0069] The value resulting from subtracting the hole width 26 from the width of the bypass path 23 is a bypass clearance width 27 that allows the flow of the oscillation current. Oscillation currents flowing between the two semiconductor components 3, if not via a shortest path 28 between the two semiconductor components 3, pass through a via-capacitance path 29 running via the capacitive element 4 and a bypass path 30 running via the bypass clearance width 27. Not all oscillation currents flowing in the direction from the semiconductor components 3 to the capacitive element 4 converge toward the capacitive element 4, and an oscillation current passes through the bypass path 30. Thus, the oscillation currents are scattered, and vibrations can be further suppressed.

[0070] The feature of setting the bypass release width 27 equal to or larger than half the length of the short side of the capacitive element 4 will be described. The description will be made here using an example in which IGBTs are used as the semiconductor devices 3 and a diode as the capacitive element 4. In a case where the power module 100 is mounted with the capacitive element 4 having only the function of the diode, the width of the lead frame 1 only needs to be the width of a short side of the diode and need not be larger than that. Also, if the current flowing to the IGBTs coupled together is considered in view of an originally intended function, namely commutation at the time of turn-off of the IGBTs, the design is made such that at most the width of the short side of the diode is directly adopted as the width of the lead frame 1 to prevent current from leaking from the electrode of the diode.

[0071] Here, the fact that the value obtained by subtracting the hole width 26 from the width of the bypass path 23 is equal to or greater than zero means that there is a use other than commutation at the time of IGBT turn-off. In practice, this results in a disadvantage in terms of machining accuracy, and therefore, a margin of several millimeters is considered for a final shape. The fact that in the final shape, the said value is half the length of the short side of the capacitive element 4 means that, in addition to allowing current to flow to a location between the IGBTs, there is also a path leading to a location between each IGBT and the diode. This leads to the conclusion that when considering a diode that has no other function than commutation at the time of IGBT turn-off, the sole purpose is to suppress noise caused by vibrations.

[0072] In the Fig. In the comparative example shown in Figure 11A, the value obtained by subtracting the hole width from the bypass path width is zero. In this case, a path where the oscillation current is concentrated exists along the outer circumference of the hole. The oscillation current is a current that has fluctuated due to a parasitic capacitance between an IGBT and the diode. If the bypass release width 27 is set equal to or larger than half the length of the short side of the capacitive element 4, the oscillation current can flow through the bypass path 30, which is separated from the via capacitance path 29 and the shortest path 28. This can contribute to vibration suppression.

[0073] As described above, in the power module 100 according to the seventh embodiment, the leadframe 1 and the leadframe 2 each have the through-hole 8 between the capacitive element 4 and the two semiconductor devices 3. A value obtained by subtracting a distance from a length is equal to or greater than 1 / 2 of a length of a short side of the capacitive element 4, where: the length from which the distance is subtracted is a length of a portion of a perpendicular 22 from an outer periphery of the capacitive element 4 to a line segment 21 connecting a corner of a semiconductor device 3a closest to the capacitive element 4 of the two semiconductor devices 3 closest to the capacitive element 4 with a corner that is one end of a long side of another semiconductor device 3b facing the capacitive element 4 that is farther away from the capacitive element 4,wherein the perpendicular 22 is drawn downward from a center of a location where the capacitive element 4 is connected to the leadframe 1 or the leadframe 2 to the line segment; and the distance is a distance between two perpendiculars 24 and 25 drawn downward from peripheral portions of the through-hole 8 that are farthest apart from each other in a direction of the perpendicular to the perpendicular 22. Thus, an oscillation current can flow through the bypass path 30, which is separated from the through-capacitance path 29 and the shortest path 28. Consequently, oscillation currents can be scattered, thereby suppressing vibrations caused by PETT and IMPATT.

[0074] It should be understood that the various features, aspects, and functions described in one or more of the individual embodiments may be applied alone or in various combinations to one or more of the embodiments of the disclosure, depending on their applicability to the particular embodiment with which they are described. DESCRIPTION OF REFERENCE SYMBOLS 1 lead frame 1a connection part 1b Through hole 2 leadframe 3 Semiconductor component 4 capacitive element 5 Leadframe 6 Electrode 7 through hole 8 through hole 11 Flat band antenna 12 Mass 13 insulating dielectric 14 verticals 15 shortest path 16 Via capacity path 17 Bypass path 21 line segment 22 verticals 23 Bypass path width 24 right angles 25 verticals 26 hole width 27 Bypass clearance width 28 shortest path 29 Via capacity path 30 Bypass path 100 power modules 200 power module 201 Leadframe 202 bridging part 300 power module 301 Leadframe 302 bridging part< / vergleichsbeispiel>

Claims

[1] Power module (100), comprising: two semiconductor components (3), each having an electrode (6) on a one-sided surface and an other-sided surface of the semiconductor component (3); a flat plate-shaped first electrically conductive metal pattern connected to the electrode (6) on the one-sided surface of each of the two semiconductor devices (3) arranged in a same plane; a flat-plate-shaped second electrically conductive metal pattern connected to the electrode (6) on the other surface of each of the two semiconductor devices (3); and a capacitive element (4) arranged between the first electrically conductive metal pattern and the second electrically conductive metal pattern and forming a capacitance between the first electrically conductive metal pattern and the second electrically conductive metal pattern, wherein the two semiconductor components (3) and the capacitive element (4) are arranged at the apices of a triangle in the same plane, the first electrically conductive metal pattern and the second electrically conductive metal pattern are each formed to have a flat plate shape with a contour within which the three vertices and three sides of the triangle are encompassed, assumed that a shortest connection length path between the two semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern is defined as a first shortest path, and a shorter path and a longer path from two shortest connection length paths between the capacitive element (4) and the two respective semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern are defined as a second shortest path and a third shortest path, respectively, (first shortest path)≥(second shortest path) and ((first shortest path) 2 +(second shortest path) 2 )≥(third shortest path) 2 are fulfilled, assumed that a resonance frequency defined as a first resonance frequency from two capacitances interfering between the one-sided surfaces and the other-sided surfaces of the two semiconductor components (3) and two inductances generated between the one-sided surfaces and between the other-sided surfaces of the two semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, a resonant frequency defined as a second resonant frequency from a capacitance generated by the capacitive element (4) and a capacitance acting interferingly between the one-sided surface and the other-sided surface of one of the two semiconductor components (3), and two inductances generated between the capacitive element (4) and the one-sided surface of one of the semiconductor components (3) and between the capacitive element (4) and the other-sided surface of one of the semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, and a resonant frequency resulting from a capacitance generated by the capacitive element (4) and a capacitance interfering between the one-sided surface and the other-sided surface of another of the two semiconductor components (3), and two inductances generated between the capacitive element (4) and the one-sided surface of the other of the semiconductor components (3) and between the capacitive element (4) and the other-sided surface of the other of the semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern is defined as a third resonant frequency, the first electrically conductive metal pattern and the second electrically conductive metal pattern each have a thickness equal to or greater than twice a skin depth through which current flows due to the skin effect generated by the first resonant frequency, the second resonant frequency, and the third resonant frequency of current paths, and the first electrically conductive metal pattern, the second electrically conductive metal pattern and the capacitive element (4) reduce vibrations caused by any one of the first resonance frequency, the second resonance frequency and the third resonance frequency of the current paths, each of which is present between two elements arbitrarily selected from the two semiconductor devices (3) and the capacitive element (4). [2] Power module (100) according to claim 1, comprising: n, where "n" represents an integer not less than 3, semiconductor devices (3), each of which has an electrode (6) on a one-sided surface and an other-sided surface of the semiconductor device (3); a flat plate-shaped first electrically conductive metal pattern connected to the electrode (6) on the one-sided surface of each of the n semiconductor devices (3) arranged in a same plane; a flat-plate-shaped second electrically conductive metal pattern connected to the electrode (6) on the one-sided surface of each of the n semiconductor devices (3); and a capacitive element (4) arranged between the first electrically conductive metal pattern and the second electrically conductive metal pattern and forming a capacitance between the first electrically conductive metal pattern and the second electrically conductive metal pattern, wherein two adjacent semiconductor components (3) selected from the n semiconductor components (3) and the capacitive element (4) are arranged at vertices of a triangle in the same plane, the first electrically conductive metal pattern and the second electrically conductive metal pattern each characterized by are that they have a flat plate shape with a contour within which the three vertices and three sides of the triangle are encompassed, assumed that a shortest connection length path between the two adjacent semiconductor devices (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern is defined as a first shortest path, and a shorter path and a longer path from two shortest connection length paths between the capacitive element (4) and the two respectively adjacent semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, are defined as a second shortest path and a third shortest path, respectively, (first shortest path)≥(second shortest path) and ((first shortest path)² + (second shortest path)²) ≥ (third shortest path)² are fulfilled, assumed that a resonance frequency defined as a first resonance frequency from two capacitances interfering between the one-sided surfaces and the other-sided surfaces of the two adjacent semiconductor components (3) and two inductances generated between the one-sided surfaces and between the other-sided surfaces of the two semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, a resonant frequency defined as a second resonant frequency from a capacitance generated by the capacitive element (4) and a capacitance acting interferingly between the one-sided surface and the other-sided surface of one of the two semiconductor elements (3), and two inductances generated between the capacitive element (4) and the one-sided surface of one of the semiconductor elements (3) and between the capacitive element (4) and the other-sided surface of one of the semiconductor elements (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, and a resonant frequency resulting from a capacitance generated by the capacitive element (4) and a capacitance interfering between the one-sided surface and the other-sided surface of another of the two adjacent semiconductor components (3), and two inductances generated between the capacitive element (4) and the one-sided surface of the other of the semiconductor components (3) and between the capacitive element (4) and the other-sided surface of the other of the semiconductor components (3) on the first electrically conductive metal pattern and the second electrically conductive metal pattern, is defined as a third resonant frequency, the first electrically conductive metal pattern and the second electrically conductive metal pattern each have a thickness equal to or greater than twice a skin depth through which current flows due to the skin effect generated by the first resonant frequency, the second resonant frequency, and the third resonant frequency of current paths, and with the n semiconductor devices (3), the first electrically conductive metal pattern, the second electrically conductive metal pattern and the capacitive element (4) also to reduce vibrations caused by any one of the first resonance frequency, the second resonance frequency and the third resonance frequency of the current paths, each of which is present between two elements arbitrarily selected from the two adjacent semiconductor devices (3) and the capacitive element (4). [3] Power module (100) according to claim 2, wherein the two adjacent semiconductor components (3) are two power semiconductor components in each of which a depletion layer is formed at the time of turn-off or at the time of switching from forward to reverse voltage, assumed that a frequency determined according to a movement and discharge time required for majority-side charge carriers to pass through the depletion layer within each power semiconductor device at the time of turn-off or at the time of turn-off is defined as a first natural oscillation frequency, and a frequency determined according to a movement and discharge time required for minority-side charge carriers to pass through the depletion layer within the bipolar type power semiconductor device at the time of turn-off or at the time of turn-off is defined as a second natural frequency, each of the two adjacent power semiconductor components is a power semiconductor component that has only the first natural frequency, or a power semiconductor component that has both the first natural frequency and the second natural frequency, the first resonance frequency, the second resonance frequency and the third resonance frequency are included in a frequency range in which the first natural frequency and the second natural frequency are distributed, and Vibrations caused by the first or second natural frequency and any of the first, second and third resonant frequencies, which approach each other and thus reinforce each other, are suppressed. [4] Power module (100) according to claim 2, wherein a combination is formed such that each of the two semiconductor components (3) is an insulated gate bipolar transistor, a bipolar transistor or a metal oxide semiconductor field effect transistor, and the capacitive element (4) is a pn junction diode or a Schottky junction diode, or a combination is formed such that each of the two semiconductor components (3) is a pn junction diode or a Schottky diode and the capacitive element (4) is an insulated gate bipolar transistor, a bipolar transistor or a metal oxide semiconductor field effect transistor. [5] Power module (100) according to claim 2, wherein each of the two adjacent semiconductor components (3) is a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor in reverse bias, and the capacitive element (4) is a capacitor which is arranged between the first electrically conductive metal pattern and the second electrically conductive metal pattern and which is formed from an insulating filler. [6] Power module (100) according to claim 2, wherein the first electrically conductive metal pattern functions as a flat antenna (11), wherein the second electrically conductive metal pattern functions as a ground (12), upon a change in a voltage of each of the two semiconductor components (3) or the capacitive element (4), and fr=c0 / (2Le√εr), where c0 represents a speed of light, εr represents a dielectric constant of an element, and Le represents a length of a long side of the flat plate antenna (11), which indicates a fundamental radiation frequency of a radio wave and is obtained from the longitudinal and transverse dimensions of the flat plate antenna (11), is a frequency higher than the first resonance frequency, the second resonance frequency, and the third resonance frequency. [7] The power module (100) according to claim 2, wherein one or both of the first electrically conductive metal pattern and the second electrically conductive metal pattern each have two or more through holes (7) on a perpendicular (14) drawn downward from a location where the capacitive element (4) is connected to the first electrically conductive metal pattern or the second electrically conductive metal pattern to a shortest connection path between the two adjacent semiconductor devices (3). [8] Power module (100) according to claim 2, wherein each of the two adjacent semiconductor components (3) and the capacitive element (4) located at the vertices of the triangle has a rectangular shape, the capacitive element (4) is arranged such that one longitudinal side thereof faces one longitudinal side of each of the two adjacent semiconductor components (3), one or both of the first electrically conductive metal pattern and the second electrically conductive metal pattern each have a through hole (8) between the capacitive element (4) and the two adjacent semiconductor components (3), and a value obtained by subtracting a distance from a length is equal to or greater than 1 / 2 of a length of a short side of the capacitive element (4), wherein the length from which the distance is subtracted is a length of a portion of a perpendicular (22) from an outer periphery of the capacitive element (4) to a line segment (21) connecting a corner of a semiconductor device (3) closest to the capacitive element (4) of the two adjacent semiconductor devices (3) to a corner that is an end of a long side of another of the semiconductor devices (3) facing the capacitive element (4) that is farther away from the capacitive element (4), the perpendicular (22) being drawn downward to the line segment (21) from a center of a location where the capacitive element (4) is connected to the first electrically conductive metal pattern or the second electrically conductive metal pattern; and the distance is a distance between two perpendiculars (24, 25) drawn downwards to the perpendicular (22) from circumferential portions of the through-hole (8) which are furthest apart from each other in a direction of the perpendicular.

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