METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Method for manufacturing a semiconductor device comprising: Stacking a first substrate (52) and a second substrate (54) such that a rear surface (54b) of the second substrate (54) faces a front surface (52a) of the first substrate (52); and Connecting the first substrate (52) to the second substrate (54) by causing an electric current to flow between the first substrate (52) and the second substrate (54), wherein the first substrate (52) and the second substrate (54) each consist of a compound semiconductor, and the compound semiconductor contains a first element and a second element that is connected to the first element and has an electronegativity that is 1.5 or more lower than that of the first element, The procedure also exhibits: Before connecting the first substrate (52) to the second substrate (54), perform at least one of the following steps: Forming a high-resistance region (56) in the front face (52a) of the first substrate (52) and / or the rear face (54b) of the second substrate (54) by introducing a dopant or a dissimilar material different from the compound semiconductor into the corresponding front face (52a) and / or rear face (54b) by ion implantation or by epitaxial growth of a semiconductor material containing a dopant on the corresponding front face (52a) and / or rear face (54b) and / or by annealing the first substrate (52) and / or the second substrate (54); and Forming a region of high thermal resistance in the front face (52a) of the first substrate (52) and / or the rear face (54b) of the second substrate (54) by introducing a dopant or a dissimilar material different from the compound semiconductor into the corresponding front face (52a) and / or rear face (54b) by means of ion implantation and / or by annealing the first substrate (52) and / or the second substrate (54), wherein the region of high thermal resistance has a higher thermal resistance than its surrounding area.

Description

[0001] The present invention relates to a method for manufacturing a semiconductor device.

[0002] Regarding a method for manufacturing a semiconductor device, various techniques have been proposed for separating and joining a substrate consisting of a compound semiconductor. For example, JP 2019-126 838 A discloses a technique for cutting and separating a substrate containing gallium oxide in a method for manufacturing a semiconductor device. In this manufacturing process, a laser beam is first directed onto the substrate along a planned cutting and separation line to form a modified area along the planned cutting line. This modified area is more brittle than the other areas of the substrate. The substrate is then cut along the planned cutting line using a cutting tool.Since this manufacturing process involves cutting the substrate at the modified area formed along the planned cutting line, the substrate can be cut at a higher speed than with conventional cutting or separating.

[0003] In the manufacturing process according to JP 2019-126838A, the laser beam is applied along the planned cutting line of the substrate, such that the width of the modified area is greater than the width of the cutting edge. Therefore, when the substrate is cut by the cutting edge, the modified area remains on the cut surface. Because the modified area has been damaged by the laser beam, the cut surface is not uniform, which can affect the performance of the semiconductor device.

[0004] WO 2020 / 098 401 A1 discloses a method for fabricating a gallium oxide semiconductor structure, comprising: providing a gallium oxide single-crystal wafer with an implantation surface; performing ion implantation from the implantation surface into the gallium oxide single-crystal wafer such that implanted ions reach a preset depth and an implantation defect layer is formed at the preset depth; bonding the implantation surface to a substrate with high thermal conductivity to obtain a first composite structure; performing an annealing treatment on the first composite structure such that the gallium oxide single-crystal wafer is peeled away in the first composite structure along the implantation defect layer, thereby obtaining a second composite structure and a third composite structure;and performing a surface treatment on the second composite structure to remove a first damaged layer in order to obtain a gallium oxide semiconductor structure comprising a first gallium oxide layer and the substrate with high thermal conductivity.

[0005] US Patent 2005 / 0272224A1 discloses a method for dividing a substrate, whereby any substrate is divided into chips with the same square shape, and all split facets can be flat. In this method, an electron beam with an intensity that causes a dislocation inside the substrate is directed onto a substrate surface to create a crack starting from such a dislocation, and a split facet is formed to divide the substrate.

[0006] JP 2014-203953A discloses a method for fabricating a semiconductor element, comprising: preparing a semiconductor wafer in which a plurality of light-emitting elements are formed on a GaO wafer substrate having first and second principal surfaces that are (-201) planes or (101) planes; joining a first support plate to the second principal surface of the GaO wafer substrate by means of a peelable bonding material; joining a second support plate to the first principal surface of the GaO wafer substrate by means of the peelable bonding material to form a laminate; and forming grooves from the second support plate of the laminate, reaching the center of the first support plate, by cutting with a cutting edge and cutting the GaO wafer substrate to divide the plurality of light-emitting elements into element units.

[0007] DE 69 332 465 T2 discloses a method for cutting an oxide single-crystal wafer comprising a superconducting oxide layer applied to the surface, comprising: scribing the wafer such that a groove is formed along a cutting line, and applying a bending moment to the wafer, wherein the groove is scribed on a crystal surface of the wafer and the wafer is heated locally in the groove by means of a Pt heating wire.

[0008] JP 2004-148438A discloses a method for cutting a brittle material by creating a slit using electrical discharges. The slit thus created is heated, and a thermal voltage is generated within the slit to cut the brittle material by performing a further electrical discharge.

[0009] The object of the present invention is to provide a technique for preventing damage to a substrate consisting of a compound semiconductor by efficiently bonding the substrates. This object is achieved by a method for fabricating a semiconductor device with the features of claim 1. The dependent claims are directed to advantageous embodiments of the invention.

[0010] Electronegativity is a value that indicates the ability of an atom in a molecule to attract an electron. In the present invention, electronegativity refers to Pauling electronegativity.

[0011] It is known that if the difference in electronegativity between the first and second elements is equal to or greater than 1.5, the bond between them exhibits a strong ionic bond. In a compound semiconductor exhibiting ionic bonding, the charges generated when an electric current flows move within the semiconductor, likely disrupting the polarity within the crystal. Furthermore, the flow of an electric current likely induces thermal stress and disrupts the crystal structure. The crystal structure of the compound semiconductor exhibiting ionic bonding is likely altered by the passage of an electric current.

[0012] In the manufacturing process according to the invention, the first substrate and the second substrate are first stacked on top of each other. The first substrate and the second substrate each consist of a compound semiconductor. The compound semiconductor contains the first element and the second element, which is bonded to the first element and has an electronegativity 1.5 or more times lower than that of the first element. As described above, the crystal structure of the compound semiconductor, which exhibits ionic bonding properties, is likely to be disturbed by the flow of an electric current. Therefore, by causing the electric current to flow between the first and second substrates, the crystal structure at the interface between the first and second substrates is disturbed, and the area surrounding the interface is melted.When the electric current is stopped, the disordered crystal structures realign as the molten semiconductor material solidifies. As a result, the first and second substrates can be efficiently bonded together.

[0013] The features and advantages of the present invention will become clear with reference to the following detailed description and the accompanying drawings, in which identical parts are designated by the same reference numerals. The drawings show: Fig. 1 a top view of a semiconductor substrate in a manufacturing process according to a first embodiment not in accordance with the invention; Fig. 2 a cross-sectional view showing a process for introducing a dopant into the semiconductor substrate; Fig. 3 a cross-sectional view showing a process for causing an electric current to flow through the semiconductor substrate; Fig. 4 a cross-sectional view showing a state in which the semiconductor substrate is subdivided; Fig. 5 a cross-sectional view showing a process for arranging an electrode on a semiconductor substrate in a manufacturing process according to a second embodiment not according to the invention; Fig. 6 a cross-sectional view showing a state in which the semiconductor substrate is subdivided; Fig. 7 a cross-sectional view showing a process for dividing a semiconductor substrate along a plane direction or surface direction of the semiconductor substrate in a manufacturing process according to a modified example not according to the invention; Fig. 8 a cross-sectional view showing a process for implanting ions into the surface of a semiconductor substrate in a manufacturing process according to a third embodiment according to the invention; Fig. 9 a cross-sectional view showing a process for stacking semiconductor substrates; and Fig. Figure 10 shows a cross-sectional view illustrating a process for causing an electric current to flow through the semiconductor substrates.

[0014] The following describes non-inventive embodiments that serve to clarify the invention, as well as an embodiment of the present invention with reference to the technical elements listed below. The following technical elements can even be useful when used independently of one another.

[0015] According to one embodiment of the present invention, a method for fabricating a semiconductor device comprises the following steps: stacking or layering a first substrate and a second substrate on top of each other; and connecting the first substrate and the second substrate to each other by causing an electric current to flow between the first substrate and the second substrate. The first substrate and the second substrate each consist of a compound semiconductor. The compound semiconductor comprises a first element and a second element connected to the first element, the second element having an electronegativity 1.5 or more times lower than that of the first element.

[0016] In this manufacturing process, the first and second substrates are stacked on top of each other. Each substrate consists of a compound semiconductor containing the first element and a second element bonded to the first element, the latter having an electronegativity 1.5 or more times lower than that of the first element. The crystal structure of the compound semiconductor, which exhibits ionic bonding properties, is likely to be disrupted by the flow of an electric current. Therefore, by causing an electric current to flow between the first and second substrates, the crystal structure at the interface between them is disrupted, and the area surrounding the interface is melted.When the flow of electric current is stopped, the disordered crystal structures realign as the molten semiconductor material solidifies. As a result, the first and second substrates can be efficiently bonded together.

[0017] The manufacturing process may also include a step for introducing a dopant or a dissimilar material, different from the compound semiconductor, onto the surface of the first substrate prior to the stacking step of the first and second substrates. In the stacking step, the second substrate may be stacked onto the surface of the first substrate.

[0018] In such a configuration, the resistance of the first substrate's surface is increased by introducing a dopant or dissimilar material. The second substrate is then stacked onto the surface of the first substrate, which now exhibits increased resistance. When an electric current is introduced between the first and second substrates, the temperature at the interface between them tends to rise. This readily melts the semiconductor material at the interface, allowing the two substrates to bond efficiently together.

[0019] The manufacturing process may also include a step to increase the resistance of a surface layer section of the first substrate and / or a surface layer section of the second substrate by subjecting the first substrate and / or the second substrate to a heat treatment such as annealing or tempering before the step to join the first substrate and the second substrate.

[0020] In such a configuration, the resistance of the interface between the first and second substrates can be increased if the first and second substrates are brought into contact such that the section of the surface layer with the increased resistance is located at the interface between the first and second substrates. Therefore, when an electric current is introduced between the first and second substrates, the temperature at the interface—that is, the temperature at the contact surface—tends to rise. As a result, the semiconductor material can be easily melted at the interface, and the first and second substrates are efficiently bonded together.

[0021] The manufacturing process may also include a step to increase the thermal resistance of a surface layer section of the first substrate and / or a surface layer section of the second substrate by subjecting the first substrate and / or the second substrate to a heat treatment such as annealing or tempering before the step to join the first substrate and the second substrate.

[0022] In such a configuration, the thermal resistance at the interface between the first and second substrates can be increased if the first and second substrates are brought into contact such that the surface layer section with the increased thermal resistance is located at the interface between the first and second substrates. When an electric current is caused to flow between the first and second substrates, heat is likely to stagnate at the interface between them, i.e., at the contact surface, and thus the temperature at the interface can easily rise. As a result, the semiconductor material at the interface is readily melted, and the first and second substrates can be efficiently bonded together.

[0023] According to one embodiment of the present invention, the compound semiconductor in the manufacturing process can be an oxide semiconductor, and the first element can be oxygen. Furthermore, the compound semiconductor can consist of β-Ga₂O₃. First embodiment, not according to the invention

[0024] The following describes a method for manufacturing a semiconductor device 10 of a first embodiment with reference to the drawings. In the manufacturing method of the first embodiment, the semiconductor device 10 is manufactured using a semiconductor substrate 12 in the wafer state, as shown in Fig. Figure 1 shows the manufacturing process of the first embodiment, which is characterized by a process for dividing or partitioning the semiconductor substrate 12, which consists of a special material as described later. This manufacturing process can be used for various semiconductor devices that utilize the special material and their semi-finished products. The following description focuses primarily on the process for partitioning the semiconductor substrate 12, and the description of the other manufacturing processes is omitted.

[0025] The in Fig. The semiconductor substrate 12 shown in Figure 1 consists of a compound semiconductor. In particular, the semiconductor substrate 12 consists of β-Ga₂O₃. However, the material of the semiconductor substrate 12 is not limited to β-Ga₂O₃. A compound semiconductor containing a first and a second element bonded together, where the difference in electronegativity between the first and second elements is equal to or greater than 1.5, can be used as the material of the semiconductor substrate 12. More generally, it is simply necessary that the semiconductor substrate 12 consists of a material exhibiting ionic bonding properties. In the case of β-Ga₂O₃, O corresponds to the first element and has an electronegativity of 3.44, and Ga corresponds to the second element and has an electronegativity of 1.81.The compound semiconductor forming the semiconductor substrate 12 may also contain an element different from the first and second elements. Examples of the compound semiconductor forming the semiconductor substrate 12 that is not β-Ga₂O₃ include gallium oxide semiconductors such as (Ga, Rh)₂O₃, (Ga, Ir)₂O₃, (Ga, Bi)₂O₃, as well as ZnGa₂O₄ and other oxide semiconductors.

[0026] In Fig. 1 corresponds to a plane containing an X-direction and a Z-direction, a (100) crystal plane of β-Ga2O3, and a plane containing a Y-direction and the Z-direction corresponds to a (001) crystal plane of β-Ga2O3. Furthermore, a plane containing the X-direction and the Y-direction, i.e., a plane along a surface 12a, corresponds to a (010) crystal plane of β-Ga2O3. In other words, in Fig. 1 corresponds to the Y direction of a crystal orientation of

[100] , the X direction corresponds to a crystal orientation of

[001] , and the Z direction corresponds to a crystal orientation of

[010] .

[0027] As it is in Fig. As shown in Figure 1, the semiconductor substrate 12 has several element regions 30, each formed with a semiconductor device 10, and several planned division regions or plan division regions 32 around the respective element regions 30. The planned division regions 32 correspond to areas that will be cut later. The element regions 30 are arranged in a grid pattern along the X and Y directions.

[0028] In the manufacturing process of the first embodiment, a dopant is first introduced into the semiconductor substrate 12 by means of ion implantation. In this case, the dopant is introduced selectively along the planned division regions 32, as described in Fig. Figure 2 shows that the dopant to be introduced is not particularly restricted, and, for example, Fe or V can be used. As shown in Figure 2, the dopant to be introduced is not particularly restricted. Fig. As shown in Figure 2, the dopant is introduced into the interior of the semiconductor substrate 12, thus forming a high-resistance region 34. Due to the introduction of the dopant, the high-resistance region 34 exhibits a higher resistance than an surrounding or peripheral region, i.e., a higher resistance than the element regions 30. In the areas connected to the Fig. The representation of the internal structure of the semiconductor substrate 12 is omitted in the two subsequent cross-sectional views.

[0029] As it is in Fig. As shown in Figure 3, probes 16 are then brought into contact with a front surface 12a and a rear surface 12b of the semiconductor substrate 12. Here, each probe 16 is brought into contact with the semiconductor substrate 12 within the planned subdivision area 32. As shown in Fig. As shown in Figure 3, in this process, where the front surface 12a and the rear surface 12b of the semiconductor substrate 12 are provided or are present, the probe 16 can be brought into contact with only one location within the planned division areas 32 or with several locations within the planned division areas 32. Furthermore, the probe 16 can also be brought into contact with the front surface 12a and the rear surface 12b at locations other than the planned division areas 32.

[0030] Subsequently, an electric current is caused to flow through each probe 16 in contact with the semiconductor substrate 12. Since the dopant was introduced into the high-resistance region 34 within the planned division region 32, the high-resistance region 34 exhibits a higher resistance than the surrounding area. Therefore, when the electric current is caused to flow in the substrate 12, the temperature of the high-resistance region 34 rises to a higher temperature than that of its surrounding area. Consequently, when the electric current is caused to flow in the substrate 12, a large thermal stress is exerted on the high-resistance region 34.Since the semiconductor substrate 12 consists of a compound semiconductor exhibiting ionic bonding properties, the polarity within the crystal is likely to be disturbed when an electric current flows through the semiconductor substrate 12. Because the planned division area 32 is provided along the (100) and (001) planes of β-Ga2O3, a gap is likely to occur readily. For these reasons, in this process, if an electrical power of, for example, approximately 800 W / cm² is applied... 2 exceeds, is applied to the semiconductor substrate 12, the semiconductor substrate 12 is divided along the planned division areas 32, as shown in Fig. Figure 4 shows that the semiconductor substrate 12 is divided into several semiconductor devices 10. Second embodiment, not according to the invention

[0031] In a manufacturing process of a second embodiment, the technique that causes the electric current to flow in the semiconductor substrate 12 differs from that of the first embodiment. In the manufacturing process of the second embodiment, the process up to the process that is described in Fig. 2 is the same as in the first embodiment. In the second embodiment, the process shown in Fig. Figure 2 shows an electrode 18 formed on the surface 12a of the semiconductor substrate 12, as shown in Fig. Figure 5 shows that the electrode 18 is formed along the planned division area 32 on the surface 12a of the semiconductor substrate 12. The electrode 18 can, for example, be an electrode that forms a Schottky contact with the semiconductor substrate 12. The electrode 18 can be configured to cover the entire surface of the planned division area 32 on the surface 12a of the semiconductor substrate 12, or it can be formed at intervals or intermittently on the surface of the planned division area 32 on the surface 12a of the semiconductor substrate 12.

[0032] Subsequently, an electric current is caused to flow through the semiconductor substrate 12 via the electrode 18, which is located on the surface 12a of the semiconductor substrate 12. For example, an electric current can be caused to flow between the electrode 18(s) and the rear surface 12b of the semiconductor substrate 12. This is achieved by applying an electrical power of approximately 800 W / cm². 2 If the semiconductor substrate 12 exceeds the specified limit, the semiconductor substrate 12 can be divided along the planned division areas 32 as in the first embodiment, as shown in Fig. Figure 6 is shown. As a result, the semiconductor substrate 12 is divided into several semiconductor devices 10.

[0033] As described above, in the manufacturing process of the first and second embodiments, the semiconductor substrate 12 can be easily divided by applying an electric current to or flowing through it. Therefore, the semiconductor substrate 12 can be divided much faster than, for example, by cutting with a blade, which is conventionally used to divide semiconductor substrates. Furthermore, in the embodiments described above, the semiconductor substrate 12 can be divided at low cost without the need for a blade or cutting strip to protect the surface of the semiconductor substrate during the cutting process.

[0034] Since in the first and second embodiments described above the semiconductor substrate 12 is divided using the gap of the compound semiconductor caused by the electric current flowing through the semiconductor substrate 12, no damage is likely to occur on the cut surface. Therefore, the cut surfaces are essentially uniform, and the semiconductor devices 10 can be manufactured with high yield.

[0035] In the first and second embodiments described above, the entire semiconductor substrate 12 consists of β-Ga₂O₃. Alternatively, only the planned partition regions 32 in the semiconductor substrate 12 can consist of β-Ga₂O₃. That is, a region other than the planned partition regions 32 (for example, the element regions 30 or similar) can contain an element other than O and Ga.

[0036] Furthermore, in the embodiments described above, a current flow is caused between the front surface 12a and the rear surface 12b of the semiconductor substrate 12. According to another example, two or more probes or two or more electrodes 18 can be arranged at any position on the front surface 12a of the semiconductor substrate 12, and an electric current flow can be caused only in the vicinity of the front surface 12a of the semiconductor substrate, i.e., in the surface layer section adjacent to the front surface 12a. Alternatively, it can be caused in a similar manner that the electric current flows only in the vicinity of the rear surface 12b of the semiconductor substrate 12.

[0037] In the first and second embodiments described above, the high-resistance region 34 is formed by ion implantation of the dopant. The formation of the high-resistance region 34 is not limited to ion implantation of the dopant. The high-resistance region 34 can be formed by introducing the dopant via epitaxial growth. According to another example, the resistance of the planned division region 32 can be increased by introducing a dissimilar or dissimilar material, different from the material forming the semiconductor substrate 12, into the planned division region 32. Instead of the material in Fig. In the process shown in Figure 2, for example, a groove can be formed by etching from the surface 12a along the planned parting area 32, and the interior of the groove can be filled with a dissimilar material (for example, SiO2 or similar). With such a configuration, it is possible to form a high-resistance region 34 extending from the surface 12a of the semiconductor substrate 12 to a predetermined depth (i.e., the depth of the groove).

[0038] Furthermore, in the first and second embodiments, the high-resistance region 34 is formed by introducing the dopant. According to another example, a region with high thermal resistance, exhibiting a higher thermal resistance than or surrounding area, can be formed by introducing a dopant. The region of high thermal resistance can be formed by introducing a dissimilar material as described above. In the region of high thermal resistance, when an electric current is induced to flow, heat tends to stagnate even more readily than in the surrounding area, and the temperature is likely to rise more than in the surrounding area. Therefore, a large thermal stress or load can also be exerted by forming such a region of high thermal resistance.The high-resistance region 34 and the region of high thermal resistance described above do not necessarily need to be formed. That is, in the technique described here, it is not always necessary to carry out a process for introducing a dopant or a dissimilar material. Even with such a configuration, the semiconductor substrate 12 can be divided along the cleavage plane by causing the electric current to flow through the semiconductor substrate 12.

[0039] In the first and second embodiments, the process for dividing or subdividing the semiconductor substrate 12 into the semiconductor devices 10 was mainly described. Alternatively, the techniques described in the first and second embodiments can also be used, for example, for a step to thin or dilute the semiconductor substrate 12. As is shown, for example, in Fig. As shown in Figure 7, a high-resistance region 40 is selectively formed on or at a desired depth from the surface 12a of the semiconductor substrate 12 by ion implantation of a dopant. The probes 16 are then brought into contact with the front surface 12a and the rear surface 12b of the semiconductor substrate 12, and an electric current is caused to flow through the probes 16 in the semiconductor substrate 12, allowing the semiconductor substrate 12 to be divided along the high-resistance region 40. By defining the surface along the high-resistance region 40 as the (100) plane or the (001) plane of β-Ga₂O₃, i.e., by defining the surface to be divided as the (100) plane or the (001) plane of β-Ga₂O₃, the semiconductor substrate 12 can be divided even more easily. In this way, the semiconductor substrate 12 can be made thinner.

[0040] The formation of the high-resistance region 40 is not limited to ion implantation of the dopant. For example, if the semiconductor substrate 12 is produced by epitaxial growth during the substrate fabrication step, a semiconductor material containing the dopant can grow epitaxially to a depth at which the high-resistance region 40 is formed. Furthermore, the semiconductor substrate 12 exhibiting the high-resistance region 40 can be fabricated using other materials.

[0041] In the first and second embodiments described above, the semiconductor substrate 12 is stratified along the planned division areas 32 by applying an electrical power of approximately 800 W / cm². 2The surface 12a of the semiconductor substrate 12 is divided as the electrical power applied to the semiconductor substrate 12 increases. In this process, a groove is formed on the surface 12a of the semiconductor substrate 12 in the thickness direction along the planned division area 32. That is, the described technique is also useful as a technique for forming a groove on the surface 12a of the semiconductor substrate 12. Third embodiment according to the invention

[0042] A manufacturing process according to a third embodiment is described below. The manufacturing process of the third embodiment is characterized by a process for joining two semiconductor substrates 52 and 54, each consisting of a special material described later. The manufacturing process of the third embodiment can be used for various semiconductor devices made of the special material and their semi-finished products. The following mainly describes the process for joining the semiconductor substrates 52 and 54, and the description of the other manufacturing processes is omitted. The semiconductor substrate 52 and the semiconductor substrate 54 are examples of a "first substrate" and a "second substrate," respectively.

[0043] The semiconductor substrates 52 and 54 consist of similar compound semiconductors as in the first and second embodiments. That is, the semiconductor substrates 52 and 54 consist of β-Ga₂O₃. However, the material of the semiconductor substrates 52 and 54 is not limited to β-Ga₂O₃. A compound semiconductor containing a first element and a second element bonded together can be used as the material of the semiconductor substrates 52 and 54, where the difference in electronegativity between the first element and the second element is equal to or greater than 1.5. In general terms, it is simply necessary that the semiconductor substrate 12 consists of a material exhibiting ionic bonding properties. In β-Ga₂O₃, O corresponds to the first element and has an electronegativity of 3.44, and Ga corresponds to the second element and has an electronegativity of 1.81.The compound semiconductor forming the semiconductor substrate 12 can also contain an element other than the first and second elements. Examples of the compound semiconductor forming the semiconductor substrate 12 can include gallium oxide semiconductors such as (Ga, Rh)₂O₃, (Ga, Ir)₂O₃, (Ga, Bi)₂O₃, and ZnGa₂O₄, as well as other oxide semiconductors.

[0044] As it is in Fig. As shown in Figure 8, a dopant is first introduced into a surface 52a of the semiconductor substrate 52 by means of ion implantation. In this case, the dopant is introduced over the entire surface 52a of the semiconductor substrate 52. As a result, a high-resistance region 56, in which ions are implanted, is formed in a region facing the surface 52a of the semiconductor substrate 52, i.e., in a surface layer section of the surface 52a of the semiconductor substrate 52. The dopant to be introduced is not particularly restricted, and, for example, Fe or V can be used. As shown in Figure 8, the dopant is introduced in a specific way. Fig. As shown in Figure 9, the semiconductor substrate 54 is then stacked or layered onto the surface 52a of the semiconductor substrate 52.

[0045] The stacked semiconductor substrates 52 and 54 are then subjected to heat treatment (annealing, heating, or similar) in an oxygen-containing atmosphere. The oxygen-containing atmosphere refers to an atmosphere containing oxygen as an element. The semiconductor substrates 52 and 54 are subjected to heat treatment in an atmosphere such as oxygen gas (O2 gas). As a result, the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 exhibits high resistance. That is, in this process, the resistance in the region of and / or near the interface 55 of the semiconductor substrates 52 and 54, which contains the high-resistance region 56, is further increased.

[0046] This causes an electric current to flow between semiconductor substrate 52 and semiconductor substrate 54. As described in Fig.As shown in Figure 9, probes 59 are brought into contact with the front surface 54a of the semiconductor substrate 54 and the rear surface 52b of the semiconductor substrate 52. Then, an electric current is caused to flow through the semiconductor substrates 52 and 54 via the probes 59. The high-resistance region 56 is formed on the surface 52a of the semiconductor substrate 52. Furthermore, the resistance near the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 is increased by the heat treatment. When an electric current is caused to flow through the stack of semiconductor substrates 52 and 54, the temperature near the interface 55 therefore rises to a higher temperature than the surrounding area. As a result, a molten layer 60, in which the semiconductor material is molten, forms near the interface 55, and the crystal structure in the molten layer 60 is disrupted.When the flow of the electric current is subsequently stopped, the disordered crystal structures are rearranged during the solidification of the molten layer 60, and the semiconductor substrate 52 and the semiconductor substrate 54 can be joined together. As described above, in the manufacturing process of the third embodiment, the semiconductor substrates 52 and 54 can be easily joined together by inducing an electric current flow in the stacked semiconductor substrates 52 and 54.

[0047] In the third embodiment, the entire semiconductor substrates 52 and 54 are formed from β-Ga2O3. According to another example, only the region near the front surface 52a of the semiconductor substrate 52 and the region near the rear surface 54b of the semiconductor substrate 54, i.e., only the regions facing the interface, can consist of β-Ga2O3.

[0048] In the third embodiment, the high-resistance region 56 is formed by ion implantation of the dopant. According to another example, the high-resistance region 56 can be formed by epitaxial growth of a semiconductor material containing a dopant on the surface 52a of the semiconductor substrate 52. According to yet another example, the high-resistance region 56 can be formed on the surface 52a by forming a dissimilar material (for example, SiO2 or similar) that differs from the material forming the semiconductor substrate 52.

[0049] In the third embodiment, the high-resistance region 56 is formed in the surface layer section adjacent to the front surface 52a of the semiconductor substrate 52. According to another example, the high-resistance region can be formed in the surface layer section adjacent to the rear surface 54a of the semiconductor substrate 54. Furthermore, the high-resistance region 56 can be formed both in the surface layer section adjacent to the front surface 52a of the semiconductor substrate 52 and in the surface layer section adjacent to the rear surface 54a of the semiconductor substrate 54.

[0050] In the third embodiment, the high-resistance region 56 is formed by ion implantation. Alternatively or additionally, a region of high thermal resistance, exhibiting a higher thermal resistance than the high-resistance region or its surrounding region, can be formed by ion implantation. The region of high thermal resistance can be formed by the dopant or the dissimilar material as described above. In the region of high thermal resistance, when an electric current is applied, heat tends to stagnate more readily than in the surrounding region, and the temperature is likely to rise more than in the surrounding region. Therefore, a high thermal stress can be generated by forming the region of high thermal resistance.The region of high thermal resistance can be formed in the surface layer section near the front face 52a of the semiconductor substrate 52, in the surface layer section near the rear face 54a of the semiconductor substrate 54, or in the surface layer sections of both the semiconductor substrate 52 and the semiconductor substrate 54. Similarly, the thermal resistance of the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 can be increased by heat treatment, either as an alternative or in addition to the process of increasing the resistance of the interface 55 by heat treatment. The high-resistance region 56 and the region of high thermal resistance described above need not be formed.In the technique described here, it is not always necessary to include the step of introducing a dopant or a dissimilar material. Furthermore, it is not always necessary to include the heat treatment step. Even in such a configuration, the semiconductor substrates 52 and 54 can be interconnected by causing an electric current to flow between them.

Claims

[1] Method for manufacturing a semiconductor device comprising: Stacking a first substrate (52) and a second substrate (54) such that a rear surface (54b) of the second substrate (54) faces a front surface (52a) of the first substrate (52); and Connecting the first substrate (52) to the second substrate (54) by causing an electric current to flow between the first substrate (52) and the second substrate (54), wherein the first substrate (52) and the second substrate (54) each consist of a compound semiconductor, and the compound semiconductor contains a first element and a second element that is connected to the first element and has an electronegativity that is 1.5 or more lower than that of the first element, The procedure also exhibits: Before connecting the first substrate (52) to the second substrate (54), perform at least one of the following steps: Forming a high-resistance region (56) in the front face (52a) of the first substrate (52) and / or the rear face (54b) of the second substrate (54) by introducing a dopant or a dissimilar material different from the compound semiconductor into the corresponding front face (52a) and / or rear face (54b) by ion implantation or by epitaxial growth of a semiconductor material containing a dopant on the corresponding front face (52a) and / or rear face (54b) and / or by annealing the first substrate (52) and / or the second substrate (54); and Forming a region of high thermal resistance in the front face (52a) of the first substrate (52) and / or the rear face (54b) of the second substrate (54) by introducing a dopant or a dissimilar material different from the compound semiconductor into the corresponding front face (52a) and / or rear face (54b) by means of ion implantation and / or by annealing the first substrate (52) and / or the second substrate (54), wherein the region of high thermal resistance has a higher thermal resistance than its surrounding area. [2] Method according to claim 1, wherein the compound semiconductor is an oxide semiconductor, and The first element is oxygen. [3] Method according to claim 2, wherein the compound semiconductor consists of β-Ga2O3.

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