Semiconductor device with gate insulation structure for separating gate stacks and method for manufacturing them

Abstract

Semiconductor device with: a first transistor with a first gate stack (92, 94) and first source / drain regions (82) on opposite sides of the first gate stack (92, 94); a second transistor with a second gate stack (92, 94) and second source / drain regions (82) on opposite sides of the second gate stack (92, 94); and a gate isolation structure (130) that separates the first gate stack (92, 94) from the second gate stack (92, 94), wherein the gate isolation structure (130) has the following: a dielectric coating (124) with a varying thickness along side walls of the first (92, 94) and second gate stack (92, 94), and a dielectric filler material (126) over the dielectric coating (124), wherein the dielectric filler material (126) has a seam (128), wherein the dielectric coating (124) extends continuously from a side wall of the first gate stack (92, 94) to a side wall of the second gate stack (92, 94), wherein the dielectric coating (124) is deposited on side walls and a bottom of an opening (122) by a non-conforming deposition process, wherein the non-conforming deposition process is a plasma-assisted atomic layer deposition (PEALD) process which deposits a thinner layer at an upper end of the opening (122) than at a lower end of the opening (122).

Description

background

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, so that more components can be integrated into a given area.

[0003] Document US 2019 / 0139957A1 describes self-aligned gate-edge trigate and FinFET devices, wherein a semiconductor structure comprises multiple semiconductor fins arranged over a substrate and projecting through a top surface of a trench isolation region. A gate structure defines a channel region in each of the multiple semiconductor fins. Source and drain regions are located at opposite ends of the channel regions of each of the multiple semiconductor fins on opposite sides of the gate structure. The semiconductor structure also includes multiple gate-edge isolation structures. Individual gate-edge isolation structures alternate with individual semiconductor ribs.

[0004] Document US 2011 / 0 198 675 A1 describes a spacer structure of a field-effect transistor comprising a substrate, a gate structure having a sidewall that lies above the substrate, a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure, an oxygen-sealing layer adjacent to the sidewall of the gate structure, an oxygen-containing layer adjacent to the sidewall of the oxygen-containing layer and having a section extending over the substrate, and a second oxygen-containing layer adjacent to the oxygen-containing layer and extending over the section of the oxygen-containing layer above the substrate, with an outer edge of the second oxygen-containing layer being offset from the inner edge of the silicide region.

[0005] Document DE 10 2020 124 631 A1 describes a method for forming a semiconductor device, comprising: forming a gate structure over a fin, the fin projecting upwards over a substrate; forming an opening in the gate structure; forming a first dielectric layer along side walls and a bottom of the opening, the first dielectric layer being non-conformal, the first dielectric layer having a first thickness near an upper surface of the gate structure distal to the substrate and a second thickness near the bottom of the opening, the first thickness being greater than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, the first dielectric layer being formed from a first dielectric material and the second dielectric layer being formed from a second dielectric material that differs from the first dielectric material.

[0006] Document DE 10 2020 109 494 B3 describes a gate stack that can be etched to form a trench extending through the stack, the trench removing a section of the stack to divide it into a first and a second gate section. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap within the dielectric material. The air gap can extend from below the gate stack to an area inserted between the end of the first gate section and the end of the second gate section. Contacts can be formed between the first and second gate sections, electrically isolated from each other by the dielectric material and the air gap formed within it.

[0007] Document US 2019 / 0 378 903 A1 describes a semiconductor device with a channel region extending from a substrate. The semiconductor device contains a gate trace on the channel region. The semiconductor device also includes a gate isolation layer located between a first and second segment of the gate trace. The gate isolation layer is in contact with the gate trace and contains a gap within the layer.

[0008] Document DE 10 2018 100 297 A1 describes a semiconductor device with a first gate structure arranged over a substrate. The first gate structure extends in a first direction. A second gate structure is arranged over the substrate, extending in the first direction. A dielectric material is arranged between the first and second gate structures. An air gap is arranged within the dielectric material.

[0009] Document US 2017 / 0 025 511 A1 describes semiconductor devices with gate electrodes embedded on a substrate. Each gate electrode may extend longitudinally in a first direction, and individual gate electrodes may be arranged in the first direction. The semiconductor devices may include first and second gate spacers extending in the first direction and along the respective sidewalls of the gate electrodes. The first and second gate spacers may be spaced apart in a second direction. The semiconductor devices may further include gate separation patterns, and some of the gate separation patterns may be located between two gate electrodes adjacent in the first direction and between the first and second gate spacers.

[0010] The invention is defined by the main claim and the dependent claim. Further embodiments of the invention are described by the dependent claims. Brief description of the drawings

[0011] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of a FinFET in a three-dimensional representation according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D, Fig. 19E, Fig. 19F, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 22A and Fig. Figure 22B shows sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. The Fig. 23A and Fig. Figure 23B shows sectional views of FinFETs according to some embodiments. The Fig. 24A and Fig. Figure 24B shows sectional views of FinFETs according to some embodiments. The Fig. 25A and Fig. Figure 25B shows sectional views of FinFETs according to some embodiments. The Fig. 26, Fig. 27A and Fig. Figure 27B shows sectional views of NSFETs (nanostructured field-effect transistors) according to some embodiments. Detailed description

[0012] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0013] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0014] In various embodiments, a gate-cutting process is performed to separate adjacent dummy gates and define a structure of substitute gate stacks. As part of the gate-cutting process, the dummy gates are etched to define an opening, and a gate isolation structure is then fabricated within this opening. The gate isolation structure may include: a dielectric coating (occasionally referred to as a spacer) deposited with a conical profile using a non-conforming deposition method; and a dielectric filler material deposited over the dielectric coating. By maintaining the conical profile in the dielectric coating, a relatively large width can remain at the top of the opening, thus improving the deposition window for the dielectric filler material.Therefore, the dielectric filler material can be deposited with fewer manufacturing defects, such as reduced seams / voids. Reducing the size / number of seams / voids, in turn, reduces electrical defects (e.g., short circuits) that could otherwise occur if conductive material is unintentionally trapped in exposed seams during subsequent processing steps (e.g., during the fabrication of gate or source / drain contacts).

[0015] Fig. Figure 1 shows an example of a FinFET in a three-dimensional representation according to some embodiments. The FinFET has a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Insulation regions 56 are arranged in the substrate 50, with the fin 52 extending beyond and between adjacent insulation regions 56. Although the insulation regions 56 are shown and described here as regions separated from the substrate 50, the term "substrate" used here can also refer to just the semiconductor substrate or to a semiconductor substrate with insulation regions. Furthermore, although the fin 52 is shown as a single, continuous material rather than the substrate 50, the fin 52 and / or the substrate 50 can consist of only one material or of multiple materials. In this context, the fin 52 refers to the portion that extends between adjacent insulation regions 56.

[0016] A dielectric gate layer 92 is arranged along side walls and over a top surface of the fin 52, and a gate electrode 94 is arranged over the dielectric gate layer 92. Source / drain regions 82 are arranged on the sides of the fin 52 opposite the dielectric gate layer 92 and the gate electrode 94. Fig. Figure 1 also shows reference cross-sections that will be used in later figures. A cross-section A-A runs along a longitudinal axis of the gate electrode 94 and, for example, in a direction perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. A cross-section B-B is perpendicular to cross-section A-A and runs along a longitudinal axis of the fin 52 and, for example, in the direction of current flow between the source / drain regions 82 of the FinFET. A cross-section C-C is parallel to cross-section A-A and passes through a source / drain region of the FinFET. For clarity, later figures refer to these reference cross-sections.

[0017] Some embodiments discussed here are related to FinFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, nanostructured field-effect transistors (NSFETs; e.g., nanolayer, nanowire, gate-all-around, or similar field-effect transistors), or the like.

[0018] The Fig. Figures 2 to 22B are sectional views of intermediate stages in the fabrication of FinFETs in a device 100 according to some embodiments. In the Fig. 2 to 7 is the one in Fig. The reference cross-section A - A shown in Figure 1 is identical, except that multiple fins / FinFETs and / or gate isolation structures are used. Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 19C, Fig. 20A, Fig. 21A and Fig. 22A are along the in Fig. 1 shown reference cross-section A - A, and the Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 14C, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 17C, Fig. 18B, Fig. 19B, Fig. 19D, Fig. 19E, Fig. 20B, Fig. 21B and Fig. 22B are shown along a similar reference cross-section B - B, which is in Fig. Figure 1 is shown, with the exception that multiple fins / FinFETs and / or gate isolation structures are used. Fig. 10C and Fig. 10D are along the in Fig. The reference cross-section C - C shown in section 1 is represented, with the exception that multiple fins / FinFETs are used. Fig. 13C and Fig. Figure 19F shows top-down views of gate structures according to some embodiments.

[0019] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0020] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-FinFETs. The p-region 50P can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-FinFETs. The n-region 50N can be physically separated from the p-region 50P (as represented by a divider 51), and any number of device elements (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-region 50N and the p-region 50P.

[0021] In Fig. 3. Fins 52 are produced in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be produced by etching grooves in the substrate 50. The etching can be carried out using any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching can be anisotropic.

[0022] The fins 52 can be structured using any suitable method. For example, the fins 52 can be structured using one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller grid spacings than those achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used to structure the fins.In some embodiments, the mask (or other layer) can remain on the fins 52.

[0023] In Fig. In the embodiment shown, an insulating material 54 is deposited over the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon dioxide, a nitride, or the like, or a combination thereof, and can be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials deposited by a suitable method can also be used. In the embodiment shown, the insulating material 54 is silicon dioxide deposited by an FCVD process. After the insulating material 54 has been deposited, a tempering process can be carried out.In one embodiment, the insulating material 54 is deposited such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a coating (not shown) can first be produced along a surface of the substrate 50 and the fins 52. Subsequently, a filler material, such as one of those mentioned above, can be deposited over the coating.

[0024] In Fig. In 5, a removal process is performed on the insulating material 54 to remove excess insulating material 54 above the fins 52. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like, may be used. The planarization process exposes the fins 52 so that the top surfaces of the fins 52 and the insulating material 54 are at the same level after completion of the planarization process. In embodiments where a mask remains on the fins 52, the planarization process can expose or remove the mask so that the top surfaces of the mask or the fins 52 and the insulating material 54 are at the same level after completion of the planarization process.

[0025] In Fig. 6. The insulating material 54 is recessed to create STI regions 56 (STI: shallow trench insulation). The insulating material 54 is recessed such that the upper parts of the fins 52 protrude between adjacent STI regions 56 in the n region 50N and the p region 50P. Furthermore, the top surfaces of the STI regions 56 can have a flat surface (as shown), a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 56 can be produced flat, convex, and / or concave by a suitable etching process. The STI regions 56 can be recessed using a suitable etching process, such as an etching process that is selective for the insulating material 54 (e.g., one that etches the insulating material 54 at a higher rate than the fin material 52). For example, oxide removal can be performed. B. using dilute hydrofluoric acid (dHF acid).

[0026] The procedure, which refers to the Fig. The description in Figures 2 to 6 is only one example of how the fins 52 can be produced. In some embodiments, the fins 52 can be produced using an epitaxial growth process. For example, a dielectric layer can be produced over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Furthermore, in some embodiments, heteroepitaxial structures can be used for the fins 52. For example, the fins 52 can be formed in Fig. In a further embodiment, a dielectric layer can be produced over the top surface of the substrate 50, and a material different from that of the fins 52 can be epitaxially grown over the recessed fins 52. In these embodiments, the fins 52 have the recessed material as well as the epitaxially grown material arranged over the recessed material. In a further embodiment, a dielectric layer can be produced over the top surface of the substrate 50, and grooves can be etched through the dielectric layer. Then, heteroepitaxial structures can be epitaxially grown in the grooves using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins 52.In some embodiments where homoepitaxial or heteroepitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thus eliminating the need for prior and subsequent implantations, but in-situ and implantation doping can also be used together.

[0027] Furthermore, it can be advantageous to epitaxially grow a material in an n-region 50N (e.g., an NMOS region) that differs from a material in a p-region 50P (e.g., a PMOS region). In various embodiments, upper parts of the fins 52 can be made of silicon germanium (Si₂). x Ge 1-x, where x can be 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. Materials that can be used to fabricate the III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0028] Furthermore, in Fig. Six suitable troughs (not shown) are generated in the fins 52 and / or the substrate 50. In some embodiments, a p-trough can be generated in the n-region 50N, and an n-trough can be generated in the p-region 50P. In some embodiments, a p-trough and an n-trough are generated in both the n-region 50N and the p-region 50P.

[0029] In embodiments with different well types, different implantation steps can be performed for the n-region 50N and the p-region 50P using a photoresist and / or other masks (not shown). For example, a photoresist can be fabricated over the fins 52 and the STI regions 56 in the n-region 50N. The photoresist is patterned to expose the p-region 50P of the substrate 50. The photoresist can be fabricated by spin coating and can be patterned using suitable photolithography techniques. After the photoresist has been patterned, implantation with an n-doping material is performed in the p-region 50P, and the photoresist can act as a mask to largely prevent n-doping material from being implanted into the n-region 50N.The n-doping agents can be phosphorus, arsenic, antimony, or the like, present in the range at a concentration of 10 or less. 18 cm -3 e.g. of about 10 16 cm -3 up to about 10 18 cm -3 , are implanted. After implantation, the photoresist is removed, for example, using a suitable removal procedure.

[0030] Following implantation of the p-region 50P, a photoresist is prepared over the fins 52 and the STI regions 56 within the p-region 50P. The photoresist is then patterned to expose the n-region 50N of the substrate 50. The photoresist can be prepared by spin coating and patterned using suitable photolithography techniques. After the photoresist has been patterned, implantation of a p-doping agent is performed within the n-region 50N. The photoresist can then act as a mask to largely prevent further p-doping from being implanted into the p-region 50P. The p-doping agents can be boron, boron fluoride, indium, or similar substances present in the region at a concentration of 10⁻⁵ or less. 18 cm -3 e.g. of about 10 16 cm -3 up to about 10 18 cm -3, are implanted. After implantation, the photoresist can be removed, for example, using a suitable removal procedure.

[0031] Following the implantation of the n-region 50N and the p-region 50P, a tempering process can be performed to repair implantation damage and activate the implanted p- and / or n-doping materials. In some embodiments, the grown materials of the epitaxial fins can be doped in situ during growth, thus eliminating the need for implantation; however, in-situ and implantation doping can also be used together.

[0032] In Fig. In step 7, a dielectric dummy layer 60 is produced on the fins 52. The dielectric dummy layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using suitable methods. A dummy gate layer 62 is produced over the dielectric dummy layer 60, and a mask layer 64 is produced over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dielectric dummy layer 60 and subsequently planarized, for example, using CMP. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can have a conductive or a non-conductive material selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metals.The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other methods for depositing the selected material. The dummy gate layer 62 can also be made of other materials that exhibit high etch selectivity with respect to the etching of insulating regions, such as the insulating regions 56 and / or the dielectric dummy layer 60. The mask layer 64 can comprise one or more layers of, for example, silicon nitride, silicon oxide nitride, or the like. In this example, only one dummy gate layer 62 and only one mask layer 64 are produced across the n-region 50N and the p-region 50P. It should be noted that the dielectric dummy layer 60 is shown, for illustrative purposes only, to cover only the fins 52.In some embodiments, the dielectric dummy layer 60 can be deposited in such a way that it covers the STI areas 56, extending over the STI areas 56 and between the dummy gate layer 62 and the STI areas 56.

[0033] The Fig. Figures 8A to 22B show various further steps in the manufacture of exemplary devices. Fig. Figures 8A to 22B show structural elements in the n-region (50N) and the p-region (50P). For example, the structures shown in the Fig. Figures 8A to 22B are used for the n-region 50N and the p-region 50P. Differences (if any) between the structures in the n-region 50N and the p-region 50P are described in the text accompanying each figure.

[0034] In the Fig. 8A and Fig. 8B will be mask layer 64 (see Fig. 7) structured using suitable photolithography and etching processes to produce masks 74. The structure of the masks 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the structure of the masks 74 can also be transferred to the dielectric dummy layer 60 using a suitable etching process to produce dummy gates 72. The dummy gates 72 cover respective channel regions 58 of the fins 52. The structure of the masks 74 can be used to physically separate each of the dummy gates 72 from adjacent dummy gates 72. The dummy gates 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective epitaxial fins 52.

[0035] In the Fig. 8A and Fig. 8B. Gate sealing spacers 80 can also be manufactured on exposed surfaces of the dummy gates 72, the masks 74, and / or the fins 52. The gate sealing spacers 80 can be manufactured by thermal oxidation or by deposition followed by anisotropic etching. The gate sealing spacers 80 can be made of silicon oxide, silicon nitride, silicon oxide nitride, or the like.

[0036] After the production of the gate sealing spacers 80, implantations for lightly doped source / drain regions (LDD regions; not shown individually) can be performed. In embodiments with different device types, the procedure can be carried out similarly to the above, with reference to Fig. In the implantations discussed in section 6, a mask, such as a photoresist, can be fabricated over the n-region 50N, leaving the p-region 50P exposed. Dopants of a suitable type (e.g., p-conducting) can then be implanted into the exposed fins 52 in the p-region 50P. The mask can then be removed. The aforementioned n-dopants can be used as the n-dopants, and the aforementioned p-dopants can be used as the p-dopants. The lightly doped source / drain areas can have a doping concentration of approximately 10 15 cm -3 up to about 10 19 cm-3 have. A tempering process can repair implant damage and activate the implanted dopants.

[0037] In the Fig. 9A and Fig. 9B, gate spacers 86 are manufactured on the gate gasket spacers 80 along the side walls of the dummy gates 72 and the masks 74. The gate spacers 86 can be manufactured by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material for the gate spacers 86 can be silicon oxide, silicon nitride, silicon oxide nitride, silicon carbonitride, a combination thereof, or the like.

[0038] It should be noted that the above description presents a general method for manufacturing spacers and LDD areas. However, other processes and procedures can also be used. For example, fewer or additional spacers can be used, or a different sequence of steps can be employed (e.g., the gate seal spacers 80 can be etched without etching before the gate spacers 86 are manufactured, resulting in L-shaped gate seal spacers; spacers can be manufactured and removed; and / or the like). Furthermore, the n- and p-devices can also be manufactured using different structures and steps. For example, the LDD areas for n-devices can be manufactured before the gate seal spacers 80 are manufactured, while the LDD areas for p-devices can be manufactured after the gate seal spacers 80 are manufactured.

[0039] In the Fig. 10A and Fig. In 10B, source / drain epitaxy regions 82 are generated in the fins 52. The source / drain regions 82 are generated in the fins 52 such that each dummy gate 72 is located between adjacent pairs of source / drain epitaxy regions 82. In some embodiments, the source / drain epitaxy regions 82 can extend into and even penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the source / drain epitaxy regions 82 at a suitable lateral distance from the dummy gates 72, so that the source / drain epitaxy regions 82 do not short-circuit subsequently manufactured gates of the resulting FinFETs.

[0040] The source / drain epitaxy regions 82 in the n-region 50N can be fabricated by masking the p-region 50P of the fins 52 and by etching source / drain regions of the fins 52 in the n-region 50N to create recesses in the fins 52. The source / drain epitaxy regions 82 in the n-region 50N are then grown epitaxially in the recesses. The source / drain epitaxy regions 82 can consist of any suitable material, such as a material suitable for n-FinFETs. For example, if the fin 52 is silicon, the source / drain epitaxy regions 82 in the n-region 50N can consist of materials that introduce tensile stress into the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The source / drain epitaxy regions 82 in the n-region 50N can have surfaces that are raised relative to the respective surfaces of the fins 52, and they can have chamfers.

[0041] The source / drain epitaxy regions 82 in the p-region 50P can be created by masking the n-region 50N and by etching source / drain regions of the fins 52 in the p-region 50P to create recesses in the fins 52. The source / drain epitaxy regions 82 in the p-region 50P are then grown epitaxially in the recesses. The source / drain epitaxy regions 82 can consist of any suitable material, such as a material suitable for p-FinFETs. For example, if the fin 52 is silicon, the source / drain epitaxy regions 82 in the p-region 50P can consist of materials that introduce compressive stress into the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The source / drain epitaxy regions 82 in the p-region 50P may also have surfaces that are raised relative to the respective surfaces of the fins 52, and they may have chamfers.

[0042] The source / drain epitaxy regions 82 and / or the fins 52 can be implanted with dopants to create source / drain regions, similar to the process discussed above for generating lightly doped source / drain regions, and they can subsequently be annealed. The source / drain regions can have a doping concentration of approximately 10 19 cm -3 up to about 10 21 cm -3 The aforementioned dopants can be used as the n- and / or p-doping agents for the source / drain regions. In some embodiments, the source / drain epitaxy regions 82 can be doped in situ during growth.

[0043] Due to the epitaxy processes used to generate the source / drain epitaxy regions 82 in the n-region 50N and the p-region 50P, the upper surfaces of the source / drain epitaxy regions have chamfers that extend laterally outwards beyond the side walls of the fins 52. In some embodiments, these chamfers cause adjacent source / drain regions 82 of the same FinFET to merge, as shown in Fig. Figure 10C shows that in other embodiments, adjacent source / drain regions 82 remain separated after completion of the epitaxy process, as shown in Fig. 10D is shown. In the embodiments shown in the Fig. 10C and Fig. As shown in Figure 10D, gate spacers 86 are manufactured to cover a portion of the fin sidewalls 52 that extends over the STI regions 56, thereby blocking epitaxial growth. In some further embodiments, the spacer etching used to manufacture the gate spacers 86 can be modified to remove the spacer material, allowing the epitaxially grown area to extend to the surface of the STI regions 56.

[0044] In the Fig. 11A and Fig. 11B will be a first interlayer dielectric (ILD) 88 over the one in the Fig. 10A and Fig. The structure shown in Figure 10B is deposited. The first ILD 88 can be made of a dielectric material and can be deposited using a suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials include phosphorus silicate glass (PSG), borosilicate glass (BSG), boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials deposited using a suitable method can also be used. In some embodiments, a contact etch stop layer (CESL) 87 is produced between the first ILD 88 and the source / drain epitaxy regions 82, the masks 74, and the gate spacers 86. The CESL 87 can have a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which has a lower etch rate than the material of the overlying first ILD 88.

[0045] In the Fig. 12A and Fig. 12B A planarization process, such as a CMP, can be performed to bring the top surface of the first ILD 88 to the same level as the top surfaces of the dummy gates 72 or the masks 74. The planarization process can also remove the masks 74 on the dummy gates 72, as well as portions of the gate seal spacers 80 and the gate spacers 86 along the side walls of the masks 74. After the planarization process, the top surfaces of the dummy gates 72, the gate seal spacers 80, the gate spacers 86, the CESL 87, and the first ILD 88 are at the same level. Therefore, the top surfaces of the dummy gates 72 are exposed by the first ILD 88. In some embodiments, the masks 74 can remain, and in this case, during the planarization process, the top of the first ILD 88 is brought to the same level as the tops of the masks 74.

[0046] In the Fig. From 13A to 17C, a gate cutting process is performed to create a gate isolation structure 130 (see Fig. 17A to 17C) which extends through certain of the dummy gates 72, thereby separating and structuring the dummy gates 72. In various embodiments, the gate cutting process can be used to define a structure of replacement gate structures to be manufactured subsequently.

[0047] Let's start with the Fig. 13A to 13C, in which a hard mask 120 can be deposited and structured over the first ILD 88, the dummy gates 72, the gate sealing spacers 80, the CESL 87 and the gate spacers 86. The hard mask 120 can be structured such that openings 122 are created which expose parts of the dummy gates 72. Fig. Figure 13 shows a top-down view of the hard mask 120 and the openings 122. The positions of the dummy gates 72 and the fins 52 are shown in the phantom for reference. As also shown in Fig. Figure 13C shows the positions of cross-sections A-A and B-B. For clarity, subsequent figures refer to these cross-sections. In particular, the Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A and Fig. 17A Representations along the cross-section A - A (e.g. in a direction parallel to a longitudinal direction of the fins 52) and through one of the openings 122, and the Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B and Fig. Figure 17C shows representations along the cross-section B - B (e.g. in a direction perpendicular to the longitudinal direction of the fins 52) and through one of the openings 122.

[0048] The material of the hard mask 120 can be selected such that it can be selectively structured with respect to the material of underlying layers, such as the dummy gates 72 and / or the first ILD 88. The hard mask 120 can, for example, comprise a suitable material such as silicon nitride, silicon oxide nitride, silicon carbon nitride, amorphous silicon, Al₂O₃, or the like, which is deposited using a suitable process such as PVD, CVD, ALD, combinations thereof, or the like.

[0049] The hard mask 120 can be structured, for example, using a combination of photolithography and etching, to include the openings 122 that expose portions of the dummy gates 72. The structure of the openings 122 can correspond to gate cutting positions of the dummy gates 72 (e.g., areas where adjacent portions of the dummy gates 72 are to be physically separated). Due to the etching process used to structure the hard mask 120, the width of the openings 122 on the top side of the hard mask 120 may be smaller than the width of the openings 122 on the bottom side of the hard mask 120. For example, the etching process may leave a slight overhang on the top side of the hard mask 120, resulting in a slightly smaller critical dimension (e.g., width) at the top ends of the openings 122 than at their bottom ends.

[0050] In the Fig. 14A and Fig. In 14B, the openings 122 are extended through the dummy gates 72 and the fins 52 into the substrate 50. Extending the openings 122 can be accomplished by one or more etching processes, such as dry etching, wet etching, or a combination thereof. For example, extending the openings 122 can involve a first etching process to remove portions of the dummy gates 72 and portions of the dielectric dummy layer 60 that are not covered by the hard mask 120. Subsequently, a second etching process can remove portions of the fins 52 that are not covered by the hard mask 120, thereby extending the openings 122 through the fins 52 and into the substrate 50. The second etching process can be the same etching process as the first etching process, which is used to remove parts of the dummy gates 72 and the dielectric dummy layer 60, or it can be a separate etching process.The second etching process can be a selective etching process that selectively etches the fins 52 and the substrate 50 at a higher rate than the STI areas 56. This allows the openings 122 to extend to different (i.e., smaller) depths in the STI areas 56 than in the substrate 50. Furthermore, the second etching process allows the fins 52 to be etched laterally at different depths with a different circumference. For example, a width W2 of the openings 122 on the top surface of the fins 52 can be smaller than a maximum width W1 of the openings 122 in the cross-section of . Fig. 14B. In some embodiments, the maximum width W1 can be 28 nm to 38 nm, and the width W2 can be 13 nm to 30 nm. Other dimensions are possible in other embodiments.

[0051] In the Fig. 15A and Fig. A dielectric coating 124 is deposited on the hard mask 120, on the side walls of the openings 122, and along the underside of the openings 122. The dielectric coating 124 may also be referred to below as a spacer 124 or a spacer layer 124. The dielectric coating 124 may consist of silicon nitride, silicon oxide nitride, silicon carbon nitride, silicon carbon oxide nitride, or the like, and is deposited using a non-conforming deposition process. Due to the non-conforming deposition process, the dielectric coating 124 may have different thicknesses when it extends along the side walls of the dummy gates 72. In some embodiments, the thickness T1 of the dielectric coating 124 on the top side of the first ILD 88 may differ from the thickness T2 of the dielectric coating 124 on the underside of the first ILD 88 or on the top sides of the fins 52.In particular, the thickness T1 can be smaller than the thickness T2, and the width W2 at an upper end of the openings 122 can be larger than a width W3 on the underside of the first ILD 88 or the upper sides of the fins 52. This advantageously enlarges a deposition window for a dielectric filler material subsequently deposited into the openings 122 to the increased width at the upper end of the openings 122 after deposition of the dielectric coating 124.

[0052] In the invention, the non-conforming deposition process is a PEALD process (PEALD: plasma-enhanced atomic layer deposition), in which plasma treatment is used to achieve the different widths of the dielectric coating 124 described above. In the PEALD process, precursor process gases, such as a nitrogen plasma (N₂ plasma), can be introduced into a deposition chamber. The precursor process gases can also include thermal SiH₂I₂ (which is heated, for example, to a gaseous state), hydrogen plasma (H₂ plasma), or the like, and / or combinations thereof, if the dielectric coating 124 comprises silicon nitride. By introducing a nitrogen plasma precursor as part of the PEALD process, a nitrogen plasma treatment is performed on the surfaces exposed by the openings 122.Nitrogen plasma treatment can worsen the incubation time for the deposition of the dielectric coating 124 at the upper ends of the openings 122 compared to their lower ends, resulting in a thinner dielectric coating 124 deposited at the upper ends of the openings 122 than at their lower ends. In some embodiments, the PEALD plasma treatment can be carried out, for example, at a temperature of 300 °C to 600 °C and at a pressure of 1.0 kPa to 12.0 kPa (7.5 Torr to 90 Torr) for a duration of 10 min to 60 min. In other embodiments, the PEALD process can be carried out with different process parameters.

[0053] In the Fig. 16A and Fig. In embodiment 16B, a dielectric filler material 126 is deposited in the openings 122 above the dielectric coating 124. In some embodiments, the dielectric filler material 126 can be a similar material (e.g., silicon nitride) to the dielectric coating 124. However, the dielectric filler material 126 can be deposited using a different process than the dielectric coating 124. For example, the dielectric filler material 126 can be deposited using a conformal process, such as an ALD process, instead of the non-conformal PEALD process used to deposit the dielectric coating 124. In some embodiments, the ALD process for depositing the dielectric filler material 126 can be a thermal process without the use of plasma.As part of the ALD process, the dielectric filler material 126 can be deposited onto the surfaces of the openings 122 until parts of the dielectric filler material 126 fuse together, defining a seam 128 and filling the openings 122. Due to the profile of the dielectric coating 124 (which is, for example, thinner at the upper ends of the openings 122), a deposition window for the dielectric filler material 126 can be enlarged, and relatively small seams 128 can form in the dielectric filler material 126. Furthermore, the seams 128 can have a cavity 128' in a lower part of the dielectric filler material 126, which can advantageously reduce the dielectric constant of the resulting gate insulation structure, thereby reducing parasitic capacitance.

[0054] In the Fig. In sections 17A to 17C, excess portions of the dielectric coating 124 and the dielectric filler material 126 (e.g., portions outside the openings 122) are removed by a planarization process. The hard mask 120 can also be removed by the planarization process. The planarization process can be a CMP process, a back-etching process, or the like, or a combination thereof. This results in gate isolation structures 130 that retain portions of the dielectric coating 124 and the dielectric filler material 126. The gate isolation structures 130 can be used to physically separate portions of the dummy gates 72 and to aid in defining the structure of replacement gate structures to be manufactured subsequently.

[0055] Based on the exemplary deposition processes described above, the gate isolation structures 130 can have certain advantageous dimensions. Fig. Figure 17C shows a detailed representation of the gate isolation structures 130 in a similar cross-section as Fig. 17B (e.g., along the aforementioned cross-section B-B). The dielectric coating 124 can have a transverse dimension D1 on the top surface of the fin 52 (e.g., on a plane of the underside of the first ILD 88) and a transverse dimension D2 on a plane of the top surface of the first ILD 88. The transverse dimension D2 can be smaller than the transverse dimension D1 due to the deposition process used to produce the dielectric coating 124 (e.g., PEALD with nitrogen plasma). In some embodiments, the transverse dimension D1 can be 3.8 nm to 22.5 nm, while the transverse dimension D2 can be 3 nm to 18 nm. A ratio of the transverse dimension D1 to the transverse dimension D2 can be, for example, 1.1 to 1.5.It has been found that producing the dielectric coating 124 with the aforementioned dimensions / profiles offers advantages, such as an increase in the deposition window for the dielectric filler material 126, thereby reducing the size of the seam 128 and manufacturing defects. For example, the seam 128 can have a transverse dimension D4 in an upper part of the gate insulation structure 130 of 1.5 nm to 9 nm. It has been found that producing a seam with the aforementioned dimensions advantageously reduces manufacturing defects. In particular, a seam with the aforementioned dimensions can be so small that the risk of over-etching the gate insulation structure 130 or the entrapment of metal particles in the seam during subsequent contact manufacturing processes and the resulting short circuits is avoided.Furthermore, the seam 128 in a lower part of the gate isolation structure 130 can have a cavity 128' which can have a transverse dimension D3 of 0.5 nm to 3 nm at its widest point in a cross-sectional view. The transverse dimension D3 of the cavity 128' can be larger than the transverse dimension D4 of the upper part of the seam 128. It has been found that by using a cavity with the aforementioned dimensions, the dielectric constant of the gate isolation structure 130 can be reduced, thereby lowering the parasitic capacitance. Furthermore, the dielectric filler material 126 has a transverse dimension D5 on the same plane as the top of the first ILD 88, a transverse dimension D6 on the top of the fin 52 (e.g. on the same plane as the bottom of the first ILD 88) and a transverse dimension D7 at a widest point of the dielectric filler material 126 in a sectional view (e.g. in the fin 52).The transverse dimension D5 can be larger than the transverse dimension D6, and the transverse dimension D7 can each be larger than the transverse dimensions D5 and D6. In some embodiments, the transverse dimension D5 can be 3.3 nm to 19.5 nm, the transverse dimension D6 can be 2.5 nm to 15 nm, and the transverse dimension D7 can be 5 nm to 15 nm. For example, the ratio of transverse dimension D6 to transverse dimension D5 can be 0.7 to 0.9, and the ratio of transverse dimension D6 to transverse dimension D7 can be 0.4 to 0.6.

[0056] The Fig. Figures 18A to 22B show the following steps for replacing the dummy gates 72 with functional gate stacks and for creating various contacts. Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A and Fig. Figure 22A shows representations along the cross-section A - A (e.g. in a direction parallel to a longitudinal direction of the fins 52) and through one of the gate isolation structures 130, and the Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B and Fig. Figure 22B shows representations along the cross-section B - B (e.g. in a direction perpendicular to the longitudinal direction of the fins 52) and through one of the gate isolation structures 130. Fig. Figures 19C to 19F show different representations of the device after the functional gate stacks have been manufactured.

[0057] In the Fig. 18A and Fig. In embodiment 18B, the dummy gates 72 are removed in one or more etching steps, creating recesses 90. Portions of the dielectric dummy layer 60 within the recesses 90 may also be removed. In some embodiments, only the dummy gates 72 are removed, and the dielectric dummy layer 60 remains and is exposed by the recesses 90. In some embodiments, the dielectric dummy layer 60 is removed from the recesses 90 in a first region of a die (e.g., a logic core region) and remains in the recesses 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gates 72 are removed using an anisotropic dry etching process.The etching process can, for example, be a dry etching process using one or more reactive gases that selectively etch the dummy gates 72, but only minimally or not at all etch the first ILD 88, the gate isolation structures 130, and the gate spacers 86. Each recess 90 exposes and / or overlays a channel region 58 of a respective fin 52. Each channel region 58 is positioned between adjacent pairs of source / drain epitaxy regions 82. During removal, the dielectric dummy layer 60 can be used as an etch stop layer when etching the dummy gates 72. The dielectric dummy layer 60 can optionally be removed after the dummy gates 72 have been removed.

[0058] In the Fig. 19A to 19F are used to manufacture dielectric gate layers 92 and gate electrodes 94 for replacement gates. Fig. Figure 19F shows a top-down view and the positions of various cross-sections. Fig. 19A shows a sectional view along a line A - A of Fig. 19F (e.g., through the gate isolation structure 130). Fig. 19B shows a sectional view along a line B - B of Fig. 19F (e.g., through the gate isolation structure 130). Fig. 19C shows a sectional view along a line C - C of Fig. 19F (which, for example, does not extend through the gate isolation structure 130 and is parallel to the cross-section A - A), and Fig. 19D shows a sectional view along a line D - D of Fig. 19F (which, for example, does not extend through the gate isolation structure 130 and is parallel to the cross-section B - B). Fig. Figure 19E shows a detailed representation of area 89 of the Fig. 19B and Fig. 19D.

[0059] The dielectric gate layers 92 comprise one or more layers deposited in the recesses 90, for example, on the top surfaces and side walls of the fins 52 and on the side walls of the gate gasket spacers 80 and the gate spacers 86. The dielectric gate layers 92 can also be produced on the top surface of the first ILD 88. In some embodiments, the dielectric gate layers 92 comprise one or more dielectric layers, such as silicon oxide, silicon nitride, a metal oxide, a metal silicate, or the like. For example, in some embodiments, the dielectric gate layers 92 comprise an interface layer of silicon oxide produced by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.The dielectric gate layers 92 can comprise a dielectric layer with a k-value greater than approximately 7.0. Molecular beam deposition (MBD), ALD, PECVD, and the like can be used as manufacturing processes for the dielectric gate layers 92. In embodiments where parts of the dummy gate dielectric 60 remain in the recesses 90, the dielectric gate layers 92 comprise the material of the dummy gate dielectric 60 (e.g., SiO2).

[0060] The gate electrodes 94 are deposited over the dielectric gate layers 92 and fill the remaining portions of the recesses 90. The gate electrodes 94 can be made of a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, or tungsten, combinations thereof, or multilayers thereof. Although in the Fig. 19B and Fig. Figure 19D shows a single-layer gate electrode 94. The gate electrode 94 can have any number of coating layers 94A, any number of output work adjustment layers 94B, and a filler material 94C, as shown in Fig. Figure 19E shows that in some embodiments, the order of the coating layers 94A and the output work setting layers 94B can be reversed. After filling the recesses 90, a planarization process, such as CMP, can be performed to remove the excess portions of the dielectric gate layers 92 and the gate electrode material 94 located above the top surface of the first ILD 88. The remaining portions of the gate electrode material 94 and the dielectric gate layers 92 thus form substitute gates of the resulting FinFETs. The gate electrodes 94 and the dielectric gate layers 92 can be collectively referred to as a “gate stack.” The gate and the gate stack can extend along the side walls of the channel region 58 of the fins 52.Furthermore, each of the gate insulation structures 130 separates an adjacent first and second gate stack (each having a dielectric gate layer 92 and a corresponding gate electrode 94), as shown in the . Fig. 19A and Fig. 19F is shown.

[0061] The dielectric gate layers 92 can be fabricated simultaneously in the n-region 50N and the p-region 50P, so that they consist of the same materials in each region, and the gate electrodes 94 can likewise be fabricated simultaneously in each region, so that they also consist of the same materials. In some embodiments, the dielectric gate layers 92 in each region can be fabricated using different processes, so that they may have different materials, and / or the gate electrodes 94 in each region can be fabricated using different processes, so that they may have different materials. Different masking steps can be used to mask and expose corresponding regions when different processes are used.

[0062] In the Fig. 20A and Fig. In embodiment 20B, a gate mask 96 is fabricated over the gate stacks (which comprise a dielectric gate layer 92 and a corresponding gate electrode 94). This gate mask can be positioned between opposing portions of the gate spacers 86. In some embodiments, fabricating the gate mask 96 involves recessing the gate stack, creating a recess directly above the gate stack and between opposing portions of the gate spacers 86. The recess can also expose sidewalls of the gate insulation structures 130. The gate mask 96 can extend further along the sidewalls of the gate insulation layers. A gate mask 96, comprising one or more layers of dielectric material such as silicon nitride, silicon oxide nitride, or the like, is filled into the recess, and subsequently, excess portions of the dielectric material extending over the first ILD 88 are removed by a planarization process.The gate mask 96 is optional and can be omitted in some embodiments. In these embodiments, the gate stack can be at the same level as the top of the first ILD 88.

[0063] As also in the Fig. 20A and Fig. As shown in Figure 20B, in some embodiments, first-level source / drain contacts 112 are produced by the first ILD 88. Openings for the source / drain contacts 112 are created by the first ILD 88. The openings can be produced using suitable photolithography and etching processes. A coating (not shown), such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are deposited in the openings. The coating can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Excess material can be removed from the top surface of the first ILD 88 by a planarization process, such as CMP. The remaining coating and conductive material form the source / drain contacts 112 in the openings.A silicide can be produced at an interface between the source / drain epitaxy regions 82 and the source / drain contacts 112 by means of a tempering process. The source / drain contacts 112 are physically and electrically connected to the source / drain epitaxy regions 82. Due to the relatively small size of the seams 128, the source / drain contacts 112 can be manufactured in such a way that the gate insulation structures 130 are not damaged (e.g., by over-etching and unwanted inclusion of metal particles).

[0064] In the Fig. 21A and Fig. In 21B, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable layer produced by flowable CVD. In some embodiments, the second ILD 108 is made from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and it can be deposited by a suitable method such as CVD and PECVD. Gate contacts 110 produced later ( Fig. 16A and Fig. 16B) penetrate the second ILD 108 and the gate mask 96 (if present) to contact the top of the recessed gate electrode 94.

[0065] In the Fig. 22A and Fig. In some embodiments of 22B, gate contacts 110 and second-level source / drain contacts 114 are produced by the second ILD 108. Openings for the source / drain contacts 114 are created by the second ILD 108 up to the first-level source / drain contacts 112, and openings for the gate contacts 110 are created by the second ILD 108 and the gate mask 96 (if present). The openings can be produced by suitable photolithography and etching processes. A coating (not shown), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are deposited in the openings. The coating can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Excess material can be removed from the top of the second ILD 108 using a planarization process, such as CMP.The remaining coating and conductive material form the source / drain contacts 114 and the gate contacts 110 in the openings. The source / drain contacts 114 are physically and electrically connected to the source / drain contacts 112, and the gate contacts 110 are physically and electrically connected to the gate electrodes 106. The source / drain contacts 112 and the gate contacts 110 can be manufactured in different processes or in the same process. Although it is shown that the source / drain contacts 112 and the gate contacts 110 are manufactured in the same cross-sections, it is understood that they can each be manufactured in different cross-sections, thus preventing short-circuiting of the contacts. Furthermore, the materials chosen for the source / drain contacts 114 can be the same as, or different from, those used for the source / drain contacts 112 and / or the gate contacts 110.In this way, FinFET devices are manufactured in the semiconductor device 100 with gate isolation structures 130 that separate adjacent gate stacks 92 / 94.

[0066] The Fig. Figures 1 to 22B show a specific configuration of the gate isolation structure 130. Other embodiments may have different configurations of the gate isolation structure 130. For example, the Fig. 23A and Fig. 23B a device 150 according to some embodiments. Fig. 23A shows a representation along the cross-section A - A of Fig. 1 and through a gate isolation structure 130, and Fig. 23B shows a representation along the cross-section B - B of Fig. 1 and by a gate isolation structure 130. The device 150 may be similar to the device 100, where similar reference numerals denote similar elements manufactured by similar processes. In contrast to the device 100, which has cavities 128' in the lower portions of the seam 128, the gate isolation structures 130 in the device 150 do not have cavities 128'. The cavities 128' can be omitted, for example, by controlling the deposition process for the dielectric filler material 126 and / or by controlling aspect ratios of the openings into which the dielectric filler material 126 is deposited. The seam 128 may have a relatively small transverse dimension to achieve the aforementioned advantages.

[0067] As another example, the Fig. 24A and Fig. 24B a device 200 according to some embodiments. Fig. 24A shows a representation along the cross-section A - A of Fig. 1 and through a gate isolation structure 130, and Fig. 24B shows a representation along the cross-section B - B of Fig. 1 and by the gate isolation structure 130. The device 200 may be similar to the device 100, where similar reference numerals denote similar elements manufactured by similar processes. In contrast to the device 100, in which the dielectric coating 124 does not fuse, the gate isolation structures 130 in the device 200 may have a fused dielectric coating 124 extending continuously from a side wall of a first gate stack to a side wall of a second gate stack. In particular, a lower portion of the dielectric coating 124 (e.g., a portion located in the fin 52, the substrate 50, and the STI area 56) may fuse onto the top surface of the fin 52 / STI area 56. The lower portion of the dielectric coating 124 may also have a cavity 132 formed by the fusion.The filler material 126 can be arranged above the fused lower part of the dielectric coating 124 and can have the seam 128, which has a relatively small transverse dimension in order to achieve the aforementioned advantages.

[0068] As another example, the Fig. 25A and Fig. 25B a device 250 according to some embodiments. Fig. 25A shows a representation along the cross-section A - A of Fig. 1 and through a gate isolation structure 130, and Fig. 25B shows a representation along the cross-section B - B of Fig. 1 and by the gate isolation structure 130. The device 250 may be similar to the device 100, where similar reference numerals denote similar elements that are manufactured by similar processes. In contrast to the device 100, in which the dielectric coating 124 directly contacts the dielectric filler material 126, the gate isolation structure 130 in the device 250 may also have a further dielectric coating 134 between the dielectric coating 124 and the dielectric filler material 126. In some embodiments, the dielectric coating 134 may comprise an oxide material, such as an oxide of the material of the dielectric coating 124. For example, if the dielectric coating 124 comprises silicon nitride, the dielectric coating 134 may comprise silicon oxide nitride. The dielectric coating 134 can be an intrinsic oxide that is formed when the dielectric coating 124 is exposed to the atmosphere, causing it to oxidize.In some embodiments, the dielectric coating 124 can be exposed to the atmosphere while the device 250 is transported between deposition tools (e.g., a PEALD tool used to deposit the dielectric coating 124 and an ALD tool used to deposit the dielectric filler material 126). Other coating materials for the dielectric coating 124 are also possible.

[0069] The disclosed FinFET embodiments could also be used for nanostructured devices, such as nanostructured field-effect transistors (NSFETs; e.g., nanolayer, nanowire, gate-all-around, or similar field-effect transistors). In one NSFET embodiment, the fins are replaced by nanostructures created by structuring a stack of alternating channel layers and sacrificial layers. Similar to the embodiments described above, dummy gate stacks and source / drain regions are created. Gate isolation structures are also fabricated to extend through the dummy gate stacks, as described above. After the dummy gate stacks are removed, the sacrificial layers in the channel regions can be partially or completely removed. The replacement gate structures are fabricated in a similar manner to the embodiments described above.The replacement gate structures can partially or completely fill openings created by removing the sacrificial layers, and they can partially or completely enclose the channel layers in the channel regions of the NSFET devices. ILDs and contacts with the replacement gate structures and the source / drain regions can be fabricated in a similar manner to the embodiments described above.

[0070] Fig. Figure 26 shows a perspective view of an NSFET according to some embodiments. Fig. 27A and Fig. Figure 27B shows sectional views of various exemplary gate isolation structures 130 in an NSFET context. Fig. 26 NSFET devices have nanostructures 55 (e.g., nanolayers, nanowires, or the like) arranged over fins 52 on a substrate 50 (e.g., a semiconductor substrate), the nanostructures 55 acting as channel regions for the NSFET devices. The nanostructures 55 can be p-nanostructures, n-nanostructures, or a combination thereof. STI regions 56 are arranged between adjacent fins 52, which can extend over and between adjacent STI regions 56. A dielectric gate material 92 is arranged over the top surfaces of the fins 52 and along the top, side, and bottom surfaces of the nanostructures 55. Gate electrodes 94 are arranged over the dielectric gate material 92. Source / drain epitaxy regions 82 are arranged on the fins 52 on opposite sides of the gate stacks 92 / 94.

[0071] Fig. Figure 23 also shows reference cross-sections that are used in later figures. A cross-section X - X runs along a longitudinal axis of the gate electrode 94 and, for example, in a direction perpendicular to a current flow direction between the source / drain epitaxy regions 82 of an NSFET device. A cross-section Y - Y is perpendicular to the cross-section X - X and is parallel to a longitudinal axis of a fin 52 of the NSFET device and, for example, in a current flow direction between the source / drain epitaxy regions 82 of the NSFET devices. Fig. Figure 27A shows an exemplary NSFET device in which a gate isolation structure 130 (as described above with reference to the Fig. (as described in sections 1 to 22B) is integrated along the cross-section X - X of Fig. 26, and Fig. Figure 27B shows the NSFET device in which the gate isolation structure 130 is integrated, along the cross-section Y - Y of Fig. 26. Various structural elements of the Fig. 26 to 27B may be similar to those mentioned above with reference to the Fig. 1 to 22B have been described, where similar reference numbers denote similar elements that are produced using similar processes. Fig. 27A and Fig. Figure 27B shows the gate isolation structures 130 in an NSFET device context. Fig. 27A and Fig. Figure 27B shows gate isolation structures 130 according to the device 100 described above, but in other embodiments gate isolation structures 130 according to one of the devices 150, 200 or 250 described above may also be used.

[0072] In various embodiments, a gate isolation structure can include: a dielectric coating (occasionally referred to as a spacer) deposited with a conical profile using a non-conforming deposition process; and a dielectric filler material deposited over the dielectric coating. By maintaining the conical profile in the dielectric coating, a relatively large width can remain at the top of the opening, thus improving the deposition window for the dielectric filler material. Therefore, the dielectric filler material can be deposited with fewer manufacturing defects, such as reduced seams / voids. Reducing the size / number of seams / voids, in turn, reduces electrical defects (e.g., short circuits) that might otherwise occur during subsequent processing steps (e.g.,(during the manufacture of gate or source / drain contacts) a conductive material is unintentionally trapped in exposed seams.

[0073] In some embodiments, a semiconductor device comprises: a first transistor with a first gate stack and first source / drain regions on opposite sides of the first gate stack; a second transistor with a second gate stack and second source / drain regions on opposite sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack, wherein the gate isolation structure comprises: a dielectric coating of varying thickness along sidewalls of the first and second gate stacks, the thickness resulting from a non-conforming deposition process in the form of a plasma-enhanced atomic layer deposition (PEALD) process, in which the dielectric coating is deposited thinner at the upper end of the aperture than at its lower end, and a dielectric filler material above the dielectric coating.wherein the dielectric filler material has a seam. Optionally, in some embodiments, the dielectric coating has a lateral portion along a bottom surface of the dielectric filler material, wherein the varying thickness of the dielectric coating increases in the direction of the lateral portion of the dielectric coating. Optionally, in some embodiments, a cavity is arranged in a lower portion of the seam, wherein the cavity is wider than an upper portion of the seam. Optionally, in some embodiments, the semiconductor device further comprises a second dielectric coating between the dielectric coating and the dielectric filler material. Optionally, in some embodiments, the dielectric coating comprises a first dielectric material,and the second dielectric layer comprises an oxide of the first dielectric material. Optionally, in some embodiments, the dielectric layer extends continuously from a side wall of the first gate stack to a side wall of the second gate stack. Optionally, in some embodiments, the semiconductor device further comprises a cavity in a lower part of the dielectric layer.

[0074] In some embodiments, a semiconductor device comprises: the first gate stack in an interlayer dielectric; the second gate stack in the interlayer dielectric; and the gate isolation structure between the first and second gate stacks, wherein the gate isolation structure contacts a side wall of the first gate stack and a side wall of the second gate stack. The gate isolation structure comprises: the dielectric coating, wherein a first transverse dimension of the dielectric coating is smaller than a second transverse dimension of the dielectric coating, wherein the first transverse dimension of the dielectric coating is measured in a plane of a top surface of the interlayer dielectric, and the second transverse dimension of the dielectric coating is measured in a plane of a bottom surface of the interlayer dielectric.on the top surface of a fin; and the dielectric filler material above the dielectric coating, wherein the dielectric filler material has a seam. Optionally, in some embodiments, a first transverse dimension of the dielectric filler material is larger than a second transverse dimension of the dielectric filler material, wherein the first transverse dimension of the dielectric filler material is measured in the plane of the top surface of the interlayer dielectric and the second transverse dimension of the dielectric filler material is measured in the plane of the bottom surface of the interlayer dielectric. Optionally, in some embodiments, the ratio of the second transverse dimension of the dielectric filler material to its first transverse dimension is 0.7 to 0.9.Optionally, in some embodiments, a third transverse dimension of the dielectric filler material is larger than the first and second transverse dimensions of the dielectric filler material, wherein the third transverse dimension is measured at a widest point of the dielectric filler material in a sectional view and in a plane below the underside of the interlayer dielectric. Optionally, in some embodiments, the ratio of the second transverse dimension of the dielectric filler material to its third transverse dimension is 0.4 to 0.6. Optionally, in some embodiments, the seam has an upper part and a lower part, wherein the lower part has a cavity with a larger transverse dimension than the upper part. Optionally, in some embodiments, the ratio of the second transverse dimension of the dielectric coating to its first transverse dimension is 1.1 to 1.5.

[0075] In some embodiments, a method comprises the following steps: structuring an opening such that it extends through a dummy gate stack; depositing a dielectric coating on side walls and a bottom of the opening, wherein the deposition of the dielectric coating is carried out by a non-conforming deposition process; depositing a dielectric filler material in the opening above the dielectric coating, wherein the deposition of the dielectric filler material is carried out by a different type of deposition process than the deposition of the dielectric coating and includes creating a seam in the dielectric filler material; removing the dummy gate stack; and creating a first gate stack and a second gate stack on opposite sides of the dielectric coating.According to the invention, the non-conforming deposition process is a plasma-assisted atomic layer deposition (PEALD) process, wherein in the PEALD process the dielectric coating is deposited at an upper end of the opening in a thinner layer than at its lower end. Optionally, in some embodiments, the dielectric filler material is deposited using an atomic layer deposition (ALD) process. Optionally, in some embodiments, the PEALD process includes a nitrogen plasma treatment. Optionally, in some embodiments, the non-conforming deposition process includes fusing the dielectric coating at a lower part of the opening. Optionally, in some embodiments, the process further includes oxidizing the dielectric coating prior to the deposition of the dielectric filler material.

Claims

[1] Semiconductor device with: a first transistor with a first gate stack (92, 94) and first source / drain regions (82) on opposite sides of the first gate stack (92, 94); a second transistor with a second gate stack (92, 94) and second source / drain regions (82) on opposite sides of the second gate stack (92, 94); and a gate isolation structure (130) that separates the first gate stack (92, 94) from the second gate stack (92, 94), wherein the gate isolation structure (130) has the following: a dielectric coating (124) with a varying thickness along side walls of the first (92, 94) and second gate stack (92, 94), and a dielectric filler material (126) over the dielectric coating (124), wherein the dielectric filler material (126) has a seam (128), wherein the dielectric coating (124) extends continuously from a side wall of the first gate stack (92, 94) to a side wall of the second gate stack (92, 94), wherein the dielectric coating (124) is deposited on side walls and a bottom of an opening (122) by a non-conforming deposition process, wherein the non-conforming deposition process is a plasma-assisted atomic layer deposition (PEALD) process which deposits a thinner layer at an upper end of the opening (122) than at a lower end of the opening (122). [2] Semiconductor device according to claim 1, wherein the dielectric coating (124) has a laterally extending part between the filler material and a flat trench insulation (56). [3] Semiconductor device according to claim 1 or 2, wherein a cavity (128') is arranged in a lower part of the seam (128), wherein the cavity (128') is wider than an upper part of the seam (128) and a maximum width of the gate insulation structure lies below a top surface of a fin into which the gate insulation structure extends. [4] Semiconductor device according to one of the preceding claims, further comprising a second dielectric coating between the dielectric coating (124) and the dielectric filler material (126). [5] Semiconductor device according to claim 4, wherein the dielectric coating (124) comprises a first dielectric material and the second dielectric coating comprises an oxide of the first dielectric material (124). [6] Semiconductor device according to one of the preceding claims, further comprising a cavity (132) in a lower part of the dielectric coating (124), wherein a maximum width of the gate insulation structure lies below a top surface of a fin into which the gate insulation structure extends. [7] Procedure with the following steps: Structuring an opening (122) such that it extends through a dummy gate stack (72); Deposition of a dielectric coating (124) on side walls and a bottom of the opening (122), wherein the deposition of the dielectric coating (124) is carried out using a non-conforming deposition process; Deposition of a dielectric filler material (126) in the opening (122) over the dielectric coating (124), wherein the deposition of the dielectric filler material (126) is carried out using a different type of deposition process than the deposition of the dielectric coating (124) and includes the creation of a seam (128) in the dielectric filler material (126); Removing the dummy gate stack (72); and Creating a first gate stack (92, 94) and a second gate stack (92, 94) on opposite sides of the dielectric coating (124), wherein the non-conforming deposition process is a plasma-assisted atomic layer deposition process, PEALD process, wherein in the PEALD process the dielectric coating (124) is deposited at an upper end of the aperture (122) thinner than at the lower end of the aperture (122). [8] Method according to claim 7, wherein the deposition of the dielectric filling material (126) is carried out using an atomic layer deposition process, ALD process. [9] Method according to claim 7, wherein the PEALD process comprises performing a nitrogen plasma treatment. [10] Method according to any one of claims 7 to 9, wherein the non-conforming deposition process comprises fusing the dielectric coating (124) at a lower part of the opening (122). [11] Method according to any one of claims 7 to 10, further comprising oxidizing the dielectric coating (124) before depositing the dielectric filling material (126).

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