Semiconductor processing equipment and method for reducing layout dimensions using a non-perpendicular process arrangement

The integration of a non-perpendicular particle bombardment process post-photolithography addresses the limitations of end-to-end separation distances, enabling more efficient use of wafer area and denser interconnect structures in semiconductor manufacturing.

DE102022100197B4Active Publication Date: 2026-06-03TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Filing Date
2022-01-05
Publication Date
2026-06-03

AI Technical Summary

Technical Problem

Existing photolithographic processes struggle to produce structural elements with small end-to-end separation distances, leading to inefficient use of wafer area and limitations in integrating conductive vias and other interconnect structures.

Method used

A semiconductor processing system that incorporates a non-perpendicular particle bombardment process following photolithography to reduce end-to-end separation distances by bombarding photoresist sidewalls with angled particles, allowing for more precise and efficient layout adjustments.

Benefits of technology

Enables the placement of conductive vias closer together, optimizing wafer area utilization and improving the density of interconnect structures without requiring additional masks, thus enhancing the overall efficiency of semiconductor manufacturing.

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Abstract

The process, which is carried out by a semiconductor processing system (100), comprises the following steps: Store, in a layout database (110) of the semiconductor processing plant, layout data associated with an initial layout (112) for a wafer (102); Extracting, by means of a layout analyzer (114) of the semiconductor processing equipment (100), layout structural element data (116) that specify dimensions associated with structural elements of the first layout (112), from the layout data; Compare, using the layout analyzer (114) of the semiconductor processing equipment (100), the layout structural element data (116) with selection rules; and Selecting, by the layout analyzer (114) of the semiconductor processing equipment (100), a non-vertical particle bombardment process to implement the first layout (112) in the wafer (102) in response to the layout structural element data (116) that satisfy the selection rules.
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