COMMON TUBE STRUCTURE, LAYOUT AND PROCEDURE

Abstract

Integrated circuit structure, IC structure (100), comprising: a first continuous trough (WA, WB) which is one of an n-trough or a p-trough, wherein the first continuous trough (WA, WB) a first trough section (WAS, WBS) that runs in a first direction (Y); a second trough section (WAPn, WBPn) extending in a second direction (X, -X) orthogonal to the first direction (Y) from the first trough section (WAS, WBS); and a third trough section (WAPn, WBPn) extending parallel to the second trough section (WAPn, WBPn) in the second direction (X, -X) from the first trough section (WAS, WBS), exhibits; a second continuous trough (WB, WA) which is the other of the n-trough or the p-trough, wherein the second continuous trough (WB, WA) a fourth trough section (WBS, WAS) that runs in the first direction (Y); a fifth trough section (WBPn, WAPn) extending in a third direction (-X, X) opposite to the second direction (X, -X) from the fourth trough section (WBS, WAS); and a sixth trough section (WBPn, WAPn) extending in the third direction (-X, X) and parallel to the fifth trough section (WBPn, WAPn) from the fourth trough section (WBS, WAS), exhibits; a third continuous tub, which a seventh tub section running in the first direction (Y); an eighth tub section extending in the second direction (X, -X) from the seventh tub section; and a ninth tub section, which extends in the second direction (X, -X) parallel to the eighth tub section from the seventh tub section, exhibits; and a silicon through-hole structure, TSV structure (TSVS), positioned between the third continuous well and the first and second continuous wells (WB, WA); wherein the first and second continuous troughs (WB, WA), the TSV structure (TSVS) and the third continuous trough are aligned along the second direction (X, -X).

Description

BACKGROUND

[0001] The ongoing trend toward miniaturization of integrated circuits (ICs) has led to ever smaller devices that consume less power but offer greater functionality at higher speeds than previous technologies. This miniaturization has been achieved through design and manufacturing innovations that adhere to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, revise, and verify designs for semiconductor devices while ensuring that the design and manufacturing specifications of the IC structures are met.

[0002] US 2020 / 0 143 874 A1 and US 2021 / 0 098 470 A1 describe integrated circuit structures with wells shared by more than two rows of IC devices, each having a first section running in a direction orthogonal to the rows and several sections extending from the first section into the rows. US 2021 / 0 157 751 A1 describes a stacking and via-plating of integrated circuit structures. US 2012 / 0 304 142 A1 describes a placement of silicon vias in standard cell logic blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The invention is defined by the integrated circuit structures and the method for fabricating an integrated circuit structure according to the independent claims. The dependent claims define preferred embodiments. Aspects of the present disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1A is a diagram of an IC structure according to some embodiments. Fig. Figure 1B is a diagram of an IC structure according to some embodiments. Fig. 1C is a diagram of an IC package according to some embodiments. Fig. Figure 2 is a flowchart of a method for operating an IC component according to some embodiments. Fig. Figure 3 is a flowchart of a process for manufacturing an IC structure according to some embodiments. Fig. Figure 4 is a diagram of IC layout diagrams according to some embodiments. Fig. Figure 5 is a flowchart of a method for generating an IC layout diagram according to some embodiments. Fig. 6A to 6C are diagrams of IC layout diagrams according to some embodiments. Fig. Figure 7 is a flowchart of a method for generating an IC layout diagram according to some embodiments. Fig. Figure 8 is a block diagram of an IC layout diagram generation system according to some embodiments. Fig. Figure 9 is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, steps, activities, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples. Other components, values, activities, materials, arrangements, or the like are envisaged. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples in this disclosure. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially related terms such as "below," "under," "below," "above," "over," and the like can be used here to simplify the description and to describe the relationship of one element or feature to another element(s) or feature(s) as depicted in the figures. These spatially related terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially related terms used here can be interpreted accordingly.

[0006] In various embodiments, an IC structure based on an IC layout diagram features a well shared by more than two rows of IC devices. This well comprises a first section extending in a direction orthogonal to the rows and several sections extending from the first section into the rows. The first section corresponds to a boundary of an IC block containing the IC devices, such as a block between through-silicon vias (TSVs) or a location within such a block. The IC block containing the shared well provides latch-up protection by accommodating a single pick-up structure, for example.A portion of a tap cell allows each of the multiple sections to be prestressed, so that the shared trough is prestressed using a number of tap structures that is less than the number of multiple sections. Compared to approaches where a row or pair of rows of IC devices corresponds to a single trough with at least one tap structure, the IC block containing the shared trough uses fewer tap structures, thus enabling improved space utilization for the IC devices.

[0007] Fig. Figure 1A is a diagram of an IC structure 100 according to some embodiments. The IC structure 100, which in some embodiments is also referred to as IC block 100, corresponds to a circuit section, e.g., a digital circuit block, of the substrate of an IC die, e.g., an IC structure 100D, which is described below with reference to Fig. 1B is discussed, and in some embodiments is further integrated into an IC package, e.g., one described below with reference to Fig. The IC package 100P, discussed in section 1C, has been included. In addition to the IC structure 100, it shows... Fig. 1A the directions X and Y.

[0008] The IC structure 100 is an example of an IC structure that can be implemented by performing the following steps with reference to Fig. 3 discussed procedure 300 or part thereof based on an IC layout diagram, e.g. an IC layout diagram 600A to 600C, which is shown below with reference to Fig. 6A to 6C will be discussed and produced.

[0009] Fig. Figure 1A shows a top view of the IC structure 100 (its XY plane), which has boundary regions 100A and 100B extending in the Y direction, as well as IC devices 100C located between the boundary regions 100A and 100B. In the embodiment shown in Fig. As shown in Figure 1A, five rows R1 to R5 of IC devices 100C extend in the X direction, which in some embodiments is also referred to as the row direction.

[0010] The IC structure 100 has a continuous well WA, which in some embodiments is also referred to as a shared well WA, comprising a section WAS located in the boundary region 100A and extending in the Y-direction, and sections WAP1 to WAP3 extending from section WAS in the positive X-direction within one or more corresponding rows R1 to R5. A continuous well WB, which in some embodiments is also referred to as a shared well WB, comprises a section WBS located in the boundary region 100B and extending in the Y-direction, and sections WBP1 to WBP3 extending in the negative X-direction within one or more corresponding rows R1 to R5.The IC structure 100 also includes at least one instance of a receiver structure PA located in the continuous trough WA and at least one instance of a receiver structure PB located in the continuous trough WB, as discussed below.

[0011] The alignment of the in Fig. The IC structure 100 shown in Figure 1A is an example provided for illustrative purposes. In some embodiments, the boundary regions 100A and 100B and the sections WAS and WBS extend in the X direction, while the rows R1 to R5 and the sections WAP1 to WAP3 and WBP1 to WBP3 extend in the Y direction. In some embodiments, the IC structure 100 has an orientation that differs from that shown in Figure 1A. Fig. The orientation shown in 1A is reversed horizontally and / or vertically.

[0012] Each of the figures in this revelation, e.g. Fig. Figure 1A is simplified for illustrative purposes. The figures show views of IC structures, dies, packages, and layout diagrams, with various elements included and omitted to simplify the discussion below. In various embodiments, a depicted IC structure, die, package, and / or layout diagram may, in addition to the elements shown in Figure 1A, include the following: Fig. Figures 1A to 1C, 4 and 6A to 6C show one or more elements corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures or other transistor elements, insulation structures or the like.

[0013] In various embodiments, IC devices 100C include a logic gate or other digital circuit or a combination thereof, a component of a signal or application processor, a memory, a high-bandwidth memory (HBM), a system on an IC (SoIC), a transmitter and / or receiver, an application-specific IC (ASIC), a large-scale integration (LSI) or very large-scale integration (VLSI) circuit, a voltage or current regulator, or the like.

[0014] IC devices 100C feature both n-type metal oxide-semiconductor transistors (NMOS transistors) and p-type metal oxide semiconductor transistors (PMOS transistors) (not shown). The NMOS transistors are located in one of the continuous wells WA or WB, and the PMOS transistors are located in the other continuous well WA or WB.

[0015] In the embodiment that is in Fig. As shown in Figure 1A, IC devices 100C extend along each of the rows R1 to R5 with a height CH1, which in some embodiments is also referred to as cell height CH1, from the boundary region 100A to the boundary region 100B. In various embodiments, the IC structure 100 features IC devices 100C that are designed differently, e.g., having one or more gaps in one or more rows and / or extending partially between the boundary regions 100A and 100B in one or more rows, such that the NMOS and PMOS transistors are located in the continuous wells WA and WB.

[0016] In the embodiment that is in Fig. As shown in Figure 1A, the IC devices correspond to each of a total of five rows R1 to R5 of the IC structure 100. In different embodiments, IC devices 100C correspond to each of fewer or more than a total of five rows and / or one subset of the total number of rows of the IC structure 100.

[0017] The IC structure 100 is configured such that it has a total area which includes at least one area occupied by the IC devices 100C and the boundary regions 100A and 100B. In some embodiments, the total area of ​​the IC structure 100 is equal to the total area occupied by the IC devices 100C and the boundary regions 100A and 100B. In some embodiments, the total area of ​​the IC structure 100 is larger than the total area occupied by the IC devices 100C and the boundary regions 100A and 100B, and the IC structure 100 has, in addition to the IC devices 100C and the boundary regions 100A and 100B, one or more regions (not shown), e.g., one or more dummy devices.

[0018] A well, e.g., the continuous well WA or WB, is a continuous section of a semiconductor wafer, e.g., a silicon wafer (Si wafer) or an epitaxial Si layer, suitable for forming one or more IC devices, e.g., the IC devices 100C. In various embodiments, a well is a p-well based on the semiconductor section containing one or more acceptor dopants, e.g., boron (B) or aluminum (Al), or an n-well based on the semiconductor section containing one or more donor dopants, e.g., phosphorus (P) or arsenic (As). The continuous well WA is one of the p-well or the n-well, and the continuous well WB is the other of the p-well or the n-well.

[0019] In some embodiments, the IC structure is composed of 100 layers of one or more insulating structures (in Fig. 1A (not shown), i.e., surrounded by a structure containing one or more dielectric materials such that each of the continuous wells WA and WB is electrically isolated from the substrate outside the IC structure 100. The dielectric materials include one or more silicon dioxide (SiO2), silicon nitride (Si3N4), and / or a dielectric material with a high k-value, e.g., a dielectric material with a k-value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HFO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), or another suitable material. In some embodiments, the IC structure 100 is partially surrounded by one or more insulating structures such that one of the continuous wells WA or WB, or both, is continuous with one or more sections of the substrate (not shown) outside the IC structure 100.

[0020] In the embodiment that is in Fig. As shown in Figure 1A, the continuous troughs WA and WB have the same total number of corresponding sections WAP1 to WAP3 (WAPn) and WBP1 to WBP3 (WBPn). In some embodiments, the continuous troughs WA and WB have different numbers of corresponding sections, e.g., WAPn and WBPn±1.

[0021] In the embodiment that is in Fig. As shown in Figure 1A, each of the continuous troughs WA and WB has a total of n = 3 corresponding sections WAPn and WBPn. In various embodiments, one or both of the continuous troughs WA or WB have a total of n that is less than or greater than three corresponding sections WAPn or WBPn.

[0022] In some embodiments, one of the continuous troughs WA or WB, or both, has a total number n of corresponding sections ranging from five (5) to 75. In some embodiments, one of the continuous troughs WA or WB, or both, has a total number n of corresponding sections ranging from 15 to 50. In some embodiments, one of the continuous troughs WA or WB, or both, has a total number n of corresponding sections ranging from 25 to 40.

[0023] In some embodiments, the continuous well sections WAPn and / or WBPn, with a total number of n, allow the IC structure 100 to have a dimension, e.g., in the Y-axis direction, that corresponds to a size of the IC devices 100C. In some embodiments, the continuous well sections WAPn and / or WBPn, with a total number of n, allow the IC structure 100 to have a dimension that corresponds to a dimension of one or more substrate elements (in Fig. (1A not shown) outside the IC structure 100, e.g., a height of a TSV structure TSVS, which is referred to below. Fig. 1B and Fig. 1C is discussed, corresponds.

[0024] In the embodiment that is in Fig. As shown in Figure 1A, the continuous wells WA and WB have respective sections WAPn and WBPn, which are continuous with each other based on the corresponding single section WAS or WBS extending in the Y direction and located in the corresponding boundary region 100A or 100B. In various embodiments, one or both of the continuous wells WA or WB have respective sections WAPn or WBPn, which are continuous with each other based on multiple instances of the corresponding section WAS or WBS extending in the Y direction and / or one or more instances of the corresponding section WAS or WBS located outside the corresponding boundary region 100A or 100B in the IC structure 100.

[0025] Due to the design discussed above, the IC structure has 100 continuous trays WA and WB, which are designed, for example, in an interlocking, twisted or other configuration so that each of the continuous trays WA and WB is used jointly by more than two rows, e.g., the rows R1 to R5.

[0026] Each instance of the take-up structures PA and PB, which in some embodiments are also collectively referred to as the take-up structure, has a heavily doped region within a corresponding section WAPx (one of the sections WAPn) of the continuous trough WA or WBPx (one of the sections WBPn) of the continuous trough WB and has an n- or p-doping that corresponds to the n-trough or p-trough type of the corresponding continuous trough WA or WB.

[0027] Each instance of the pickup structure PA or PB also has one or more conductive elements (not shown) configured to electrically connect the pickup structure to, or be in contact with, a corresponding power distribution structure (not shown). The IC structure 100 is configured such that the continuous n-tub WA or WB and the corresponding instance of the pickup structure PA or PB are electrically connected to a power distribution structure configured to have a power supply voltage, and the continuous p-tub WA or WB and the corresponding instance of the pickup structure PA or PB are electrically connected to a power distribution structure configured to have a reference voltage, e.g., ground.

[0028] Each of the consumer structures PA and PB is thus configured to avoid latch-up events during operation by, for example, using the power supply voltage to bias one of the continuous wells WA or WB, which is an n-well, thus preventing forward biasing of diodes having the corresponding well WA or WB and source / drain terminals of transistors located in the corresponding continuous well WA or WB, thereby preventing latch-up events by preventing forward biasing of a diode having one of the continuous wells WA or WB and a p-source / drain terminal of a PMOS transistor of IC devices 100 C located in one of the continuous wells WA or WB.

[0029] In the embodiment that is in Fig. As shown in Figure 1A, instances of the consumer structures PA are located in sections WAP2 and WAP3, instances of the consumer structures PB are located in sections WBP1 and WBP2, a first instance of each of the consumer structures PA and PB is located in row R2, a second instance of each of the consumer structures PA and PB is located in row R4, and the instances of the consumer structures PA and PB are aligned in the Y direction and are located between IC devices 100C.

[0030] In various embodiments, instances of the pickup structures PA and / or PB are arranged differently. In some embodiments, instances of the pickup structures PA and / or PB are not aligned in the Y direction. In some embodiments, one or more instances of the pickup structures PA and / or PB are located in the boundary region 100A and / or the boundary region 100B and are therefore adjacent to a corresponding section WAS or WBS, or both.

[0031] In the embodiment that is in Fig. As shown in Figure 1A, the IC structure 100 has a total of two instances each of the consumer structures PA and PB, three sections each of WAPn and WBPn and five rows R1 to R5, so that it corresponds to ratios of three sections WAPn to two consumer structures PA, three sections WBPn to two consumer structures PB and five rows R1 to R5 to two instances each of the consumer structures PA and PB.

[0032] In some embodiments, the IC structure 100 has different numbers of one or more instances of the recipient structures PA and / or PB, sections WAPn and / or WBPn and / or series R1 to R5 than those shown in Fig. 1A shown, whereby one or more of the corresponding ratios have different values ​​than those shown in Fig. 1A corresponds to the embodiment shown.

[0033] In some embodiments, one of the ratios of sections WAPn to instances of the recipient structures PA, or the ratio of sections WBPn to instances of the recipient structures PA, or both of these ratios, has a value ranging from two to twenty. In some embodiments, one of the ratios of sections WAPn to instances of the recipient structures PA, or the ratio of sections WBPn to instances of the recipient structures PB, or both of these ratios, has a value ranging from five to fifteen. In some embodiments, one of the ratios of sections WAPn to instances of the recipient structures PA, or the ratio of sections WBPn to instances of the recipient structures PB, or both of these ratios, has a value equal to ten (10).

[0034] In some embodiments, the ratio of the rows, e.g., rows R1 to R5, of IC devices 100C to the instances of the receiver structures PA and / or PB has a value ranging from three to forty. In some embodiments, the ratio of the rows of IC devices 100C to the instances of the receiver structures PA and / or PB has a value ranging from ten to thirty. In some embodiments, the ratio of the rows of IC devices 100C to the instances of the receiver structures PA and / or PB has a value equal to twenty (20).

[0035] As the ratios of sections WAPn and / or WBPn and / or rows of IC devices 100C to the instances of the consumer structures PA and / or PB increase, the total number of instances of the consumer structures PA and PG for a given size of the IC structure 100 decreases, so that the area occupied by the consumer structures PA and PB decreases in relation to the total area of ​​the IC structure 100 and the area that can be occupied by IC devices 100C increases in relation to the total area of ​​the IC structure 100.

[0036] The area over which a given pickup structure PA or PB, as discussed above, can avoid latch-up events is limited by several factors, such as the element geometry, doping levels, and / or circuit application. Accordingly, the relationships discussed above exhibit upper limits based on relevant design criteria.

[0037] Due to the design discussed above, the IC structure 100, by incorporating the section WAS or WBS running in the Y direction and the sections WAPn or WBPn extending into the rows of IC devices 100C, each has continuous troughs WA and WB that are shared by more than two rows of IC devices 100C. Thus, by incorporating one or more of the take-up structures PA or PB that can pre-tension sections WAPn or WBPn, the IC structure 100 is able to achieve latch-up protection in such a way that the number of take-up structures PA or PB is less than the number of sections WAPn or WBPn.In comparison to approaches where each trough corresponding to one or two rows of IC devices has at least one receiving structure, the IC structure 100, which has one of the continuous troughs WA or WB or both, uses fewer receiving structures, which is why it is capable of improved space utilization for the IC devices.

[0038] Fig. Figure 1B is a diagram of an IC structure 100D according to some embodiments. In addition to a top view of the IC structure 100D, it shows Fig. 1B the above with reference to Fig. 1A directions X and Y discussed. The IC structure 100D, which in some embodiments is also referred to as IC die 100D, is an IC die, an IC die section or other section of a semiconductor wafer, or an entire semiconductor wafer containing one or more instances of the above with reference to Fig. 1A discusses IC structure 100 and two or more copies of the TSV structure TSVS.

[0039] The IC structure 100D is an example of an IC die or IC die section that can be constructed by carrying out the entirety of the following with reference to Fig. 3 discussed procedure 300 or part thereof based on one or more IC layout diagrams, e.g. one or more of the IC layout diagrams 600A to 600C, which are below with reference to Fig. 6 will be discussed, produced.

[0040] A TSV structure, e.g., the TSV structure TSVS, is an element of an IC die that has one or more TSVs surrounded by one or more insulation structures, e.g., a TSV insulation structure TSVI, which are designed to electrically isolate the one or more TSVs from adjacent IC die elements.

[0041] A TSV (thermal segment) is a conductive segment extending from the front face of a semiconductor substrate, such as an IC die with the IC structure 100D, to the back face of the substrate. It is designed to electrically connect one or more structures located on the front face of the substrate to one or more structures located on the back face. A TSV contains one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other materials suitable for providing a low-resistance electrical connection between the front and back faces of a substrate.

[0042] In the embodiment that is in Fig. As shown in Figure 1B, IC structure 100D has three instances of TSV structures TSVS aligned in the X direction. A first instance of IC structure 100 is located between the first and second instances of TSV structures TSVS, and a second and third instance of IC structure 100 are located between the second and third instances of TSV structures TSVS. Thus, IC structure 100D has instances of both IC structure 100 and TSV structure TSVS aligned in the X direction.

[0043] The orientation and number of copies of the IC structure 100 and the TSV structure TSVS, which are in Fig. The examples shown in Figure 1B are provided for illustrative purposes. In different embodiments, the IC structure 100D has different numbers of instances of the IC structure 100 and / or the TSV structure TSVS than those shown in Figure 1B. Fig. 1B shown on and / or has a different orientation than that shown in Fig. 1B shown, e.g. in the Y direction.

[0044] In the embodiment that is in Fig. As shown in Figure 1B, the IC structure 100D comprises instances of a TSV structure TSVS, each containing a single TSV located within a TSV isolation structure TSVI. In some embodiments, the IC structure 100D comprises one or more instances of a TSV structure TSVS that has more than one TSV located within a TSV isolation structure TSVI, or no TSV located within a TSV isolation structure TSVI, e.g., a dummy region where the TSV isolation region TSVI corresponds to an entire TSV structure TSVS. In some embodiments, the IC structure 100D has, at one or more locations, for which in Fig. Figure 1B shows that they have one instance of a TSV structure TSVS, one or more structures other than one instance of a TSV structure TSVS, e.g. one or more instances of an IC structure 100, an IC circuit or device block or other IC die element.

[0045] In various embodiments, the IC structure 100D includes instances of the IC structure 100 that represent an identical embodiment of the IC structure 100 or more than one embodiment of the IC structure 100, e.g. embodiments with different orientations, numbers of receiver structures and / or IC devices 100C.

[0046] The in Fig. The number of instances of IC structure 100 shown in Figure 1B, which are located between adjacent instances of TSV structure TSVS, are examples. In various embodiments, IC structure 100D has one or more instances of IC structure 100 located between adjacent instances of TSV structure TSVS that are greater than two.

[0047] In some embodiments, the IC structure 100D, by virtue of the design discussed above, has one or more instances of the IC structure 100, in which one of the boundary regions 100A or 100B or both and one of the continuous trough regions WAS or WBS, each described above with reference to Fig. 1A discussed, or both are located next to an instance of a TSV insulation structure TSVI. In some embodiments, a boundary region 100A or 100B or a continuous trough region WAS or WBS next to an instance of a TSV insulation structure TSVI is considered to be located next to the corresponding instance of the TSV structure TSVS and the TSV is located in the adjacent instance of the TSV insulation structure TSVI.

[0048] Due to the design discussed above, the IC structure 100D has one or more instances of the IC structure 100 and is therefore able to implement the advantages discussed above with reference to the IC structure 100.

[0049] Fig. Figure 1C shows an IC package 100P according to some embodiments. In addition to the IC package 100P, Figure 1C shows... Fig. 1C the above with reference to Fig. 1A the discussed X-direction and a Z-direction orthogonal to each of the X- and Y-directions. Fig. 1C thus corresponds to a sectional view of each of the in Fig. 1A and Fig. Top views shown in 1B.

[0050] The IC package 100P is an example of an IC package that has one or more instances of an IC structure 100D and is constructed by carrying out the entirety described below with reference to Fig. 3 of the discussed procedures 300 or part thereof is produced.

[0051] In addition to the IC structure 100D, the IC package 100P has IC dies D1 and D2, which are electrically and mechanically connected to the IC structure 100D by bump structures B in such a way that the IC structure 100D and the IC dies D1 and D2 are aligned in the Z direction.

[0052] The arrangement and number of IC dies D1 and D2 and the instances of IC structure 100D, which are in Fig. The examples shown in Figure 1C are provided for illustrative purposes. In different embodiments, the IC package 100P has a different number of IC dies and / or instances of the IC structure 100D than those shown in Figure 1C. Fig. 1C shown and / or it has a different arrangement than that shown in Fig. 1C depicted, e.g. more than one instance of the IC structure 100D and / or in addition to the IC die D1 or D2 at least one IC die (not shown) which is electrically and mechanically connected to the IC structure 100D at a corresponding top or bottom surface.

[0053] In various embodiments, the IC package 100P is a 2.5D IC package, a 3D IC package, an integrated fan-out package (InFO package), or another type of IC package suitable for accommodating an IC structure 100D that includes instances of a TSV structure TSVS.

[0054] Each of the IC dies D1 and D2 is an IC die, an IC die section, another section of a semiconductor wafer, or an entire semiconductor wafer. In some embodiments, one or both of the IC dies D1 or D2 is a substrate with a fan-out arrangement, e.g., an interposer.

[0055] A bump structure, e.g., a bump structure B, is a conductive structure that lies over and is in contact with sections of the IC structure 100D and / or the dies D1 and / or D2, thereby providing electrical connections between the IC structure 100D and the dies D1 and / or D2. In some embodiments, the bump structures contain lead. In some embodiments, the bump structures contain lead-free materials such as tin, nickel, gold, silver, copper, or other materials suitable for providing electrical connections with external conductive elements. In some embodiments, the bump structures have substantially spherical shapes. In some embodiments, the bump structures are controlled collapse chip connection bumps (C4 bumps), sphere lattice bumps, micro-bumps, or the like.

[0056] In some embodiments, the IC package 100P has no bump structures B between the IC structure 100D and one of the IC dies D1 or D2 or both, and the IC structure 1D is directly bonded to the corresponding one of the IC dies D1 or D2 or both and thus electrically connected to it.

[0057] In some embodiments, some or all instances of the TSV structure TSVS on one or more instances of the IC structure 100D and one or more hump structures B, if present, are part of a power distribution structure of the IC package 100P.

[0058] Due to the design discussed above, the IC-Package 100P has at least one instance of the IC structure 100D, in which one or more instances of the IC structure 100 are located alongside one or more instances of the TSV structure TSVS, making the IC-Package 100P capable of implementing the advantages discussed above with reference to the IC structure 100.

[0059] Fig. Figure 2 is a flowchart of a method 200 for operating an IC device according to some embodiments. The method 200 is associated with an IC structure that has shared wells, e.g., the one described above with reference to Fig. IC structure 100 discussed in 1A to 1C is usable.

[0060] The order in which the activities of procedure 200 in Fig. Figure 2 is for illustrative purposes only; the activities of procedure 200 can be carried out in sequences that differ from the one shown in Fig. The two depicted models differ. In some embodiments, the following are performed before, between, during and / or after the activities described in Fig. 2 are shown, additional activities to those in Fig. 2 as shown.

[0061] In some embodiments, some or all of the activities of method 200 are a subset of a method for operating a circuit that has shared wells, e.g., the IC devices 100C, which are referred to above. Fig. 1A discussed a method for operating an IC die, e.g. the IC structure 100D, which was discussed above with reference to Fig. 1B was discussed, and / or a method for operating an IC package, e.g. the IC package 100P, which was discussed above with reference to Fig. 1C was discussed.

[0062] In activity 210, a power supply voltage is maintained at a first consumer structure, and a reference voltage is maintained at a second consumer structure. Maintaining the power supply voltage includes obtaining the power supply voltage from a first power distribution structure, and maintaining the reference voltage includes obtaining the reference voltage from a second power distribution structure that is separate from the first power distribution structure.

[0063] In some embodiments, maintaining the power supply voltage at the first consumer structure includes maintaining the power supply voltage at one instance of one of the consumer structures PA and PB, and maintaining the reference voltage at the second consumer structure includes maintaining the reference voltage at one instance of the other of the consumer structures PA and PB, as described above with reference to Fig. It was discussed in section 1A.

[0064] In some embodiments, the first consumer structure is one of several first consumer structures and includes maintaining the power supply voltage at the first consumer structure, as well as maintaining the power supply voltage at each of the several first consumer structures. In some embodiments, the second consumer structure is one of several second consumer structures and includes maintaining the reference voltage at the second consumer structure, as well as maintaining the reference voltage at each of the several second consumer structures.

[0065] In activity 220, the first pickup structure is used to bias an n-tub shared by more than two rows of IC devices, and the second pickup structure is used to bias a p-tub shared by more than two rows of IC devices. Using the first pickup structure to bias the shared n-tub includes biasing the shared n-tub with the power supply voltage, and using the second pickup structure to bias the shared p-tub includes biasing the shared p-tub with the reference voltage.Biasing the common n-well with the power supply voltage includes preventing forward bias of a diode having the n-well and an S / D terminal of a PMOS transistor of the IC devices, and biasing the common p-well with the reference voltage includes preventing forward bias of a diode having the p-well and an S / D terminal of an NMOS transistor of the IC devices.

[0066] In some embodiments, using the first pickup structure to pre-tension the common n-tub includes using one instance of either pickup structure PA or PB to pre-tension a corresponding one of the continuous tubs WA or WB, and using the second pickup structure to pre-tension the common p-tub includes using one instance of the other pickup structure PA or PB to pre-tension the corresponding other of the continuous tubs WA or WB, as described above with reference to Fig. It was discussed in section 1A.

[0067] In some embodiments, using one instance of the receiving structures PA or PB to pre-tension the corresponding one of the continuous troughs WA or WB includes using multiple instances of one of the receiving structures PA or PB to pre-tension the corresponding one of the continuous troughs WA or WB, and includes using one instance of the other receiving structures PA or PB to pre-tension the corresponding other of the continuous troughs WA or WB, as described above with reference to Fig. It was discussed in section 1A.

[0068] In some embodiments, the shared n-tub is a shared n-tub of several shared n-tubs, wherein each shared n-tub has a corresponding first pickup structure of several first pickup structures, and the pre-tensioning of the shared n-tub comprises using each first pickup structure of the several first pickup structures to pre-tension a corresponding shared n-tub of the several shared n-tubs.In some embodiments, the power supply voltage is a power supply voltage of several power supply voltages, and includes using each first-drainer structure of the several first-drainer structures to bias the corresponding common n-tub of the several common n-tubs, biasing each of several subsets of the several common n-tubs with a corresponding power supply voltage of the several power supply voltages.In some embodiments, the shared p-tub is a shared p-tub of several shared p-tubs, each shared p-tub has a corresponding second-tub structure of several second-tub structures, and pre-tensioning the shared p-tub comprises using each second-tub structure of the several second-tub structures to pre-tension a corresponding shared p-tub of the several shared p-tubs.

[0069] In activity 230, the power supply and reference voltages are used in some embodiments to operate the IC devices. Operating the IC devices includes operating PMOS transistors located in the shared n-well, corresponding to more than two rows of IC devices, and operating NMOS transistors located in the shared p-well, corresponding to more than two rows of IC devices.

[0070] In some embodiments, operating the IC devices includes operating IC devices 100C, which are described above with reference to Fig. 1A were discussed. In some embodiments, operating the IC devices includes operating the IC devices located between TSV structures, e.g., TSV structures TSVS, which were discussed above with reference to Fig. 1B and Fig. 1C discussed above. In some embodiments, operating the IC devices includes operating an IC die, e.g., the IC device 100D, which was discussed above with reference to Fig. 1B and Fig. 1C was discussed. In some embodiments, operating the IC devices includes operating an IC package, e.g., the IC package 100P, which was discussed above with reference to Fig. 1C was discussed.

[0071] By performing some or all of the activities of the procedure 200, the power supply and reference voltages are used to bias one n-tub, which is shared by more than two rows of IC devices, and one p-tub, which is shared by more than two rows of IC devices, thereby obtaining the advantages discussed above with reference to the IC structure 100.

[0072] Fig. Figure 3 is a flowchart of a process 300 for fabricating an IC structure according to some embodiments. The process 300 can be carried out to fabricate the IC structure 100 described above with reference to Fig. 1A and Fig. 1B was discussed, the IC structure 100D, which was mentioned above with reference to Fig. 1B and Fig. 1C was discussed, and / or the IC package 100P, which was mentioned above with reference to Fig. 1C was discussed, to form.

[0073] In some embodiments, the activities of method 300 are performed in the order described in Fig. 3 is carried out. In some embodiments, the activities of method 300 are performed in a different order than that shown in Fig. The steps of the process are carried out in the sequence shown in section 3. In some embodiments, one or more additional steps are performed before, during, and / or after the steps of process 300. In some embodiments, performing some or all of the steps of process 300 includes performing one or more of the steps shown below with reference to the IC manufacturing system 900. Fig. 9 activities discussed.

[0074] In activity 310, each is set up from a first trough and a second trough such that it has a first section extending in a first direction and a second and a third section extending from the first section in a second direction orthogonal to the first direction. Setting up the first and second troughs includes setting up one of the first or the second trough as an n-trough in a first IC die and the other of the first or the second trough as a p-trough in the first IC die.

[0075] In some embodiments, the configuration of the first trough comprises having the first section extending in the first direction and the second and third sections extending from the first section in the second direction; the configuration of the continuous trough WA comprises having the section WAS extending in the Y direction and two sections WAPn extending in the X direction; the configuration of the second trough comprises having the first section extending in the first direction and the second and third sections extending from the first section in the second direction; the configuration of the continuous trough WB comprises having the section WBS extending in the Y direction and two sections WBPn extending in the X direction, as described above with reference to Fig. It was discussed in section 1A.

[0076] In some embodiments, the first tub is a first tub of several first tubs, the second tub is a second tub of several second tubs, and the arrangement of each of the first and second tubs comprises such that it has a first section extending in a first direction, and a second and a third section extending from the first section in a direction orthogonal to the first direction.

[0077] In some embodiments, setting up a well, e.g., the first and / or the second well, includes performing one or more implantation processes in an area of ​​a semiconductor substrate corresponding to the well, wherein for one or more as above with reference to Fig. 1A, the given dopants discussed in Section 1A are used to achieve a predetermined doping concentration. In some embodiments, setting up a well includes setting up one of the first or the second well by performing one or more implantation processes, wherein a region of the substrate outside that of one of the first or the second well is considered to be set up as the other of the first or the second well, e.g., setting up the first well as an n-well by performing a P and / or an As implantation, whereby a region outside the first well is set up as a p-well based on the fact that it is part of a p-substrate.

[0078] In some embodiments, setting up each of the first and second troughs includes arranging one of the first or the second trough, or both, next to a TSV structure, e.g., arranging one of the continuous troughs WA and WB, or both of the IC structure 100, next to one or more instances of the TSV structure TSVS, as above with reference to Fig. 1B was discussed.

[0079] In some embodiments, setting up each of the first and second vats includes setting up each of the first and second vats based on one or more of the cells 400A to 400C, which are described below with reference to Fig. 4 will be discussed, and one or more of the IC layout diagrams 600A to 600C, which are shown below with reference to Fig. 6A to 6C will be discussed.

[0080] In activity 320, IC devices are formed, comprising a first receiver structure electrically connected to the first well and a second receiver structure electrically connected to the second well. The formation of the IC devices includes forming at least one PMOS transistor in at least one of the second or third sections of the first or second well, configured as the n-well, and forming at least one NMOS transistor in at least one of the second or third sections of the first or second well, configured as the p-well.

[0081] The formation of the pickup structures, which are electrically connected to the first and second vats, involves carrying out one or more implantation processes, wherein the first pickup structure has the same doping type as that of the first vat and a higher doping concentration than that of the first vat, and the second pickup structure has the same doping type as that of the second vat and a higher doping concentration than that of the second vat.

[0082] The formation of the consumer structures electrically connected to the first and second troughs includes forming an electrical connection from the first consumer structure to a first power distribution structure configured to have one of a power supply voltage or a reference voltage, and forming an electrical connection from the second consumer structure to a second power distribution structure configured to have the other of the power supply voltage or the reference voltage.

[0083] In some embodiments, forming the IC devices having the first and second pickup structures includes forming IC devices and one or more instances of each of the pickup structures PA and PB described above with reference to Fig. They were discussed in section 1A.

[0084] In some embodiments, the IC devices are one instance of IC devices from several instances of IC devices, the first well is a first well from several first wells, the second well is a second well from several second wells, and comprises forming the IC devices having the first and second pickup structures, forming each instance of the IC device from several instances of IC devices having the first and second pickup structures corresponding to a first well of several first wells and a second well of several second wells.

[0085] The formation of the IC devices, which have the first and second customer structures, involves the assembly of multiple IC devices, e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices, by performing multiple manufacturing operations, e.g., one or more from lithography, diffusion, deposition, etching, planarizing, or any other operation suitable for assembling the multiple IC devices in the semiconductor wafer.

[0086] In some embodiments, forming the IC devices having the first and second pickup structures includes forming the IC devices having the first and second pickup structures based on one or more of the cells 400A to 400C described below with reference to Fig. 4 will be discussed, and one or more of the IC layout diagrams, 600A to 600C, which are shown below with reference to Fig. 6A to 6C will be discussed.

[0087] In activity 330, in some embodiments, a TSV structure is erected in the first IC die next to the first or second well. Erecting the TSV structure includes erecting a TSV that extends between the front and back of the first IC die and is surrounded by a TSV insulation structure.

[0088] In some embodiments, erecting the TSV structure includes erecting one TSV structure next to each of the first and second tubs. In some embodiments, erecting the TSV structure includes erecting at least one instance of the TSV structure TSVS, as described above with reference to Fig. 1B and Fig. 1C was discussed.

[0089] In some embodiments, the first tub is a first tub of several first tubs, the second tub is a second tub of several second tubs, the TSV structure is a TSV structure of several TSV structures, and erecting the TSV structure includes erecting each TSV structure of the several TSV structures next to a corresponding first tub of the several first tubs and / or a corresponding second tub of the several second tubs.

[0090] The construction of the TSV structure involves performing several manufacturing activities, including the deposition and structuring of one or more photoresist layers, the performance of one or more etching processes, and the performance of one or more deposition processes, whereby one or more conductive materials are arranged to form a continuous low-resistance structure extending between the front and back of the IC die and surrounded by one or more continuous dielectric layers, thereby electrically isolating the continuous low-resistance structure from adjacent elements, e.g., the first or second well.

[0091] In activity 340, in some embodiments, the TSV structure is electrically connected to a second IC die of an IC package. In various embodiments, the electrical connection of the TSV structure to the second IC die includes either a direct connection of the TSV structure to the second IC die or a connection of the TSV structure to the second IC die via a bump structure. In some embodiments, the electrical connection of the TSV structure to the second IC die of the IC package includes an electrical connection of the TSV structure to the second IC die of a 2.5D IC package, a 3D IC package, or an InFO package.

[0092] In some embodiments, the electrical connection of the TSV structure to the second IC die of the IC package comprises an electrical connection of at least one instance of the TSV structure TSVS to at least one of the IC dies D1 or D2 of the above with reference to Fig. 1C discussed IC packages 100P.

[0093] Electrically connecting the TSV structure to the second IC die comprises performing one or more IC package manufacturing operations, thereby connecting a portion of the IC die, or the entire IC die, containing the TSV structure to the second IC die of the IC package. In various embodiments, the one or more IC package manufacturing operations comprise one or more from a die singulation process, injection molding or deposition, a bonding process, a metal deposition process, a soldering process, an annealing process, or another process suitable for manufacturing an IC package.

[0094] In some embodiments, activity 340 is repeated so that the TSV structures of several IC dies are electrically connected to the first or second IC die and / or one or more IC dies in addition to the first and second IC die.

[0095] By performing some or all of the activities of process 300, an IC structure is produced in which a first and a second well of more than two rows of IC devices are used jointly, thereby obtaining the advantages discussed above with reference to IC structures 100 and 100D and IC package 100P.

[0096] Fig. Figure 4 is a diagram of IC layout diagrams of cells 400A to 400C according to some embodiments. Fig. Figure 4 shows a top view of each cell 400A to 400C and the above with reference to Fig. 1A and Fig. 1B discussed directions X and Y.

[0097] An IC layout diagram, e.g., an IC layout diagram that includes one or more of the cells 400A to 400C, is produced using a manufacturing process, e.g., process 300, which is described above with reference to Fig. 3 was discussed, and / or the IC manufacturing process, which is described below with reference to Fig. 9 discussed IC manufacturing system 900 is connected as part of the definition of one or more elements of an IC structure, e.g. the IC structure 100, which is referred to above. Fig. 1A to 3, which was discussed, can be used.

[0098] In various embodiments, a cell, e.g., cell 400A to 400C, is a self-contained cell that is included in a cell library such as one described below with reference to Fig. 8 cell library 807 discussed, or part of a larger IC layout diagram, e.g., one or more of the IC layout diagrams 600A to 600C, which are described below with reference to Fig. 6A to 6C will be discussed.

[0099] In some embodiments, one or more of the cells 400A to 400C are generated by one or more activities of a method, e.g., a method 500, which is described below with reference to Fig. 5 will be discussed and carried out.

[0100] Each of the cells 400A to 400C has boundaries B1 to B4, basin areas WR1 and WR2, and in some embodiments, a pickup area PR1 positioned in basin area WR1 and a pickup area PR2 positioned in basin area WR2. Cell 400A has a cell height CH1, and each of the cells 400B and 400C has a cell height CH2.

[0101] The orientations shown for each of cells 400A to 400C are examples provided for illustrative purposes. Each of cells 400A to 400C can be rotated and / or reversed with respect to one or both of the X and Y directions.

[0102] A trough area, e.g., trough area WR1 or WR2, is an area in an IC layout diagram that is part of the definition of a section or the entirety of one or more n-trough or p-trough structures, e.g., a continuous trough WA or WB, as described above with reference to Fig. 1A was discussed, in a section of a semiconductor substrate, e.g. the one mentioned above with reference to Fig. The IC structure 100 or 100D discussed in 1A to 3 is included in the manufacturing process.

[0103] A customer area, e.g., customer area PR1 or PR2, is an area in an IC layout diagram that is part of the definition of a customer structure, e.g., customer structure PA or PB, which is described above with reference to Fig. Items 1A to 3, which were discussed, have been incorporated into the manufacturing process.

[0104] In some embodiments, one or more of the cells 400A to 400C are referred to as the boundary cell. In some embodiments where a cell 400A to 400C has consumer areas PR1 and PR2, the cell 400A to 400C is referred to as the consumer cell, coupling cell, or sampling cell.

[0105] Each of the trough areas WR1 and WR2 can be used as part of the definition of a section of one of the continuous troughs WA or WB, and each of the take-up areas PR1 and PR2 can be used as part of the definition of an instance of the take-up structure PA or PB corresponding to the continuous trough WA or WB, as above with reference to Fig. 1A to 3 were discussed and will be discussed in more detail below.

[0106] Each of the cells 400A to 400C has a boundary defined by boundaries B1 to B4. Boundaries B1 and B3 extend in the X direction, and boundaries B2 and B4 extend in the Y direction. Each of the cells 400A to 400C has a basin area WR1 that extends in the Y direction from boundary B1 to boundary B3 and in the X direction from boundary B4 to boundary B2.

[0107] Cell 400A has a trough area WR1 that extends along the entire boundary B4 from boundary B1 to boundary B3 and along a portion of boundary B2 between boundary B1 and trough area WR2. Trough area WR1 extends along the entire boundary B1 from boundary B4 to boundary B2 and along a portion of boundary B3 between boundary B4 and trough area WR2.

[0108] Cell 400B has a basin area WR1 that extends along the entire boundary B4 from boundary B1 to boundary B3, and along a first part of boundary B2 between boundary B1 and basin area WR2, and a second part of boundary B2 between basin area WR2 and boundary B3. Basin area WR1 extends along the entire boundary B1 and along the entire boundary B3 from boundary B4 to boundary B2.

[0109] Cell 400C has a trough area WR1 that extends along the entire boundary B4 from boundary B1 to boundary B3 and along a portion of boundary B2 between a first section of trough area WR2 and a second section of trough area WR2. Trough area WR1 extends along a portion of boundary B1 between boundary B4 and the first section of trough area WR2 and along a portion of boundary B3 between boundary B4 and the second section of trough area WR2 from boundary B4 to boundary B2.

[0110] In the embodiments described in Fig. As shown in Figure 4, the basin area WR1 designates a section of cell 400A to 400C extending along boundary B4, and basin area WR2 designates one or two additional sections of cell 400A to 400C as shaded areas. In some embodiments, basin area WR2 corresponds to a section of cell 400A to 400C extending along boundary B4, and basin area WR1 corresponds to one or the two additional sections of cell 400A to 400C indicated by shaded areas, in which basin areas WR1 and WR2 are considered to be inversely related.

[0111] Various embodiments of the cells 400A to 400C can be combined, defining sections of n-well and / or p-well structures that are shared by more than two rows of IC devices, as shown below and with reference to Fig. 5 to 7 will be discussed in more detail.

[0112] In the embodiment that is in Fig. As shown in Figure 4, cell height CH1 is a single cell height corresponding to the height of a row of IC devices containing a single instance of a PMOS transistor aligned in the Y direction with a single instance of an NMOS transistor, and cell height CH2 is a double cell height equal to twice the height of cell CH1 and corresponding to two rows of IC devices. In some embodiments, cells 400A to 400C have different cell heights than those shown in Figure 4. Fig. 4 shown, e.g. one of the cells has 400B or 400C or both have a cell height of CH1.

[0113] In each of the embodiments described in Fig. As shown in Figure 4, cells 400A to 400C each have basin areas WR1 and WR2 with boundaries defined by limits extending in the X or Y direction. In some embodiments, one or more of cells 400A to 400C have basin areas WR1 and WR2 with boundaries defined by one or more limits that are oriented differently, for example, by running diagonally with respect to the X and Y directions. In some embodiments, a cell 400A to 400C does not have basin area WR2, so that the boundaries of basin area WR1 coincide with the cell boundaries B1 to B4.

[0114] Due to the design discussed above, each of the IC layout diagrams corresponding to cells 400A to 400C has a trough area WR1 extending from boundaries B1 and B4 to respective boundaries B3 and B2, and can thereby define sections of trough structures shared by more than two rows of IC devices, as shown below with reference to Fig. 5 to 7 will be discussed in more detail, thereby obtaining the advantages discussed above with reference to the IC structure 100.

[0115] Fig. Figure 5 is a flowchart of a procedure 500 for generating an IC layout diagram, e.g., an IC layout diagram of a cell 400A to 400C, which is described above with reference to Fig. 4 was discussed, according to some embodiments.

[0116] In some embodiments, generating the IC layout diagram includes generating the IC layout diagram that represents an IC structure, e.g., the one described above with reference to Fig. 1A to 1C corresponds to the IC structure 100 discussed, which is manufactured on the basis of the generated IC layout diagram.

[0117] In some embodiments, the entire method 500 or a part thereof is performed by a processor of a computer, e.g. a processor 802 of an IC layout diagram generation system 800, which is described below with reference to Fig. 8 is discussed and carried out.

[0118] Some or all of the activities of Procedure 500 may be part of a design process carried out in a design department, e.g., one of those described below with reference to Fig. The design department discussed in section 920 will be carried out.

[0119] In some embodiments, the activities of method 500 are performed in the order described in Fig. 5 is carried out. In some embodiments, the activities of method 500 are carried out simultaneously and / or in a different order than that shown in Fig. The sequence shown in section 5 is carried out. In some embodiments, one or more activities are carried out before, between, during and / or after the execution of one or more activities of the method 500.

[0120] In activity 510, in some embodiments, an IC layout diagram of a stored cell is obtained from a storage device, wherein the stored cell comprises one or both of the first and second well regions. In some embodiments, the stored cell comprises each of the first well regions extending from a first cell boundary to a second cell boundary and not extending from a third cell boundary to a fourth cell boundary.

[0121] In some embodiments, obtaining the IC layout diagram of the stored cell from the storage device includes obtaining the IC layout diagram of the stored cell from the cell library 807 of an IC layout diagram generation system 800, described below with reference to Fig. 8 will be discussed.

[0122] In activity 520, the first trough area is extended from a first cell boundary to a second cell boundary, wherein the first and second cell boundaries are opposite boundaries of the cell in a first direction. In some embodiments, the first direction is orthogonal to that of a cell height, e.g., to that described above with reference to Fig. 4 discussed cell height CH1 or CH2 orthogonal X-direction.

[0123] In some embodiments, extending the first basin area from the first cell boundary to the second cell boundary includes extending the first basin area along the entire third cell boundary and part of the fourth cell boundary. In some embodiments, extending the first basin area from the first cell boundary to the second cell boundary includes extending the first basin area along the entire third cell boundary and the entire fourth cell boundary. In some embodiments, extending the first basin area from the first cell boundary to the second cell boundary includes extending the first basin area along part of the third cell boundary and part of the fourth cell boundary.

[0124] In some embodiments, extending the first basin area from the first cell boundary to the second cell boundary includes extending basin area WR1 from boundary B4 to boundary B2 as described above with reference to Fig. 4 discussed cells 400A to 400C.

[0125] In activity 530, the first trough area is extended from a third cell boundary to a fourth cell boundary, wherein the third and fourth cell boundaries are opposite boundaries of the cell in a direction orthogonal to the first direction. In some embodiments, the second direction is that of a cell height, e.g., the Y-direction of the cell described above with reference to Fig. 4 cell heights discussed: CH1 or CH2.

[0126] In some embodiments, extending the first basin area from the third cell boundary to the fourth cell boundary includes extending the first basin area along the entire first cell boundary. In some embodiments, extending the first basin area from the third cell boundary to the fourth cell boundary includes extending the first basin area along a portion of the second cell boundary.

[0127] In some embodiments, extending the first basin area from the third cell boundary to the fourth cell boundary includes extending basin area WR1 from boundary B1 to boundary B3 as described above with reference to Fig. 4 discussed cells 400A to 400C.

[0128] In some embodiments, extending the first basin area from the third cell boundary to the fourth cell boundary comprises increasing the size of the first basin area of ​​the stored cell obtained in activity 510 and decreasing the size of the second basin area of ​​the stored cell obtained in activity 510.

[0129] In activity 540, in some embodiments, each of the first and second trough areas overlaps with a receiving area. In some embodiments, the overlap of each of the first and second trough areas with the receiving area includes an overlap of trough area WR1 with receiving area PR1 and an overlap of trough area WR2 with receiving area PR2, as described above with reference to Fig. 4 was discussed.

[0130] In Activity 550, in some embodiments, the IC layout diagram is stored in a storage device. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in non-volatile, computer-readable memory or a cell library, e.g., a database, and / or it includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in the cell library 807 or over a network 814 of the IC layout diagram generation system 800, which is described below with reference to Fig. 8 will be discussed.

[0131] In activity 560, in some embodiments, the IC layout diagram is arranged within an IC layout diagram of an IC die. In various embodiments, arranging the IC layout diagram within the IC layout diagram of the IC die involves rotating the IC layout diagram about one or more axes, translating the IC layout diagram relative to one or more additional IC layout diagrams in one or more directions, and / or reversing the first and second well areas.

[0132] In some embodiments, arranging the IC layout diagram in the IC layout diagram of the IC die includes arranging the IC layout diagram in one of the IC layout diagrams 600A to 600C, which are described below with reference to Fig. 6A to 6C will be discussed.

[0133] In some embodiments, arranging the IC layout diagram in the IC layout diagram of the IC die comprises performing one or more steps of a method 700, which is described below with reference to Fig. 7 will be discussed.

[0134] In activity 570, in some embodiments, at least one semiconductor mask or at least one component in a layer of a semiconductor IC is manufactured based on the IC layout diagram. The manufacturing of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is described below with reference to Fig. 9 discussed.

[0135] In activity 580, one or more manufacturing activities are performed in some embodiments based on the IC layout diagram. In some embodiments, performing one or more manufacturing activities includes performing one or more lithographic exposures based on the IC layout diagram. Performing one or more manufacturing activities, e.g., one or more lithographic exposures, based on the IC layout diagram is described below with reference to Fig. 9 discussed.

[0136] By performing some or all of the activities of procedure 500, an IC layout diagram is produced that corresponds to an IC structure in which a first and a second well of more than two rows of IC devices are used, thereby obtaining the advantages discussed above with reference to IC structure 100.

[0137] Fig. 6A to 6C are diagrams of the respective IC layout diagrams 600A to 600C according to some embodiments. Fig. 6A to 6C show top views of the respective IC layout diagrams 600A to 600C and the above with reference to Fig. 1A, Fig. 1B and Fig. 4 directions discussed: X and Y.

[0138] Each of the IC layout diagrams 600A to 600C has an IC device area ICR that has rows R1 to R5 corresponding to rows R1 to R5 of IC devices 100C, which are described above with reference to Fig. 1A were discussed. The IC fixture area ICR is an area in each of the IC layout diagrams 600A to 600C that contains multiple cells and / or other IC layout elements that are set up as part of the definition of multiple IC fixtures, e.g., IC fixtures 100C, for inclusion in a manufacturing process. The representation of the IC fixture area ICR in each of Fig. Sections 6A to 6C have been simplified for the purpose of explanation, as above with reference to Fig. It was discussed in section 1A.

[0139] The IC layout diagrams 600A to 600C also show respective limit ranges BR1A to BR1C, which correspond to the above with reference to Fig. The boundary ranges BR1A and BR2A, which correspond to the boundary range 100A discussed above, and the respective boundary ranges BR2A to BR2C, which correspond to the boundary range 100B also discussed above, are defined. Each of the boundary ranges BR1A and BR2A contains multiple instances of cell 400A, each of the boundary ranges BR1B and BR2B contains multiple instances of cell 400B, and each of the boundary ranges BR1C and BR2C contains multiple instances of cell 400C, each of which is described above with reference to Fig. 4 were discussed.

[0140] The number of rows R1 to R5 and the number of cells 400A to 400C that are in Fig. Figures 6A to 6C are provided for illustrative purposes. In various embodiments, one or more of the IC layout diagrams 600A to 600C may have one or more different numbers of rows or cells than those shown in Figure 600A to 600C. Fig. The numbers shown are from 6A to 6C.

[0141] As discussed below, each of the IC layout diagrams 600A to 600C features the corresponding instances of cells 400A to 400C and the IC device area ICR, which are arranged to define well areas WR1 and WR2 extending in both the X and Y directions. In some embodiments, the well areas WR1 and WR2 correspond to those described above with reference to Fig. 1A discussed continuous tubs WA and WB.

[0142] In the embodiment that is in Fig. As shown in Figure 6A, each of the boundary regions BR1A and BR2A in each of the rows R1 to R5 contains one instance of cell 400A. In boundary region BR1A, the instances of cell 400A in rows R1, R3, and R5 correspond to those shown in Figure 6A. Fig. 4 illustrated embodiment and the examples of cell 400A in rows R2 and R4 correspond to those in Fig. 4. The embodiment shown is rotated about the x-axis. In the limit region BR2A, the examples of cell 400A in rows R2 and R4 correspond to those shown in Fig. 4 in the embodiment shown, which is rotated about the y-axis and has reversed trough areas WR1 and WR2, and the examples of cell 400A in rows R1, R3 and R5 correspond to the examples in rows R2 and R4, which are rotated further about the y-axis.

[0143] In the embodiment that is in Fig. As shown in Figure 6B, the boundary region BR1B has one instance of cell 400B in rows R1 and R2, one instance of cell 400B in rows R3 and R4, and one instance of cell 400B occupying part of row R5, with each instance of cell 400B being the one shown in Figure 6B. Fig. The embodiment shown in Figure 4 corresponds to the boundary region BR2B, which comprises one instance of cell 400B occupying part of row R1, one instance of cell 400B in rows R2 and R3, and one instance of cell 400B in rows R4 and R5, each instance of cell 400B being the one shown in Figure 4. Fig. 4 corresponds to the embodiment shown, which is rotated around the y-axis and has reversed tub areas WR1 and WR2.

[0144] In the embodiment that is in Fig. As shown in Figure 6C, the boundary region BGR1C has one instance of cell 400C occupying part of row R1, one instance of cell 400C in rows R2 and R3, and one instance of cell 400C in rows R4 and R5, with each instance of cell 400C being the one shown in Figure 6C. Fig. The embodiment shown in 4A corresponds to the boundary region BR2C, which has one instance of cell 400C in rows R1 and R2, one instance of cell 400C in rows R3 and R4, and one instance of cell 400C occupying part of row R5, with each instance of cell 400C being the one shown in Fig. 4 corresponds to the embodiment shown, which is rotated around the y-axis and has reversed tub areas WR1 and WR2.

[0145] In the embodiments described in Fig. As shown in Figures 6A to 6C, each of the IC layout diagrams 600A to 600C features instances of a single cell 400A to 400C positioned in each of the corresponding boundary regions BR1A to BR1C and BR2A to BR2C, thereby aligning the corresponding well regions WR1 and WR2 of cells 400A to 400C and the IC device region ICR in the X-direction. In various embodiments, one or more of the IC layout diagrams 600A to 600C feature instances of more than one cell 400A to 400C positioned in one or both of the corresponding boundary regions BR1A to BR1C and BR2A to BR2C, thereby aligning the corresponding well regions WR1 and WR2 of cells 400A to 400C and the IC device region ICR differently in the X-direction.

[0146] Each of the IC layout diagrams 600A to 600C has one or more instances of a pickup area (not shown) in each of the well areas WR1 and WR2, corresponding to one or more pickup structures in the well structures manufactured based on IC layout diagrams 600A to 600C. The number of pickup areas corresponds, as discussed above, to the pickup structures PA and PB of IC structure 100. Fig. 1A to 3 are related to the number of rows of the IC device area ICR and the number of sections of the trough areas WR1 and WR2 that run in the X direction.

[0147] In some embodiments, one or more customer areas are included, for example, as one or more sampling cells in the IC device area ICR and thus correspond to those described in Fig. 1A shows the customer structures PA and PB. In some embodiments, the one or more customer areas are customer areas PR1 and PR2, which are contained in one or more instances of the cells 400A to 400C contained in the corresponding IC layout diagram 600A to 600C.

[0148] Through the designs discussed above, each of the IC layout diagrams 600A to 600C features each of the well areas WR1 and WR2, which are configured to define sections of well structures shared by more than two rows of IC devices, as shown below with reference to Fig. 7 is discussed in more detail, thereby obtaining the advantages discussed above with reference to IC structure 100. In embodiments having one or more customer areas PR1 and PR2, the area defined by the IC fixture area ICR that is available for IC fixtures is further increased, thereby further improving layout efficiency and routing flexibility compared to approaches where one or more customer areas are positioned within an IC fixture area.

[0149] Fig. Figure 7 is a flowchart of a procedure 700 for generating an IC layout diagram, e.g., one of the ones above with reference to Fig. IC layout diagrams 600A to 600C, discussed in sections 6A to 6C, are shown in some embodiments. In some embodiments, generating the IC layout diagram includes generating the IC layout diagram that is shown above with reference to Fig. 1A to 3 corresponds to the discussed IC structure 100, which is manufactured based on the generated IC layout diagram.

[0150] In some embodiments, the entire method 700 or a part thereof is executed by a computer processor. In some embodiments, the entire method 700 or a part thereof is executed by a processor 802 of the following with reference to Fig. The IC layout diagram generation system 800 discussed in section 8 was executed.

[0151] Some or all of the activities of Procedure 700 may be part of a design process carried out in a design department, e.g., the one described below with reference to Fig. The design department discussed in section 920 will be carried out.

[0152] In some embodiments, the activities of method 700 are performed in the order described in Fig. Figure 7 is shown. In some embodiments, the activities are carried out simultaneously and / or in a different order than shown. Fig. The sequence shown in section 7 is carried out. In some embodiments, one or more activities are carried out before, between, during and / or after the execution of one or more activities of the method 700.

[0153] In activity 710, several boundary cells are obtained in some embodiments. Obtaining the several boundary cells comprises obtaining each boundary cell of the several boundary cells, which has a first trough area extending from a first boundary to a second boundary and from a third boundary to a fourth boundary.

[0154] In various embodiments, obtaining the multiple boundary cells includes obtaining some or all of the multiple boundary cells that have the same or different orientations and / or have a first and a second basin area with the same or reversed markings.

[0155] In some embodiments, obtaining the multiple boundary cells includes obtaining pluralityes of one or more of the above with reference to Fig. 4 cells 400A to 400C discussed. In some embodiments, obtaining the multiple boundary cells includes performing one or more steps of the method 500, described above with reference to Fig. 5 was discussed.

[0156] In some embodiments, obtaining the multiple boundary cells includes obtaining the multiple boundary cells from a cell library, e.g., the one described below with reference to Fig. 8 cell library discussed 807.

[0157] In activity 720, the multiple boundary cells are arranged in a first and a second boundary region, thereby defining a first section of each of the first and second basin regions extending in a first direction. In some embodiments, defining the first section includes aligning the third and fourth boundaries of the plurality in the first direction.

[0158] In some embodiments, arranging the multiple boundary cells includes realigning one or more of the boundary cells and / or reversing the first and second basin sections of one or more of the boundary cells, as described above with reference to Fig. 4 was discussed.

[0159] In some embodiments, the arrangement of the multiple boundary cells in the one or more boundary regions comprises an arrangement of two or more of the cells 400A to 400C in the as above with reference to Fig. 6A to 6C discussed boundary areas BR1A to BR1C and BR2A to BR2C.

[0160] In activity 730, the first and second boundary areas are aligned with an IC device area, thereby defining several basin area sections of each of the first and second basin areas, extending in a second direction orthogonal to the first direction.

[0161] Aligning the first and second boundary areas with the IC device design area involves aligning the n-well and p-well areas of each of the boundary areas with the n-well and p-well areas of the IC device design area.

[0162] In some embodiments, aligning the first and second boundary regions with the IC device region includes aligning two or more of the cells 400A to 400C in the boundary regions BR1A to BR1C and BR2A to BR2C with the as described above with reference to Fig. IC device design area ICR discussed in sections 6A to 6C.

[0163] Activity 740 generates an IC layout diagram that includes the multiple boundary cells and the IC device design area. The generation of the IC layout diagram is performed by a processor, such as the 802 processor described below. Fig. The IC layout generation system 800 discussed in Section 8 is performed. In some embodiments, generating the IC layout diagram, which includes the multiple boundary cells and the IC device design area, involves executing one or more automated-place-and-route algorithms (APR algorithms), thereby arranging one or more functional cells in the IC device area.

[0164] In some embodiments, generating the IC layout diagram includes generating one of the IC layout diagrams 600A to 600C, which are referenced above. Fig. 6A to 6C were discussed.

[0165] In some embodiments, the multiple boundary cells are a plurality of boundary cells of multiple pluralitys of boundary cells, the IC device design area is an IC device design area of ​​multiple IC device design areas, and generating the IC layout diagram includes generating the IC layout diagram that has the multiple pluralitys of boundary cells and the multiple IC device design areas.

[0166] In some embodiments, generating the IC layout diagram, which includes the multiple boundary cells and the IC device design area, comprises generating the IC layout diagram which further includes one or more TSV areas that are part of the definition of one or more TSV structures, e.g., the TSV structure TSVS, referred to above. Fig. 1B and Fig. 1C was discussed, and are set up for inclusion in a manufacturing process.

[0167] In activity 750, in some embodiments, the IC layout diagram is stored in a storage device. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in non-volatile, computer-readable memory or a cell library, e.g., a database, and / or it includes storing the IC layout diagram over a network. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in a computer-readable storage medium 804 and / or over the network 814 described below with reference to Fig. 8 discussed IC layout diagram generation system 800.

[0168] In activity 760, in some embodiments, at least one semiconductor mask or at least one component in a layer of a semiconductor IC is manufactured based on the IC layout diagram. The manufacturing of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is described below with reference to the IC manufacturing system 900 and Fig. 9 discussed.

[0169] In activity 770, one or more manufacturing activities are performed in some embodiments based on the IC layout diagram. In some embodiments, performing one or more manufacturing activities includes performing one or more lithographic exposures based on the IC layout diagram. Performing one or more manufacturing activities, e.g., one or more lithographic exposures, based on the IC layout diagram is described below with reference to Fig. 9 discussed.

[0170] By performing some or all of the activities of procedure 700, an IC layout diagram is produced that corresponds to an IC structure in which a first and a second well of more than two rows of IC devices are used jointly, thereby obtaining the advantages discussed above with reference to IC structure 100 and IC layout diagrams 600A to 600C.

[0171] Fig. Figure 8 is a block diagram of the IC layout diagram generation system 800 according to some embodiments. The methods described in this document for designing IC layout diagrams according to one or more embodiments can be implemented, for example, using the IC layout design generation system 800.

[0172] In some embodiments, the IC layout diagram generation system 800 is a general-purpose computing device comprising a hardware processor 802 and a non-volatile, computer-readable storage medium 804. The storage medium 804 is, among other things, encoded with, i.e., stored in, computer program code 806, i.e., a set of executable instructions. The execution of the instructions 806 by the hardware processor 802 constitutes (at least in part) an EDA tool, performing a procedure, e.g., the one described above with reference to Fig. 5 described methods 500 for generating an IC layout diagram and / or the above with reference to Fig. 7 described procedures 700 for generating an IC layout diagram (hereinafter referred to as “the processes and / or procedures listed”), or implements a part thereof.

[0173] The processor 802 is electrically coupled to the computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I / O interface 810 via the bus 808. A network interface 812 is also electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814, so that the processor 802 and the computer-readable storage medium 804 can connect to external elements via the network 814. The processor 802 is configured to execute the computer program code 806 encoded in the computer-readable storage medium 804, in order to enable the IC layout diagram generation system 800 to perform all or part of the processes and / or procedures listed.In one or more embodiments, the 802 processor is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0174] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or such device or apparatus). For example, the computer-readable storage medium 804 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a solid magnetic disk, and / or an optical disk. In one or more embodiments utilizing optical disks, the computer-readable storage medium 804 comprises a compact disc read-only memory (CD-ROM), a rewritable compact disc (CD-R / W), and / or a digital video disc (DVD).

[0175] In one or more embodiments, the computer-readable storage medium 804 stores computer program code 806 configured to enable the IC layout diagram generation system 800 (where its implementation constitutes (at least in part) the EDA tool) to be used for performing the processes and / or methods mentioned, or a part thereof. In one or more embodiments, the computer-readable storage medium 804 also stores information that facilitates the performance of the processes and / or methods mentioned, or a part thereof. In one or more embodiments, the computer-readable storage medium 804 stores a cell library 807 of cells, including cells as disclosed in this document, e.g., those referred to above. Fig. 4 to 7 discussed cells 400A to 400C.

[0176] The IC layout diagram generation system 800 features the I / O interface 810. The I / O interface 810 is coupled to an external circuit arrangement. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, ball bearing, touchscreen, and / or cursor direction keys to transmit information and instructions to the processor 802.

[0177] The IC Layout Diagram Generating System 800 also features the Network Interface 812 coupled to the Processor 802. The Network Interface 812 allows the System 800 to communicate with the Network 814, to which one or more other computer systems are connected. The Network Interface 812 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, the processes and / or methods mentioned, or a part thereof, are implemented in two or more IC Layout Diagram Generating Systems 800.

[0178] The IC Layout Diagram Generation System 800 is configured to receive information through the I / O interface 810. The information received through the I / O interface 810 contains one or more instructions, data, design rules, libraries of standard cells, and / or other parameters configured for processing by the processor 802. The information is transmitted to the processor 802 via the bus 808. The IC Layout Diagram Generation System 800 is also configured to receive user interface (UI) information through the I / O interface 810. This information is stored as the user interface (UI) 842 on the computer-readable medium 804.

[0179] In some embodiments, the processes and / or methods listed, or a part thereof, are implemented as a standalone software application for execution by a processor. In some embodiments, the processes and / or methods listed, or a part thereof, are implemented as a software application that is part of an additional software application. In some embodiments, the processes and / or methods listed, or a part thereof, are implemented as a plug-in to a software application. In some embodiments, at least one of the processes / methods listed is implemented as a software application that is part of an EDA tool. In some embodiments, the processes and / or methods listed, or a part thereof, are implemented as a software application used by the IC Layout Design Generation System 800.In some embodiments, a layout diagram containing standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0180] In some embodiments, the processes are implemented as functions of a program stored on a non-volatile, computer-readable recording medium. Examples of a non-volatile, computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in mass storage or memory units, e.g., one or more from an optical disc such as a DVD, a magnetic disk such as a hard drive, a semiconductor memory such as a ROM, RAM, memory card, and the like.

[0181] Fig. Figure 9 is a block diagram of an IC manufacturing system 900 and an associated IC manufacturing process according to some embodiments. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an integrated semiconductor circuit is manufactured using the manufacturing system 900 based on an IC layout diagram.

[0182] In Fig. 9 The IC manufacturing system 900 comprises units such as a design department 920, a masking department 930, and an IC manufacturer / producer (“producer”) 950, which interact with each other in the design, development, and manufacturing cycles and / or in providing services related to the manufacture of an IC device 960. The units in the system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each unit interacts with one or more of the other units and provides services to one or more of the other units and / or receives services from one or more of the other units.In some embodiments, two or more from Design Department 920, Mask Department 930, and IC Manufacturer 950 are owned by a single larger company. In some embodiments, two or more from Design Department 920, Mask Department 930, and IC Manufacturer 950 are located side-by-side in a common facility and use common resources.

[0183] Design department (or design team) 920 creates an IC design layout diagram 922. The IC design layout diagram 922 has various geometric structures, e.g., a cell 400A to 400C and / or an IC layout diagram 600A to 600C, which are described above with reference to Fig. The geometric structures discussed in sections 4 to 7 correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 960 to be manufactured. The different layers are combined to form various IC elements. For example, a section of the IC design layout diagram 922 shows various IC elements such as an active region, a gate electrode, a source and a drain, metal traces or vias of an interlayer interconnect, and openings for bond pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers to be placed on the semiconductor substrate. The design section 920 implements a proper design process to form the IC design layout diagram 922.The design process comprises one or more steps, including logical design, physical design, or placement and routing. The IC design diagram 922 is presented in one or more data files containing information regarding the geometric structures. For example, the IC design layout diagram 922 can be expressed in a GDSII file format or a DFII file format.

[0184] The mask department 930 comprises the data preparation unit 932 and the mask fabrication unit 944. The mask department 930 uses the IC design layout diagram 922 to fabricate one or more masks for use in creating the various layers of the IC device 960 according to the IC design layout diagram 922. The mask department 930 performs the mask data preparation unit 932, in which the IC design layout diagram 922 is translated into a corresponding data file (RDF). The mask data preparation unit 932 provides the RDF to the mask fabrication unit 944. The mask fabrication unit 944 includes a mask writer. A mask writer converts the RDF into an image on a substrate such as a mask (reticule) 945 or a semiconductor wafer 953. The design layout diagram 922 is processed by the mask data creation 932 so that it meets certain properties of the mask writer and / or requirements of the IC manufacturer 950. In Fig. Figure 9 shows the mask data preparation 932 and the mask production 944 as separate elements. In some embodiments, the mask data preparation 932 and the mask production 944 can be referred to together as mask data preparation.

[0185] In some embodiments, the mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancements to correct image defects such as those that may result from diffraction, interference, other process effects, and the like. The OPC regulates the IC design layout diagram 922. In some embodiments, the mask data preparation 932 also includes resolution enhancement techniques (RET) such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, an inverse lithography technology (ILT) is also used, which treats the OPC as an inverse imaging problem.

[0186] In some embodiments, the mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout diagram 922, which has undergone OPC processes, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variations in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout diagram 922 to compensate for constraints during mask production 944, which may also undo some of the modifications made by the OPC to satisfy the mask generation rules.

[0187] In some embodiments, the mask data preparation 932 includes a lithography process checking (LPC) that simulates the processing that will be implemented by the IC fabricator 950 to produce the IC fixture 960. The LPC simulates this processing based on the IC design layout diagram 922 to generate a simulated fabricated device such as the IC fixture 960. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC fabrication cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the fabrication process. The LPC takes into account various factors such as aerial image contrast, depth of focus (DOPF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, the OPC and / or the MRC are repeated by the LPC after the creation of a simulated manufactured device in order to further refine the IC design layout diagram 922 if the shape of the simulated device does not come close enough to meeting the design rules.

[0188] It should be understood that the above description of mask data preparation 932 has been simplified for clarity. In some embodiments, data preparation 932 includes additional features such as a logical operation (LOP) to modify the IC design layout diagram 922 according to manufacturing rules. Furthermore, the processes applied to the IC design layout diagram 922 during data preparation 932 can be performed in a variety of different sequences.

[0189] Following mask data preparation 932 and during mask fabrication 944, a mask 945 or a group of masks 945 is fabricated based on the modified IC design layout diagram 922. In some embodiments, mask fabrication 944 includes performing one or more lithographic exposures based on the IC design layout diagram 922. In some embodiments, an electron beam (E-beam) or a mechanism of multiple E-beams is used to form a structure on a mask (a photomask or a reticulum) 945 based on the modified IC design layout diagram 922. The mask 945 can be formed by various technologies. In some embodiments, the mask 945 is formed using a binary technology. In some embodiments, a mask structure has opaque and transparent regions.An irradiation beam, such as an ultraviolet (UV) or EUV beam, used to expose the image-sensitive material layer (e.g., a photoresist) deposited on a wafer, is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of Mask 945 has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) deposited in the opaque areas of the binary mask. In another example, Mask 945 is formed using a phase-shift technology. In a phase-shift mask version (PSM version) of Mask 945, various features in the structure formed on the phase-shift mask are arranged to have a suitable difference to improve resolution and image quality.In various examples, the phase-shift mask can be a weakened PSM or an alternating PSM. The mask(s) produced by the mask fabrication 944 is / are used in a variety of processes. For example, such a mask can be used in an ion implantation process to form different doped regions in the semiconductor wafer 953, in an etching process to form different etched regions in the semiconductor wafer 953, and / or in other suitable processes.

[0190] The IC Producer 950 is an IC manufacturing facility that includes one or more manufacturing facilities for producing a variety of different IC products. In some embodiments, the IC Producer 950 is a semiconductor foundry. For example, one manufacturing facility may be provided for the front-end manufacturing of several IC products (the front-end-of-line manufacturing, FEOL manufacturing), while a second manufacturing facility may provide the back-end manufacturing for coupling and packaging the IC products (a back-end-of-line manufacturing, BEOL manufacturing), and a third manufacturing facility may provide other services for the foundry operation.

[0191] The IC fabricator 950 comprises wafer fabrication tools 952 configured to perform various fabrication operations on the semiconductor wafer 953 to produce the IC device 960 according to the mask(s), e.g., the mask 945. In various embodiments, the fabrication tools 950 comprise one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed in this document.

[0192] The IC maker 950 uses mask(s) 945, manufactured by the mask department 930, to manufacture the IC device. Therefore, the IC maker 950 uses the IC design layout diagram 922, at least indirectly, to manufacture the IC device 960. In some embodiments, the semiconductor wafer 953 is manufactured by the IC maker 950 using mask(s) to form the IC device 960. In some embodiments, the IC manufacturing process includes performing one or more lithographic exposures based at least partially on the IC design layout diagram 922. The semiconductor wafer 953 has a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer 953 further has one or more of different doped regions, dielectric elements, multi-level interconnects, and the like (formed in subsequent manufacturing steps).

[0193] Details relating to an IC manufacturing system (e.g., the System 900 from Fig. 9) and an associated IC manufacturing process can be found, for example, in US patent 9,256,709 B2, granted on February 9, 2016; US patent 2015 / 0 278 429 A1, published on October 1, 2015, which preceded the grant; US patent 2014 / 0 040 838 A1, published on February 6, 2014, which preceded the grant; and US patent 7,260,442 B2, granted on August 21, 2007.

[0194] In some embodiments, an IC structure has a first continuous trough, which is one of an n-trough or a p-trough, wherein the first continuous trough has a first trough section extending in a first direction, a second trough section extending in a second direction orthogonal to the first direction from the first trough section, and a third trough section extending parallel to the second trough section in the second direction from the first trough section.In some embodiments, the IC structure has a second continuous well, which is the other of the n-well or the p-well, wherein the second continuous well section comprises a fourth well section extending in the first direction, a fifth well section extending from the fourth well section in a third direction opposite to the second direction, and a sixth well section extending from the fourth well section in the third direction and parallel to the fifth well section. In some embodiments, the second and fifth well sections correspond to a first row of IC devices, and the third and sixth well sections correspond to a second row of IC devices.In some embodiments, the IC structure comprises a third continuous trough, which includes a seventh trough section extending in the first direction, an eighth trough section extending in the second direction from the seventh trough section, and a ninth trough section extending in the second direction parallel to the eighth trough section from the seventh trough section, and a TSV structure positioned between the third continuous trough and the first and second continuous troughs. In some embodiments, the first and second continuous troughs, the TSV structure, and the third continuous trough are aligned along the second direction. In some embodiments, each of the fourth and seventh trough sections is positioned along a boundary of an isolation structure of the TSV structure.In some embodiments, a first IC die comprises the IC structure, an IC package comprises the first IC die and a second IC die, and the TSV structure is electrically connected to the second IC die. In some embodiments, the first continuous well is the n-well and comprises a single pickup structure electrically connected to a first power distribution structure configured to provide a power supply voltage, and the second continuous well is the p-well and comprises a single pickup structure electrically connected to a second power distribution structure configured to provide a reference voltage.

[0195] In some embodiments, an IC structure comprises a first and a second TSV insulation structure oriented along a first direction, a first continuous well, which is either an n-well or a p-well, wherein the first continuous well has a first well section adjacent to the first TSV insulation structure and several second well sections extending in the first direction from the first well section, and a second continuous well, which is the other of the n-well or the p-well, wherein the second continuous well has a third well section adjacent to the second TSV insulation structure and several fourth well sections extending in a second direction opposite to the first direction from the third well section.wherein the multiple second well sections alternate with the multiple fourth well sections along a third direction orthogonal to the first and second directions. In some embodiments, the IC structure has multiple tap structures, each tap structure of the plurality of tap structures comprising a first tap structure electrically connected to the first continuous well and a first power distribution structure, and a second tap structure electrically connected to the second continuous well and a second power distribution structure separate from the first power distribution structure.wherein the number of tap structures of the plurality of tap structures is less than the number of well sections of each of the plurality of second well sections and the plurality of fourth well sections. In some embodiments, the ratio of the number of well sections of each of the plurality of second well sections and the plurality of fourth well sections to the number of tap structures of the plurality of tap structures has a value ranging from five to fifteen. In some embodiments, a tap structure of the plurality of tap structures is adjacent to one from the first or the third well section. In some embodiments, the first and second continuous wells are contained in a first die of a 3D IC package, and the first TSV insulation structure surrounds a first TSV structure that is electrically connected to a second die of the 3D IC package.and surrounds the second TSV insulation structure a second TSV structure which is electrically connected to the second die. In some embodiments, the IC structure has multiple rows of IC devices, each row of IC devices having a first transistor located in a second well section of the multiple second well sections and a second transistor located in a fourth well section of the multiple fourth well sections.

[0196] In some embodiments, a method for fabricating an IC structure comprises arranging each of an n-well and a p-well in a first IC die such that it has a first section extending in a first direction and a second and a third section extending in a second direction orthogonal to the first direction from the first section, and forming IC devices comprising a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. The forming of the IC devices comprises forming a PMOS transistor in the second or third section of the n-well and forming an NMOS transistor in the second or third section of the p-well.In some embodiments, such setup of each of the n-tub and the p-tub comprises having the second and third sections extending in the second direction from the first section, and such that the second and third sections of the n-tub and the p-tub have an interlocking configuration. In some embodiments, the setup of the n-tub comprises performing an implantation process on a p-substrate, and the setup of the p-tub comprises setting up a region outside the n-tub as a p-tub based on the fact that it is a section of the p-substrate.In some embodiments, forming the IC devices comprises forming a first electrical connection from the first consumer structure to a first power distribution structure configured to have a power supply voltage, and forming a second electrical connection from the second consumer structure to a second power supply structure configured to have a reference voltage. In some embodiments, the method comprises forming a TSV structure in the first die adjacent to the first section of the n-well or the first section of the p-well. In some embodiments, the method comprises electrically connecting the TSV structure to a second IC die of an IC package.

Claims

[1] Integrated circuit structure, IC structure (100), comprising: a first continuous trough (WA, WB) which is one of an n-trough or a p-trough, wherein the first continuous trough (WA, WB) a first trough section (WAS, WBS) that runs in a first direction (Y); a second trough section (WAPn, WBPn) extending in a second direction (X, -X) orthogonal to the first direction (Y) from the first trough section (WAS, WBS); and a third trough section (WAPn, WBPn) extending parallel to the second trough section (WAPn, WBPn) in the second direction (X, -X) from the first trough section (WAS, WBS), exhibits; a second continuous trough (WB, WA) which is the other of the n-trough or the p-trough, wherein the second continuous trough (WB, WA) a fourth trough section (WBS, WAS) that runs in the first direction (Y); a fifth trough section (WBPn, WAPn) extending in a third direction (-X, X) opposite to the second direction (X, -X) from the fourth trough section (WBS, WAS); and a sixth trough section (WBPn, WAPn) extending in the third direction (-X, X) and parallel to the fifth trough section (WBPn, WAPn) from the fourth trough section (WBS, WAS), exhibits; a third continuous tub, which a seventh tub section running in the first direction (Y); an eighth tub section extending in the second direction (X, -X) from the seventh tub section; and a ninth tub section, which extends in the second direction (X, -X) parallel to the eighth tub section from the seventh tub section, exhibits; and a silicon through-hole structure, TSV structure (TSVS), positioned between the third continuous well and the first and second continuous wells (WB, WA); wherein the first and second continuous troughs (WB, WA), the TSV structure (TSVS) and the third continuous trough are aligned along the second direction (X, -X). [2] IC structure (100) according to claim 1, wherein the second (WAPn, WBPn) and fifth tub section (WBPn, WAPn) correspond to a first series of IC devices (100C), and the third (WAPn, WBPn) and sixth tub section (WBPn, WAPn) correspond to a second series of IC devices (100C). [3] IC structure (100) according to claim 1 or 2, wherein each of the fourth and seventh tub sections is positioned along a boundary of an isolation structure (TSVI) of the TSV structure (TSVS). [4] IC structure (100) according to one of claims 1 to 3, wherein a first IC die (100D, D1) comprises the IC structure (100), an IC package (100P) comprises the first IC die (100D, D1) and a second IC die (100D, D2), and The TSV structure (TSVS) is electrically connected to the second IC die (100D, D2). [5] IC structure (100) according to one of claims 1 to 4, wherein the first continuous trough (WA, WB) is the n-trough and has a single consumer structure (PA, PB) that is electrically connected to a first power distribution structure that is configured to have a power supply voltage, and the second continuous trough (WB, WA) is the p-trough and has a single consumer structure (PB, PA) electrically connected to a second power distribution structure configured to have a reference voltage. [6] Integrated circuit structure, IC structure (100), comprising: a first and a second silicon through-hole insulation structure, TSV insulation structure (TSVI), aligned along a first direction (X, -X); a first continuous trough (WA, WB) which is one of an n-trough or a p-trough, wherein the first continuous trough (WA, WB) a first tub section (WAS, WBS) next to the first TSV isolation structure (TSVI); and several second trough sections (WAPn, WBPn) extending in the first direction (X, -X) from the first trough section (WAS, WBS); and a second continuous trough (WB, WA) which is the other of the n-trough or the p-trough, wherein the second continuous trough (WB, WA) a third tub section (WBS, WAS) next to the second TSV isolation structure (TSVI); and several fourth trough sections (WBPn, WAPn) extending in a second direction (-X, X) opposite to the first direction (X, -X) from the third trough section (WBS, WAS), wherein the multiple second trough sections (WAPn, WBPn) alternate along a third direction (Y) orthogonal to the first (X, -X) and second direction (-X, X) with the multiple fourth trough sections (WBPn, WAPn). [7] IC structure (100) according to claim 6, further comprising several tap structures (PA, PB), wherein each tap structure (PA, PB) of the plurality of tap structures (PA, PB) a first consumer structure (PA, PB) that is electrically connected to the first continuous trough (WA, WB) and a first power distribution structure; and a second consumer structure (PB, PA) that is electrically connected to the second continuous trough (WB, WA) and a second power distribution structure separate from the first power distribution structure, and a number of tap structures (PA, PB) of the plurality of tap structures (PA, PB) is less than a number of trough sections of each of the plurality of second trough sections (WAPn, WBPn) and the plurality of fourth trough sections (WBPn, WAPn). [8] IC structure (100) according to claim 7, wherein the ratio of the number of trough sections of each of the plurality of second trough sections (WAPn, WBPn) and the plurality of fourth trough sections (WBPn, WAPn) to the number of tap structures (PA, PB) of the plurality of tap structures (PA, PB) has a value ranging from five to fifteen. [9] IC structure (100) according to claim 7 or 8, wherein a tap structure (PA, PB) of the plurality of tap structures (PA, PB) is located next to one from the first (WAS, WBS) or the third trough section (WBS, WAS). [10] IC structure (100) according to one of claims 6 to 9, wherein the first (WB, WA) and the second continuous well (WB, WA) are contained in a first die (100D, D1) of a 3D IC package (100P), the first TSV isolation structure (TSVI) surrounds a first TSV structure that is electrically connected to a second die (100D, D2) of the 3D IC package (100P), and the second TSV insulation structure (TSVI) surrounds a second TSV structure that is electrically connected to the second die (100D, D2). [11] IC structure (100) according to any one of claims 6 to 10, further comprising several rows of IC devices (100C), wherein each row of IC devices (100C) of the several rows of IC devices (100C) a first transistor located in a second well section (WAPn, WBPn) of several second well sections (WAPn, WBPn); and a second transistor located in a fourth well section (WBPn, WAPn) of several fourth well sections (WBPn, WAPn). [12] Method for manufacturing an integrated circuit structure, IC structure (100), wherein the method such an arrangement of each of an n-tub and a p-tub in a first IC die (100D, D1) such that it has a first section (WAS, WBS) extending in a first direction (Y), and a second and a third section (WAPn, WBPn) extending in a second direction (X, -X) orthogonal to the first direction (Y) from the first section; and a formation of IC devices (100C) comprising a first pickup structure (PA, PB) electrically connected to the n-well and a second pickup structure (PB, PA) electrically connected to the p-well, includes wherein the formation of the IC devices (100C) includes forming a PMOS transistor in the second or third section (WAPn, WBPn) of the n-well and forming an NMOS transistor in the second or third section (WAPn, WBPn) of the p-well; wherein the method further comprises: erecting a silicon through-hole structure, TSV structure (TSVS), in the first die (100D, D1) next to the first section (WAS, WBS) of the n-well or the first section (WBS, WAS) of the p-well. [13] Method according to claim 12, wherein such a setup of each of the n-tub and the p-tub, comprising having the second and the third (WAPn, WBPn) sections extending in the second direction (X, -X) from the first section (WAS, WBS), comprises the second and the third sections (WAPn, WBPn) of the n-tub and the p-tub having an interlocking configuration. [14] Method according to claim 12 or 13, wherein Setting up the n-tub involves performing an implantation process on a p-substrate, and Setting up the p-tub includes setting up an area outside the n-tub based on the fact that it is a section of the p-substrate, as the p-tub. [15] Method according to any one of claims 12 to 14, wherein the forming of the IC devices (100C) forming a first electrical connection from the first consumer structure (PA, PB) to a first power distribution structure configured to have a power supply voltage; and forming a second electrical connection from the second consumer structure (PB, PA) to a second power supply structure, which is set up to have a reference voltage, includes. [16] Method according to any one of claims 12 to 15, further comprising electrically connecting the TSV structure (TSVS) to a second IC die (100D, D2) of an IC package (100P).

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