High-texture interface layer for improving a ferroelectric layer

Abstract

Integrated circuit chip, IC chip comprising a memory cell (102), wherein the memory cell (102) comprises: a lower electrode (108); a ferroelectric layer (106) located above the lower electrode (108); an upper electrode (110) located above the ferroelectric layer (106); and a first interface layer (104, 104b) between the ferroelectric layer (106) and the lower electrode (108), wherein a top surface (114) of the first interface layer (104, 104b) has a higher texture uniformity than a top surface (112) of the lower electrode (108) in order to improve the remanent polarization of the ferroelectric layer (106); and wherein the first interface layer (104, 104b) is an amorphous dielectric, amorphous metal, or amorphous metal oxide.

Description

BACKGROUNDMany modern electronic devices include nonvolatile memory. A nonvolatile memory is an electronic memory capable of storing data even when not powered. One of a number of promising candidates for the next generation of nonvolatile memories is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal oxide semiconductor (CMOS) logic fabrication processes. CN 1 13 130 498 A discloses a ferroelectric memory structure and its manufacturing method.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common practice in the industry, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be increased or decreased as needed in the interest of clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiments of a memory cell where an interfacial layer with high texture uniformity is located at the bottom of a ferroelectric layer. FIGS. 2A and 2B illustrate cross-sectional views of some embodiments of the memory cell of FIG. 1, wherein the material type of the interfacial layer is varied. FIG. 3 illustrates a cross-sectional view of some alternative embodiments of the memory cell of FIG. 1, wherein an additional interfacial layer is located on the ferroelectric layer. FIGS. 4A-4D illustrate cross-sectional views of some embodiments of the memory cell of FIG. 3 where the material types of the interfacial layers are varied. FIG. 5 illustrates a cross-sectional view of some alternative embodiments of the memory cell of FIG. 1, wherein interfacial layers with high texture uniformity are alternately stacked with ferroelectric layers. FIG. 6 illustrates a cross-sectional view of some alternative embodiments of the memory cell of FIG. 5, wherein an additional interfacial layer is on an uppermost ferroelectric layer of ferroelectric layers. FIGS. 7A and 7B illustrate various views of some embodiments of the memory cell of FIG. 1, where the memory cell is integrated into an interconnect structure of an integrated circuit (IC) chip. FIGS. 8A-8C illustrate cross-sectional views of some alternative embodiments of the memory cell of FIG. 7A, wherein a layout of the memory cell is varied. FIG. 9 illustrates a cross-sectional view of some alternative embodiments of the memory cell of FIG. 7A, wherein an additional interfacial layer is located on a top surface of the ferroelectric layer as in FIG. 3. FIGS. 10A-10E illustrate cross-sectional views of some alternative embodiments of the memory cell of FIG. 9 wherein a layout of the memory cell is varied. FIGS. 11A and 11B illustrate cross-sectional views of some embodiments of an IC chip that includes memory cells integrated into individual single transistor single capacitor (1T1C) cells and configured as in FIG. 7A. FIG. 12 illustrates a top view layout view of some embodiments of the IC chip of FIGS. 11A and 11B. FIG. 13 illustrates a cross-sectional view of some embodiments of an IC chip including a ferroelectric field effect transistor (FeFET) in which an interfacial layer with high texture uniformity is located at the bottom of a ferroelectric layer. FIGS. 14-26 illustrate a series of cross-sectional views of some embodiments of a method of forming an IC chip that includes memory cells integrated into individual 1T1C cells and in which interfacial layers with high texture uniformity are located at bottom surfaces of the ferroelectric layers. FIG. 27 illustrates a block diagram of some embodiments of the method of FIGS. 14-26. Figures 28 and 29 illustrate a series of cross-sectional views of some first alternative embodiments of the method of Figures 14-26. Figures 30-32 illustrate a series of cross-sectional views of a second alternative embodiment of the method of Figures 14-26. Figures 33-35 illustrate a series of cross-sectional views of a third alternative embodiment of the method of Figures 14-26. Figures 36-40 illustrate a series of cross-sectional views of a fourth alternative embodiment of the method of Figures 14-26.DETAILED DESCRIPTIONThe present disclosure provides many different embodiments or examples for implementing different features of this disclosure. Concrete examples of components and arrangements will be described below in order to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, forming a first structural element over or on a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not automatically provide a relationship between the various embodiments and / or configurations discussed.Furthermore, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to facilitate the description to describe the relationship of an element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be otherwise oriented (rotated 90 degrees, or other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.An integrated circuit (IC) chip may include a memory cell in an interconnect structure of the IC chip. The memory cell may include a bottom electrode, a ferroelectric layer overlying the bottom electrode, and a top electrode overlying the ferroelectric layer. The interconnect structure may include a bottom electrode wire underlying the memory cell, a top electrode wire overlying the memory cell, and vias extending from the bottom and top electrode wires to the bottom and top electrodes, respectively.A challenge with the memory cell is that a top surface of the bottom electrode may have low texture uniformity. Because the ferroelectric layer is formed on the top surface of the bottom electrode, the low texture uniformity may result in a high degree of variation and degradation in the properties of the ferroelectric layer. For example, the remanent polarization may vary greatly, which may result in a low production yield in mass production. As another example, the remanent polarization may degrade, which may cause read operations to be prone to errors. Furthermore, a memory cell having a small footprint may have less texture uniformity than a same memory cell having a large footprint. A small footprint may be, for example, a footprint that extends over an area of no more than about 0.25 square micrometers or another suitable value. As electronic devices and memory cells become smaller and smaller, the low texture uniformity may become an ever greater challenge.Various embodiments of the present disclosure relate to a memory cell wherein an interfacial layer is located at a bottom side of a ferroelectric layer between a bottom electrode and a ferroelectric layer. The interface layer is a different material than the bottom electrode and the ferroelectric layer, and has a top surface with high texture uniformity compared to a top surface of the bottom electrode. The barrier layer may be, for example, a dielectric, a metal oxide, or a metal that is: (1) amorphous; (2) single crystalline; (3) crystalline with small grain size variation; (4) crystalline with a high percentage of grains that have a common orientation; (5) crystalline with a high percentage of grains with small grain size; or (6) any combination of the above. Such materials have been found to result in high texture uniformity on the top surface of the barrier layer. Regardless of the materials listed above for the boundary layer, other suitable materials are also conceivable.Because the barrier layer may be a dielectric, a metal oxide, or an amorphous or crystalline metal, the barrier layer may be incorporated into embedded memory structures and processes without fear of deleterious contamination by the barrier layer. Because the ferroelectric layer is formed on the top surface of the bottom electrode, and because the top surface has high texture uniformity, the properties of the ferroelectric layer may be improved and / or may have high uniformity. For example, the remanent polarization may have high uniformity, which may result in a low production yield in mass production. As another example, the remanent polarization may be improved, thereby causing read operations to be less prone to errors. Furthermore, the high uniformity may allow for a larger scale down of the memory cell.FIG. 1 shows a cross-sectional view 100 of some embodiments of a memory cell 102 where an interfacial layer 104 with high texture uniformity is located at a bottom of a ferroelectric layer 106. The memory cell 102 may be, for example, a metal-ferroelectric-metal (MFM) cell, a ferroelectric capacitor, a ferroelectric tunnel junction (FTJ), another structure suitable for data storage, or any combination of the foregoing.The interface layer 104 overlies a bottom electrode 108, the ferroelectric layer 106 overlies the interface layer 104, and a top electrode 110 overlies the ferroelectric layer 106. The interface layer 104 is a different material than the ferroelectric layer 106 and the bottom electrode 108 and directly contacts the bottom electrode 108 at a top surface 112 of the bottom electrode 108. The ferroelectric layer 106 has a remanent polarization and contacts the interface layer 104 directly at an upper side 114 of the interface layer 104.The top surfaces 112, 114 of the bottom electrode 108 and the barrier layer 104 have relatively low texture uniformity and high texture uniformity, respectively. In other words, as compared to the top surface 112 of the bottom electrode 108, the top surface 114 of the interfacial layer 104 has higher texture uniformity. The texture may correspond to, for example, the deviation of a surface from a perfectly flat plane with respect to location, roughness, waviness, one or more other suitable parameters, or any combination of the above.Forming the ferroelectric layer 106 on a surface having high texture uniformity rather than low texture uniformity has been found to improve the properties of the ferroelectric layer 106 and / or increase the uniformity of the properties of the ferroelectric layer 106. Non-limiting examples of such properties include remanent polarization, crystalline quality, surface roughness, texture, other suitable properties, or any combination of the foregoing. Therefore, because the ferroelectric layer 106 is formed on the top surface 114 of the interface layer 104 and not on the top surface 112 of the bottom electrode 108, the characteristics of the ferroelectric layer 106 may be improved and / or may have high uniformity. For example, the remanent polarization of the ferroelectric layer 106 may have high uniformity, which may result in a low production yield in mass production. As another example, the remanent polarization of the ferroelectric layer 106 may be improved (e.g., increased), which may reduce the susceptibility of reads to errors. If the interface layer 104 were omitted and the ferroelectric layer 106 was formed on the top side 112 of the lower electrode 108, the properties of the ferroelectric layer 106 could be deteriorated and / or could have a low uniformity.In some embodiments, the memory cell 102 is formed as a volume of material across a wafer and / or batch of wafers. Furthermore, the remanent polarization or other suitable property of the ferroelectric layer 106 is measured at multiple locations of the memory cell 102 that are distributed across the wafer and / or batch of wafers. In at least some of these embodiments, the measurements have little variation (e.g., high uniformity) due to the high texture uniformity on the top surface 114 of the interfacial layer 104. The variation may be determined as, for example, (MAX-MIN) / (2xAVG)*100, where MAX corresponds to the maximum measurement, MIN corresponds to the minimum measurement, and AVG corresponds to the average of the measurements. A minor variation may be, for example, a variation of less than 10%, 5%, or another suitable value.Because the properties of the ferroelectric layer 106 may be improved and / or have high uniformity, the memory cell 102 may be reduced more than would otherwise be possible. For example, the memory cell 102 may be scaled down such that a footprint of the ferroelectric layer 106 has a small area of less than about 0.25 square micrometers or other suitable value. A footprint may correspond to a two-dimensional (2D) projection of the ferroelectric layer 106 onto the top side 112 of the bottom electrode 108, for example. In some embodiments, the 2D projection has the same area as a top side of the ferroelectric layer 106 and / or as a bottom side of the ferroelectric layer 106.As mentioned above, the texture may correspond to, for example, the deviation of a surface from a perfectly flat plane with respect to location, roughness, waviness, one or more other suitable parameters, or any combination of the above. The "ply" may refer to the direction of the predominant surface structure, for example. The roughness may refer to a measure of spaced-apart surface irregularities, for example. Curl parameters may relate, for example, to a measure of spaced surface irregularities overlaid by the roughness. As compared with the irregularities of roughness, the irregularities of the corrugation are larger and have a larger pitch.In some embodiments, the texture at the tops 112, 114 of the bottom electrode 108 and the interfacial layer 104, respectively, is measured by interferometry, atomic force microscopy (AFP), other suitable methodology, or any combination of the foregoing, and / or is measured using a profiler or other suitable instrument. In some embodiments, the texture on the top surface 112 of the bottom electrode 108 is measured as described above before the interface layer 104 is formed, and / or the texture on the top surface 114 of the interface layer 104 is measured as described above before the ferroelectric layer 106 is formed.In some embodiments, the texture on the tops 112, 114 of the bottom electrode 108 and the interfacial layer 104, respectively, is quantified by one, two, three, or more texture parameters. Such texture parameters may include, for example, arithmetic mean deviation / average roughness (e.g., Ra), root mean square roughness (e.g., Rq), average ripple (e.g., Wa), total ripple (e.g., Wt), ripple spacing (e.g., Wsm), one or more other suitable parameters, or any combination of the above. If the texture is quantified using multiple texture parameters, the texture parameters may be combined into a single size by an average function, a weighted average function, or another suitable function.In some embodiments, the variation for a set of measurements is a percentage determined as (MAX-MIN) / (2xAVG)*100, where MAX corresponds to the maximum measurement, MIN corresponds to the minimum measurement, and AVG corresponds to the average of the measurements. Further, in some embodiments, the uniformity for the set of measurements is a percentage determined as 100 VARIATION, where VARIATION is determined as above. For example, if VARIATION is 5%, the uniformity may be 95%. Thus, in some embodiments, the texture variation and / or uniformity of a surface (e.g., the bottom electrode top surface 112 or the top surface 114 of the interfacial layer 104) may be determined as above from a set of measurements that quantify the texture of the surface.In some embodiments, the texture variation or uniformity on the top surface 112 of the bottom electrode 108 and the texture variation or uniformity on the top surface 114 of the interfacial layer 104 are each determined as above from a set of measurements determined by measuring the texture at multiple different locations distributed across the top surface 112, 114. In some embodiments, the memory cell 102 is formed as a volume of material across a wafer and / or batch of wafers. Furthermore, as above, the texture variation or uniformity on the top surface 112 of the bottom electrode 108 and the texture variation or uniformity on the top surface 114 are each determined from a set of measurements determined by measuring the texture of the top surface 112, 114 at multiple locations of the memory cell 102 distributed across the wafer and / or batch of wafers.In some embodiments, the texture on the tops 112, 114 of the bottom electrode 108 and the interfacial layer 104, respectively, is quantified using the average roughness (e.g., Ra). For example, a first set of average roughness measurements may be measured at multiple locations uniformly distributed across the top surface 112 of the bottom electrode 108, and a second set of average roughness measurements may be measured at multiple locations uniformly distributed across the top surface 114 of the interfacial layer 104. In some embodiments, the average of the second set of measurements may be less than the average of the first set of measurements due to the high texture uniformity on the top surface 114 of the interfacial layer 104. Furthermore, the variation of the second set of measurements may be less than that of the first set of measurements. In other words, the uniformity of the second set may be higher than that of the first set.In some embodiments, the interfacial layer 104 is or comprises: (1) an amorphous dielectric; (2) an amorphous metal oxide; (3) an amorphous metal; (4) one or more other suitable materials; or (5) or any combination of the foregoing. The amorphous metal may be limited to, for example, one or more metal elements or consist essentially of one or more metal elements. The amorphous dielectric may optionally be or comprise a metal oxide and may optionally comprise an oxide. It has been found that the amorphousness of the interface layer 104 may result in high texture uniformity on the top surface 114 of the interface layer 104.In other embodiments, the interfacial layer 104 is or comprises: (1) a crystalline dielectric; (2) a crystalline metal oxide; (3) a crystalline metal; (4) has one or more other suitable materials; or (5) or any combination of the foregoing. The crystalline metal may be, for example, limited to one or more metal elements or consist essentially of one or more metal elements. The crystalline dielectric may optionally be or comprise a metal oxide and may optionally comprise an oxide.In some embodiments where the interfacial layer 104 is a crystalline dielectric, a crystalline metal oxide, or a crystalline metal, the interfacial layer: (1) single crystalline; (2) a small grain size variation; (3) a high percentage of grains with a common orientation; (4) a high percentage of grains with a small grain size; or (5) any combination of the above. It has been found that such crystalline properties may result in high texture uniformity on the top surface 114 of the interfacial layer 104. In at least some embodiments, properties (1) through (4) are ordered from "most effective" through "least effective" as texture uniformity increases.The grain size variation may be determined as, for example, (MAX-MIN) / (2xAVG)*100, where MAX corresponds to the maximum grain size, MIN corresponds to the minimum grain size, and AVG corresponds to the average grain size. The small grain size variation at (2) may be, for example, a grain size variation of less than about 10%, about 5%, or another suitable value. The high percentage at (3) and / or (4) may be, for example, a majority of the grains and / or may be, for example, a percentage greater than about 90%, about 95%, or another suitable value. The co-orientation at (3) may be represented, for example, by the Miller index or other suitable designation system and / or may be measured, for example, by X-ray diffraction analysis (XRD) or by other suitable methodology. Furthermore, the common orientation at (3) may be, for example, a most common or majority grain orientation. In some embodiments where the interfacial layer 104 is crystalline titanium nitride, more than 90% of the grains may have a common orientation of (111). The small grain size at (4) may correspond to, for example, the average grain size, the maximum grain size, the average grain size, or the like, which is no greater than about 1 nanometer, 0.5 nanometer, or another suitable value.Because the barrier layer 104 may be a dielectric, a metal oxide, or a metal, the barrier layer 104 may be incorporated into embedded memory structures and processes without fear of the barrier layer 104 causing harmful contamination of process tools and / or the structure surrounding the barrier layer 104.In some embodiments where the interfacial layer 104 is or comprises a crystalline dielectric or a crystalline metal oxide, the crystalline dielectric or crystalline metal oxide has a crystallization temperature above about 400 degrees Celsius, about 700 degrees Celsius, about 1000 degrees Celsius, or another suitable value. For example, the crystalline dielectric or metal oxide may be or may comprise alumina (e.g., Al 2 O 3), silicon oxide (e.g., SiO 2), ruthenium oxide (e.g., RuO), another suitable material, or any combination of the above.In some embodiments where the interfacial layer 104 is or comprises a dielectric or metal oxide, regardless of whether amorphous or crystalline, the interfacial layer 104 has a high energy band gap. Such a large energy band gap may be, for example, a band gap that is larger than that of the ferroelectric layer 106. For example, the ferroelectric layer 106 may be or comprise hafnium zirconium oxide (e.g., HZO), while the barrier layer 104 may be or comprise aluminum oxide (e.g., Al 2 O 3). However, other suitable materials are also conceivable. The large energy band gap at the interface layer 104 may reduce leakage current.In some embodiments, a thickness T i of the interfacial layer 104 is greater than 0 and is about 5-100 angstroms, about 5-50 angstroms, about 50-100 angstroms, or another suitable value. If the thickness T i is less than about 50 angstroms and the barrier layer 104 is crystalline, an average grain size of the barrier layer 104 is generally less than about 5 angstroms (e.g., 0.5 nanometers), regardless of the material.In some embodiments, the ferroelectric layer 106 is or comprises a binary oxide, a ternary oxide or nitride, a quaternary oxide, one or more other suitable ferroelectric materials, or any combination of the above. The binary oxide may be or comprise, for example, hafnium oxide (for example, hafnium or HfO2) and / or one or more other suitable binary oxides. The ternary oxide or nitride may include, for example, hafnium silicate (for example, HfSiO x), hafnium zirconate (for example, HfZrO x), barium titanate (for example, BaTiO 3), lead titanate (for example, PbTiO 3), strontium titanate (for example, SrTiO 3), calcium manganite (for example, CaNbO 3), bismuth ferrite (for example, BiFeO 3), aluminum scandium nitride (for example, AlScN), aluminum gallium nitride (for example, AlGaN), Aluminum yttrium nitride (e.g., AlYN), may be or comprise one or more other suitable ternary oxides and / or nitrides, or any combination of the above. The quaternary oxide may be or comprise, for example, barium strontium titanate (e.g., BaSrTiOx) and / or one or more other suitable quaternary oxides.In some embodiments, a thickness T f of the ferroelectric layer 106 is about 50-200 angstroms, about 50-125 angstroms, about 125-200 angstroms, or another suitable value. For example, the thickness T f may be about 120 angstroms or another suitable value. If the thickness T f is too small (e.g., less than about 50 angstroms or another suitable value) or too large (e.g., greater than about 200 angstroms or another suitable value), the ferroelectric layer 106 may not exhibit a ferroelectric response or an unusually small ferroelectric response. In other words, if the thickness T f is too small or too large, the ferroelectric layer 106 may not have a remanent polarization or may have an unusually small remanent polarization.In some embodiments, the bottom electrode 108 and / or the top electrode 110 are or comprise titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), ruthenium (e.g., Ru), platinum (e.g., Pt), iridium (e.g., Ir), molybdenum (e.g., Mo), tungsten (e.g., W), doped polysilicon, one or more other suitable conductive materials, or any combination of the foregoing. In some embodiments, the bottom electrode 108 is a same material as the top electrode 110. In other embodiments, the bottom electrode 108 is a different material than the top electrode 110.In some embodiments, the bottom electrode 108 is crystalline. Furthermore, in at least some embodiments where the bottom electrode 108 is crystalline, the bottom electrode 108 is: (1) polycrystalline; (2) a high grain size variation; (3) a low percentage of grains with a common orientation; (4) a low percentage of grains with a small grain size; or (5) any combination of the above. It has been found that such crystalline properties may result in low texture uniformity on the top surface 112 of the bottom electrode 108. The high grain size variation at (2) may be, for example, a grain size variation greater than that of the interfacial layer 104 and / or greater than about 10%, about 20%, about 50%, or another suitable value. The common orientation at (3) may be, for example, the most common or the majority grain orientation. The low percentage at (3) may be, for example, a percentage less than that of the barrier layer 104 and / or less than about 10%, about 5%, or another suitable value. Similarly, the low percentage at (4) may be, for example, a percentage that is less than that of the barrier layer 104 and / or less than about 10%, about 5%, or another suitable value. Grain size variation and small grain size are as described above with respect to the boundary layer 104.In some embodiments, a thickness T be of the bottom electrode 108 is about 50-200 angstroms, about 50-125 angstroms, about 125-200 angstroms, or another suitable value. If a thickness T be is too thin (e.g., less than about 50 angstroms or another suitable value), a resistance of the bottom electrode 108 may be too high. The high resistance may result in poor efficiency and / or may prevent operation of the memory cell 102 at standard voltages.In some embodiments, a ratio of the thickness T be of the bottom electrode 108 to the thickness T i of the barrier layer 104 is about 0.5-40, about 0.5-20, about 20-40, or another suitable value. In some embodiments, a sum of the thickness T be of the bottom electrode 108 and the thickness T i of the barrier layer 104 is about 55-300 angstroms, about 55-180 angstroms, about 180-300 angstroms, or another suitable value. If the sum is too large (e.g., greater than about 300 angstroms or another suitable value), the height of the memory cell 102 may be too large. This may result in processing issues during formation of the memory cell 102 and / or integrating the memory cell 102 into embedded memory processing process flows.In some embodiments, a thickness T te of the top electrode 110 is about 100-300 angstroms, about 100-200 angstroms, about 200-300 angstroms, or another suitable value. If the thickness T te of the top electrode 110 is too great (e.g., greater than about 300 angstroms or another suitable value), a height of the memory cell 102 may be too great.During operation of memory cell 102, the remanent polarization of ferroelectric layer 106 is used to represent a bit of data. For example, a positive polarity of the remanent polarization may represent a binary "0", while a negative polarity of the remanent polarization may represent a binary "1", or vice versa.In order to set the remanent polarization to the positive polarity, a first write voltage is applied to the ferroelectric layer 106 from the upper electrode 110 to the lower electrode 108. In order to set the remanent polarization to the negative polarity, a second write voltage is applied to the ferroelectric layer 106 from the upper electrode 110 to the lower electrode 108. The first and second write voltages have opposite polarities and have orders of magnitude greater than the coercive voltage. In some embodiments, to read the polarity of the remanent polarization, the remanent polarization is set to the positive or negative polarity as described above. As the polarity of the remanent polarization changes, a current pulse occurs. Otherwise, no current pulse occurs. Therefore, the current pulse can be used to identify the polarity of the remanent polarization.Referring now to FIGS. 2A and 2B, there are shown cross-sectional views 200A, 200B of some embodiments of the memory cell 102 of FIG. 1, wherein the interfacial layer 104 is a group 1 material and a group 2 material, respectively. In other words, the boundary layer 104 in FIG. 2A is a boundary layer 104 g1 of the group 1 and in FIG. 2B is a boundary layer 104 g2 of the group 2.A group 1 material is a dielectric or metal oxide that is amorphous or crystalline as described with reference to FIG. 1. The dielectric may optionally be or comprise a metal oxide and may optionally comprise an oxide. In some embodiments, the metal oxide is conductive. For example, the metal oxide may be conductive in embodiments where the metal oxide is or comprises ruthenium oxide (e.g., RuOx), iridium oxide (e.g., IrOx), or other suitable material. In other embodiments, the metal oxide is dielectric.A Group 2 material is conductive and is an amorphous or crystalline metal as described with reference to FIG. 1. The metal is conductive and may be, for example, limited to one or more metal elements or consist essentially of one or more metal elements.In FIG. 3, a cross-sectional view 300 of some alternative embodiments of the memory cell 102 of FIG. 1 is shown, wherein the memory cell 102 comprises an additional interfacial layer 104. The additional interface layer 104 is adjacent to the top electrode 110, between the top electrode 110 and the ferroelectric layer 106, and may therefore be referred to as a top interface layer 104 t. Furthermore, the interface layer 104 of FIG. 1 is adjacent to the bottom electrode 108, between the bottom electrode 108 and the ferroelectric layer 106, and may therefore be referred to as the bottom interface layer 104 b.The lower and upper interface layers 104 b, 104 tare each as described for the interface layer 104 of FIG. 1. In some embodiments, the lower and upper barrier layers 104 b, 104 tare the same material. In other embodiments, the lower and upper interfacial layers 104 b, 104 tare different materials. Further, the lower and upper interface layers 104 b, 104 thave an interface lower layer thickness T bi and an interface upper layer thickness T ti, respectively, which are as described for the interface layer thickness T i in FIG. 1.In some embodiments, a ratio of the thickness T te of the top electrode 110 and the upper interfacial thickness T ti is about 1-60, about 1-30, about 30-60, or another suitable value. In some embodiments, a sum of the thickness T te of the top electrode 110 and the upper interfacial thickness T ti is about 105-400 angstroms, about 105-250 angstroms, about 250-400 angstroms, or another suitable value. If the sum is too thin (e.g., less than about 105 angstroms or another suitable value), then the etching to form a top electrode via (TEVA) on top electrode 110 may over etch to ferroelectric layer 106. For example, over-etching may enhance contamination of the process tools, and / or the material of the TEVA may contaminate the ferroelectric layer 106. In addition, the over-etching may result in a high resistance from the upper electrode 110 to the TEVA due to a small contact area, for example. If the sum is too thick (e.g., greater than about 400 angstroms or another suitable value), the height of the memory cell 102 may be too large. As above, this may result in issues with processing during the formation of the memory cell 102 and / or integrating the memory cell 102 into embedded memory processing process flows.In some embodiments where the lower interface layer 104 bis or comprises a dielectric or metal oxide, regardless of whether amorphous or crystalline, the lower interface layer 104 bhas a high energy band gap. Similarly, in some embodiments where the upper interfacial layer 104 tis or comprises a dielectric or metal oxide, regardless of whether amorphous or crystalline, the upper interfacial layer 104 thas a high energy band gap. A large energy band gap may be, for example, a band gap larger than that of the ferroelectric layer 106. The large energy band gap at the lower interface layer 104 band / or the large energy band gap at the upper interface layer 104 tmay reduce leakage currents.Referring now to FIGS. 4A-4D, cross-sectional views 400A-400D of some embodiments of the memory cell 102 of FIG. 3 are shown, wherein the lower and upper interfacial layers 104 b, 104 tare varied between Group 1 materials and Group 2 materials. A Group 1 material is a dielectric or metal oxide that is amorphous or crystalline as described with reference to FIG. 1, while a Group 2 material is conductive and is a metal that is amorphous or crystalline as described with reference to FIG. 1.In FIG. 4A, the lower and upper interfacial layers 104 b, 104 fare Group 1 materials and are therefore both Group 1 interfacial layers 104 g1 In FIG. 4B, the lower and upper interfacial layers 104 b, 104 fare Group 1 material and Group 2 material, respectively, and are Group 1 interfacial layer 104 g1 and Group 2 interfacial layer 104 g2 respectively. In FIG. 4C, the lower and upper interfacial layers 104 bare 104 b, 104 tare respectively a group 2 material and a group 1 material, and are therefore respectively an interfacial layer 104 g2 of the group 2 and an interfacial layer 104 g1 of the group 1. in FIG. 4D, the lower and upper interfacial layers 104 b, 104 fare respectively materials of the group 2 and are therefore both interfacial layers 104 g2 of the group 2.Referring now to FIG. 5, a cross-sectional view 500 of some alternative embodiments of the memory cell 102 of FIG. 1 is shown, in which the memory cell 102 includes a plurality of interfacial layers 104 and a plurality of ferroelectric layers 106. The interface layers 104 are alternately stacked with the ferroelectric layers 106 from the lower electrode 108 to the upper electrode 110. Furthermore, the interface layers 104 are paired with the ferroelectric layers 106 to form multiple interface ferroelectric pairs 502. The interface layer 104 of each interface-ferroelectric pair 502 is underlying the ferroelectric layer 106 of the interface-ferroelectric pair 502 to improve the uniformity of the ferroelectric layer 106, as described with reference to FIG. 1. In alternative embodiments, the memory cell 102 includes more or fewer interface ferroelectric pairs 502.Generally, the greater a remanent polarization of a ferroelectric layer, the better. The remanent polarization can be increased with increasing thickness of the ferroelectric layer. However, the orthorhombic phase is responsible for the remanent polarization. Furthermore, above a certain thickness, a ratio of the orthorhombic phase to other phases decreases. Therefore, the ability to increase the remanent polarization by thickness is limited. By alternately stacking the plurality of interfacial layers 104 with the plurality of ferroelectric layers 106, this thickness constraint can be overcome and an increased remanent polarization can be achieved.Referring now to FIG. 6, a cross-sectional view 600 of some alternative embodiments of the memory cell 102 of FIG. 5 is shown, wherein an additional interfacial layer 104 is located on an uppermost ferroelectric layer of the ferroelectric layers 106. The additional interface layer 104 is adjacent to the upper electrode 110 and may therefore be referred to as an upper interface layer 104 t. Similarly, an interface layer adjacent to the lower electrode 108 may be referred to as a lower interface layer 104 b.Although FIGS. 5 and 6 do not illustrate the interfacial layers 104 as Group 1 and / or 2 materials, it should be understood that the interfacial layers 104 may also be Group 1 and / or 2 materials. In some embodiments, the interfacial layers 104 of FIG. 5 are a Group 1 or 2 material. In some embodiments, the upper interfacial layer 104 tof FIG. 6 is a Group 1 material, while the remaining interfacial layers 104 of FIG. 6 are a Group 1 or 2 material. In alternative embodiments, the upper interfacial layer 104 tof FIG. 6 is a Group 2 material while the remaining interfacial layers 104 of FIG. 6 are a Group 1 or 2 material. In alternative embodiments, the interfacial layers 104 of FIG. 5 or 6 periodically alternate between a Group 1 material and a Group 2 material, or vice versa, from the bottom electrode 108 to the top electrode 110.Referring now to FIG. 7A, a cross-sectional view 700A of some embodiments of the memory cell 102 of FIG. 1 is shown, where the memory cell 102 is integrated into an interconnect structure 702 of an IC chip.An upper electrode wire 704 t overlies the memory cell 102, and a top electrode via (TEVA) 706 textends downwardly from the upper electrode wire 704 ttoward the upper electrode 110. A bottom electrode wire 704 bis below the memory cell 102, and a bottom electrode via (BEVA) 706 bextends upward from the bottom electrode wire 704 bto the bottom electrode 108. The BEVA 706b includes a BEVA barrier 708 and a BEVA body 710. The BEVA barrier 708 cup-covers a bottom surface of the BEVA body 710 to separate the BEVA body 710 from the bottom electrode wire 704b. In alternative embodiments, the BEVA barrier 708 is omitted so that the BEVA body 710 directly contacts the bottom electrode wire 704 b. For example, the BEVA barrier 708 may be configured to block or at least substantially reduce diffusion of material from the bottom electrode wire 704 bto the bottom electrode 108.In some embodiments, the upper electrode wire 704 t, the TEVA 706 t, and the lower electrode wire 704 bare copper, aluminum, tungsten, one or more other suitable metals, or any combination of the foregoing. In some embodiments, the BEVA body 710 is - or comprises - (1) a same material as the top electrode wire 704 t, the TEVA 706 t, the bottom electrode wire 704 b, or any combination of the foregoing; (2) a same material as the BEVA barrier 708; (3) a same material as the bottom electrode 108; (4) one or more other suitable materials; or (5) any combination of the foregoing. In some embodiments, the BEVA barrier 708 is or comprises titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, one or more other suitable materials, or any combination of the foregoing. In some embodiments, a thickness of the BEVA barrier 708 is about 50-200 angstroms or another suitable value.A hard mask 712 overlies the top electrode 110, and the TEVA 706t extends from the top electrode wire 704t through the hard mask 712 to the top electrode 110. In alternative embodiments, the hard mask 712 is omitted. The hard mask 712 may be or include, for example, titanium nitride, silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, metal oxide, one or more other suitable materials, or any combination of the foregoing. The metal oxide may be or comprise, for example, titanium oxide, aluminum oxide, one or more other suitable metal oxides, or any combination of the above. In some embodiments, a thickness of the hard mask 712 is about 50-400 angstroms or another suitable value.As described with reference to FIG. 1, the interfacial layer 104 is configured to improve the properties of the ferroelectric layer 106 and / or to increase the uniformity of the properties of the ferroelectric layer 106. For example, the interfacial layer 104 may improve (e.g., increase) the remanent polarization of the ferroelectric layer 106 and increase the uniformity of the remanent polarization. In some embodiments, the interfacial layer 104 is a group 1 material as described with reference to FIG. 2A. In other embodiments, the interfacial layer 104 is a group 2 material as described with reference to FIG. 2B.The bottom electrode 108, the interface layer 104, and the ferroelectric layer 106 have a first common width and each form a pair of first common sidewalls 714 on opposite sides of the memory cell 102. Furthermore, the top electrode 110 and the hard mask 712 have a second common width and each form a pair of second common sidewalls 716 on the opposing sides of the memory cell 102. The second common width is less than the first common width, and the second common sidewalls 716 are laterally between the first common sidewalls 714. The first and second common sidewalls 714, 716 have planar profiles, but may alternatively have curved profiles or other suitable profiles.A sidewall spacer structure 718 overlies the ferroelectric layer 106 and is located on the second common sidewalls 716. The sidewall spacer structure 718 may be or include, for example, titanium nitride, silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, metal oxide, one or more other suitable materials, or any combination of the foregoing. The metal oxide may be or comprise, for example, titanium oxide, aluminum oxide, one or more other suitable metal oxides, or any combination of the above. In some embodiments, sidewall spacer structure 718 is a same material as hard mask 712.A plurality of intermetal dielectric (IMD) layers 720 surround the lower electrode wire 704 band the upper electrode wire 704 t, respectively. Further, a first etch stop layer 722, a second etch stop layer 724, and a buffer layer 726 separate the IMD layers 720. The first etch stop layer 722 vertically surrounds the BEVA 706b between the bottom electrode wire 704b and the memory cell 102. The second etch stop layer 724 and the buffer layer 726 conformally cover the first etch stop layer 722 and the memory cell 102. Furthermore, the second etch stop layer 724 is located between the buffer layer 726 and the memory cell 102.The IMD layers 720 may be or include, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, one or more other suitable dielectrics, or any combination of the above. The first etch stop layer 722 and / or the second etch stop layer 724 may be or comprise, for example, metal nitride, metal oxide, metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, one or more other suitable dielectrics, or any combination of the above. In some embodiments 724, the first etch stop layer 722 and the second etch stop layer are a same material. In some embodiments, a thickness of the first etch stop layer 722 is about 150-350 angstroms or another suitable value. In some embodiments, a thickness of the second etch stop layer 724 is about 50-300 angstroms or another suitable value. The buffer layer 726 may be or comprise, for example, tetraethyl orthosilicate (TEOS) oxide and / or another suitable dielectric. In some embodiments, a thickness of the buffer layer 726 is about 50-300 angstroms or another suitable value.FIG. 7B illustrates a top view 700B of some embodiments of the memory cell 102 of FIG. 7A. The cross-sectional view 700A of FIG. 7A may be along line A, for example. The memory cell 102 has a square or rectangular top layout, and the second common sidewalls 716 are laterally offset from and between the first common sidewalls 714. In alternative embodiments, memory cell 102 may have a circular top layout or other suitable top layout. Furthermore, the upper layouts of the BEVA 706 band the TEVA 706 tare shown in dashed lines and laid over the memory cell 102. The BEVA 706 band the TEVA 706 thave a square or rectangular top layout, but may also have a circular top layout or other suitable top layout.Referring now to FIGS. 8A-8C, cross-sectional views 800A-800C of some alternative embodiments of the memory cell 102 of FIG. 7A are shown in which a layout of the memory cell 102 is varied.In FIG. 8A, the BEVA barrier 708 and the BEVA body 710 are omitted, and a lower electrode barrier 802 and the lower electrode 108 form the BEVA 706b. The bottom electrode barrier 802 is located between the bottom electrode 108 and the bottom electrode wire 704 band may be, for example, as described with respect to the BEVA barrier 708 in FIG. 7A. The bottom electrode barrier 802, the bottom electrode 108, the interfacial layer 104, the ferroelectric layer 106, the top electrode 110, and the hard mask 712 are recessed at the BEVA 706 b, and the TEVA 706 tis laterally offset from a center of the memory cell 102.In FIG. 8B, the BEVA 706 b, the BEVA barrier 708, the BEVA body 710, the sidewall spacer structure 718, the second etch stop layer 724, and the hard mask 712 are omitted. Furthermore, a lower electrode barrier 802, the lower electrode 108, the interface layer 104, the ferroelectric layer 106, and the upper electrode 110 form a bottom side of an upper electrode barrier 804. The lower electrode barrier 802 is located between the lower electrode 108 and the lower electrode wire 704b, while the upper electrode barrier 804 is located between the upper electrode 110 and the TEVA 706t. For example, the lower electrode barrier 802 and / or the upper electrode barrier 804 may be as described as the BEVA barrier 708 in FIG. 7A.In FIG. 8C, the bottom electrode 108, the interfacial layer 104, the ferroelectric layer 106, the top electrode 110, and the hard mask 712 have a common width and each form a pair of common sidewalls on opposite sides of the memory cell 102. Further, the sidewall spacer structure 718 lines the common sidewalls. The common side walls have planar profiles, but may also have curved profiles or other suitable profiles.In FIG. 9, a cross-sectional view 900 of some alternative embodiments of the memory cell 102 of FIG. 7A is shown, wherein the memory cell 102 further comprises an additional interfacial layer 104 as in FIG. 3. For example, the additional interface layer 104 may be referred to as an upper interface layer 104 t, while the interface layer 104 of FIG. 7A may be referred to as a lower interface layer 104 b, for example.The bottom electrode 108, the bottom interface layer 104 b, the ferroelectric layer 106, and the top interface layer 104 thave a first common width and form a pair of first common sidewalls on opposite sides of the memory cell 102. Furthermore, the top electrode 110 and the hard mask 712 have a second common width and each form a pair of second common sidewalls on the opposing sides of the memory cell 102. The second common width is less than the first common width, and the second common sidewalls are laterally between the first common sidewalls. Further, the sidewall spacer structure 718 overlies the upper interfacial layer 104 tand is on the second common sidewalls.In some embodiments, the lower interface layer 104 bis a Group 2 material as described with reference to FIG. 2B, while the upper interface layer 104 tis a Group 1 material as described with reference to FIG. 2A. In alternative embodiments, the lower interface layer 104 band / or the upper interface layer 104 tare one or more other suitable materials.Referring now to FIGS. 10A-10E, there are shown cross-sectional views 1000A-1000E of some alternative embodiments of the memory cell 102 of FIG. 9, wherein a layout of the memory cell 102 is varied.In FIG. 10A, the upper interface layer 104 t, the upper electrode 110, and the hard mask 712 have a common width less than that of the ferroelectric layer 106. Furthermore, the sidewall spacer structure 718 overlies the ferroelectric layer 106 at a sidewall of the upper interfacial layer 104t. In some embodiments, the lower interface layer 104 bis a Group 1 material as described with reference to FIG. 2A, while the upper interface layer 104 tis a Group 2 material as described with reference to FIG. 2B. In alternative embodiments, the lower interface layer 104 band / or the upper interface layer 104 tare one or more other suitable materials.In FIG. 10B, the memory cell 102 is as in FIG. 8A, except that the memory cell 102 further includes the upper interfacial layer 104 tof FIG. 9. In some embodiments, the lower interface layer 104 bis a Group 2 material as described with reference to FIG. 2B, while the upper interface layer 104 tis a Group 1 material as described with reference to FIG. 2A. In alternative embodiments, the lower and upper interfacial layers 104 b, 104 fare Group 1 materials as described with reference to FIG. 2A. In alternative embodiments, the lower interface layer 104 band / or the upper interface layer 104 tare one or more other suitable materials.In FIG. 10C, memory cell 102 is as in FIG. 10B, except that upper interfacial layer 104 t, upper electrode 110, and hard mask 712 have a common width that is less than that of ferroelectric layer 106. Furthermore, the sidewall spacer structure 718 overlies the ferroelectric layer 106 at a sidewall of the upper interfacial layer 104t. In some embodiments, the lower and upper interfacial layers 104 b, 104 fare Group 2 materials as described with reference to FIG. 2B. In alternative embodiments, the lower interface layer 104 bis a Group 1 material as described with reference to FIG. 2A, while the upper interface layer 104 tis a Group 2 material as described with reference to FIG. 2B. In alternative embodiments, the lower interface layer 104 band / or the upper interface layer 104 tare one or more other suitable materials.In FIG. 10D, the memory cell 102 is as in FIG. 8B, except that the memory cell 102 further includes the upper interfacial layer 104 tof FIG. 9. In some embodiments, the lower and upper interfacial layers 104 b, 104 fare Group 1 materials as described with reference to FIG. 2A. In alternative embodiments, the lower interface layer 104 bis a Group 1 material as described with reference to FIG. 2A, while the upper interface layer 104 tis a Group 2 material as described with reference to FIG. 2B. In alternative embodiments, the lower interface layer 104 bis a Group 2 material as described with reference to FIG. 2B, while the upper interface layer 104 tis a Group 1 material as described with reference to FIG. 2A. In alternative embodiments, the lower and upper interfacial layers 104 b, 104 fare Group 2 materials as described with reference to FIG. 2B. In alternative embodiments, the lower interface layer 104 band / or the upper interface layer 104 tare one or more other suitable materials.In FIG. 10E, the memory cell 102 is as in FIG. 8C, except that the memory cell 102 further includes the upper interfacial layer 104 tof FIG. 9. In some embodiments, the lower and upper interfacial layers 104 b, 104 fare Group 1 materials as described with reference to FIG. 2A. In alternative embodiments, the lower interface layer 104 bis a Group 1 material as described with reference to FIG. 2A, while the upper interface layer 104 tis a Group 2 material as described with reference to FIG. 2B. In alternative embodiments, the lower interface layer 104 bis a Group 2 material as described with reference to FIG. 2B, while the upper interface layer 104 tis a Group 1 material as described with reference to FIG. 2A. In alternative embodiments, the lower and upper interfacial layers 104 b, 104 fare Group 2 materials as described with reference to FIG. 2B. In alternative embodiments, the lower interface layer 104 band / or the upper interface layer 104 tare one or more other suitable materials.Although FIGS. 7A and 8A-8C illustrate the memory cells 102 having a single interfacial layer 104 and a single ferroelectric layer 106 stacked from the lower electrode 108 to the upper electrode 110, alternatively, the memory cells 102 may also have a plurality of interfacial layers 104 and a plurality of ferroelectric layers 106 stacked from the lower electrode 108 to the upper electrode 110, as in FIG. 5. although FIGS. 9 and 10A-10E illustrate the memory cells 102 having a single ferroelectric layer stacked between two interfacial layers 104 from the lower electrode 108 to the upper electrode 110, alternatively, the memory cells 102 may also have a plurality of ferroelectric layers 106 stacked alternately with a plurality of interfacial layers 104 from the lower electrode 108 to the upper electrode 110, as in FIG. 6.In FIG. 11A, a cross-sectional view 1100A of some embodiments of an IC chip including memory cells 102 is shown, wherein the memory cells 102 are integrated into individual single transistor single capacitor (1T1C) cells 1102. The memory cells 102 are each as their counterpart is described with reference to FIG. 7A.The 1T1R cells 1102 include individual drain regions 1104 and individual drain-side conductive paths 1106. The drain regions 1104 are doped regions of a substrate 1108 and each have a doping type opposite an adjacent region of the substrate 1108. Furthermore, the drain regions 1104 are electrically separated by a trench isolation structure 1110 and partially surround or define access transistors 1112 (partially shown) used to individually select the memory cells 102. The trench isolation structure 1110 extends into a top surface of the substrate 1108 and includes silicon oxide and / or one or more other suitable dielectric materials. The substrate 1108 may be, for example, a bulk silicon substrate or other suitable semiconductor substrate.The drain-side conductive paths 1106 electrically couple the drain regions 1104 to the memory cells 102. Furthermore, the drain-side conductive paths 1106 are formed by an interconnect structure 702 within which the memory cells 102 are arranged. The interconnect structure 702 includes a plurality of wires 704 and a plurality of vias 706. The plurality of wires 704 includes upper electrode wires 704 tand lower electrode wires 704 b. In some embodiments, the upper electrode wires 704 tcorresponds to bit lines BL. The plurality of vias 706 include TEVAs 706 t. One level of vias 706 closest to substrate 1108 is in interlayer dielectric (ILD) layer 1114, while the remaining levels of vias 706 and wires 704 are in IMD layers 720. The wires 704 and the vias 706 may be or include, for example, copper, aluminum, one or more other suitable metals, or a combination of the foregoing.An edge region 1116 on one side of the 1T1R cells 1102 receives peripheral devices 1118 (only one of which is shown). The peripheral devices 1118 may be, for example, metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (finFETs), gate all around field effect transistors (GAA-FETs), or another suitable type of semiconductor device. Each of the peripheral devices 1118 includes a pair of source / drain regions 1120 in the substrate 1108, as well as a gate electrode 1122 and a gate dielectric layer 1124 disposed between the source / drain regions 1120.In FIG. 11B, a cross-sectional view 1100B of some embodiments of the IC chip of FIG. 11A is shown along an axis orthogonal to the axis along which the cross-sectional view 1100A of FIG. 11A extends. The 1T1R cells 1102 include individual memory cells 102, individual drain-side conductive paths 1106, individual access transistors 1112, and individual source-side conductive paths 1126. The memory cells 102 are each as their counterpart is described with reference to FIG. 7A.The access transistors 1112 are located on the substrate 1108 between the substrate 1108 and the interconnect structure 702 and are electrically separated by the trench isolation structure 1110. The access transistors 1112 include individual drain regions 1104, individual source regions 1128, individual gate dielectric layers 1130, and individual gate electrodes 1132. The gate electrodes 1132 are overlying the gate dielectric layers 1130, respectively, and form word lines in some embodiments. The drain and source regions 1104, 1128 are doped regions of the substrate 1108 and each have a doping type opposite an adjacent region of the substrate 1108. Furthermore, the drain and source regions 1104, 1128 are respectively adjacent to the gate electrodes 1132. The access transistors 1112 may be, for example, MOSFETs, finFETs, GAA-FETs, or any other suitable type of semiconductor device.The drain-side conductive paths 1106 electrically couple the drain regions 1104 to the memory cells 102, and the source-side conductive paths 1126 electrically couple the source regions 1128 to the source lines SL. The drain-side and source-side conductive paths 1106, 1126 are formed by the plurality of wires 704 and the plurality of vias.Although FIGS. 11A and 11B are illustrated using memory cell embodiments as in FIG. 7A, memory cell embodiments as in any of FIGS. 1, 2A, 2B, 3, 4A-4D, 5, 6, 8A-8C, 9, and 10A-10E are also conceivable in alternative embodiments. For example, the memory cells 102 of FIGS. 11A and 11B may include additional interfacial layers 104 on top surfaces of the ferroelectric layers 106, as in FIG. 9.In FIG. 12, a top view 1200 of some embodiments of the IC chip of FIGS. 11A and 11B is shown. Cross-sectional views 1100A, 1100B of FIGS. 11A and 11B may be taken along lines B and C, respectively, for example. The IC chip includes a plurality of 1T1C cells 1102 in a plurality of rows and a plurality of columns, thereby forming a memory array 1202. The peripheral devices 1118 surround the memory array 1202 at an edge region 1116 of the IC chip. The peripheral devices 1118 may implement, for example, read / write circuitry and / or other suitable circuitry for operating the 1T1R cells 1102.FIG. 13 shows a cross-sectional view 1300 of some embodiments of an IC chip comprising a ferroelectric field effect transistor (FeFET) 1302, wherein an interfacial layer 104 with high texture uniformity is located at a bottom of a ferroelectric layer 106. A pair of source / drain regions 1304 are located in a substrate 1108, and a channel region 1306 of the substrate 1108 separates the source / drain regions 1304. The source / drain regions 1304 may be, for example, doped regions of the substrate 1108, or another suitable semiconductor region.A gate dielectric layer 1308, a floating gate electrode 1310, the interfacial layer 104, the ferroelectric layer 106, a top gate electrode 1312, and a hard mask 1314 form a gate stack overlying the channel region 1306 and have a common width. In alternative embodiments, the floating gate electrode 1310 and / or the gate dielectric layer 1308 are omitted. The interface layer 104 and the ferroelectric layer 106 are as described with reference to any of FIGS. 1, 2A, and 2B, and the interface layer 104 has high texture uniformity to improve the properties of the ferroelectric layer 106 and / or to increase the uniformity of the properties of the ferroelectric layer 106. Such characteristics may include, for example, remanent polarization and other suitable characteristics. In some embodiments, floating gate electrode 1310 and top gate electrode 1312 are as bottom electrode 108 and top electrode 110, respectively, are described with reference to any of FIGS. 1, 2A, and 2B.A sidewall spacer structure 1316 is on opposite sidewalls of the gate stack, and an interconnect structure 702 overlies and is electrically coupled to the FeFET 1302. The interconnect structure 702 includes a plurality of wires 704 and a plurality of vias 706 stacked to define conductive paths extending from the FeFET 1302. While only a single level of vias 706 and a single level of wires 704 are shown, other levels are also conceivable. An etch stop layer 1318 covers and lines the FeFET 1302, and an ILD layer 1114 and an IMD layer 720 are stacked over the etch stop layer 1318. The contact etch stop layer 1318 and the ILD layer 1114 surround the vias 706, and the IMD layer 720 surrounds the wires 704.In some embodiments, the hard mask 1314 is or comprises titanium nitride, silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, metal oxide, one or more other suitable materials, or any combination of the foregoing. In some embodiments, the sidewall spacer structure 718 is or comprises titanium nitride, silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, metal oxide, one or more other suitable materials, or any combination of the foregoing. In some embodiments, the contact etch stop layer 1318 is or comprises metal nitride, metal oxide, metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, one or more other suitable dielectrics, or any combination of the foregoing.During operation of the FeFET 1302, the remanent polarization of the ferroelectric layer 106 is used to represent a bit of data. For example, a positive polarity of the remanent polarization may represent a binary "0", while a negative polarity of the remanent polarization may represent a binary "1", or vice versa.To set the remanent polarization to the positive polarity, a first write voltage is applied to the ferroelectric layer 106 from the top gate 1312 to the channel region 1306 (e.g., via the source / drain regions 1304). To set the remanent polarization to the negative polarity, a second write voltage is applied to the ferroelectric layer 106 from the top gate 1312 to the channel region 1306. The first and second write voltages have opposite polarities and have orders of magnitude greater than the coercive voltage.The polarity of the remanent polarization shifts a threshold voltage of the FeFET 1302. Depending on whether the remanent polarization is of the positive polarity or the negative polarity, the threshold voltage is at a first threshold or a second threshold. To read the polarity of the remanent polarization, a read voltage that is less than the coercive voltage and is between the first and second threshold voltages is applied from the upper gate 1312 to a source of one of the source / drain regions 1304. Depending on whether the channel region 1306 is conductive, the remanent polarity has the positive polarity or the negative polarity.Although FIG. 13 illustrates the FeFET 1302 with a single interface layer 104 on the ferroelectric layer 106, the FeFET 1302 may alternatively include a pair of interface layers 104 on the ferroelectric layer 106, as in FIG. 3. although FIG. 13 illustrates the FeFET 1302 with a single interface layer 104 and a single ferroelectric layer 106 stacked from the floating gate electrode 1310 to the top gate electrode 1312, the FeFET 1302 may alternatively include a plurality of interface layers 104 and a plurality of ferroelectric layers 106 stacked from the floating gate electrode 1310 to the top gate electrode 1312, as in FIG. 5 or 6.Referring now to FIGS. 14-26, a series of cross-sectional views 1400-2600 of some embodiments of a method of forming an IC chip including memory cells are shown, wherein the memory cells are integrated into individual 1T1C cells and include individual interface layers having high texture uniformity at bottom surfaces of individual ferroelectric layers. Cross-sectional views 1400-2600 may correspond to alternative embodiments of the IC chip of FIG. 11A, for example, wherein the memory cells are as in FIG. 9. Further, cross-sectional views 1400- 2600 may be taken along line B in FIG. 12, for example.As illustrated by cross-sectional view 1400 of FIG. 14, an interconnect structure 702 is partially formed over and electrically coupled to a plurality of access transistors 1112 (only partially shown) and a peripheral device 1118. The access transistors 1112 are individual to a plurality of 1T1C cells 1102 to be formed and are respectively located on a plurality of 1T1C cells 1102 to be formed, and the peripheral device 1118 is located on an edge region 1116 of the IC chip to be formed. Access transistors 1112 and peripheral device 1118 are located on and partially formed by a substrate 1108 and are separated by a trench isolation structure 1110 in substrate 1108. The access transistors 1112 and the peripheral device 1118 may be, for example, as described with reference to FIGS. 11A and 11B.The interconnect structure 702 includes a plurality of wires 704 and a plurality of vias 706 stacked in a dielectric structure. The dielectric structure includes an ILD layer 1114 and a first IMD layer 720 aover the ILD layer 1114. The plurality of wires 704 includes a plurality of bottom electrode wires 704 balong a top surface of the interconnect structure 702. The lower electrode wires 704b are individual to and are respectively located on the 1T1C cells 1102 to be formed. Further, the bottom electrode wires 704 bare electrically coupled to the drain regions 1104 of the access transistors 1112, respectively. The first IMD layer 720 amay be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), one or more other suitable deposition processes, or a combination of the foregoing, and / or using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), one or more other suitable deposition processes, or a combination of the foregoing, for example. The wires 704 and the vias 706 may be formed by, for example, CVD, PVD, ALD, electroless plating, electroplating, one or more other suitable deposition processes, or any combination of the foregoing, and / or using CVD, PVD, ALD, electroless plating, electroplating, one or more other suitable deposition processes, or any combination of the foregoing.As illustrated by cross-sectional view 1500 of FIG. 15, a first etch stop layer 722 is deposited or otherwise formed on the interconnect structure 702. It should be noted that for clarity, a lower portion of the interconnect structure 702 has been omitted from the drawings here and in the subsequent figures. The first etch stop layer 722 is a dielectric and may be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing.As also illustrated by cross-sectional view 1500 of FIG. 15, BEVAs 706 bare formed that each extend through the first etch stop layer 722 to the bottom electrode wires 704 b. The BEVAs 706b include individual BEVA bodies 710 and individual BEVA barriers 708 that respectively cover undersides of the BEVA bodies 710 in a cup shape. The BEVA bodies 710 and / or the BEVA barriers 708 may be formed by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the above, and / or using CVD, PVD, ALD, one or more other suitable deposition processes, or a combination of the above.As illustrated by cross-sectional view 1600 of FIG. 16, a bottom electrode layer 1081 is deposited over the BEVAs 706 band the first etch stop layer 722. The bottom electrode layer 108 lis conductive and may be or comprise, for example, titanium nitride, tantalum nitride, ruthenium, platinum, iridium, molybdenum, tungsten, doped polysilicon, one or more other suitable conductive materials, or any combination of the foregoing. The bottom electrode layer 108L may be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing.As illustrated by cross-sectional view 1700 of FIG. 17, a lower interfacial layer 104 bis deposited over the lower electrode layer 108 l. The lower interface layer 104 bmay be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the above.The bottom electrode layer 108land the bottom interface layer 104 bhave individual tops 112 and 114, respectively, and with relatively low texture uniformity and high texture uniformity. In other words, compared to the top surface 112 of the lower electrode layer 108 l, a top surface 114 of the lower interfacial layer 104 bhas a higher texture uniformity. The texture may correspond to, for example, the deviation of a surface from a perfectly flat plane with respect to location, roughness, waviness, one or more other suitable parameters, or any combination of the above. The "ply" may refer to the direction of the predominant surface structure, for example. The roughness may refer to a measure of spaced-apart surface irregularities, for example. Curl parameters may relate, for example, to a measure of spaced surface irregularities overlaid by the roughness. As compared with the irregularities of roughness, the irregularities of the corrugation are larger and have a larger pitch.In some embodiments, the texture on the tops 112, 114 of the bottom electrode layer 108 land the bottom interfacial layer 104 b, respectively, is measured by interferometry, AFP, other suitable methodology, or any combination of the foregoing, and / or is measured using a profiler or other suitable instrument.In some embodiments, the texture on the tops 112, 114 of the bottom electrode layer 108 land the bottom interfacial layer 104 b, respectively, is quantified from the average roughness. For example, a first set of average roughness measurements may be measured at multiple locations uniformly distributed across the top surface 112 of the lower electrode layer 108 l, and a second set of average roughness measurements may be measured at multiple locations uniformly distributed across the top surface 114 of the lower interfacial layer 104 b. In some embodiments, the average of the second set of measurements may be less than the average of the first set of measurements due to the higher texture uniformity on the top surface 112 of the lower interfacial layer 104 b. Furthermore, the variation of the second set of measurements may be less than that of the first set of measurements. The variation for a set of measurements (e.g., the first or second set of measurements) may be determined as, for example, (MAX-MIN) / (2xAVG), where MAX corresponds to the maximum measurement, MIN corresponds to the minimum measurement, and AVG corresponds to the average of the measurements.In some embodiments, the lower interfacial layer 104 bis or comprises: (1) an amorphous dielectric; (2) an amorphous metal oxide; (3) an amorphous metal; (4) one or more other suitable materials; or (5) or any combination of the foregoing. The amorphous metal may be limited to, for example, one or more metal elements or consist essentially of one or more metal elements. The amorphous dielectric may optionally be or comprise a metal oxide and may optionally comprise an oxide. It has been found that the amorphousness of the lower interface layer 104 bmay result in high texture uniformity on the top surface 112 of the lower interface layer 104 b.In other embodiments, the lower interfacial layer 104 bis or comprises: (1) a crystalline dielectric; (2) a crystalline metal oxide; (3) a crystalline metal; (4) one or more other suitable materials; or (5) or any combination of the foregoing. The crystalline metal may be, for example, limited to one or more metal elements or consist essentially of one or more metal elements. The crystalline dielectric may optionally be or comprise a metal oxide and may optionally comprise an oxide.In some embodiments where the lower interfacial layer 104 bis a crystalline dielectric, metal oxide, or metal, the interfacial layer is: (1) single crystalline; (2) a small grain size variation; (3) a high percentage of grains with a common orientation; (4) a high percentage of grains with a small grain size; 5) any combination of the above. It has been found that such crystalline properties may result in high texture uniformity on the top surface 114 of the lower interfacial layer 104 b. In at least some embodiments, properties (1) through (4) are ordered from "most effective" through "least effective" as texture uniformity increases.The grain size variation may be determined as, for example, (MAX-MIN) / (2xAVG)*100, where MAX corresponds to the maximum grain size, MIN corresponds to the minimum grain size, and AVG corresponds to the average grain size. The small grain size variation at (2) may be, for example, a grain size variation of less than about 10%, about 5%, or another suitable value. The high percentage at (3) and / or (4) may be, for example, a percentage greater than about 90%, about 95%, or another suitable value. The grain orientation at (3) may be represented, for example, by the Miller index or other suitable designation system and / or may be measured, for example, by XRD or by other suitable methodology. In some embodiments where the lower interfacial layer 104 bis crystalline titanium nitride, more than 90% of the grains may have a common orientation of (111). The small grain size at (4) may correspond to, for example, the average grain size, the maximum grain size, the average grain size, or the like, which is no greater than about 1 nanometer, 0.5 nanometer, or another suitable value.In some embodiments where the lower interfacial layer 104 bis or comprises a crystalline dielectric or metal oxide, the crystalline dielectric or metal oxide has a crystallization temperature above about 400 degrees Celsius, about 700 degrees Celsius, about 1000 degrees Celsius, or another suitable value. For example, the crystalline dielectric or metal oxide may be or comprise alumina (e.g., Al 2 O 3), silicon oxide (e.g., SiO 2), ruthenium oxide (e.g., RuO), another suitable material, or any combination of the above.In some embodiments where the lower interface layer 104 bis or comprises a dielectric or metal oxide, regardless of whether amorphous or crystalline, the lower interface layer 104 bhas a high energy band gap. Such a large energy band gap may be, for example, a band gap larger than that of the ferroelectric layer subsequently formed on the lower interface layer 104 b. The large energy band gap can reduce the leakage current.In some embodiments, a thickness T bi of the lower interfacial layer 104 bis greater than 0 and is about 5-100 angstroms, about 5-50 angstroms, about 50-100 angstroms, or another suitable value. If the thickness T bi is less than about 50 angstroms and the lower interfacial layer 104 bis crystalline, an average grain size of the lower interfacial layer 104 bis generally less than about 5 angstroms or another suitable value.As illustrated by cross-sectional view 1800 of FIG. 18, a ferroelectric layer 106 is deposited directly on the lower interface layer 104 b. In at least some embodiments, the lower interfacial layer 104 bfunctions as a crystalline seed for the ferroelectric layer 106. The deposition may be performed, for example, by CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the above.As mentioned above, a top surface 112 of the lower interfacial layer 104 bhas higher texture uniformity than a top surface 114 of the lower electrode layer 108 l. Forming the ferroelectric layer 106 on a surface having high texture uniformity rather than low texture uniformity has been found to improve the properties of the ferroelectric layer 106 and / or increase the uniformity of the properties of the ferroelectric layer 106. Non-limiting examples of such properties include remanent polarization, surface roughness, texture uniformity, other suitable properties, or any combination of the foregoing. Therefore, because the ferroelectric layer 106 is formed on the top surface 112 of the lower interface layer 104 band not on the top surface 114 of the lower electrode layer 108 l, the characteristics of the ferroelectric layer 106 may be improved and / or may have high uniformity. For example, the remanent polarization may have high uniformity, which may result in a low production yield in mass production. As another example, the remanent polarization may be improved, thereby causing read operations to be less prone to errors. Because the properties of the ferroelectric layer 106 may be improved and / or have a high uniformity, the memory cells to be formed may be reduced to a greater extent than would otherwise be possible.As also illustrated by cross-sectional view 1800 of FIG. 18, an upper interfacial layer 104 tis deposited over the ferroelectric layer 106. In alternative embodiments, the upper interfacial layer 104 tis omitted to form memory cells according to embodiments as in FIG. 7A. The upper interface layer 104 tmay be, for example, as described with reference to FIG. 17, and / or may be deposited, for example, by CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the above. If the upper interface layer 104 thas an energy band gap that is larger than that of the ferroelectric layer 106, the upper interface layer 104 tmay reduce the leakage current in the formed memory cells.As illustrated by cross-sectional view 1900 of FIG. 19, an upper electrode layer 110 lis deposited over the upper interface layer 104 t, and a hard mask layer 712 lis deposited over the upper electrode layer 110 l. The upper electrode layer 110 land / or the hard mask layer 712 lmay be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing.As illustrated by cross-sectional view 2000 of FIG. 20, hard mask layer 712 lis patterned to segment hard mask layer 712 linto hard masks 712 that are individual to 1T 1C cells 1102 to be formed. As will be seen below, the hard masks 712 have structures for memory cells to be formed. The patterning may be performed, for example, by a photolithography / etching process or other suitable patterning process.As also illustrated by cross-sectional view 2000 of FIG. 20, a first etch is performed into the top electrode while hard mask 712 is in place. In some embodiments in which the hard mask layer 712 lis patterned by a photolithography / etching process, an etching of the photolithography / etching process is the same as the first etching. The first etching stops at the upper interface layer 104 t, and transfers patterns of the hard masks 712 to the upper electrode layer 110 l, thereby segmenting the upper electrode layer 110 l. The segments are individual to and are located on the 1T1C cells 1102 to be formed, respectively, and are referred to as top electrodes 110 below. In some embodiments, the upper interface layer 104 tis a Group 1 material while the lower interface layer 104 bis a Group 2 material. A group 1 material is a dielectric or metal oxide that is amorphous or crystalline as described with reference to FIG. 17. A Group 2 material is conductive and is an amorphous or crystalline metal as described with reference to FIG. 17.As illustrated by cross-sectional view 2100 of FIG. 21, a sidewall spacer structure 718 is formed on common sidewalls formed by the hard masks 712 and the top electrodes 110. A process for forming the sidewall spacer structure 718 may include, for example: 1) depositing a sidewall spacer layer, and 2) etching back the sidewall spacer layer. However, other suitable processes are also conceivable. The sidewall spacer layer may be deposited, for example, by CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing.As illustrated by cross-sectional view 2200 of FIG. 22, a second etch is performed into the upper and lower interfacial layers 104 t, 10 b 4, the ferroelectric layer 106, and the lower electrode layer 108 lwhile the sidewall spacer structures 718 and the hard masks 712 are in place. The second etching stops at the first etch stop layer 722. Further, the second etching transfers patterns of the hard masks 712 and the sidewall spacer patterns 718 to the lower electrode layer 108 l, the upper and lower interface layers 104 t, 104 b, and the ferroelectric layer 106, thereby segmenting the aforementioned layers. The segments of the lower electrode layer 108 lare individual to, and are respectively located on, the 1T1C cells 1102 to be formed, and will be referred to as lower electrodes 108 hereinafter. The lower and upper electrodes 108 110, segments of the lower and upper interfacial layers 104 b, 104 t, and segments of the ferroelectric layer 106 form memory cells 102 on the formed 1T 1C cells 1102, respectively.As illustrated by cross-sectional views 2300- 2600 of FIGS. 23-26, interconnect structure 702 is completed over and around memory cells 102.As illustrated by cross-sectional view 2300 of FIG. 23, a second etch stop layer 724 is formed covering the memory cells 102 and laterally offset from the edge region 1116. As such, a process for forming the second etch stop layer 724 may include, for example: 1) depositing the second etch stop layer 724 covering the memory cells 102 and the edge region 1116; and 2) patterning the second etch stop layer 724 to remove it from the edge region 1116. However, other suitable processes are also conceivable. The second etch stop layer 724 may be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing. The patterning may be performed, for example, by a photolithography / etching process or other suitable process.As illustrated by cross-sectional view 2400 of FIG. 24, a buffer layer 726 and a second IMD layer 720 bare deposited covering the memory cells and the edge region 1116 over the first and second etch stop layers 722, 724. In alternative embodiments, buffer layer 726 is omitted. The buffer layer 726 and / or the second IMD layer 720 bmay be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing.As also illustrated by cross-sectional view 2400 of FIG. 24, the second IMD layer 720 b, the buffer layer 726, and the first and second etch stop layers 722, 724 are patterned to form a plurality of via openings 2402 (see FIG. 24 ). Via openings 2402 expose top electrodes 110 on memory cells 102 and a wire 704 on edge region 1116, respectively. The patterning may be performed, for example, by one or more photolithography / etching processes and / or one or more other suitable patterning processes.As illustrated by cross-sectional view 2500 of FIG. 25, the second IMD layer 720 bis further patterned to form a plurality of wire openings 2502 overlapping with the via openings 2402. The patterning may be performed, for example, by a photolithography / etching process or one or more other suitable patterning processes.As illustrated by cross-sectional view 2600 of FIG. 26, a plurality of additional wires 704 and a plurality of additional vias 706 are formed that fill via openings 4202 (see, for example, FIG. 24 ) and wire openings 5202 (see, for example, FIG. 25 ). The plurality of additional wires 704 respectively fill the wire openings 2502 and include a plurality of upper electrode wires 704 tthat are individual to and respectively overlie the memory cells 102. The plurality of additional vias 706 each fill the via openings 2402 and include a plurality of TEVAs 706 tthat are individual to and are respectively located on the top electrodes 110. Further, the TEVAs 706 textend from the upper electrode wires 704 tto the upper electrodes 110, respectively.A process for forming the additional wires 704 and the additional via openings 706 may include, for example: 1) depositing a metal layer filling the via openings 2402 and the wire openings 2502; and 2) performing planarization into the metal layer and the second IMD layer 720 buntil tops of the second IMD layer 720 band the metal layer are flush with each other. However, other suitable processes are also conceivable. The metal layer may be deposited by, for example, CVD, PVD, ALD, electroless plating, electroplating, one or more other suitable deposition processes, or any combination of the foregoing.Although FIGS. 14-26 are described with reference to a method, it should be understood that the structures shown in FIGS. 14-26 are not limited to the method, but rather may be stand alone and independent of the method. Although FIGS. 14-26 are described as a series of actions, it should be understood that the order of the actions may be changed in other embodiments. Although FIGS. 14-26 illustrate and describe a particular series of actions, some actions illustrated and / or described may be omitted in other embodiments. Moreover, actions not illustrated and / or described may be present in other embodiments.Referring now to FIG. 27, a block diagram 2700 of some embodiments of the method of FIGS. 14-26 is shown.At 2702, an interconnect structure is formed partially over a substrate, the interconnect structure comprising a bottom electrode wire at a memory region. See, for example, Fig. 14.At 7204, an etch stop layer is deposited over the interconnect structure. See, for example, Fig. 15.At 2706, a bottom electrode via is formed extending through the etch stop layer to the bottom electrode wire. See, for example, Fig. 15.At 2708, a bottom electrode layer, an interfacial layer, a ferroelectric layer, and a top electrode layer are deposited to be stacked on the bottom electrode via, wherein a top surface of the interfacial layer has high texture uniformity compared to the texture uniformity of the bottom electrode layer. See, for example, Figs. 16-19.At 2710, a hard mask is formed over the top electrode layer. See, for example, Figs. 19 and 20.At 2712, a first etch is performed into the top electrode layer with the hard mask in place to form a top electrode. See, for example, Fig. 20.At 7214, a sidewall spacer structure is formed overlying the ferroelectric layer at common sidewalls formed by the hard mask and the top electrode. See, for example, Fig. 21.At 2716, a second etch is performed into the ferroelectric layer, the interfacial layer, and the bottom electrode layer with the hard mask and sidewall spacer structure in place to form a memory cell. See, for example, Fig. 22.At 2718, the interconnect structure over the memory cell and around the memory cell is completed. See, for example, Figs. 23-26.Although the block diagram 2700 of FIG. 27 is illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of such actions or events is not to be interpreted in a limiting sense. For example, some actions may be performed in a different order than shown and / or described herein and / or concurrently with other actions or events. Moreover, not all illustrated actions need be required to implement one or more aspects or embodiments of the description herein, and one or more of the actions shown herein may also be performed in one or more separate actions and / or phases.Referring now to Figures 28 and 29, there is shown a series of cross-sectional views 2800, 2900 of some first alternative embodiments of the method of Figures 14-26, wherein the first etch extends through the upper interfacial layer 104t. The first alternative embodiments may be performed, for example, to form the memory cells as in FIG. 10A.As illustrated by cross-sectional view 2800 of FIG. 28, the actions described with reference to FIGS. 14-20 are performed as described with reference to FIGS. 14-20, except that the first etch described with reference to FIG. 20 further extends into the upper interface layer 104 tand stops on the ferroelectric layer 106. Thus, the first etching transfers patterns of the hard masks 712 to the upper electrode layer 110 land the upper interface layer 104 t, thereby segmenting the upper electrode layer 110 land the upper interface layer 104 t. In some embodiments, the upper interfacial layer 104 tis a Group 2 material while the lower interfacial layer 104 bis a Group 1 material. A group 1 material is a dielectric or metal oxide that is amorphous or crystalline as described with reference to FIG. 17. Further, a Group 2 material is conductive and is an amorphous or crystalline metal as described with reference to FIG. 17.As illustrated by cross-sectional view 2900 of FIG. 29, the actions described with respect to FIGS. 21-26 are performed as described with respect to FIGS. 21-26.Although FIGS. 28 and 29 are described with reference to a method, it should be understood that the structures shown in FIGS. 28 and 29 are not limited to the method, but rather may be stand alone and independent of the method. Although FIGS. 28 and 29 are described as a series of actions, it should be understood that the order of the actions may be changed in other embodiments. Although FIGS. 28 and 29 illustrate and describe a particular set of actions, some actions illustrated and / or described may be omitted in other embodiments. Moreover, actions not illustrated and / or described may be present in other embodiments.Referring now to FIGS. 30 and 32, a series of cross-sectional views 3000-3200 of some second alternative embodiments of the method of FIGS. 14-26 are shown wherein the lower electrodes 108 and the lower electrode barriers 802 form the BEVAs 706b. The second alternative embodiments may be performed, for example, to form the memory cells as in FIG. 10B.As illustrated by cross-sectional view 3000 of FIG. 30, the actions described with reference to FIG. 14 are performed. Further, a first etch stop layer 722 is deposited on the interconnect structure 702 and then patterned to form BEVA openings 3002 exposing the bottom electrode wires 704 b. The first etch stop layer 722 is a dielectric and may be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing. The patterning may be performed, for example, by a photolithography / etching process or other suitable patterning process.As illustrated by cross-sectional view 3100 of FIG. 31, a bottom electrode blocking layer 8021 and a bottom electrode layer 108 lare deposited over the first etch stop layer 722 and line the BEVA openings 3002, thereby forming BEVAs 706 b. The bottom electrode layer 108 lis conductive and may be or comprise, for example, titanium nitride, tantalum nitride, ruthenium, platinum, iridium, molybdenum, tungsten, doped polysilicon, one or more other suitable conductive materials, or any combination of the foregoing. The bottom electrode blocking layer 8021 is conductive and may be or comprise, for example, titanium nitride, platinum, aluminum-copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, one or more other suitable conductive materials, or any combination of the above. The bottom electrode layer 108 land / or the bottom electrode barrier layer 8021may be deposited by, for example, CVD, PVD, ALD, other suitable deposition processes, or any combination of the above.As illustrated by cross-sectional view 3200 of FIG. 32, the actions described with reference to FIGS. 17-26 are performed as described with reference to FIGS. 17-26, except that the second etch described with reference to FIG. 22 also extends into the lower electrode blocking layer 8021 to segment the lower electrode blocking layer 8021 into lower electrode blocks 802 that are individual to the lower electrodes 108. In some embodiments, the upper interface layer 104 tis a Group 1 material while the lower interface layer 104 bis a Group 1 or 2 material.In alternative embodiments, the first etch described with reference to FIG. 20 extends into the upper interfacial layer 104 t, as in FIG. 28. In at least some of these embodiments, the upper interfacial layer 104 tis a Group 2 material while the lower interfacial layer 104 bis a Group 1 or 2 material. Furthermore, in alternative embodiments, the upper interfacial layer 104 tmay also be omitted. Such alternative embodiments may form, for example, the memory cells 102 as in FIG. 8A.Although FIGS. 30-32 are described with reference to a method, it should be understood that the structures shown in FIGS. 30-32 are not limited to the method, but rather may be stand alone and independent of the method. Although FIGS. 30-32 are described as a series of actions, it should be understood that the order of the actions may be changed in other embodiments. Although FIGS. 30-32 illustrate and describe a particular series of actions, some actions illustrated and / or described may be omitted in other embodiments. Moreover, actions not illustrated and / or described may be present in other embodiments.Referring now to Figures 33-35, there is shown a series of cross-sectional views 3300-3500 of some third alternative embodiments of the method of Figures 14-26, with the second etch omitted. The third alternative embodiments may be performed, for example, to form the memory cells as in FIG. 10E.As illustrated by cross-sectional view 3300 of FIG. 33, the actions described with reference to FIGS. 14-19 are performed as described with reference to FIGS. 14-19. In alternative embodiments, the upper interfacial layer 104 tmay also be omitted. Such alternative embodiments may form, for example, the memory cells 102 as in FIG. 8C. Further, the first etching described with reference to FIG. 20 is performed as described with reference to FIG. 20, except that the first etching further extends through the upper interface layer 104 t, the ferroelectric layer 106, the lower interface layer 104 b, and the lower electrode layer 108 lto form the memory cells 102.As illustrated by cross-sectional view 3400 of FIG. 34, a sidewall spacer structure 718 is formed on common sidewalls formed by the hard masks 712, the lower and upper electrodes 108, 110, the lower and upper interfacial layers 104 b, 104 t, and the ferroelectric layer 106. The sidewall spacer structure 718 may be formed, for example, as described with reference to FIG. 21 or according to another suitable process.As illustrated by cross-sectional view 3500 of FIG. 35, the actions described with reference to FIGS. 23-26 are performed as described with reference to FIGS. 23-26.Although FIGS. 33-35 are described with reference to a method, it should be understood that the structures shown in FIGS. 33-35 are not limited to the method, but rather may be stand alone and independent of the method. Although FIGS. 33-35 are described as a series of actions, it should be understood that the order of the actions may be changed in other embodiments. Although FIGS. 33-35 illustrate and describe a particular series of actions, some actions illustrated and / or described may be omitted in other embodiments. Moreover, actions not illustrated and / or described may be present in other embodiments.Referring now to Figures 36-40, there is shown a series of cross-sectional views 3600-4000 of some fourth alternative embodiments of the method of Figures 14-26, with the first and second etching omitted. The fourth alternative embodiments may be performed, for example, to form the memory cells as in FIG. 10D.As illustrated by cross-sectional view 3600 of FIG. 36, the actions described with reference to FIG. 14 are performed as described with reference to FIG. 14. Further, a first etch stop layer 722, a buffer layer 726, and a second IMD layer 720 bare deposited to be stacked over the interconnect structure 702 such that the buffer layer 726 is interposed between the first etch stop layer 722 and 722 of the second IMD layer 720 b. In alternative embodiments, buffer layer 726 is omitted. The first etch stop layer 722, the buffer layer 726, and the second IMD layer 720 bmay be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the foregoing.As illustrated by cross-sectional view 3700 of FIG. 37, the first etch stop layer 722, the buffer layer 726, and the second IMD layer 720 bare patterned to form cell openings 3702 that expose the lower electrode wires 704 b, respectively. The patterning may be performed, for example, by a photolithography / etching process or other suitable patterning process.As illustrated by cross-sectional view 3800 of FIG. 38, a bottom electrode blocking layer 8021 is deposited over the second IMD layer 720 b, lining the cell openings 3702. The actions described with reference to FIGS. 16-19 are then performed as described with reference to FIGS. 16-19 to deposit a bottom electrode layer 108l, a bottom interface layer 104b, a ferroelectric layer 106, a top interface layer 104t, and a top electrode layer 110l. Further, an upper electrode blocking layer 804 lis deposited over the upper electrode layer 110 l. The above layers or any combination of the above layers may be deposited by, for example, CVD, PVD, ALD, one or more other suitable deposition processes, or any combination of the above. In alternative embodiments, the upper interfacial layer 104 tis omitted to form the memory cells as in FIG. 8B.As illustrated by cross-sectional view 3900 of FIG. 39, planarization is performed into lower electrode layer 108 l, lower interface layer 104 b, ferroelectric layer 106, upper interface layer 104 t, upper electrode layer 110 l, lower electrode blocking layer 8021, and upper electrode blocking layer 804 luntil upper surfaces thereof are flush with an upper surface of second IMD layer 720 b. Thereby, the above layers are segmented to form memory cells 102. Segments of the lower and upper electrode barriers 802l, 804l will be referred to herein as lower electrode barriers 802 and upper electrode barriers 804, respectively. Similarly, segments of the lower and upper electrode layers 108 l, 1101are hereinafter referred to as lower electrodes 108 and upper electrodes 110, respectively. Planarization may be performed, for example, by chemical mechanical polishing (CMP) and / or other suitable planarization.As illustrated by cross-sectional view 4000 of FIG. 40, the actions described with respect to FIGS. 24-26 are performed as described with respect to the figures, except that the actions deposit a third IMD layer 720 cin place of the second IMD layer 720 band then structure the second and third IMD layers 720 b, 720 c.Although FIGS. 36-40 are described with reference to a method, it should be understood that the structures shown in FIGS. 36-40 are not limited to the method, but rather may be stand alone and independent of the method. Although FIGS. 36-40 are described as a series of actions, it should be understood that the order of the actions may be changed in other embodiments. Although FIGS. 36-40 illustrate and describe a particular series of actions, some actions illustrated and / or described may be omitted in other embodiments. Moreover, actions not illustrated and / or described may be present in other embodiments.In some embodiments, the present disclosure includes an IC chip including a memory cell, the memory cell including: a bottom electrode; a ferroelectric layer overlying the bottom electrode; a top electrode overlying the ferroelectric layer; and a first interfacial layer between the ferroelectric layer and the bottom electrode, wherein a top surface of the first interfacial layer has a higher texture uniformity than a top surface of the bottom electrode to improve the remanent polarization of the ferroelectric layer. In some embodiments, the first interfacial layer is a monocrystalline dielectric, metal oxide, or metal. In some embodiments, the first interfacial layer is a crystalline dielectric, metal, or metal oxide in which at least 90% of the grains share a common orientation. In some embodiments, the first interfacial layer has a crystallization temperature above about 400 degrees Celsius. In some embodiments, the first interfacial layer is a crystalline dielectric, metal, or metal oxide, wherein at least 90% of the grains have a grain size of less than about 1 nanometer. In some embodiments, the first interfacial layer is an amorphous dielectric, metal, or metal oxide. In some embodiments, the memory cell further includes: a second interfacial layer between the top electrode and the ferroelectric layer, the second interfacial layer having a larger energy band gap than the ferroelectric layer. In some embodiments, the second interface layer is a same material as the first interface layer. In some embodiments, the first interface layer is a dielectric or metal oxide and the second interface layer is a metal, or vice versa.In some embodiments, the present disclosure provides another IC chip comprising a memory cell, the memory cell comprising: a bottom electrode; a ferroelectric layer overlying the bottom electrode; a top electrode overlying the ferroelectric layer; and a first interfacial layer overlying and directly contacting the ferroelectric layer and the bottom electrode, wherein the first interfacial layer is an amorphous material, a single crystal material, or a crystalline material in which a majority of the grains in the first interfacial layer have a common orientation and / or have a grain size less than about 1 nanometer. In some embodiments, the top electrode directly contacts the ferroelectric layer. In some embodiments, the IC chip further includes: a second interface layer that is between and directly contacts the ferroelectric layer and the top electrode, wherein the second interface layer is an amorphous or crystalline material different from that of the ferroelectric layer. In some embodiments, the first interface layer has a larger energy band gap than the ferroelectric layer. In some embodiments, the bottom electrode, the ferroelectric layer, the top electrode, and the first interfacial layer form a common sidewall. In some embodiments, the bottom electrode, the ferroelectric layer, the top electrode, and the first interfacial layer form a common sidewall that is laterally offset from a sidewall of the top electrode, and wherein the IC chip further comprises: a sidewall spacer overlying the ferroelectric layer and extending from the common sidewall to the sidewall of the top electrode. In some embodiments, the bottom electrode, the ferroelectric layer, and the first interfacial layer have individual U-shaped profiles with tops that are flush with each other. In some embodiments, the IC chip further includes a conductive wire underlying the memory cell, wherein the memory cell forms a BEVA that protrudes downward toward the conductive wire, and wherein the bottom electrode, the ferroelectric layer, the first interfacial layer, and the top electrode have individual tops that are recessed at the BEVA.In some embodiments, the present disclosure provides a method comprising: depositing a bottom electrode layer over a substrate; depositing a first interfacial layer overlying the bottom electrode layer; depositing a ferroelectric layer overlying and directly overlying the first interfacial layer; depositing a top electrode layer overlying the ferroelectric layer; and patterning the bottom and top electrode layers, the first interfacial layer, and the ferroelectric layer to form a memory cell; wherein a top surface of the first interfacial layer has greater texture uniformity than a top surface of the bottom electrode layer. In some embodiments, the first interfacial layer is an amorphous dielectric, metal, or metal oxide, and the bottom electrode layer is crystalline. In some embodiments, the first interfacial layer and the bottom electrode layer are crystalline, and wherein the first interfacial layer has a higher percentage of grains having a grain size of less than about 1 nanometer than the bottom electrode layer.

Claims

An integrated circuit, IC, chip comprising a memory cell (102), the memory cell (102) comprising: a bottom electrode (108); a ferroelectric layer (106) overlying the bottom electrode (108); a top electrode (110) overlying the ferroelectric layer (106); and a first interfacial layer (104, 104b) between the ferroelectric layer (106) and the bottom electrode (108), wherein a top surface (114) of the first interfacial layer (104, 104b) has a higher texture uniformity than a top surface (112) of the bottom electrode (108) to improve the remanent polarization of the ferroelectric layer (106); and wherein the first interfacial layer (104, 104b) is an amorphous dielectric, amorphous metal, or amorphous metal oxide.The IC chip of claim 1, wherein the memory cell (102) further comprises: a second interfacial layer (104, 104t) between the top electrode (110) and the ferroelectric layer (106), wherein the second interfacial layer (104, 104t) has a larger energy band gap than the ferroelectric layer (106).The IC chip of claim 2, wherein the second interface layer (104, 104t) is a same material as the first interface layer (104, 104b).The IC chip of claim 2, wherein the first interfacial layer (104, 104b) is a dielectric or a metal oxide and the second interfacial layer (104, 104t) is a metal, or vice versa.An integrated circuit, IC, chip comprising a memory cell (102), the memory cell (102) comprising: a bottom electrode (108); a ferroelectric layer (106) overlying the bottom electrode (108); a top electrode (110) overlying the ferroelectric layer (106); and a first interfacial layer (104, 104b) overlying and directly contacting the ferroelectric layer (106) and the bottom electrode (108), wherein the first interfacial layer (104, 104b) is an amorphous material.The IC chip of claim 5, wherein the top electrode (110) directly contacts the ferroelectric layer (106).The IC chip of claim 5 or 6, further comprising: a second interface layer (104, 104t) located between and directly contacting the ferroelectric layer (106) and the top electrode (110), wherein the second interface layer (104, 104t) is an amorphous or crystalline material different from that of the ferroelectric layer (106).The IC chip of any of the preceding claims 5 to 7, wherein the first interface layer has a larger energy band gap than the ferroelectric layer.The IC chip of any one of the preceding claims 5 to 8, wherein the bottom electrode (108), the ferroelectric layer (106), the top electrode (110), and the first interfacial layer (104, 104b) form a common sidewall.The IC chip of any of the preceding claims 5 to 9, wherein the bottom electrode (108), the ferroelectric layer (106), and the first interfacial layer (104, 104b) form a common sidewall (714) laterally offset from a sidewall (716) of the top electrode (110), and wherein the IC chip further comprises: a sidewall spacer (718) overlying the ferroelectric layer (106) and extending from the common sidewall (714) to the sidewall (716) of the top electrode (110).The IC chip of any of the preceding claims 5 to 10, wherein the bottom electrode (108), the ferroelectric layer (106) and the first interfacial layer (104, 104b) have individual U-shaped profiles with tops that are flush with each other.The IC chip of any of the preceding claims 5 to 11, further comprising: a conductive wire (704b) underlying the memory cell (102), wherein the memory cell (102) forms a bottom electrode via, BEVA, (706b) that protrudes downward toward the conductive wire (704b), and wherein the bottom electrode (108), the ferroelectric layer (106), the first interfacial layer (104, 104b), and the top electrode (110) have individual tops that are recessed at the BEVA (706b).A method comprising: depositing a bottom electrode layer (108) over a substrate; depositing a first interfacial layer (104, 104b) overlying the bottom electrode layer (108); depositing a ferroelectric layer (106) overlying and directly overlying the first interfacial layer (104, 104b); depositing a top electrode layer (110) overlying the ferroelectric layer (106); and patterning the bottom and top electrode layers (110), the first interfacial layer (104, 104b), and the ferroelectric layer (106) to form a memory cell (102); wherein a top surface (114) of the first interfacial layer (104, 104b) has greater texture uniformity than a top surface (122) of the bottom electrode layer (108); wherein the first interfacial layer (104, 104b) is an amorphous dielectric, metal or metal oxide, and wherein the bottom electrode layer (108) is crystalline.

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