Fixture layout design to improve fixture performance

Abstract

Integrated chip (300, 400, 800) with: an isolation region (108) arranged in a substrate (101) and enclosing an active region (110); a gate structure (112) having a base region (112b) and a gate extension finger (112e) projecting outwardly from a sidewall of the base region (112b) along a first direction (124) beyond opposite sides of the active region (110); a source contact (116) disposed in the active region (110); a drain contact (118) disposed in the active region (110) and separated from the source contact (116) by the gate extension finger (112e); and a first plurality of conductive contacts (120) disposed on the gate structure (112) and separated along the first direction (124), the first plurality of conductive contacts (120) being separated by spaces overlying the gate extension finger (112e); a second gate extension finger (112e) projecting outwardly from the sidewall of the base region (112b) and separated from the gate extension finger (112e) along a second direction (126) perpendicular to the first direction (124), wherein the first plurality of conductive contacts (120) extends over a majority of a length (114, 702, 1102) of the second gate extension finger (112e); and a gate interconnect (402a) connected to the gate extension finger (112e), the second gate extension finger (112e), and the base region (112b) by the first plurality of conductive contacts (120) and extending in the second direction (126) between a first contact of the first plurality of conductive contacts (120) disposed on the gate extension finger (112e) and a second contact of the first plurality of conductive contacts disposed on the second gate extension finger (112e).

Description

BACKGROUND

[0001] Integrated circuits (ICs) can contain various types of transistor devices depending on the IC's application. In recent years, the growing market for cellular and radio frequency (RF) devices has led to a sharp increase in the use of high-performance transistor devices. For example, high-performance transistor devices are often used in power amplifiers for RF transmit / receive chains due to their ability to handle high breakdown voltages (e.g., greater than approximately 50 V) and high frequencies. High-performance transistor devices are also used in integrated power management circuits, automotive electronics, sensor interfaces, flat-panel display driver applications, and more.

[0002] US 6,404,030 B1 discloses a structure for a multi-finger transistor. Conductive gate fingers extending beyond the gate oxide layers and also beyond the active regions are formed such that each gate finger represents a continuous conductive line providing and connecting the gates of the multiple active regions.

[0003] US 2017 / 0271329 A1 discloses a transistor device comprising a source contact extending in a first direction, a gate finger extending in the first direction adjacent to the source contact, and a drain contact adjacent to the gate finger, wherein the gate finger is located between the drain contact and the source contact. The device further comprises a gate jumper extending in the first direction, a gate bus connected to the gate jumper and the gate finger, and a gate signal distribution bus spaced from the gate bus in the first direction and connecting the gate jumper.

[0004] JP 2018-074025 A discloses a semiconductor device having multiple gate fingers of a transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1A-1C show some embodiments of an integrated chip having a high performance transistor device with a low gate resistance. The Fig. 2A-2C show some embodiments of diagrams illustrating device parameters of a disclosed high-performance transistor device as a function of the length of a gate extension finger. Fig. 3 shows a three-dimensional view of some further embodiments of an integrated chip comprising a disclosed high-performance transistor device. Fig. 4A shows a three-dimensional view of some illustrative examples of an integrated chip including a disclosed high-performance transistor device. Fig. Figure 4B shows some embodiments of a graph illustrating a gate extension finger resistance as a function of length for the disclosed high power transistor device of Fig. 4A. The Fig. 5A-5E show some further illustrative examples of an integrated chip having a disclosed high-performance transistor device. The Fig. 6A-6B show cross-sectional views of some further illustrative examples of integrated chips having various interconnect configurations connected to a disclosed high-performance transistor device. The Fig. 7A-7C show top views of some further illustrative examples of an integrated chip including a disclosed high-performance transistor device at various heights above a substrate. Fig. 8A shows a three-dimensional view of some further embodiments of an integrated chip having a high-performance transistor device with a low gate resistance. Fig. Figure 8B shows some embodiments of a graph illustrating a gate extension finger resistance as a function of length for the disclosed high power transistor device of Fig. 8A. The Fig. 9A-9E show some further embodiments of an integrated chip having a high performance transistor device with a low gate resistance. The Fig. 10A-10B show cross-sectional views of some further illustrative examples of integrated chips having various interconnect configurations connected to a disclosed high-performance transistor device. The Fig. 11A-11C show top views of some further embodiments and illustrative examples of an integrated chip including a disclosed high-performance transistor device at various heights above a substrate. The Fig. 12A-16C illustrate some embodiments of a method for fabricating an integrated chip having a high performance transistor device with a low gate resistance. The Fig. 17A-21C show some further embodiments of a method for manufacturing an integrated chip having a high performance transistor device with a low gate resistance. Fig. 22 shows a flow diagram of some embodiments of a method for manufacturing an integrated chip having a high performance transistor device with a low gate resistance. DETAILED DESCRIPTION

[0006] Improved semiconductor devices according to the invention and a corresponding manufacturing method are provided in independent claims 1, 12 and 20. The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples throughout the present invention. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] High-performance transistor devices (e.g., high-voltage transistor devices) are used in many modern electronic devices. A common type of high-performance transistor device is a high electron mobility transistor (HEMT) device. HEMT devices may comprise a plurality of semiconductor layers stacked above a base substrate. The plurality of semiconductor layers includes an active layer and a depletion layer that contacts a top surface of the active layer to form a heterojunction at their interface. A two-dimensional electron gas (2DEG) is inherently present along the interface between the active layer and the depletion layer, allowing electrons to move freely across the interface.

[0009] A HEMT device may include an active region enclosed by an isolation region that confines the 2DEG to the active region. A source contact and a drain contact are disposed above the active region. A gate structure is disposed in the active region between the source contact and the drain contact. In some embodiments, the gate structure may include a doped semiconductor (e.g., p-doped gallium nitride (GaN)) that can disrupt the underlying 2DEG and prevent electrons from moving freely beneath the gate structure. The gate structure may include a base region and one or more rectangular-shaped gate extension fingers that protrude outward from a sidewall of the base region to extend across an entire width of the active region and block the movement of electrons between the source contact and the drain contact.The gate structure is contacted by conductive contacts located above it. The conductive contacts are typically limited to an area above the base region, as the base region can be wider than the gate extension fingers and is therefore easier to contact.

[0010] Over time, the demands for high-performance transistor devices have increased. For example, as data speeds in wireless transmission increase, higher-power devices are being used in base stations to meet data speed requirements. One way HEMT devices can achieve higher output power (e.g., greater than about 10 watts (W), greater than about 180 W, or other similar values) is by increasing the number of gate extension fingers extending outward from a base region of a gate structure. However, increasing the number of gate extension fingers can result in a transistor device size becoming too wide to fit into a standard package. Alternatively, higher output power can be achieved by increasing the lengths of the gate extension fingers.However, it should be well understood that by increasing the lengths of the gate extension fingers, a gate resistance of the gate extension fingers is increased and an RF performance of the transistor device is reduced (e.g., reduction of the gain and / or the power added efficiency (PAE)).

[0011] The present disclosure, in some embodiments, relates to an integrated chip having a transistor device configured to provide high output power while maintaining a relatively low gate resistance (e.g., a resistance across a gate extension finger less than about 10 ohms, less than about 5 ohms, or other similar values). In some embodiments, the transistor device includes a gate structure disposed over a substrate. The gate structure includes a base region and a gate extension finger extending outwardly from a sidewall of the base region along a first direction. The gate extension finger extends to a length that extends beyond opposite sides of an active area in the substrate.A source contact and a drain contact are arranged in the active region and are separated by the gate extension finger along a second direction perpendicular to the first direction. A first plurality of conductive contacts are arranged on the gate extension finger and separated along the first direction such that they extend over a majority of the length of the gate extension finger. By separating the first plurality of conductive contacts over a majority of the length of the gate extension finger, an alternative path is provided for current to reach different parts of the gate extension finger, thereby reducing the resistance of the gate extension finger and improving the performance of the transistor device (e.g., power efficiency (PAE), gain, etc.).

[0012] The Fig. 1A-1C show some embodiments of an integrated chip having a high-performance transistor device with a relatively low gate resistance. Fig. 1A shows a three-dimensional view 100 of the integrated chip, Fig. Figure 1B shows a sectional view 128 of the integrated chip taken along the cross-section line AA' of Fig. 1A has been created, and Fig. Figure 1C shows a sectional view 134 of the integrated chip taken along the cross-section line BB' of Fig. 1A has been created.

[0013] The integrated chip includes an isolation region 108 disposed in a substrate 101. The isolation region 108 extends along a closed and uninterrupted path enclosing an active region 110 in the substrate 101. In some embodiments, the high-performance transistor device may include a high electron mobility transistor (HEMT) device (e.g., a depletion-mode HEMT (D-HEMT), an enhancement-mode HEMT (E-HEMT), a pseudomorphic HEMT (a p-HEMT), or other similar devices). In some of these embodiments, the substrate 101 may include an active layer 104 (i.e., a channel layer) disposed over a base substrate 102 and a barrier layer 106 disposed over the active layer 104.A two-dimensional electron gas (2DEG) 130 may be present along an interface between the active layer 104 and the barrier layer 106. In other embodiments, the high-performance transistor device may comprise a silicon CMOS device, a silicon-germanium heterojunction bipolar transistor (SiGe HBT), or other similar devices.

[0014] A gate structure 112 is disposed above the substrate 101. The gate structure 112 includes a base region 112b and one or more gate extension fingers 112e extending laterally outward from a sidewall of the base region 112b along a first direction 124. In some embodiments, the base region 112b may be disposed directly above the isolation region 108, while the one or more gate extension fingers 112e extend in the first direction 124 to a length 114 that extends beyond opposite edges of the active region 110. One or more source contacts 116 and one or more drain contacts 118 are disposed above the active region 110.The one or more gate extension fingers 112e extend between the one or more source contacts 116 and the one or more drain contacts 118 to separate the one or more source contacts 116 and the one or more drain contacts 118 along a second direction 126 that is perpendicular to the first direction 124. For example, in some embodiments, a first gate extension finger extends between a first source contact and a drain contact, and a second gate extension finger extends between a second source contact and the drain contact.

[0015] A first plurality of conductive contacts 120 is disposed over the gate structure 112 and enclosed by a dielectric structure 132. The first plurality of conductive contacts 120 are separated from each other by non-zero spacings 122 across the length 114 of the one or more gate extension fingers 112e. In some embodiments, the first plurality of conductive contacts 120 may be spaced apart in the first direction 124 to extend across a majority of the length 114 of the one or more gate extension fingers 112e (e.g., across 50% of the length 114, across 75% of the length 114, across 90% of the length 114, or other similar values). In some embodiments, the non-zero distances 122 between adjacent ones of the first plurality of conductive contacts 120 are substantially equal, such that the first plurality of conductive contacts 120 are arranged at a substantially constant pitch.

[0016] By spacing the first plurality of conductive contacts 120 apart with non-zero distances 122, a distance between one of the first plurality of conductive contacts 120 and a portion of the one or more gate extension fingers 112e remains relatively small. Since a resistance of a conductor is proportional to a length of the conductor (e.g., R=ρL / A, where R is a resistance, ρ is a resistivity, L is a length, and A is a cross-sectional area), the relatively small distance between the first plurality of conductive contacts 120 and a portion of the one or more gate extension fingers 112e provides one or more gate extension fingers 112e with a relatively low resistance. By having a resistance of the one or more gate extension fingers 112e relatively low, a performance (e.g.,a power efficiency (PAE), a gain or the like) of the transistor device can be improved.

[0017] Fig. 2A shows a graph 200 illustrating some example embodiments of a gate extension finger resistance (illustrated on the y-axis) as a function of a gate extension finger length (illustrated on the x-axis).

[0018] Diagram 200 shows a resistor 202 of a gate extension finger in a gate structure, which is contacted by conductive contacts located thereabove, which are completely confined to an area above a base region of the gate structure. If a length (e.g., corresponding to the length 114 of Fig. 1A) of the gate extension finger is increased from about 150 µm to about 750 µm, the resistance 202 of the gate extension finger increases by over 500%. For example, the resistance 202 increases from about 5.4 ohms (Ω) at a length of 150 µm to about 28.7 Ω at a length of 750 µm. Therefore, contacting the gate structure with conductive contacts that are entirely confined to an area above the base region causes the length of the gate extension finger to increase, which in turn has a significant effect on the resistance 202.

[0019] The diagram 200 further shows a resistance 204 of a gate extension finger (e.g., measured over a length 114 of the gate extension finger, as in Fig. 1A) in a disclosed transistor device having a gate structure contacted by overlying conductive contacts extending over a majority of a length of a gate extension finger. As a length of the gate extension finger is increased from about 150 µm to about 750 µm, the resistance 204 of the gate extension finger increases by less than or equal to about 15%. Therefore, contacting the gate structure with conductive contacts extending over a majority of the length of the gate extension finger mitigates an increase in resistance as a length of a gate extension finger is increased.

[0020] It will be appreciated that mitigating an increase in the resistance of a gate extension finger will result in improvements in other performance parameters of a transistor device. Fig. For example, Figure 2B shows a graph 206 illustrating some embodiments of power efficiency (PAE) (shown on the y-axis) as a function of a gate extension finger length (shown on the x-axis).

[0021] Diagram 206 shows a PAE 208 of a transistor device with a gate structure contacted by overlying conductive contacts that are entirely confined to an area above a base region of the gate structure. The PAE 208 drops by more than 50% when a gate extension finger length is increased from about 50 µm to about 750 µm. For example, the PAE 208 drops from about 65% at a length of 50 µm to about 30% at a length of 750 µm. Increasing the gate extension finger length therefore has a significant impact on the PAE 208.

[0022] Diagram 206 further illustrates a PAE 210 of a disclosed transistor device having a gate structure contacted by conductive contacts thereover that extend over a majority of a gate extension finger. The PAE 210 drops by about 2% when a gate extension finger length is increased from about 150 µm to about 750 µm. For example, the PAE 210 drops from about 63% at a length of 150 µm to about 61% at a length of 750 µm. Therefore, increasing the length of the gate extension finger has a minimal impact on the PAE 210 of the disclosed transistor device.

[0023] Fig. 2C shows a graph 212 illustrating some embodiments of gain (shown on the y-axis) as a function of a gate extension finger length (shown on the z-axis).

[0024] Diagram 212 shows a gain 214 of a transistor device with a gate structure contacted by overlying conductive contacts that are entirely confined to an area above a base region of the gate structure. The gain 214 drops by almost 90% when a gate extension finger length is increased from approximately 50 µm to approximately 750 µm. For example, the gain 214 drops from over 18 dB at a length of 50 µm to approximately 2 dB at a length of 750 µm. Increasing the length of the gate extension finger therefore has a significant impact on the gain 214.

[0025] Diagram 212 further shows a gain 216 of a disclosed transistor device having a gate structure contacted by overlying conductive contacts extending over a majority of a gate extension finger. The gain 216 drops by less than 10% when increasing a gate extension finger length from about 150 µm to about 750 µm. For example, the gain 216 drops from about 16.5 dB for a gate length of 150 µm to about 15.1 dB for a gate length of 750 µm. Therefore, increasing the gate extension finger length has a minimal impact on the gain 216 of the disclosed transistor device.

[0026] Fig. 3 shows a three-dimensional view of some further embodiments of an integrated chip 300 having a high performance transistor device with a low gate resistance.

[0027] The integrated chip 300 includes an isolation region 108 disposed within a substrate 101 and extending along a closed and uninterrupted path enclosing an active region 110. In some embodiments, the substrate 101 may include an active layer 104 disposed over a base substrate 102 and a barrier layer 106 disposed over the active layer 104. A 2DEG (not shown) is present along an interface between the active layer 104 and the barrier layer 106. In some embodiments, the base substrate 102 may comprise a first semiconductor material (e.g., silicon, silicon carbide, sapphire, or the like), the active layer 104 may comprise a second semiconductor material (e.g., a first III-V semiconductor material, gallium nitride (GaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or the like), and the barrier layer 106 may comprise a third semiconductor material (e.g.,a second III-V semiconductor material, aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium aluminum gallium nitride (InAlGaN), indium aluminum arsenide (InAlAs), indium aluminum gallium arsenide (InAlGaAs), indium aluminum gallium phosphate (InAlGaP), silicon germanium (SiGe), or the like. In some embodiments, the isolation region 108 may comprise one or more semiconductor materials having a crystalline disorder that disrupts lateral propagation of the 2DEG.

[0028] A gate structure 112 is disposed above the substrate 101. The gate structure 112 includes a base region 112b and one or more gate extension fingers 112e extending laterally outward from a sidewall of the base region 112b along a first direction 124. The one or more gate extension fingers 112e are located above the active region 110 and separate one or more source contacts 116 and one or more drain contacts 118 along a second direction 126 that is perpendicular to the first direction 124. In some embodiments, the one or more gate extension fingers 112e extend outward from the base region 112b to a length 114. In some embodiments, the gate structure 112 may include a lower gate portion and a gate electrode disposed above the lower gate portion. In some embodiments, the lower gate portion may comprise a dielectric material (e.g.,an oxide, a nitride, or the like). In other embodiments, the lower gate portion may comprise a semiconductor material (e.g., p-doped gallium nitride). In some embodiments, the gate electrode may comprise a metal (e.g., aluminum, titanium, copper, tungsten, tantalum, or the like) or doped polysilicon.

[0029] In some embodiments, the one or more source contacts 116 comprise a plurality of discrete source contact segments 116a-116c that are aligned along the direction 124 and that are separated from each other along the first direction 124. In some further embodiments, the one or more drain contacts 118 may also comprise a plurality of discrete drain contact segments that are aligned along the first direction 124 and that are separated from each other along the first direction 124are separated from each other. In such embodiments, the one or more gate extension fingers 112e may extend contiguously along the first direction 124 beyond outer sidewalls of the plurality of discrete source contact segments and / or drain contact segments. In some further embodiments, the active region 110 may also extend contiguously beyond the outer sidewalls of the plurality of discrete source contact segments and / or drain contact segments. In some embodiments, adjacent ones of the plurality of discrete source contact segments and / or drain contact segments are separated from each other by a non-zero pitch 302. In some embodiments, the non-zero pitch 302 may be in a range between about 50 µm and about 75 µm, between about 30 µm and about 50 µm, or other similar values.

[0030] A first plurality of conductive contacts 120 is disposed on the gate structure 112, and a second plurality of conductive contacts 304 is disposed on the one or more source contacts 116 and the one or more drain contacts 118. The first plurality of conductive contacts 120 are spaced apart from each other across the one or more gate extension fingers 112e such that the first plurality of conductive contacts 120 extends a majority of the length 114 of the one or more gate extension fingers 112e. In some embodiments, one of the second plurality of conductive contacts 304 is disposed on respective ones of the plurality of discrete source contact segments and drain contact segments.

[0031] In some embodiments, the non-zero spacing 302 between adjacent ones of the plurality of discrete source contact segments and drain contact segments may be aligned with the first plurality of conductive contacts 120 along the second direction 126 (e.g., such that the first plurality of conductive contacts 120 is between the sidewalls of the discrete source / drain contact segments along the first direction 124), thereby increasing a spacing between the plurality of discrete source / drain contact segments and the first plurality of conductive contacts 120. Increasing a spacing between the plurality of discrete source / drain contact segments and the first plurality of conductive contacts 120 mitigates the increase in capacitance (e.g.,a capacitance between the gate structure 112 and the one or more source contacts 116 and / or the one or more drain contacts 118) that may occur as a result of the placement of the first plurality of conductive contacts 120 on the one or more gate extension fingers 112e. By mitigating the increase in capacitance between the gate structure 112 and the one or more source contacts 116 and / or the one or more drain contacts 118, the disclosed transistor device may operate with good performance over a wide range of operating frequencies (e.g., above 1 gigahertz (GHz), between about 1 GHz and about 8 GHz, between about 24 GHz and about 40 GHz, greater than about 67 GHz, or other similar values).

[0032] In some embodiments, the length 114 of the one or more gate extension fingers 112e may be greater than or equal to about 500 micrometers (µm). In other embodiments, the length 114 may be greater than or equal to about 750 µm. By having the length 114 of the one or more gate extension fingers 112e greater than or equal to about 500 µm, the disclosed transistor device may achieve relatively high power (e.g., greater than about 10 watts (W), greater than about 180 W, or other similar values). While a gate extension finger length 114 of greater than about 500 µm would typically cause the gate structure 112 to have a relatively high gate resistance, which would be detrimental to device operation, by distributing the plurality of conductive contacts along the length 114 of the one or more gate extension fingers 112e, the gate resistance also remains relatively low.The relatively low gate resistance enables the disclosed transistor device to have good power efficiency (PAE) and / or good gain. The fact that the disclosed transistor device can be operated with good performance over a wide power and / or frequency range enables the use of the disclosed transistor device in a wide range of applications (e.g., base stations, radar, wireless communication applications, power amplifiers, low-noise amplifiers, etc.).

[0033] Fig. 4A shows a three-dimensional view of some further illustrative examples of an integrated chip 400 having a high-performance transistor device with a low gate resistance.

[0034] The integrated chip 400 includes an isolation region 108 disposed in a substrate 101 and enclosing an active region 110. A gate structure 112 is disposed above the substrate 101. The gate structure 112 includes a base region 112b and one or more gate extension fingers 112e extending laterally outward from a sidewall of the base region 112b along a first direction 124. The one or more gate extension fingers 112e separate one or more source contacts 116 and one or more drain contacts 118 located above the active region 110.

[0035] A first interconnect layer is disposed over the substrate 101 and includes one or more first gate interconnects 402a and one or more first source / drain interconnects 402b. The one or more first gate interconnects 402a are disposed directly over a first plurality of conductive contacts 120 on the base region 112b and the one or more gate extension fingers 112e and extend parallel (e.g., along the first direction) to the one or more gate extension fingers 112e. In some embodiments, the one or more first gate interconnects 402a each have a bottom surface facing the substrate 101 and contacting the first plurality of conductive contacts on the base region 112b and the one and / or more gate extension fingers 112e.The one or more first source / drain interconnects 402b are disposed directly above the one or more source contacts 116 and / or the one or more drain contacts 118. In some embodiments, the one or more first gate interconnects 402a extend parallel to the one or more first source / drain interconnects 402b. A second interconnect layer is disposed above the first interconnect layer. The second interconnect layer includes one or more second source / drain interconnects 406 connected to the one or more first source / drain interconnects 402b by one or more interconnect vias 404.

[0036] By connecting the one or more first gate interconnects 402a to the first plurality of conductive contacts 120 on the base region 112b and the one or more gate extension fingers 112e, an alternative path is provided for current to flow to different parts of the one or more gate extension fingers 112e, resulting in a relatively low gate resistance for relatively long gate extension fingers (e.g., gate extension fingers with a length greater than about 500 µm, greater than about 750 µm, etc.). For example, Fig. 4B is a graph 408 illustrating some example embodiments of a gate extension finger resistance 410 (illustrated on the y-axis) as a function of a gate extension finger length (illustrated on the x-axis). As shown in graph 408, the resistance 410 increases by less than or equal to about 12.5% ​​as a gate extension finger length increases from about 150 µm to about 750 µm. For example, the resistance 410 increases from about 3.2 Ω at a length of 150 µm to about 3.6 Ω at a length of 750 µm.

[0037] Fig. 5A shows a top view 500 of some further illustrative examples of an integrated chip having a high-performance transistor device with a relatively low resistance. Fig. 5B-5E show cross-sectional views of the integrated chip of Fig. 5A, which were created along different cross-sectional lines. Fig. 5B shows a sectional view 502 taken along the line AA' of Fig. 5A has been created, Fig. 5C shows a sectional view 504 taken along the line BB' of Fig. 5A has been created, Fig. 5D shows a sectional view 506 taken along the line CC' of Fig. 5A has been created, and Fig. 5E shows a sectional view 508 taken along the line DD' of Fig. 5A. It should be understood that the plan view 500 of Fig. 5A does not show the upper interconnects to simplify the top view.

[0038] The integrated chip includes an isolation region 108 extending along a closed and uninterrupted path enclosing an active region 110. A gate structure 112 is disposed over the substrate 101. The gate structure 112 includes a base region 112b and one or more gate extension fingers 112e extending outward from a sidewall of the base region 112b along a first direction 124. The one or more gate extension fingers 112e extend between one or more source contacts 116 and one or more drain contacts 118 located over the active region 110.In some embodiments, the gate structure 112, the one or more source contacts 116, and / or the one or more drain contacts 118 may be disposed in recesses in the substrate 101 such that a portion of the gate structure 112, the one or more source contacts 116, and / or the one or more drain contacts 118 are located below a top surface of the substrate 101.

[0039] A first interconnect layer is disposed in a dielectric structure 132 above the substrate 101. The first interconnect layer includes one or more first gate interconnects 402a connected to the gate structure 112 through a first plurality of conductive contacts 120, and one or more first source / drain interconnects 402b connected to the one or more source contacts 116 and / or the one or more drain contacts 118 through a second plurality of conductive contacts 304. A second interconnect layer is disposed in the dielectric structure 132 above the first interconnect layer. The second interconnect layer includes one or more second source / drain interconnects 406 connected to the one or more first source / drain interconnects 402b through a plurality of interconnect vias 404.In some embodiments, the first plurality of conductive contacts 120, the second plurality of conductive contacts 304, the first interconnect layer, the plurality of interconnect vias 404, and the second interconnect layer may comprise tungsten, aluminum, copper, ruthenium, and / or the like. In some embodiments, the dielectric structure 132 may comprise a plurality of stacked inter-level dielectric (ILD) layers 132a-132c. In some embodiments, the plurality of stacked ILD layers 132a-132c may comprise a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon-doped oxide, SiCOH), or the like.

[0040] It should be understood that in various embodiments, a width of the one or more second source / drain interconnects 406 may vary along the second direction 126. Fig. For example, FIG. 6A shows a cross-sectional view 600 of some illustrative examples of an integrated chip having one or more second source / drain interconnects 406 with a relatively small width along the second direction 126. As shown in the cross-sectional view 600, the one or more second source / drain interconnects 406 are laterally separated from an outermost sidewall of the one or more first gate interconnects 402a by a non-zero distance 602. Because the one or more second source / drain interconnects 406 are laterally separated from an outermost sidewall of the one or more first gate interconnects 402a, a capacitance between the one or more first gate interconnects 402a and the one or more second source / drain interconnects 406 decreases, but a resistance of the one or more second source / drain interconnects 406 increases.

[0041] Fig. 6B shows a cross-sectional view 604 of some embodiments of an integrated chip having one or more second source / drain interconnects 406 with a relatively large width along the second direction 126. As shown in the cross-sectional view 604, the one or more second source / drain interconnects 406 laterally overlap the one or more first gate interconnects 402a across a non-zero distance 606. Because the one or more second source / drain interconnects 406 laterally overlap the one or more first gate interconnects 402a, a capacitance between the one or more first gate interconnects 402a and the one or more second source / drain interconnects 406 increases, but a resistance of the one or more second source / drain interconnects 406 decreases.

[0042] The Fig. 7A-7C show top views of some further illustrative examples of an integrated chip with a disclosed high-performance transistor device at various heights above a substrate.

[0043] Fig. 7A shows a top view 700 of the integrated chip taken at a first elevation above a substrate. As shown in the top view 700, an isolation region 108 extends around an active region 110. A gate structure 112 includes a base region 112b disposed above the isolation region 108 and one or more gate extension fingers 112e extending laterally outward from a sidewall of the base region 112b along a first direction 124 and beyond opposite sides of the active region 110. One or more source contacts 116 and one or more drain contacts 118 are disposed in the active region 110. In some embodiments, the one or more source contacts 116 and / or the one or more drain contacts 118 may have a length 702 measured along the first direction 124.In some embodiments, the length 702 may be in a range of less than about 600 µm, less than about 500 µm, or other similar values. In some embodiments, one or more of the one or more source contacts 116 have a first width 704 measured along a second direction 126, and one or more of the one or more drain contacts 118 have a second width 706 measured along the second direction 126. In some embodiments, the first width 704 may be greater than the second width 706. In some embodiments, the first width 704 may be less than about 600 µm, less than about 500 µm, or other similar values. In some embodiments, the second width 706 may be less than about 300 µm, less than about 200 µm, or other similar values.

[0044] Fig. 7B shows a top view 708 of the integrated chip taken at a second height above the substrate. As shown in the top view 708, a first interconnect layer extends over the one or more source contacts (e.g., 116 of Fig. 7A), the one or more drain contacts (e.g. 118 of Fig. 7A) and the gate structure (e.g. 112 of Fig. 7A). The first interconnect layer includes a first gate interconnect 402a over the gate structure and a first source / drain interconnect 402b over the one or more source contacts and the one or more drain contacts. The first source / drain interconnect 402b has a third width 710 over the one or more source contacts and a fourth width 712 over the one or more drain contacts, measured along the second direction 126. In some embodiments, the third width 710 may be less than about 600 µm, less than about 500 µm, less than about 300 µm, or other similar values. In some embodiments, the fourth width 712 may be less than about 300 µm, less than about 200 µm, or other similar values.

[0045] Fig. 7C shows a top view 714 of the integrated chip taken at a third height above the substrate. As shown in the top view 714, a second interconnect layer is located above the first interconnect layer. The second interconnect layer includes second source / drain interconnects 406 above the first source / drain interconnects 402b. The second source / drain interconnects 406 have a fifth width 716 directly above the one or more source contacts and a sixth width 718 directly above the one or more drain contacts, measured along a second direction 126. In some embodiments, the fifth width 716 may be less than about 600 μm, less than about 500 μm, less than about 300 μm, or other similar values. In some embodiments, the sixth width 718 may be less than about 300 µm, less than about 200 µm, or other similar values.The second interconnect layer further includes a second gate interconnect 720 over the first gate interconnects (e.g., 402a of FIG. Fig. 7B) and the base area (e.g. 112b of Fig. 7A). The second gate interconnect 720 is connected to the first gate interconnects by one or more interconnect vias 404.

[0046] Fig. 8A shows a three-dimensional view of some further embodiments of an integrated chip 800 having a high-performance transistor device with a low gate resistance.

[0047] The integrated chip 800 includes an isolation region 108 disposed in a substrate 101 and enclosing an active region 110. A gate structure 112 is disposed above the substrate 101. The gate structure 112 includes a base region 112b and one or more gate extension fingers 112e extending laterally outward from a sidewall of the base region 112b along a first direction 124. The one or more gate extension fingers 112e separate one or more source contacts 116 and one or more drain contacts 118 located above the active region 110. In some embodiments, the one or more source contacts 116 and / or the one or more drain contacts 118 are separated from each other along a second direction 126 that is perpendicular to the first direction 124.In some embodiments, the one or more source contacts 116 and / or the one or more drain contacts 118 each comprise discrete source contact segments and / or drain contact segments separated along the first direction 124.

[0048] A first interconnect layer is disposed over the substrate 101. The first interconnect layer includes first gate interconnects 402a connected to the gate structure 112 through a first plurality of conductive contacts 120 arranged to extend a majority of a length of the one or more gate extension fingers 112e. The first interconnect layer further includes first source / drain interconnects 402b connected to the one or more source contacts 116 and the one or more drain contacts 118 through a second plurality of conductive contacts 304. The first source / drain interconnects 402b have discrete parts 402b1-402b2 (e.g., source / drain interconnect parts 402b1-402b2) that are aligned along the first direction 124 and that are separated from each other by the first gate interconnects 402a.A second interconnect layer is disposed over the first interconnect layer and includes second source / drain interconnects 406 connected to the first source / drain interconnects 402b through a plurality of interconnect vias 404. The second source / drain interconnects 406 extend contiguously beyond the discrete portions 402b1-402b2 of the first source / drain interconnects 402b and over the first gate interconnects 402a.

[0049] In some embodiments, the first gate interconnects 402a include first gate interconnect segments 402a1 extending along the second direction 126 and second gate interconnect segments 402a2 extending along the first direction 124. The second gate interconnect segments 402a2 are connected to opposite ends of the first gate interconnect segments 402a1. The first gate interconnect segments 402a1 extend in the second direction 126 between outermost ones of the one or more gate extension fingers 112e. In some embodiments, the first gate interconnect segments 402a1 extend between the discrete portions 402b1-402b2 of the first source / drain interconnects 402b.For example, in some embodiments, the first gate interconnect segments 402a1 may extend between a first source / drain interconnect portion 402b1 disposed over a first source contact segment and a second source / drain interconnect portion 402b2 disposed over a second source contact segment.

[0050] In some embodiments, the active region 110 may extend continuously in the first direction 124 beyond the first gate interconnect segments 402a1, while in other embodiments, the isolation region 108 may extend beneath the first gate interconnect segments 402a1 to divide the active region 110 into a plurality of discrete active subregions. The first gate interconnect segments 402a1 contact one of the first plurality of conductive contacts 120 on different ones of the one or more gate extension fingers 112e. The second gate interconnect segments 402a2 extend along an outer perimeter of the gate structure 112 and connect the first gate interconnect segments 402a1 to a base gate interconnect segment 402a3 located thereabove and connected to the base region 112b of the gate structure 112.By connecting the first gate interconnect segments 402a1 to the base gate interconnect segment 402a3, the first gate interconnects 402a may provide an alternative path for current to flow to different parts of the one or more gate extension fingers 112e, thereby keeping a resistance of a relatively long gate extension finger (e.g., a gate extension finger with a length greater than about 500 µm, greater than about 750 µm, etc.) relatively low. Furthermore, since the first gate interconnect segments 402a1 are located outside the gate structure 112, the first gate interconnect segments 402a1 may have a greater width than gate interconnects directly above the one or more gate extension fingers 112e (e.g., as shown in FIG. Fig. 4A), thereby further reducing a resistance of the one or more gate extension fingers 112e.

[0051] Fig. 8B shows a graph 808 illustrating some example embodiments of a gate extension finger resistance 810 (shown on the y-axis) as a function of a gate extension finger length (shown on the x-axis). As shown in graph 808, the resistance 810 drops by about 45% or more as a gate extension finger length increases from about 150 μm to about 750 μm. For example, the resistance 810 drops from about 3.9 Ω at a length of 150 μm to about 1.98 Ω at a length of 750 μm.

[0052] Fig. 9A shows a top view 900 of some further embodiments of an integrated chip with a disclosed high-performance transistor device. Fig. 9B-9E show sectional views of the integrated chip of Fig. 9A, which were created using different cross-sectional lines. Fig. 9B shows a sectional view 902 taken along the line AA' of Fig. 9A has been created, Fig. Figure 9C shows a sectional view 904 taken along the line BB' of Fig. 9A has been created, Fig. 9D shows a sectional view 906 taken along the line CC' of Fig. 9A has been created, and Fig. 9E shows a sectional view 908 taken along the line DD' of Fig. 9A. It should be understood that the plan view 900 of Fig. 9A does not show the upper interconnects to simplify the top view.

[0053] The integrated chip includes an isolation region 108 disposed in a substrate 101. The isolation region 108 extends along a closed and uninterrupted path enclosing an active region 110 in the substrate 101. A gate structure 112 is disposed above the substrate 101. The gate structure 112 includes a base region 112b and one or more gate extension fingers 112e extending laterally outward from a sidewall of the base region 112b along a first direction 124. The one or more gate extension fingers 112e separate one or more source contacts 116 and one or more drain contacts 118 located above the active region 110. In some embodiments, the one or more source contacts 116 and / or the one or more drain contacts 118 are separated from each other along a second direction 126 that is perpendicular to the first direction 124.

[0054] A first interconnect layer is disposed in a dielectric structure 132 above the substrate 101. The first interconnect layer includes one or more first gate interconnects 402a connected to the gate structure 112 through a first plurality of conductive contacts 120, and one or more first source / drain interconnects 402b connected to the one or more source contacts 116 and / or the one or more drain contacts 118 through a second plurality of conductive contacts 304. A second interconnect layer is disposed in the dielectric structure 132 above the first interconnect layer.The second interconnect layer includes one or more second source / drain interconnects 406 connected to the one or more first source / drain interconnects 402b by a plurality of interconnect vias 404, and a second gate interconnect 720 connected to the one or more first gate interconnects 402a by a plurality of interconnect vias 404.

[0055] It should be understood that in various embodiments, a width of the one or more second source / drain interconnects 406 may vary along the second direction 126. Fig. For example, FIG. 10A shows a cross-sectional view 1000 of some illustrative examples of an integrated chip having one or more second source / drain interconnects 406 with a relatively small width along a second direction. As shown in the cross-sectional view 1000, the one or more second source / drain interconnects 406 are laterally separated from an outermost sidewall of the one or more first gate interconnects 402a by a non-zero distance 1002. Because the one or more second source / drain interconnects 406 are laterally separated from the one or more first gate interconnects 402a, a capacitance between the one or more first gate interconnects 402a and the one or more second source / drain interconnects 406 decreases, but a resistance of the one or more second source / drain interconnects 406 increases.

[0056] Fig. 10B shows a cross-sectional view 1004 of some embodiments of an integrated chip having one or more second source / drain interconnects 406 with a relatively large width along the second direction 126. As shown in the cross-sectional view 1004, the one or more second source / drain interconnects 406 laterally overlap the one or more first gate interconnects 402a via a non-zero pitch 1006. Because the one or more second source / drain interconnects 406 laterally overlap the one or more first gate interconnects 402a, a capacitance between the one or more first gate interconnects 402a and the one or more second source / drain interconnects 406 increases, but a resistance of the one or more second source / drain interconnects 406 decreases.

[0057] The Fig. 11A-11C show top views of some further illustrative examples of an integrated chip with a disclosed high-performance transistor device at various heights above a substrate.

[0058] Fig. 11A shows a top view 1100 of the integrated chip taken at a first elevation above a substrate. As shown in the top view 1100, an isolation region 108 extends around an active region 110. A gate structure 112 includes a base region 112b disposed above the isolation region 108 and one or more gate extension fingers 112e extending outward from the base region 112b along a first direction 124 and beyond opposite sides of the active region 110. One or more source contacts 116 and one or more drain contacts 118 are disposed in the active region 110. In some embodiments, the one or more source contacts 116 and the one or more drain contacts 118 may have a length 1102 measured along the first direction 124.In some embodiments, the length 1102 may be less than about 600 µm, less than about 500 µm, or other similar values. In some embodiments, one or more of the one or more source contacts 116 have a first width 1104 measured along a second direction 126, and one or more of the one or more drain contacts 118 have a second width 1106 measured along the second direction 126. In some embodiments, the first width 1104 may be greater than the second width 1106. In some embodiments, the first width 1104 may be less than about 600 µm, less than about 500 µm, or other similar values. In some embodiments, the second width 1106 may be less than about 300 µm, less than about 200 µm, or other similar values.

[0059] Fig. 11B shows a top view 1108 of the integrated chip taken at a second height above the substrate. As shown in the top view 1108, a first interconnect layer extends over the one or more source contacts (e.g., 116 of Fig. 11A), the one or more drain contacts (e.g. 118 of Fig. 11A) and the gate structure (e.g. 112 of Fig. 11A). The first interconnect layer includes one or more first gate interconnects 402a directly above the gate extension fingers and a first source / drain interconnect 402b directly above the one or more source contacts and the one or more drain contacts. The one or more first gate interconnects 402a include first gate interconnect segments 402a1 having a third width 1110, second gate interconnect segments 402a2 having a fourth width 1112, and a base gate interconnect segment 402a3 having a fifth width 1114. In some embodiments, the third width 1110, the fourth width 1112, and the fifth width 1114 are less than or equal to about 300 µm, less than about 200 µm, or have other similar values. In some embodiments, the third width 1110, the fourth width 1112, and the fifth width 1114 may be greater than a width of the gate extension finger (e.g., 112e of Fig. 11A). In some embodiments, the third width 1110 may be less than or equal to the fourth width 1112 and / or the fifth width 1114.

[0060] Fig. 11C shows a top view 1116 of the integrated chip created at a third height above the substrate. As shown in the top view 1116, a second interconnect layer is located above the first source / drain interconnects 402b. The second interconnect layer includes second source / drain interconnects 406 above the first source / drain interconnects 402b and a second gate interconnect 720 above the one or more first gate interconnects (e.g., 402a of Fig. 11B) and the base area (e.g. 112b of Fig. 11A). The second source / drain interconnects 406 have a sixth width 1118 outside the active area, a seventh width 1120 directly above the one or more drain contacts, and an eighth width 1122 directly above the one or more source contacts. In some embodiments, the sixth width 1118, the seventh width 1120, and the eighth width 1122 are less than or equal to about 300 µm, less than about 200 µm, or have other similar values.

[0061] In some embodiments, a first gap 1124 may extend along the first direction 124 between first gate interconnects 402a and second source / drain interconnects 406. In some embodiments, the first gap 1124 may have a pitch of less than or equal to about 100 µm, less than about 75 µm, or other similar values. In some embodiments, a second gap 1126 may extend along the second direction 126 between first gate interconnects 402a and second source / drain interconnects 406. In some embodiments, the second gap 1126 may have a pitch of less than or equal to about 100 µm, less than about 75 µm, or other similar values.

[0062] The Fig. 12A-16C show cross-sectional views 1200-1606 of some embodiments of a method for fabricating an integrated chip having a high-performance transistor device with a low gate resistance. Fig. 12A-16C are described for a method, but it should be understood that the structures shown in these figures are not limited to the method, but can be used as structures stand-alone and independent of the method.

[0063] As shown in plan view 1200 from Fig. 12A, sectional view 1202 of Fig. 12B (drawn along line A-A') and section view 1208 of Fig. 12C (taken along line B-B'), a substrate 101 is fabricated. In some embodiments, the substrate 101 may be fabricated by forming one or more epitaxial layers over a base substrate 102. In some embodiments, the one or more epitaxial layers may include an active layer 104 formed over the base substrate 102 and a barrier layer 106 formed over the active layer 104. In some further embodiments, a buffer layer (not shown) may be formed on the base substrate 102 prior to forming the active layer 104 to mitigate lattice mismatch between the base substrate 102 and the active layer 104.

[0064] In various embodiments, the base substrate 102 may comprise silicon, silicon carbide, sapphire, or the like. In some embodiments, the active layer 104 may comprise GaN, GaAs, InGaAs, or the like. In various embodiments, the barrier layer 106 may comprise AlGaN, AlN, InAlGaN, InAlAs, InAlGaAs, InAlGaP, SiGe, or the like. In some embodiments, the active layer 104 and the barrier layer 106 may be deposited on the base substrate 102 using chemical vapor deposition processes, physical vapor deposition processes, or the like.

[0065] After fabricating the substrate 101, an isolation region 108 is formed in the substrate 101 such that it extends in a closed and uninterrupted path enclosing an active region 110. The active region 110 extends continuously along a first direction 124 and along a second direction 126 perpendicular to the first direction 124. In some embodiments, the isolation region 108 may be formed by selectively implanting ions 1204 into the substrate 101 according to a mask 1206 (e.g., photoresist). The implanted ions 1204 damage the layers of the substrate 101. The damage to the layers of the substrate 101 prevents a 2DEG 130 from extending into the isolation region 108.

[0066] As shown in the top view 1300 of Fig. 13A, the sectional view 1302 of Fig. 13B (drawn along line A-A') and section view 1304 of Fig. 13C (taken along line B-B'), one or more source contacts 116 and one or more drain contacts 118 are formed over the substrate 101 and in the active area 110. The one or more source contacts 116 are separated from the one or more drain contacts 118 along the second direction 126. In some embodiments, the one or more source contacts 116 may include discrete source contact segments 116a-116c separated from each other along the first direction 124, and the one or more drain contacts 118 may include discrete drain contact segments 118a-118c separated from each other along the first direction 124. In these embodiments, adjacent ones of the discrete source contact segments and / or drain contact segments may have sidewalls separated by a non-zero pitch 302 located directly above the active area 110.

[0067] In some embodiments, the one or more source contacts 116 and the one or more drain contacts 118 may be formed by depositing a first conductive material over the substrate 101. In some embodiments (not shown), the substrate 101 may be etched before the first conductive material is deposited so that the first conductive material extends into one or more source / drain contact recesses in the substrate 101. The first conductive material is then patterned to define the one or more source contacts 116 and the one or more drain contacts 118. In various embodiments, the first conductive material may comprise a metal, such as aluminum, tungsten, titanium, cobalt, or the like.

[0068] As shown in section view 1400 of Fig. 14A, the sectional view 1402 of Fig. 14B (taken along the line A-A') and the section view 1406 of Fig. 14C (taken along line B-B'), a gate structure 112 is formed over the substrate 101 and between adjacent ones of the one or more source contacts 116 and the one or more drain contacts 118. In some embodiments, the gate structure 112 may be formed to include a base region 112b extending along the second direction 126 and one or more gate extension fingers 112e extending outward from a sidewall of the base region 112b along the first direction 124. In some embodiments, the one or more gate extension fingers 112e have a length 114 that extends in the first direction 124 beyond opposite edges of the active area 110.

[0069] In various embodiments, the gate structure 112 may be formed by depositing a second conductive material (e.g., polysilicon, a metal, etc.) over the substrate 101 and then patterning the second conductive material to define the gate structure 112. In some embodiments (not shown), the substrate 101 may be etched prior to depositing the second conductive material so that the second conductive material extends into one or more gate recesses in the substrate 101.

[0070] In some embodiments, after forming the gate structure 112, a first inter-level dielectric (ILD) layer 132a may be formed over the substrate 101 to cover the gate structure 112. The first ILD layer 132a is then patterned to form contact openings 1404 exposing the one or more gate extension fingers 112e at a plurality of positions separated along the first direction 124. In some embodiments, the first ILD layer 132a may comprise a dielectric material (e.g., silicon oxide, borosilicate glass, or the like) formed using a deposition process (e.g., a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, sputtering, a plasma enhanced CVD (PE-CVD) process, or the like).

[0071] Conductive contacts are formed in the contact openings 1404. The conductive contacts include a first plurality of conductive contacts 120 formed on the gate structure 112 and a second plurality of conductive contacts 304 formed on the one or more source contacts 116 and / or the one or more drain contacts 118. The first plurality of conductive contacts 120 are separated along the first direction 124 and extend over a majority of the length 114 of the one or more gate extension fingers 112e (e.g., 50% of the length 114, 75% of the length 114, 90% of the length 114, or other similar values). In some embodiments, the first plurality of conductive contacts 120 and the second plurality of conductive contacts 304 may be formed using a damascene process. In some of these embodiments, the contact openings 1404 are filled with a third conductive material (e.g.,Tungsten, copper, and / or aluminum). A first planarization process (e.g., a chemical mechanical planarization (CMP) process) is then performed to remove excess portions of the third conductive material over the first ILD layer 132a.

[0072] As shown in section view 1500 of Fig. 15A, sectional view 1502 of Fig. 15B (drawn along line A-A') and section view 1504 of Fig. 15C (taken along line B-B'), a first interconnect layer is formed over the first plurality of conductive contacts 120. The first interconnect layer includes one or more first gate interconnects 402a formed over the one or more gate extension fingers 112e. The one or more first gate interconnects 402a have bottom surfaces directly connected to two or more of the first plurality of conductive contacts 120 on the same gate extension finger. The one or more first gate interconnects 402a provide another path for current to flow to different portions of the one or more gate extension fingers 112e, thereby causing a resistance of the one or more gate extension fingers 112e to be reduced.The first interconnect layer further includes one or more first source / drain interconnects 402b formed over the one or more source contacts 116 and / or the one or more drain contacts 118. The one or more first source / drain interconnects 402b have bottom surfaces directly connected to the second plurality of conductive contacts 304.

[0073] In some embodiments, the first interconnect layer may be formed using a damascene process. In some embodiments, a second ILD layer 132b is formed over the first ILD layer 132a. The second ILD layer 132b is etched to form openings, which are then filled with a fourth conductive material (e.g., tungsten, copper, and / or aluminum). A second planarization process (e.g., a CMP process) is then performed to remove excess portions of the fourth conductive material over the second ILD layer 132b.

[0074] As shown in section view 1600 of Fig. 16A, sectional view 1602 of Fig. 16B (drawn along line A-A') and section view 1604 of Fig. 16C (taken along line B-B'), a plurality of interconnect vias 404 are formed on the one or more first gate interconnects 402a and the one or more first source / drain interconnects 402b. A second interconnect layer, including one or more second source / drain interconnects 406 and a second gate interconnect 720, is formed on the plurality of interconnect vias 404. In some embodiments, the plurality of interconnect vias 404 and / or the second interconnect layer may be formed using a damascene process. In some embodiments, a third ILD layer 132c is formed over the second ILD layer 132b. The third ILD layer 132c is etched to form openings, which are then filled with a fifth conductive material (e.g., tungsten, copper, and / or aluminum). A third planarization process (e.g.,a CMP process) is subsequently performed to remove excess portions of the fifth conductive material over the third ILD layer 132c.

[0075] The Fig. 17A-21C show cross-sectional views 1700-2106 of some further embodiments of a method for manufacturing an integrated chip having a high performance transistor device with a low gate resistance.

[0076] As shown in the top view 1700 of Fig. 17A, the sectional view 1702 of Fig. 17B (drawn along the line A-A') and the section view 1704 of Fig. 17C (taken along line B-B'), a substrate 101 is fabricated by forming one or more epitaxial layers over a base substrate 102. In some embodiments, the one or more epitaxial layers may include an active layer 104 (e.g., comprising GaN, GaAs, or the like) formed over the base substrate 102 and a barrier layer 106 (e.g., comprising AlGaN, AlGaAs, or the like) formed over the active layer 104.

[0077] After fabricating the substrate 101, an isolation region 108 is formed in the substrate 101 to extend in a closed and uninterrupted path enclosing an active region 110. The active region 110 extends contiguously along a first direction 124 and along a second direction 126 perpendicular to the first direction 124.

[0078] As shown in the top view 1800 from Fig. 18A, the sectional view 1802 of Fig. 18B (drawn along the line A-A') and the section view 1804 of Fig. 18C (taken along line B-B'), one or more source contacts 116 and one or more drain contacts 118 are formed over the substrate 101 and in the active area 110. In some embodiments, the one or more source contacts 116 may each comprise discrete source contact segments separated along the first direction 124, and the one or more drain contacts 118 may each comprise discrete drain contact segments separated along the first direction 124.

[0079] As shown in the sectional view from 1900 by Fig. 19A, the sectional view 1902 of Fig. 19B (drawn along the line A-A') and the sectional view 1904 of Fig. 19C (taken along line B-B'), a gate structure 112 is formed over the substrate 101 and between adjacent ones of the one or more source contacts 116 and the one or more drain contacts 118. In some embodiments, the gate structure 112 may be formed to include a base region 112b extending along the second direction 126 and one or more gate extension fingers 112e extending outward from sidewalls of the base region 112b along the first direction 124. In some embodiments, the one or more gate extension fingers 112e have a length 114 that extends in the first direction 124 beyond opposite edges of the active area 110.

[0080] In some embodiments, after forming the gate structure 112, a first ILD layer 132a may be formed over the substrate 101 to cover the gate structure 112. The first ILD layer 132a is then patterned to form contact openings 1404 exposing the one or more gate extension fingers 112e at a plurality of positions separated along the first direction 124. Conductive contacts are formed in the contact openings 1404. The conductive contacts include a first plurality of conductive contacts 120 formed on the gate structure 112 and a second plurality of conductive contacts 304 formed on the one or more source contacts 116 and / or the one or more drain contacts 118.The first plurality of conductive contacts 120 are separated along the first direction 124 and extend over a majority of the length 114 of the one or more gate extension fingers 112e (e.g., 50% of the length 114, 75% of the length 114, 90% of the length 114, or other similar values).

[0081] As shown in the sectional view 2000 of Fig. 20A, the sectional view 2002 of Fig. 20B (drawn along line A-A') and the sectional view 2004 of Fig. 20C (taken along line B-B'), a first interconnect layer is formed over the first plurality of conductive contacts 120 and the second plurality of conductive contacts 304. The first interconnect layer includes one or more first gate interconnects 402a. The one or more first gate interconnects 402a include first gate interconnect segments 402a1 extending along the second direction 126 and second gate interconnect segments 402a2 extending along the first direction 124 and connected to the first gate interconnect segments 402a1. The first gate interconnect segments 402a1 extend between the discrete source contact segments and / or drain contact segments. The first gate interconnect segments 402a1 contact one of the first plurality of conductive contacts 120 on different ones of the one or more gate extension fingers 112e.The second gate interconnect segments 402a2 extend along an outer perimeter of the gate structure 112 and connect the first gate interconnect segments 402a1 to a base gate interconnect segment 402a3 located above and connected to the base region 112b of the gate structure 112. By connecting the first gate interconnect segments 402a1 to the base gate interconnect segment 402a3, the first gate interconnects 402a can provide an alternative path for current to flow to different parts of the gate extension fingers, thereby keeping a resistance of a relatively long gate extension finger (e.g., a gate extension finger with a length greater than about 500 µm, greater than about 750 µm, etc.) relatively low.

[0082] The first interconnect layer may further include one or more first source / drain interconnects 402b disposed above the one or more source contacts 116 and / or the one or more drain contacts 118. The one or more first source / drain interconnects 402b have bottom surfaces directly connected to the second plurality of conductive contacts 304. In some embodiments, the first plurality of conductive contacts 120, the second plurality of conductive contacts 304, and / or the first interconnect layer may be formed using a damascene process in a second ILD layer 132b.

[0083] As shown in section view 2100 of Fig. 21A, the sectional view 2102 of Fig. 21B (drawn along the line A-A') and the section view 2104 of Fig. 21C (taken along line B-B'), a plurality of interconnect vias 404 are formed over the one or more first gate interconnects 402a and the one or more first source / drain interconnects 402b. A second interconnect layer, including one or more second source / drain interconnects 406 and a second gate interconnect 720, is formed on the plurality of interconnect vias 404. In some embodiments, the plurality of interconnect vias 404 and / or the second interconnect layer may be formed using a damascene process in a third ILD layer 132c.

[0084] Fig. 22 shows a flow diagram of some embodiments of a method 2200 for manufacturing an integrated chip having a high performance transistor device with a low gate resistance.

[0085] While the disclosed method 2200 is illustrated and described herein as a series of steps or events, it should be understood that the illustrated order of these steps or events should not be construed in a limiting sense. For example, some steps may occur in different orders and / or concurrently with other steps or events than those illustrated and / or described herein. Furthermore, not all of the illustrated steps need to implement one or more aspects or embodiments of the description, and one or more of the steps described herein may be performed in one or more separate steps and / or phases.

[0086] In a step 2202, one or more epitaxial layers may be formed over a base substrate to produce a substrate. Fig. 12A-12C show some embodiments corresponding to step 2202. The Fig. 17A-17C show some alternative embodiments corresponding to step 2202.

[0087] In a step 2204, an isolation region is formed in the substrate to define an active region enclosed by the isolation region. Fig. 12A-12C show some embodiments corresponding to step 2204. The Fig. 17A-17C show some alternative embodiments corresponding to step 2204.

[0088] In a step 2206, one or more source contacts and one or more drain contacts are formed over the substrate and in the active region. Fig. 13A-13C show some embodiments corresponding to step 2206. The Fig. 18A-18C show some alternative embodiments corresponding to step 2206.

[0089] In a step 2208, a gate structure is fabricated to include a gate extension finger extending outward from a sidewall of a base region to a length that extends beyond opposite sides of the active region. Fig. 14A-14C show some embodiments corresponding to step 2208. The Fig. 19A-19C show some alternative embodiments corresponding to step 2208.

[0090] In a step 2210, a first plurality of conductive contacts are formed at different positions on the gate structure. The different positions extend over a large part of the length of the gate extension finger. Fig. 14A-14C show some embodiments corresponding to step 2210. The Fig. 19A-19C illustrate some alternative embodiments corresponding to step 2210. In some embodiments, a first plurality of conductive contacts may be formed according to steps 2212-2216. In these embodiments, in step 2212, a first ILD layer may be formed over the substrate and the gate structure, in step 2214, the first ILD layer may be patterned to form contact openings exposing various positions on the gate extension finger, and in step 2216, a conductive material may be formed in the contact openings.

[0091] In a step 2218, a first interconnect layer is formed, which includes one or more first gate interconnects connected to the first plurality of conductive contacts. Fig. 15A-15C show some embodiments corresponding to step 2218. The Fig. 20A-20C show some alternative embodiments corresponding to step 2218.

[0092] In a step 2220, a second interconnect layer is formed over the first interconnect layer. Fig. 16A-16C show some embodiments corresponding to step 2220. The Fig. 21A-21C show some alternative embodiments corresponding to step 2220.

[0093] Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising a transistor device with a gate structure including a base region and a gate extension finger protruding outwardly from a sidewall of the base region along a first direction to a length that extends beyond opposite sides of an active area in the substrate. A first plurality of conductive contacts are disposed on the gate extension finger and are separated along the first direction to extend over a majority of the length of the gate extension finger. By separating the plurality of conductive contacts over the length of the gate extension finger, a resistance of the gate extension finger may be reduced, thereby improving the performance of the transistor device.

[0094] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises: an isolation region disposed in a substrate and enclosing an active region; a gate structure having a base region and a gate extension finger extending outwardly from a sidewall of the base region along a first direction beyond opposite sides of the active region; a source contact disposed in the active region; a drain contact disposed in the active region and separated from the source contact by the gate extension finger; and a first plurality of conductive contacts disposed on the gate structure and separated along the first direction, the first plurality of conductive contacts being separated by spaces above the gate extension finger.The integrated chip includes a second gate extension finger protruding outwardly from the sidewall of the base region and separated from the gate extension finger along a second direction perpendicular to the first direction; and a gate interconnect connected to the gate extension finger, the second gate extension finger, and the base region through the first plurality of conductive contacts, and extending in the second direction between a first contact of the first plurality of conductive contacts disposed on the gate extension finger and a second contact of the first plurality of conductive contacts disposed on the second gate extension finger. In some embodiments, the substrate comprises: a base substrate; a first III-V semiconductor material on the base substrate; and a second III-V semiconductor material on the first III-V semiconductor material.In some embodiments, the base region is disposed directly above the isolation region. In some embodiments, the integrated chip further comprises a gate interconnect disposed above the gate extension finger and having a bottom surface facing the substrate, the bottom surface contacting the first plurality of conductive contacts located on the gate extension finger and the base region. In some embodiments, the source contact comprises a plurality of discrete source contact segments having sidewalls separated by one or more non-zero pitches along the first direction.In some embodiments, the integrated chip further comprises: a second gate extension finger protruding outwardly from the sidewall of the base region and separated from the gate extension finger along a second direction perpendicular to the first direction, wherein the first plurality of conductive contacts extends over a majority of a length of the second gate extension finger; and a second source contact disposed in the active region, wherein the second gate extension finger extends over the active region between the drain contact and the second source contact.In some embodiments, the integrated chip further comprises: a gate interconnect extending in the second direction between a first contact of the first plurality of conductive contacts disposed on the gate extension finger and a second contact of the first plurality of conductive contacts disposed on the second gate extension finger, the gate interconnect being connected to the base region of the gate structure by a third contact of the first plurality of conductive contacts located on the base region.In some embodiments, the integrated chip further comprises: a gate interconnect having a first gate interconnect segment extending contiguously in the second direction between a first contact of the first plurality of conductive contacts disposed on the gate extension finger and a second contact of the first plurality of conductive contacts disposed on the second gate extension finger; a second gate interconnect segment connected to the first gate interconnect segment and extending in the first direction; and a base gate interconnect segment connected to the second gate interconnect segment and connected to a third contact of the first plurality of conductive contacts disposed on the base region.In some embodiments, the first gate interconnect segment is disposed between sidewalls of the plurality of discrete source contact segments. In some embodiments, the integrated chip further comprises: a first source / drain interconnect segment disposed over a first source contact segment of the plurality of discrete source contact segments; a second source / drain interconnect segment disposed over a second source contact segment of the plurality of discrete source contact segments; and a gate interconnect disposed over the gate extension finger and having a bottom surface facing the substrate and contacting the first plurality of conductive contacts disposed on the gate extension finger and the base region, wherein the gate interconnect is located directly between the first source / drain interconnect segment and the second source / drain interconnect segment.In some embodiments, the gate extension finger has a length of more than 500 micrometers.

[0095] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises: an isolation region disposed in a substrate and defining an active area in the substrate; a gate structure having a base region and a plurality of gate extension fingers, the plurality of gate extension fingers each protruding outwardly from a sidewall of the base region along a first direction such that their length extends beyond opposite edges of the active area; a first source contact and a second source contact disposed in the active area and separated along a second direction perpendicular to the first direction; a drain contact disposed in the active area between the first source contact and the second source contact,wherein the drain contact is separated from the first source contact and the second source contact by the plurality of gate extension fingers; and a plurality of conductive contacts arranged along a majority of the length of the plurality of gate extension fingers. The integrated chip includes a gate interconnect extending contiguously in the second direction between two extension fingers of the plurality of gate extension fingers.wherein the gate interconnect directly contacts two or more of the plurality of conductive contacts on the two extension fingers of the plurality of gate extension fingers and a conductive contact on the base region. In some embodiments, the length of the plurality of gate extension fingers is greater than or equal to about 750 micrometers. In some embodiments, the plurality of conductive contacts are separated by substantially equal distances. In some embodiments, the first source contact comprises a plurality of discrete source contact segments, wherein adjacent ones of the plurality of discrete source contact segments have sidewalls facing each other; and the plurality of gate extension fingers extend beyond the sidewalls of the plurality of discrete source contact segments. In some embodiments, the active region comprises a plurality of active subregions,which are separated from each other along the first direction, wherein the plurality of gate extension fingers extend beyond two or more of the active portions. In some embodiments, the first source contact comprises a plurality of discrete source contact segments aligned along the second direction, wherein the plurality of discrete source contact segments are located in one of the plurality of active portions. In some embodiments, the integrated chip further comprises: a gate interconnect extending contiguously in the second direction between outermost ones of the plurality of gate extension fingers, wherein the gate interconnect directly contacts two or more of the plurality of conductive contacts on the plurality of gate extension fingers. In some embodiments, the integrated chip further comprises a gate interconnect,extending contiguously in the first direction directly above a first gate extension finger of the plurality of gate extension fingers, wherein the gate interconnect is connected to two or more of the plurality of conductive contacts located on the first gate extension finger.

[0096] In still other embodiments, the present disclosure relates to a method of manufacturing an integrated chip. The method comprises the following steps: forming an isolation region in a substrate to define an active area; forming a first conductive material on the active area; patterning the first conductive material to form one or more source contacts and one or more drain contacts in the active area;Fabricating a gate structure having a base region and a gate extension finger extending outward from a sidewall of the base region along a first direction to directly between the one or more source contacts and the one or more drain contacts, and a second gate extension finger extending outward from the sidewall of the base region and separated from the gate extension finger along a second direction perpendicular to the first direction; fabricating a first dielectric layer over the substrate; patterning the first dielectric layer to form contact openings exposing the gate extension finger and the second gate extension finger at a plurality of positions separated along the first direction; fabricating a second conductive material in the contact openings to form a plurality of conductive contacts;and forming a gate interconnect extending in the second direction between a first contact of the plurality of conductive contacts disposed on the gate extension finger and a second contact of the plurality of conductive contacts disposed on the second gate extension finger and connected to a third contact of the plurality of conductive contacts on the base region;

Claims

[1] Integrated chip (300, 400, 800) with: an isolation region (108) arranged in a substrate (101) and enclosing an active region (110); a gate structure (112) having a base region (112b) and a gate extension finger (112e) projecting outwardly from a sidewall of the base region (112b) along a first direction (124) beyond opposite sides of the active region (110); a source contact (116) disposed in the active region (110); a drain contact (118) disposed in the active region (110) and separated from the source contact (116) by the gate extension finger (112e); and a first plurality of conductive contacts (120) disposed on the gate structure (112) and separated along the first direction (124), the first plurality of conductive contacts (120) being separated by spaces overlying the gate extension finger (112e); a second gate extension finger (112e) projecting outwardly from the sidewall of the base region (112b) and separated from the gate extension finger (112e) along a second direction (126) perpendicular to the first direction (124), wherein the first plurality of conductive contacts (120) extends over a majority of a length (114, 702, 1102) of the second gate extension finger (112e); and a gate interconnect (402a) connected to the gate extension finger (112e), the second gate extension finger (112e), and the base region (112b) by the first plurality of conductive contacts (120) and extending in the second direction (126) between a first contact of the first plurality of conductive contacts (120) disposed on the gate extension finger (112e) and a second contact of the first plurality of conductive contacts disposed on the second gate extension finger (112e). [2] The integrated chip (300, 400, 800) of claim 1, wherein the substrate comprises: a base substrate (102); a first III-V semiconductor material on the base substrate (102); and a second III-V semiconductor material on the first III-V semiconductor material. [3] The integrated chip (300, 400, 800) of claim 1 or 2, wherein the base region (112b) is disposed directly above the isolation region (108). [4] The integrated chip (300, 400, 800) of any preceding claim, wherein the gate interconnect (402a) is disposed over the gate extension finger (112e) and has a bottom surface facing the substrate (101), the bottom surface contacting the first plurality of conductive contacts (120) located on the gate extension finger (112e) and the base region (112b). [5] The integrated chip (300, 400, 800) of any preceding claim, wherein the source contact (116) comprises a plurality of discrete source contact segments having sidewalls separated by one or more non-zero pitches along the first direction (124). [6] The integrated chip (300, 400, 800) of claim 5, further comprising: a second source contact disposed in the active region (110), wherein the second gate extension finger (112e) extends over the active region (110) between the drain contact (118) and the second source contact. [7] The integrated chip of any preceding claim, wherein the gate interconnect (402a) is connected to the base region (112b) of the gate structure (112) by a third contact of the first plurality of conductive contacts (120) located on the base region (112b). [8] The integrated chip (300, 400, 800) of claim 6, further comprising: a gate interconnect (402a) with: - a first gate interconnect segment (402a) extending contiguously in the second direction (126) between a first contact of the first plurality of conductive contacts (120) disposed on the gate extension finger (112e) and a second contact of the first plurality of conductive contacts (120) disposed on the second gate extension finger (112e); - a second gate interconnect segment (402a) connected to the first gate interconnect segment (402a) and extending in the first direction (124); and - a base gate interconnect segment (402a) connected to the second gate interconnect segment (402a) and connected to a third contact of the first plurality of conductive contacts (120) arranged on the base region (112b). [9] The integrated chip (300, 400, 800) of claim 8, wherein the first gate interconnect segment (402a) is disposed between sidewalls of the plurality of discrete source contact segments. [10] Integrated chip (300, 400, 800) according to one of claims 5 to 9, further comprising: a first source / drain interconnect segment disposed over a first source contact segment of the plurality of discrete source contact segments; a second source / drain interconnect segment disposed over a second source contact segment of the plurality of discrete source contact segments; and a gate interconnect (402a) disposed over the gate extension finger (112e) and having a bottom surface facing the substrate (101) and contacting the first plurality of conductive contacts (120) disposed on the gate extension finger (112e) and the base region (112b), the gate interconnect (402a) being located directly between the first source / drain interconnect segment and the second source / drain interconnect segment. [11] Integrated chip (300, 400, 800) according to one of the preceding claims, wherein the gate extension finger (112e) has a length (114, 702, 1102) of more than 500 micrometers. [12] Integrated chip (300, 400, 800) with: an isolation region (108) disposed in a substrate (101) and defining an active region (110) in the substrate (101); a gate structure (112) having a base region (112b) and a plurality of gate extension fingers (112e), the plurality of gate extension fingers (112e) each projecting outwardly from a sidewall of the base region (112b) along a first direction (124) such that their length (114, 702, 1102) extends beyond opposite edges of the active region (110); a first source contact and a second source contact disposed in the active region (110) and separated along a second direction (126) perpendicular to the first direction (124); a drain contact (118) disposed in the active region (110) between the first source contact and the second source contact, the drain contact (118) being separated from the first source contact and the second source contact by the plurality of gate extension fingers (112e); and a plurality of conductive contacts (120) arranged along a majority of the length (114, 702, 1102) of the plurality of gate extension fingers (112e), further comprising: a gate interconnect (402a) extending contiguously in the second direction (126) between two extension fingers (112e) of the plurality of gate extension fingers (112e), the gate interconnect (402a) directly contacting two or more of the plurality of conductive contacts (120) on the two of the extension fingers (112e) of the plurality of gate extension fingers (112e) and a conductive contact (120) on the base region (112b). [13] The integrated chip (300, 400, 800) of claim 12, wherein the length (114, 702, 1102) of the plurality of gate extension fingers (112e) is greater than or equal to about 750 micrometers. [14] The integrated chip (300, 400, 800) of claim 12 or 13, wherein the plurality of conductive contacts (120) are separated from each other by substantially equal distances. [15] Integrated chip (300, 400, 800) according to one of claims 12 to 14, wherein the first source contact (116) comprises a plurality of discrete source contact segments, adjacent ones of the plurality of discrete source contact segments having sidewalls facing each other; and wherein the plurality of gate extension fingers (112e) extend beyond the sidewalls of the plurality of discrete source contact segments. [16] The integrated chip (300, 400, 800) of any one of claims 12 to 15, wherein the active region (110) comprises a plurality of active sub-regions separated from each other along the first direction (124), wherein the plurality of gate extension fingers (112e) extend beyond two or more of the active sub-regions. [17] The integrated chip (300, 400, 800) of claim 16, wherein the first source contact (116) comprises a plurality of discrete source contact segments aligned along the second direction (126), the plurality of discrete source contact segments being located in one of the plurality of active portions. [18] The integrated chip (300, 400, 800) of any one of claims 12 to 17, wherein the gate interconnect (402a) extends continuously in the second direction between outermost ones of the plurality of gate extension fingers (112e). [19] Integrated chip (300, 400, 800) according to one of claims 12 to 18, further comprising: a gate interconnect (402a) extending contiguously in the first direction (124) directly over a first gate extension finger (112e) of the plurality of gate extension fingers (112e), the gate interconnect (402a) being connected to two or more of the plurality of conductive contacts (120) located on the first gate extension finger (112e). [20] A method for manufacturing an integrated chip (300, 400, 800) comprising the following steps: Forming an isolation region (108) in a substrate (101) to define an active region (110); Forming a first conductive material on the active region (110); Patterning the first conductive material to form one or more source contacts (116) and one or more drain contacts (118) in the active region (110); Producing a gate structure (112) having a base region (112b), a gate extension finger (112e) projecting outwardly from a sidewall of the base region (112b) along a first direction (124) to directly between the one or more source contacts (116) and the one or more drain contacts (118), and a second gate extension finger (112e) projecting outwardly from the sidewall of the base region (112b) and separated from the gate extension finger (112e) along a second direction (126) perpendicular to the first direction (124); forming a first dielectric layer over the substrate (101); Patterning the first dielectric layer to form contact openings (1404) exposing the gate extension finger (112e) and the second gate extension finger (112e) at a plurality of positions separated along the first direction (124); and Forming a second conductive material in the contact openings (1404) to form a plurality of conductive contacts (120); Producing a gate interconnect (402a) extending in the second direction (126) between a first contact of the plurality of conductive contacts (120) arranged on the gate extension finger (112e) and a second contact of the plurality of conductive contacts arranged on the second gate extension finger (112e) and connected to a third contact of the plurality of conductive contacts (120) on the base region (112b).

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