Packages with deep bond pads

Abstract

Package, comprising: a first die (2-1'), comprising: a first semiconductor substrate (5); integrated circuits (8) above and on a front side of the first semiconductor substrate (5); a plurality of dielectric layers (22, 24) over and on the front side of the first semiconductor substrate (5); a first deep bond pad (36A) that passes through the majority of dielectric layers (22, 24) and contacts the first semiconductor substrate (5); and a second deep bond pad (36B) that passes through the majority of dielectric layers (22, 24) and contacts the first semiconductor substrate (5); and a second die (2-2) above the first die (2-1), the second die having (2-2): a second semiconductor substrate (5); a third deep bond pad (36B) that touches the second semiconductor substrate (5), wherein the third deep bond pad (36B) is bonded to and physically in contact with the second deep bond pad (36B); and a first shallow potential-free bond pad (32) bonded to the first deep bond pad (36A).

Description

BACKGROUND

[0001] Hybrid bonding is a common bonding method for bonding two package components, such as wafers and dies, together. With hybrid bonding, high bond strength can be achieved without increasing the cost of forming the bonded package components.

[0002] A method is known from US patent 2021 / 0057309A1 in which two dies are bonded together by hybrid bonding. However, this method does not form bond pads that extend through a dielectric layer and are in contact with an underlying semiconductor substrate.

[0003] US 2021 / 0 257 333 A1 describes the bonding of two vias of different semiconductor structures.

[0004] Packages are known from US 2019 / 0385935 A1 in which two dies are bonded together by bonded bond pads, with a deep bond pad being bonded to a potential-free shallow bond pad. SUMMARY OF THE INVENTION

[0005] The present invention relates to a package according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of description. The Fig. Figures 1-9 show cross-sectional views of intermediate stages in the formation of a die according to some embodiments. The Fig. Figures 10-14 show cross-sectional views of some dies according to some embodiments which, although they do not correspond to the literal wording of the claim, contribute to its explanation, and which are based on the information in the Fig. The processes shown in 1 - 9 were trained. Fig. Figure 15 shows a die stack according to some embodiments which, although they do not correspond to the literal wording of the claim, contribute to its explanation and which is formed by hybrid bonding. The Fig. Figure 16 shows the bonded dies according to some embodiments which, although they do not correspond to the literal wording of the claim, contribute to its explanation. Figure 17 shows the bonded dies according to some embodiments of the invention. The Fig. Figures 18-21 show top views of some bond pads according to some embodiments. Fig. Figure 22 shows a process flow for forming a package according to some embodiments. DETAILED DESCRIPTION

[0007] The following invention provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, only examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature, as described below, may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features do not have to be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0008] Furthermore, spatially relative terms such as "below," "below," "above," "above," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to another, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0009] Device dies with deep bond pads and the method for forming them are provided. Packages with bonded dies are described. The deep bond pads can extend to a semiconductor substrate of the respective device die. When the deep bond pads are formed, the heat dissipation of the resulting package is improved, and the bonding is more reliable. The deep bond pads can be used to achieve hybrid bonding in combination with the bonding of dielectric layers. The deep bond pads can also be used in combination with shallow bond pads and / or active metal pads. The embodiments described herein are intended to provide examples to enable the manufacture or use of the subject matter of this invention, and those skilled in the art will readily find modifications that can be made while remaining within the considered scope of the various embodiments.In the various views and exemplary embodiments, the same reference numerals are used to denote identical elements. Although some embodiments of the processes may be described as being executed in a specific sequence, other embodiments of the processes can be executed in any logical order.

[0010] The Fig. Figures 1-9 show cross-sectional views of intermediate stages in the formation of a wafer and die according to several exemplary embodiments, which, although they do not correspond to the literal wording of the claim, contribute to its explanation. The corresponding processes are also shown schematically in the figure in Fig. The process flow shown in 22 is reproduced in 200.

[0011] Fig. Figure 1 shows the cross-sectional view during the formation of integrated circuits and vias in a wafer 2. The corresponding process is described as process 202 in the Fig. The process flow shown in Figure 22 is illustrated in Figure 200. According to some embodiments of the present invention, wafer 2 is a device wafer comprising active devices such as transistors and / or diodes and / or passive devices such as capacitors, inductors, resistors, or the like. According to alternative embodiments, wafer 2 is a dummy wafer without active devices. The device wafer 2 can contain a plurality of identical chips, one of which is shown. The chips are hereinafter alternatively referred to as (device) dies.

[0012] The dies 4 can be selected from various types of device dies. According to some embodiments of the present invention, the device dies 4 are logic dies, which can be main processor dies (CPU dies), graphics processor dies (GPU dies), mobile application dies, microcontroller dies (MCU dies), baseband dies (BB dies), application processor dies (AP dies), or the like. According to alternative embodiments, the dies 4 are memory dies, which can be SRAM dies (static random-access memory dies), DRAM dies (dynamic random-access memory dies), NAND memory dies, RRAM dies (resistive random-access memory dies), MRAM dies (magnetoresistive random-access memory dies), or the like. According to still alternative embodiments, the dies 4 are analog dies or dummy dies.If these are dummy dies, the dies 4 do not contain any active devices such as transistors and diodes and / or passive dies such as capacitors, resistors, inductors and the like.

[0013] According to some embodiments of the present invention, the wafer 2 comprises a semiconductor substrate 5. The semiconductor substrate 5 can be composed of crystalline silicon, crystalline germanium, crystalline silicon germanium, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. The semiconductor substrate 5 can also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation regions (STI regions) (not shown) can be formed in the semiconductor substrate 5 to isolate the active regions within the semiconductor substrate 5.

[0014] According to some embodiments, vias 6 (sometimes also referred to as silicon vias or semiconductor vias) are configured to extend into the semiconductor substrate 5. The vias 6 may be made of or contain a metallic material such as copper, nickel, tungsten, or the like. Insulating layers (not shown) surround the vias 6 and electrically isolate them from the semiconductor substrate 5. The vias 6 extend to an intermediate plane between a top and bottom face of the semiconductor substrate 5. One of the vias 6 is shown with a dashed line to indicate that it may be formed, but is not required to be. The vias 6 may have different sizes. For example, the width (or diameter) may vary.The diameter (W1) of some vias 6 (which can be used for heat conduction) is larger than the width (W2) of some other vias 6 (which can be used for conducting electrical signals). According to alternative embodiments, the device dies 4 do not have any vias therein.

[0015] According to some embodiments of the present invention, the device dies 4 are active dies comprising integrated circuit devices 8 formed on the upper surface of the semiconductor substrate 5. Exemplary integrated circuits 8 may comprise active devices such as complementary metal-oxide-semiconductor transistors (CMOS transistors) and diodes, and passive devices such as resistors, capacitors, inductors, and / or the like. The details of the integrated circuits 8 are not described here. According to alternative embodiments, the device dies 4 are dummy dies that do not contain any active devices or passive device dies.

[0016] Fig. Figure 2 shows the formation of a front-side interconnect structure 16. The corresponding process is designated as process 204 in the Fig. The process flow shown in Figure 22 illustrates the process flow 200. An interlayer dielectric (ILD) 10 is formed over the semiconductor substrate 5 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit devices 8. According to some exemplary embodiments, the ILD 10 is formed from silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. The ILD 10 can be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0017] Contact plugs 12 are formed in the ILD 10 and are used to electrically connect the integrated circuit devices 8 and vias 6 to overlying metal conductors and vias. According to some embodiments of the present invention, the contact plugs 12 are formed from a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multiple layers thereof. Forming the contact plugs 12 can include forming contact openings in the ILD 10, filling the contact openings with one or more conductive materials, and performing planarization (e.g., a chemical-mechanical polishing (CMP) process) to flatten the upper surfaces of the contact plugs 12 with the upper surface of the ILD 10.

[0018] An interconnect structure 16 is formed above the ILD 10 and the contact connectors 12. The interconnect structure 16 comprises dielectric layers 22, metal conductors (and pads) 18, and vias 20 in the dielectric layers 22. The dielectric layers 22 are subsequently referred to alternatively as intermetal dielectric (IMD) layers 22. According to some embodiments of the present invention, some or all of the dielectric layers 22 are formed from low-k dielectrics having dielectric constants (k-values) of less than about 3.0 or about 2.5. The dielectric layers 22 can be formed from a carbon-containing low-k dielectric, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.According to some embodiments of the present invention, the formation of the dielectric layers 22 comprises the deposition of a porous dielectric and subsequent curing process to expel the porous material, leaving the remaining dielectric layers 22 porous. According to alternative embodiments of the present invention, some or all of the dielectric layers 22 are formed from non-low-k dielectrics such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. Etch stop layers (not shown), which may be formed from silicon oxynitride, aluminum oxide, aluminum nitride, or the like, or combinations thereof, may be formed between the IMD layers 22 and are not shown for simplicity.

[0019] The metal conductors 18 and vias 20 are formed in the dielectric layers 22. The metal conductors 18 on the same plane are hereinafter collectively referred to as a metal layer. According to some embodiments of the present invention, the interconnect structure 16 has a plurality of metal layers interconnected by the vias 20. The metal conductors 18 and vias 20 can be formed from copper or copper alloys, and they can also be formed from other metals. The formation process can include single-damascene and dual-damascene processes. In an exemplary single-damascene process, a trench is first formed in one of the dielectric layers 22, followed by filling the trench with a conductive material.A planarization process, such as a CMP process, is then performed to remove the excess conductive material above the top surface of the IMD layer, leaving a metal conductor in the trench. In a dual-damascene process, both a trench and a via are formed in an IMD layer, with the via located below and connected to the trench. The conductive material is then filled into the trench and the via, forming a metal conductor and a via, respectively. The conductive material may include a diffusion barrier and a copper-containing metallic material above the diffusion barrier. The diffusion barrier may contain titanium, titanium nitride, tantalum, tantalum nitride, or similar materials.

[0020] With reference to Fig. 3 A dielectric surface layer 24 is deposited according to some embodiments of the present invention. The corresponding process is described as process 206 in the Fig. The process flow shown in Figure 22 is described in Figure 200. The dielectric surface layer 24 is formed from a non-low-k dielectric and can be in physical contact with the underlying dielectric layer 22 or separated from the dielectric layer 22 by other layers, such as an etch stop layer. The dielectric surface layer 24 can be a silicon oxide-based dielectric containing silicon and one or more other elements, such as oxygen, nitrogen, carbon, or the like, or combinations thereof. For example, the dielectric surface layer 24 can be formed from or contain silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), or the like.

[0021] Openings 26 and 28 are formed by etching processes in the dielectric surface layer 24. During the formation of openings 26, the metal pads in the metal conductors / pads 18 in the upper metallization layer are used as an etch stop layer, and the metal pads 18 are exposed. During the formation of openings 28, an underlying dielectric layer is used as an etch stop layer and is exposed opposite the openings 28. Although not shown, the openings 26 can have vias and trenches over the vias, which are used to form dual damascene structures.

[0022] Referring to Fig. 4. Active bond pads 30 and flat bond pads 32 are formed. The corresponding process is described as process 208 in the Fig. The process flow shown in Figure 22 is illustrated in Figure 200. The flat bond pads 32 are dummy bond pads that are electrically potential-free in the finished package. The formation process can include the deposition of a conformal barrier layer (using a conductive material such as TiN, TaN, Ti, Ta, or the like), the deposition of a metallic material such as copper, tungsten, cobalt, or the like, and performing a planarization process to remove excess material.

[0023] Fig. Figure 4 further shows the formation of openings 34 (for example, openings 34A and 34B) by a plurality of etching processes. The corresponding process is designated as process 210 in the Fig. The process flow shown in Figure 22 is illustrated in Figure 200. Most etching processes can utilize different etching gases in response to different materials of the dielectric layers 22, the ILD 10, and the etch stop layers. The upper surface of the semiconductor substrate 5 is exposed opposite opening 34A. The upper surface of the semiconductor substrate 5 and the upper surface of one of the vias 6 (if formed) are exposed opposite opening 34B. According to some embodiments, the lower surfaces of the openings 34 are planar or substantially planar with the upper surface of the semiconductor substrate 5. According to alternative embodiments, the openings 34 extend into the semiconductor substrate 5, forming depressions with a depth D1 that may be greater than approximately 1 nm. The depth D1 may also be in the range between approximately 1 nm and approximately 10 nm. The dashed lines represent the corresponding bottoms and sidewalls of the depressions.

[0024] Referring to Fig. 5. Deep bond pads 36 (for example, 36A and 36B) are formed. The corresponding process is described as process 212 in the Fig. The process flow shown in Figure 22 illustrates the formation process. The formation process may also include the deposition of a conformal barrier layer (such as TiN, TaN, Ti, Ta, or the like), the deposition of a metallic material such as copper, tungsten, cobalt, or the like, and the performance of a planarization process to remove excess material. The entire lower surface of the resulting deep bond pad 36A contacts the upper surface of the semiconductor substrate 5. Furthermore, the sidewalls of the deep bond pad 36A need not be connected to any other conductive features (such as metal features). On the other hand, the deep bond pad 36B is electrically connected to the underlying via 6. It is understood that the corresponding via 6 is shown using dashed lines to indicate that it may be formed, but does not have to be.The deep bond pads 36 can have straight sidewalls extending from the top surface of the dielectric layer 24 to the top surface of the semiconductor substrate 5.

[0025] As in Fig. As shown in Figure 6, a back-side grinding process is next performed on the back (the underside shown) of the semiconductor substrate 5 to remove a portion of the semiconductor substrate 5 until the vias 6 are exposed. The corresponding process is described as process 214 in the Fig. The process flow shown in Figure 22 is shown in Figure 200. The semiconductor substrate 5 is then slightly recessed from the back side (for example by etching), so that the vias 6 protrude from the rear surface (the lower surface shown) of the semiconductor substrate 5.

[0026] According to alternative embodiments, no vias 6 are formed, and the processes (as in the Fig. 6, Fig. 7, Fig. 8 to Fig. 9), which are carried out on the back of wafer 2, are omitted.

[0027] Next, as in Fig. Figure 6 shows that a dielectric layer 38 is deposited, followed by a CMP process or a mechanical grinding process to re-expose the vias 6. The corresponding process is described as process 216 in Figure 6. Fig. The process flow shown in Figure 22 is illustrated in Figure 200. The vias 6 thus also extend through the dielectric layer 38. According to some embodiments, the dielectric layer 38 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like.

[0028] With reference to Fig. 7 Rear distribution lines (RDLs) 40 can be formed, which have pad sections that contact the vias 6. The corresponding process is described as process 218 in the Fig. The process flow shown in Figure 22 is described in Figure 200. The RDLs 40 can be formed from aluminum, copper, nickel, titanium, or the like, according to some embodiments. A dielectric layer 42 can be formed, wherein the RDLs 40 extend into the dielectric layer 42. Although, as an example, one dielectric layer 42 and one layer of RDLs 40 are formed, a plurality of dielectric layers and a plurality of layers of RDLs can be formed, depending on the routing requirements.

[0029] Fig. Figure 8 further shows the formation of active bond pads 45, flat bond pads 47, and bond pads 46. The corresponding process is designated as process 220 in the Fig. The process flow shown in Figure 22 is described in Figure 200. The active bond pads 45 are electrically connected to the vias 6, which are further connected to the integrated circuits 8 and / or the active bond pads 30. The bond pads 46 are electrically connected to the vias 6 and the deep bond pads 36B. The shallow bond pads 47 are dummy bond pads that are electrically floating in the finished package, each being completely surrounded by dielectrics. According to some embodiments, the bond pads 46 are made of or contain titanium nitride, copper, tungsten, or the like, multiple layers thereof, and / or alloys thereof.

[0030] According to some embodiments, the bond pads 46 are formed in a dielectric surface layer 44, which may contain or be formed from silicon oxide, SiN, SiC, SiOC, SiON, SiOCN, or the like. The lower surface of the bond pads 46 may be coplanar with the lower surface of the dielectric surface layer 44.

[0031] Fig. Figure 9 shows the formation of deep bond pads 48A. The corresponding process is designated as process 222 in the Fig. The process flow 200 is shown in Figure 22. According to some embodiments, forming the deep bond pads 48A includes etching through the dielectric layers 38, 42, and 44 such that openings are formed on the back side of the semiconductor substrate 5, exposing the rear surface (the bottom surface shown) of the semiconductor substrate 5 to the openings, filling the openings with conductive materials, and performing a planarization process. The conductive materials of the deep bond pads 48A can be selected from the same group of candidate materials used to form the deep bond pads 36A. According to these embodiments, the deep bond pads 48A can be thermally bonded to the deep bond pads 36A through the semiconductor substrate 5, forming thermally conductive channels.

[0032] According to alternative embodiments, instead of forming the bond pads 46 and the RDLs 40 for connection with the via 6 and the deep bond pad 36B, a deep bond pad 48B, shown with dashed lines, is formed on the back side of the semiconductor substrate. The deep bond pad 48B can be formed simultaneously with the deep bond pad 48A. The deep bond pads 36B and 48B and the corresponding via 6 thus form thermal conductivity channels.

[0033] According to some embodiments, the lateral dimensions W3 of the deep bond pads 36 and the lateral dimensions W3' of the deep bond pads 48 are larger than the lateral dimensions W4 of the active bond pads 30 and the lateral dimensions W4' of the active bond pads 45. Accordingly, the thermal efficiency of the heat conduction paths is improved, and at the same time, more signal paths can be formed. The lateral dimensions W3 and W3' can also be greater than or equal to the lateral dimensions W5 of the shallow bond pads 32 and the lateral dimensions W5' of the shallow bond pads 47.

[0034] In a subsequent process, the wafer 2 can be singulated by a sawing process along scoring lines 50, and the fixture dies 4 are separated from each other. The corresponding process is described as process 224 in the Fig. The process flow shown in 22 is shown in 200.

[0035] The device dies 4 can have four types of bond pads, comprising the active bond pads 30, the shallow (dummy) bond pads 32, the deep bond pads 36A, and the deep bond pads 36B in any combination. This means that on a single die, one, two, three, or all four types of bond pads can be formed on the same side of the device die 4, in any combination. These combinations of bond pads can be formed on the front (alternatively referred to as the active side), the back, or both the front and back of the semiconductor substrate 5. Throughout this description, the side of the semiconductor substrate 5 containing the active integrated circuit 8 is referred to as the active side or front, and the opposite side is referred to as the inactive side or back.When formed on the reverse side, the device dies 4 can have one, two, three or four types of active bond pads 45, shallow bond pads 47, bond pads 46 and deep bond pads 48 in any combination.

[0036] Furthermore, the device dies 4 can include the integrated circuits 8, which may or may not include active devices and passive devices. The corresponding device dies 4 are active device dies. According to alternative embodiments, the device dies 4 include passive devices and no active devices. According to still alternative embodiments, the device dies 4 include neither active nor passive devices. In this case, the device dies 4 are dummy dies. Some exemplary dummy dies 4 are described in the Fig. 13, Fig. 14 and Fig. 15 shown.

[0037] In some device dies 4, the vias 6 are formed, and bond pads are formed on both the front and back sides of the respective device dies 4. The resulting device dies 4 are referred to as double-sided device dies, with some examples shown in the Fig. Figures 10, 11, and 13 to 15 are shown. In some other device dies 4, no vias 6 are formed, and the processes (as in the Fig. 6, Fig. 7, Fig. 8 to Fig. 9), which are performed on the back side of wafer 2, are omitted. The resulting device dies 4 are single-sided, with exemplary single-sided device dies 4 shown in the Fig. 12 and Fig. 15 are shown.

[0038] The Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. Figure 14 shows some exemplary device dies 4 that can be formed using the processes described in relation to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 to Fig. 9 were described. The exemplary device dies 4 are stacked to form the package as shown in Fig. Figure 15 shows how to form the device dies 4 according to these embodiments. They have different combinations of features described above. It is understood, as also mentioned above, that any other combination can be used to form other device dies, which are also within the scope of the present invention. The details (such as dielectric layers, metal conductors, vias, RDLs, etc.) of the device dies in these figures are not shown, and the details can be found with reference to the embodiments described above.

[0039] Fig. Figure 10 shows a double-sided device die 4 (also referred to as 4-3) according to some embodiments. The lower side of the corresponding device die 4 shown can be the front side, and the respective integrated circuits 8 are located at the location indicated by solid lines. According to alternative embodiments, the upper side of the corresponding device die 4 shown can be the front side, and the respective integrated circuits 8 are located at the location indicated by dashed lines.

[0040] In Fig. Figure 11 shows the top side of the corresponding device die 4 (also referred to as 4-2A) as the front side, and a dashed rectangle is also shown to indicate that the bottom side shown can instead be the front side of the respective device die 4. Passive devices 33 are also shown schematically.

[0041] Fig. Figure 12 shows a single-sided device die 4 (also referred to as 4-1) according to some embodiments. The deep bond pads 36 are shown. Some shallow bond pads 32 are also shown. The dashed lines (labeled 36) under one of the shallow bond pads 32 indicate that these shallow bond pads can also be configured as deep bond pads, which are in Fig. 15 are used to indicate that the deep bond pads 36 can also be used as an electrical connection with the integrated circuits 8.

[0042] The Fig. 13 and Fig. Figure 14 shows some exemplary dummy dies 4 that have no active devices and passive devices. Fig. Figure 13 shows a dummy die, with the rear features such as the bond pads 46 and the deep bond pads 48 shown in dashed lines to indicate that the dummy die 4 can be double-sided or single-sided. Fig. Figure 14 shows an exemplary double-sided dummy die 4 (also referred to as 4-2B) which exhibits some of the features described in Fig. Figure 13 shows the vias 6. Dashed lines indicate that the vias may be present, but are not required to be. If present, these vias and the deep bond pads 36 and 48 above and below them can be used as electrical connections and thermal paths, respectively, to connect an above-die and a below-die. The bond pads 36A ( Fig. 13), which are not connected to any vias, are used as heat channels. According to some embodiments, a single dielectric layer 24, formed from a homogeneous dielectric, exists on the front face of the device die, and the deep (dummy) bond pads 36A and 36B extend through the single dielectric layer 24. According to alternative embodiments, two dielectric layers 24A and 24B exist on the front face of the dummy die 4, with the shallow bond pads 32 located in the upper dielectric layer 24B. A single dielectric layer or two dielectric layers may also be present on the back face of the substrate 5.

[0043] Fig. Figure 15 shows a package 52 formed by bonding a plurality of layers of device dies 4 as in the Fig. Figures 10 to 12 and 14 are shown. To distinguish the device dies in the package 52, each of the device dies 4 can be followed by a hyphen and a level number indicating the level of the device die. There can be n levels of stacked device dies 4, and the integer n can be 2, 3, 4, 5, or more. In addition, the letters A, B, C, and the like are used in the same layer to distinguish the device dies 4 from one another. For example, in the package 52, the level 2 device dies have active device dies 4-2A and dummy dies 4-2B and 4-2C. An encapsulation material 54, which can be a molding compound, a mold underfill, or the like, can be used to fill the gaps between adjacent device dies 4. The exemplary device dies 4 shown can include not only integrated circuits 8 but also passive devices 33.The bonded device dies include active device dies 4-1, 4-2A, 4-3, and 4-n. Additionally, a double-sided dummy device die 4-2B and a single-sided dummy device die 4-2C are also bonded in the die stack.

[0044] According to some embodiments, electrical connectors 58, which may be solder areas, metal pillars, bond pads, or the like, are formed on the upper surface of the upper device die 4-n. According to some embodiments, the lower device die 4-1 has no electrical connectors on its lower surface and no vias therein. In each of the active device dies 4-1, 4-2A, and 4-3, there is a solid frame indicating the location of the integrated circuits 8, which also indicates which side is the front face of the corresponding device die 4. In the two device dies 4-2A and 4-3, there is also a dashed frame in each, showing an alternative embodiment in which the integrated circuits 8 are formed where the dashed frame is located, instead of where the solid frame is located. Accordingly, Fig. Figure 15 shows the front-front bond, back-back bond and front-back bond schemes, depending on where the integrated circuits 8 are located.

[0045] According to some embodiments, bonding between the device dies 4 is carried out by hybrid bonding, which includes bonding metal pads to metal pads by direct metal-to-metal bonding and fusion bonding of the dielectric surface layers. For example, both the deep bond pad 36 (see Fig. 9) as well as the shallow bond pad 32 in a fixture die 4 or a dummy die 4 (4-2B or 4-2C) with any of the deep bond pads 36 and 48 and the shallow bond pads 32 and 47 by metal-to-metal bonding. Each of the active bond pads 30 (see Fig. 9) can be bonded to an active bond pad 30 or 45 in another device die. The dielectric surface layer 24 ( Fig. 9) can be bonded to either the dielectric surface layer 24 or the dielectric surface layer 44 in the adjacent die, creating a Si-O-Si bond.

[0046] Some exemplary bonding schemes are briefly described below. It is understood that the front and back sides of each of the device dies 4 can also be interchanged, as mentioned above. Accordingly, the front-side bond pads shown can alternatively be back-side bond pads and vice versa. Bonding structure 60-1 represents the bonding of a deep bond pad 36 in a first device die 4-1 to a deep bond pad 48 of a second device die 4-2A. Bonding structure 60-2 represents the bonding of a deep bond pad 36 in a first device die 4-2A to a deep bond pad 36 of a second device die 4-3.

[0047] Bond structure 60-3 represents the bonding of a deep bond pad 36 in a first device die 4-3 to a shallow bond pad 32 of a second device die 4-2A. Bond structures 60-1, 60-2, and 60-3 are electrically connected to the semiconductor substrates 5 of the corresponding device dies 4. Bond structure 60-4 represents the bonding of a shallow bond pad (e.g., bond pad 32 in Fig. 10) in a first device die 4-3 with the flat bond pad 32 of a second device die 4-2A. The bond structure 60-4 is electrically floating. The bond structures 60-5 and 60-6 represent the bonding of active bond pads (e.g., bond pads 30 and / or 45) in adjacent device dies 4, so that the integrated circuits in adjacent device dies are electrically connected to each other.

[0048] The dummy dies 4-2B and 4-2C have no active or passive devices and can be used to fill the spaces left over from the relatively small device die 4-2A. The dummy die 4-2B is a double-sided dummy die with deep (dummy) bond pads on either one or both sides of the corresponding semiconductor substrate 5. If the via 6 is formed, the corresponding bond pads can either be dummy bond pads with no electrical function or can be used as a signal path or power path (VDD or ground) for electrically connecting the device die 4-1 to the device die 4-3. For example, if a deep bond pad is formed as part of the bond structure 60-7, the corresponding deep bond pad 36 (shown with a dashed line) can be used to make a connection with the substrate 5 of the device die 4-1.If the via 6 is not formed in the dummy die 4-2B, the deep bond pads in the dummy die 4-2B can be used for heat dissipation, for example, to conduct the heat generated in the device die 4-3 to the device die 4-1 and then to an underlying heat sink (not shown). Shallow bond pads 32 and / or 47 can also be formed in the dummy die 4-2B to improve bond strength.

[0049] The dummy die 4-2C is a single-sided die, wherein deep (dummy) bond pads and shallow bond pads are formed on one side of the corresponding semiconductor substrate 5. Through-hole vias 6 may be formed in the semiconductor substrate 5, or the semiconductor substrate 5 may be free of through-hole vias 6.

[0050] The Fig. 16 and Fig. 17 show some details of two bonded dies in Fig. 15. Fig. Figure 16 shows two wafers 2-1' and 2-2' (and / or device dies 4-1' and 4-2') which, according to some embodiments, are bonded together by front-to-back bonding. The device dies 4-1' and 4-2' can bond two device dies (such as device dies 4-2A and 4-3) in Fig. Figure 15. The direction of the arrows 66 indicates the direction in which the front faces of the corresponding device dies 4 are aligned. In the example shown, the front face of the lower device die 4-1' is bonded to the back face of the upper device die 4-2'.

[0051] Fig. Figure 17 shows two wafers 2-1" and 2-2" (and / or device dies 4-1" and 4-2") which, according to some embodiments of the invention, are bonded together by front-to-front bonding. The device dies 4-1" and 4-2" can also bond two device dies (such as device dies 4-2A and 4-3) in Fig. Figure 15 illustrates this. The direction of the arrows 68 indicates the direction in which the front faces of the corresponding device dies 4 are aligned. In the example shown, the front face of the lower device die 4-1" is bonded to the front face of the upper device die 4-2".

[0052] The Fig. 18, Fig. 19, Fig. 20 to Fig. Figure 21 shows top views of some bond pads 64 according to some embodiments. Each of the bond pads 64 can be one of the active bond pads 30 and 45 ( Fig. 9), the shallow bond pads 32 and 47, the bond pad 46, and the deep bond pad 48. It is understood that although circles and rectangles are used as examples to represent the shapes of the bond pads 64 in plan view, other shapes such as hexagons, ovals, octagons, and the like may also be used.

[0053] Referring to Fig. 18. The bond pads 64 can be arranged to have a repeating structure, for example, a matrix. The bond pads 64 can have the same size and shape. Referring to Fig. 19. The bond pads 64 can be arranged to form a staggered structure with two matrices offset from each other. The bond pads 64 can be of the same size. Furthermore, the bond pads 64 can have the same shape. Fig. Figure 20 shows bond pads 64 that are arranged in an offset pattern, with the bond pads 64A in one matrix having a size that differs from the size of the bond pads 64B in the other matrix. Fig. Figure 21 shows bond pads 64 that are arranged in an offset pattern, with the bond pads 64C in one matrix having a shape that differs from the shape of the bond pads 64D in the other matrix.

[0054] In the embodiments shown above, some processes and features according to some embodiments of the present invention for forming a three-dimensional package (3D package) are described. Other features and processes may also be provided. For example, test structures may be provided to assist in the verification testing of the 3D packaging or the 3DIC devices. The test structures may, for example, include test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D packaging or the 3DIC, the use of probes and / or probe plates, and the like. The verification test can be performed on intermediate structures as well as on the finished structure.Additionally, the structures and procedures disclosed herein can be used in conjunction with test methods that include an intermediate verification of known good dies to increase yield and reduce costs.

[0055] The embodiments of the present invention have several advantageous properties. By forming deep bond pads, heat dissipation from one device die to the other (and to the heat sink) is improved, since the heat can be conducted directly to the semiconductor substrate through these bond pads without passing through the poorly thermally conductive dielectric layers. The strong anchoring of the deep bond pads to the respective semiconductor substrates also improves bond reliability. Furthermore, shallow bond pads are combined with deep bond pads and active bond pads to further enhance bond reliability.

Claims

[1] Package, comprising: a first die (2-1'), comprising: a first semiconductor substrate (5); integrated circuits (8) above and on a front side of the first semiconductor substrate (5); a plurality of dielectric layers (22, 24) over and on the front side of the first semiconductor substrate (5); a first deep bond pad (36A) that passes through the majority of dielectric layers (22, 24) and contacts the first semiconductor substrate (5); and a second deep bond pad (36B) that passes through the majority of dielectric layers (22, 24) and contacts the first semiconductor substrate (5); and a second die (2-2) above the first die (2-1), the second die having (2-2): a second semiconductor substrate (5); a third deep bond pad (36B) that touches the second semiconductor substrate (5), wherein the third deep bond pad (36B) is bonded to and physically in contact with the second deep bond pad (36B); and a first shallow potential-free bond pad (32) bonded to the first deep bond pad (36A).

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