Semiconductor package with photonic package and interposer with waveguide and manufacturing method

Abstract

Semiconductor package comprising: a first interposer (50) comprising: - a first substrate (11); - a first redistribution structure (12) over a first side of the first substrate (11); and - a first waveguide (21A, 21B, 21C) above the first redistribution structure (12) and near a first side of the first interposer (50), the first redistribution structure (12) being located between the first substrate (11) and the first waveguide (21A, 21B, 21C); and a photonics package (100) attached to the first side of the first interposer (50), the photonics package (100) comprising: - an electronic die (122); and - a photonic die (151) having a plurality of dielectric layers (135, 148A, 148B) and a second waveguide (134A, 134B, 134C) in one of the plurality of dielectric layers, wherein a first side of the photonic die (151) is attached to the electronic die (122) and an opposite second side of the photonic die (151) is attached to the first side of the first interposer (50), wherein the second waveguide (134A, 134B, 134C) is proximate to the second side of the photonic die.

Description

BACKGROUND

[0001] Electrical signal transmission and processing are one of the techniques used for signal transmission and processing. Optical signal transmission and processing have been used in more and more applications in recent years, particularly due to the use of optical fibers for signal transmission.

[0002] Optical signal transmission and processing are typically combined with electrical signal transmission and processing to enable fully integrated applications. For example, optical fibers can be used for long-distance signal transmission, and electrical signals for short-distance signal transmission, as well as for processing and control. Thus, devices for converting between optical and electrical signals, as well as for processing optical and electrical signals, are formed, integrating optical and electrical components. Packages can therefore contain both optical (photonic) dies with optical components and electronic dies with electronic components.

[0003] US 2020 / 0395347 A1 discloses a device comprising: a first dielectric layer; a first photonic chip and a second photonic chip arranged adjacent to a first side of the first dielectric layer; a waveguide optically coupling the first photonic chip to the second photonic chip, the waveguide being arranged between the first dielectric layer and the first photonic chip and between the first dielectric layer and the second photonic chip; a first integrated circuit chip and a second integrated circuit chip arranged adjacent to the first side of the first dielectric layer;conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic chip to the first integrated circuit chip, the conductive features electrically coupling the second photonic chip to the second integrated circuit chip; and a second dielectric layer disposed adjacent the second side of the first dielectric layer. ;

[0004] DE 10 2020 119 103 A1 describes a package comprising an interposer structure comprising a first via; a first interconnect device comprising a conductive routing and which is free of active devices; an encapsulation material surrounding the first via and the first interconnect device; and a first interconnect structure above the encapsulation material connected to the first via and the first interconnect device.a first semiconductor die connected to the first interconnect structure and to the first interconnect device, and a first photonic package connected to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, the first photonic package comprising the photonic routing structure comprising a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure comprising conductive features and dielectric layers; and an electronic die connected and electrically connected to the interconnect structure.

[0005] US 2020 / 0319403 A1 discloses an optoelectric system comprising: a conductive path for supplying an input voltage to a photonic device, wherein the conductive path comprises a base structure via extending through a substrate and a photonic structure via, wherein the photonic structure via extends through a dielectric stack of a photonic device. An optoelectric system is described herein, comprising: a second structure fusion-bonded to an interlayer dielectric base stack of a first structure.

[0006] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 to 17 show cross-sectional views of a photonics package at various stages of manufacturing according to one embodiment. Fig. 18 shows a cross-sectional view of a photonics package according to another embodiment. Fig. 19 to 22 show cross-sectional views of an interposer with a waveguide at various stages of fabrication according to one embodiment. Fig. 23 shows a cross-sectional view of an interposer with multiple layers of waveguides according to one embodiment. Fig. 24 shows a cross-sectional view of an interposer with a waveguide and an organic substrate, according to one embodiment. Fig. 25A-25D show various views (e.g., cross-sectional, top view) of a semiconductor package according to an embodiment. Fig. 26 shows a cross-sectional view of a semiconductor package according to an embodiment. Fig. 27 shows a cross-sectional view of a semiconductor package according to another embodiment. Fig. 28 shows a cross-sectional view of a semiconductor package according to another embodiment. Fig. 29 shows a cross-sectional view of a semiconductor package according to another embodiment. Fig. 30 shows a cross-sectional view of a semiconductor package according to another embodiment. Fig. 31 shows a cross-sectional view of an optical local silicon interconnect (OLSI) according to one embodiment. Fig. 32 shows a cross-sectional view of a local silicon interconnect (LSI) according to one embodiment. Fig. 33 shows a cross-sectional view of a semiconductor package according to an embodiment. Fig. 34 illustrates a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples of implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments where the first and second features are formed in direct contact, but may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact.

[0009] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "down," "over," "above," "up," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. The spatially relative terms are intended to encompass various orientations of the device during use or operation in addition to the orientation illustrated in the drawings. The device may also be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.Unless otherwise indicated, the same or similar reference numerals in the various drawings refer to a same or similar element manufactured by a same or similar manufacturing process using a same or similar material (or materials).

[0010] In this disclosure, an interposer with an embedded waveguide (e.g., nitride waveguide) provides routing for both electrical and optical signals and is used as a platform for integrating various types of devices, such as III-V devices, photonic devices / packages, and electronic-die-only devices, into a semiconductor package. Various embodiments of the semiconductor package offer a performance improvement over semiconductor packages that only allow electrical signal routing between different devices within the semiconductor package. The interposer disclosed herein enables the use of high-efficiency edge-mounted optical fibers and / or vertically mounted optical fibers within the semiconductor package for communication with external devices and offers great design flexibility.In some embodiments, one or more waveguides are integrated (e.g., embedded) in a silicon interposer of a chip-on-wafer-on-substrate (CoWoS) package, and a photonic die is disposed adjacent to an integrated circuit and / or a memory stack device on the silicon interposer.

[0011] Fig. 1 to 17 show cross-sectional views of a photonics package 100 at various stages of fabrication according to one embodiment. The photonics package 100 (also referred to as an optical module) may be part of a semiconductor package (for example, a semiconductor package 500 described below in connection with Fig. 25A and the like). In some embodiments, photonics package 100 provides an I / O (input / output) interface between optical signals and electrical signals within a semiconductor package. In some embodiments, photonics package 100 provides an optical network for signal communication between components (e.g., photonic devices, integrated circuits, couplings to external fibers, etc.) within photonics package 100.

[0012] With reference to Fig. 1, a buried oxide (BOX) substrate 102 is provided according to some embodiments. The BOX substrate 102 includes an oxide layer 102B formed over a substrate 102C and a silicon layer 102A formed over the oxide layer 102B. The substrate 102C may be a material such as glass, ceramic, a dielectric, a semiconductor, or a combination thereof. In some embodiments, the substrate 102C may be a semiconductor substrate, such as a bulk semiconductor or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 102C may be a wafer, such as a silicon wafer (e.g., a 12-inch silicon wafer). Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 102C may include silicon, germanium, a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. The oxide layer 102B may be, for example, a silicon oxide or the like. In some embodiments, the oxide layer 102B may have a thickness of about 0.5 μm to about 4 μm. The silicon layer 102A, in some embodiments, may have a thickness of about 0.1 μm to about 1.5 μm. Other thicknesses are also possible. The BOX substrate 102 may have a front side or front face (e.g., the front surface shown in FIG. Fig. 1 upward facing side) and a back or back surface (for example, the one in Fig. 1 side facing down).

[0013] With reference to Fig. 2, the silicon layer 102A is patterned according to some embodiments to form silicon regions for waveguides 104, photonic components 106, and grating couplers 107. The silicon layer 102A may be patterned using suitable photolithography and etching techniques. For example, a hard mask layer (e.g., a nitride layer or other dielectric material, in Fig. 2) may be formed and patterned over the silicon layer 102A in some embodiments. The pattern of the hard mask layer may then be transferred to the silicon layer 102A through an etching process. The etching process may be, for example, a dry etching process and / or a wet etching process. For example, the silicon layer 102A may be etched to form recesses defining the waveguides 104 (also referred to as silicon waveguides 104), with the sidewalls of the remaining, unetched portions defining the sidewalls of the waveguides 104. In some embodiments, more than one photolithography and etching sequence may be used to pattern the silicon layer 102A. One or more waveguides 104 may be patterned from the silicon layer 102A.When multiple waveguides 104 are formed, the multiple waveguides 104 may be individual, separate waveguides 104 or connected to form a continuous structure. In some embodiments, one or more of the waveguides 104 form a continuous loop. Other configurations or arrangements of the waveguides 104, the photonic components 106, or the grating couplers 107 are conceivable, and other types of photonic components 106 or photonic structures may be formed. In some cases, the waveguides 104, the photonic components 106, and the grating couplers 107 may collectively be referred to as a photonic layer.

[0014] The photonic components 106 can be integrated into the waveguides 104 and formed with the silicon waveguides 104. The photonic components 106 can be optically coupled to the waveguides 104 to interact with optical signals in the waveguides 104. The photonic components 106 can, for example, include photonic devices such as photodetectors and / or modulators. For example, a photodetector can be optically coupled to the waveguides 104 to detect optical signals in the waveguides 104 and generate electrical signals corresponding to the optical signals. A modulator can be optically coupled to the waveguides 104 to receive electrical signals and generate corresponding optical signals in the waveguides 104 by modulating the optical power in the waveguides 104.In this way, the photonic components 106 facilitate the input and output (I / O) of optical signals to and from the waveguides 104. In other embodiments, the photonic components may include other active or passive components, such as laser diodes, optical signal splitters, or other types of photonic structures or devices. Optical power may be delivered to the waveguides 104, for example, through an optical fiber (see, for example, 217A and 217B in FIG. Fig. 25A) coupled to an external light source, or the optical power can be supplied by a laser diode (see, for example, 400 in Fig. 25A).

[0015] In some embodiments, the photodetectors may be formed, for example, by partially etching portions of the waveguides 104 and growing an epitaxial material on the remaining silicon of the etched portions. The waveguides 104 may be etched using acceptable photolithography and etching techniques. The epitaxial material may include, for example, a semiconductor material such as germanium (Ge), which may be doped or undoped. In some embodiments, an implantation process may be performed to introduce dopants into the silicon of the etched portions as part of the fabrication of the photodetectors. The silicon of the etched portions may be doped with p-type dopants, n-type dopants, or a combination thereof.In some embodiments, the modulators may be formed, for example, by partially etching portions of the waveguides 104 and then implanting suitable dopants into the remaining silicon of the etched portions. The waveguides 104 may be etched using acceptable photolithography and etching techniques. In some embodiments, the etched portions used for the photodetectors and the etched portions used for the modulators may be fabricated using one or more of the same photolithography or etching steps. The silicon of the etched portions may be doped with p-type dopants, n-type dopants, or a combination thereof. In some embodiments, the etched portions for the photodetectors and the etched portions for the modulators may be implanted using one or more of the same implantation steps.

[0016] In some embodiments, one or more grating couplers 107 may be integrated into the waveguides 104 and formed with the waveguides 104. The grating couplers 107 are photonic structures that allow optical signals and / or optical power to be transferred between the waveguides 104 and a photonic component, such as a vertically mounted optical fiber (e.g., optical fiber 217B as shown in Fig. 25A) or a waveguide of another photonic system. The grating couplers 107 can be fabricated using acceptable photolithographic and etching techniques. In one embodiment, the grating couplers 107 are formed after the waveguides 104 are defined. For example, a photoresist can be formed and patterned on the waveguides 104. The photoresist can be patterned with openings corresponding to the grating couplers 107. One or more etching processes can be performed using the patterned photoresist as an etch mask to form recesses in the waveguides 104 that define the grating couplers 107. The etching processes can include one or more dry etching processes and / or wet etching processes.In some embodiments, other types of couplers (not individually referenced in the drawings) may also be formed, for example, a structure that couples optical signals between the waveguides 104 and other waveguides of the photonics package 100, such as the nitride waveguides 134A (see . Fig. 14). Edge couplers may also be formed to enable optical signals and / or optical power to be transmitted between the waveguide 104 and a photonic component mounted horizontally near a sidewall of the photonics package 100. Such and other photonic structures are within the scope of the present disclosure.

[0017] With reference to Fig. 3, according to some embodiments, a dielectric layer 108 is formed on the front side of the BOX substrate 102 to form a photonic routing structure 110. The dielectric layer 108 is formed over the waveguides 104, the photonic components 106, the grating couplers 107, and the oxide layer 102B. The dielectric layer 108 may be formed from one or more layers of silicon oxide, silicon nitride, a combination thereof, or the like, and may be formed by CVD, PVD, atomic layer deposition (ALD), a spin-on dielectric process, or the like, or a combination thereof.In some embodiments, the dielectric layer 108 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and then curing it to convert it to another material, such as an oxide), or a combination thereof. Other dielectric materials may be used, prepared by any acceptable method. In some embodiments, the dielectric layer 108 is then planarized by a planarization process, such as a CMP process, a grinding process, or the like. The dielectric layer 108 may, in some embodiments, be formed to have a thickness of about 50 nm to about 500 nm over the oxide layer 102B, or to have a thickness of about 10 nm to about 200 nm over the waveguides 104.In some cases, a thinner dielectric layer 108 may enable more efficient optical coupling between a grating coupler 107 and a vertically mounted photonic component.

[0018] Due to the different refractive indices of the materials of the waveguides 104 and the dielectric layer 108, the waveguides 104 exhibit high internal reflections, so that the light is essentially confined within the waveguides 104, depending on the wavelength of the light and the refractive indices of the respective materials. In one embodiment, the refractive index of the material of the waveguides 104 is higher than the refractive index of the material of the dielectric layer 108. For example, the waveguides 104 may be formed from silicon, and the dielectric layer 108 may be formed from silicon oxide and / or silicon nitride.

[0019] With reference to Fig. 4, vias 112 and contacts 113 are formed in the dielectric layer 108 according to some embodiments. In some embodiments, the vias 112 and the contacts 113 are formed as part of forming the redistribution structure 120 (see Fig. 5) and in other embodiments, the vias 112 are not formed. In some embodiments, the vias 112 are formed by a damascene process, such as a single damascene process, double damascene process, or the like. The vias 112 may be formed, for example, by forming openings that extend through the dielectric layer 108. In some embodiments, the openings may extend partially into the oxide layer 102B or completely through the oxide layer 102B to expose the substrate 102C. In some embodiments, the openings may extend partially into the substrate 102C. The openings may be formed by acceptable photolithography and etching techniques, such as by forming and patterning a photoresist and then performing an etching process using the patterned photoresist as an etch mask.The etching process can be, for example, a dry etching process and / or a wet etching process.

[0020] Then, according to some embodiments, a conductive material may be formed in the openings, thereby forming vias 112. In some embodiments, a liner, such as a diffusion barrier layer, an adhesion layer, or the like, made of TaN, Ta, TiN, Ti, CoW, or the like may be formed in the openings (not shown) using a suitable deposition process such as ALD or the like. In some embodiments, a seed layer, which may include copper or a copper alloy, may then be deposited in the openings (not shown). The conductive material of the vias 112 may be formed in the openings, for example, by a plating process. The conductive material may be, for example, a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, or alloys thereof.A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the top surface of the dielectric layer 108 so that the top surfaces of the vias 112 and the dielectric layer 108 are flat. In other embodiments, the vias 112 may be formed using other techniques or materials.

[0021] In some embodiments, contacts 113 extend through dielectric layer 108 and are electrically connected to photonic components 106. Contacts 113 enable electrical energy or electrical signals to be transmitted to photonic components 106 and electrical signals to be transmitted from photonic components 106. Thus, photonic components 106 can convert electrical signals into optical signals transmitted by waveguides 104 and / or can convert optical signals from waveguides 104 into electrical signals. Contacts 113 can be formed before or after vias 112 are formed, and forming contacts 113 and vias 112 can share some steps, such as deposition of conductive material and / or planarization.In some embodiments, the contacts 113 are formed by a damascene process, such as a single damascene process, double damascene process, or the like. For example, in some embodiments, openings (not shown) for the contacts 113 are first formed in the dielectric layer 108 using acceptable photolithography and etching techniques. Subsequently, a conductive material may be formed in the openings, thereby forming the contacts 113. Excess conductive material may be removed by a CMP process or the like. The conductive material of the contacts 113 may be formed from a metal or metal alloy, including aluminum, copper, tungsten, or the like, which may be the same as that of the vias 112. In other embodiments, the contacts 113 may be formed using other techniques or materials.

[0022] In Fig. 5, a redistribution structure 120 is formed over the dielectric layer 108 according to some embodiments. The redistribution structure 120 includes dielectric layers 117 and conductive features 114 formed in the dielectric layers 117 and enabling connections and electrical routing. For example, the redistribution structure 120 may connect the vias 112, the contacts 113, and / or overlying devices such as electronic dies 122 (see Fig. 8). The dielectric layers 117 may be, for example, insulating or passivation layers and may be formed from one or more materials similar to those described above with respect to the dielectric layer 108, such as silicon oxide or silicon nitride, or they may be formed from a different material. The dielectric layers 117 and the dielectric layer 108 may be transparent or nearly transparent to light in a same wavelength range. The dielectric layers 117 may be formed by a similar technique as described above with respect to the dielectric layer 108 or by a different technique. The conductive features 114 may include conductive lines and vias and may be formed by a damascene process, for example, a single damascene process, a double damascene process, or the like. As in Fig. 5, conductive pads 116 are formed in the topmost layer of the dielectric layers 117. A planarization process (e.g., a CMP process or the like) may be performed after the formation of the conductive pads 116, such that the surfaces of the conductive pads 116 and the topmost dielectric layer 117 are substantially coplanar. The redistribution structure 120 may include more or fewer dielectric layers 117, conductive features 114, or conductive pads 116 than in Fig. 5. The redistribution structure 120 may, in some embodiments, be formed with a thickness of about 4 µm to about 8 µm. Other thicknesses are conceivable.

[0023] With reference to Fig. 6 and Fig. 7, in some embodiments, a portion of the redistribution structure 120 is removed and replaced with a dielectric layer 115. The removed portion of the redistribution structure 120 may be located over, or approximately over, a grating coupler 107. The material of the dielectric layer 115 may provide more efficient optical coupling between a grating coupler 107 and a vertically mounted optical fiber (see optical fiber 217B in Fig. 25A) than the material of the dielectric layers 117 of the redistribution structure 120. For example, the dielectric layer 115 may be more transparent, less lossy, or less reflective than the dielectric layers 117. In some embodiments, the material of the dielectric layer 115 is similar to that of the dielectric layers 117, but is deposited by a technique that forms the material with better quality (e.g., fewer impurities, fewer dislocations, etc.). In this way, replacing a portion of the dielectric layers 117 of the redistribution structure 120 with the dielectric layer 115 may enable more efficient operation of the photonics package 100 and reduce optical signal losses.

[0024] With reference to Fig. 6, the portion of the redistribution structure 120 may be removed, for example, using acceptable photolithography and etching techniques such as forming and patterning a photoresist and then performing an etching process to remove the dielectric layers 117 using the patterned photoresist as an etch mask. The etching process may, for example, be a dry etching process and / or a wet etching process.

[0025] With reference to Fig. 7, the dielectric layer 115 is deposited to replace the removed portion of the redistribution structure 120. The dielectric layer 115 may be formed from one or more materials similar to those described above with respect to the dielectric layer 108, such as a silicon oxide or silicon nitride, a spin-on glass, or another material. The dielectric layer 115 and the dielectric layer 108 may be transparent or nearly transparent to light in the same wavelength range. The dielectric layer 115 may be formed by a similar technique as described above with respect to the dielectric layer 108 or by a different technique. The dielectric layer 115 may be formed, for example, by CVD, PVD, spin-on coating, or the like, but another method is also conceivable.In some embodiments, a planarization process (e.g., a CMP or grinding process) is used to remove excess material of the dielectric layer 115. The planarization process may also expose the conductive pads 116. After performing the planarization process, the dielectric layer 115, the topmost dielectric layer 117, and / or the conductive pads 116 may have substantially planar surfaces.

[0026] In other embodiments, the redistribution structure 120 is not etched and the dielectric layer 115 is not formed. In such embodiments, regions of the redistribution structure 120 may be substantially free of the conductive features 114 or conductive pads 116 to enable the transmission of optical power or optical signals through the dielectric layers 117. These metal-free regions may be located, for example, between a grating coupler 107 and a vertically mounted optical fiber (see optical fiber 217B in Fig. 25A) to allow optical power or optical signals to be coupled between the waveguides 104 and the optical fiber. In some cases, a thinner redistribution structure 120 may enable more efficient optical coupling between a grating coupler 107 and a vertically mounted optical fiber.

[0027] With reference to Fig. 8, one or more electronic dies 122 are bonded to the redistribution structure 120 according to some embodiments. The electronic dies 122 may be, for example, semiconductor devices, dies, or chips that communicate with the photonic components 106 via electrical signals. In the illustrated embodiments, the electronic die 122 does not receive, transmit, or process any optical signals. In the following, the term "electronic die" is used to distinguish it from a "photonic die" (see, for example, 151 in Fig. 17), which refers to a die that can receive, transmit, or process optical signals, such as converting an optical signal into an electrical signal or vice versa. In addition to optical signals, the photonic die can also send, receive, or process electrical signals. While in Fig. 8 illustrates an electronic die 122, in other embodiments, a photonics package 100 may include two or more electronic dies 122. In some cases, multiple electronic dies 122 may be integrated into a single photonics package 100 to reduce processing costs. The electronic die 122 includes die connectors 124, which may be, for example, conductive pads, conductive pillars, or the like. In some embodiments, the electronic die 122 may have a thickness of about 10 µm to about 35 µm, and for example, about 25 µm. Other thicknesses are contemplated.

[0028] The electronic die 122 may include integrated circuits for connecting to the photonic components 106, such as circuits for controlling the operation of the photonic components 106. For example, the electronic die 122 may include, for example, controllers, drivers, transimpedance amplifiers, or the like, or combinations thereof. In some embodiments, the electronic die 122 may also include a CPU. In some embodiments, the electronic die 122 includes circuitry for processing electrical signals received from photonic components 106, for example, for processing electrical signals received from a photonic component 106 having a photodetector.In some embodiments, the electronic die 122 may control the radio frequency signaling of the photonic components 106 according to the electrical signals (digital or analog) received from another device or die. In some embodiments, the electronic die 122 may be an electronic integrated circuit (EIC) or the like that provides serializer / deserializer (SerDes) functionality. In this way, the electronic die 122 may serve as part of an I / O interface between optical signals and electrical signals within a photonics package 100. In some embodiments, the photonics packages 100 described herein may be considered system-on-chip (SoC) devices or system-on-integrated-circuit (SoIC) devices.

[0029] In some embodiments, the electronic die 122 is bonded to the redistribution structure 120 by dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., by direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, or the like). In such embodiments, covalent bonds may be formed between oxide layers, such as the topmost dielectric layer 117 and the surface dielectric layers (not shown) of the electronic die 122. During bonding, metal bonding may also occur between the die connectors 124 of the electronic die 122 and the conductive pads 116 of the redistribution structure 120.

[0030] In some embodiments, a surface treatment of the electronic die 122 is performed prior to performing the bonding process. In some embodiments, the top surfaces of the redistribution structure 120 and / or the electronic die 122 may first be activated, for example, by a dry treatment, a wet treatment, a plasma treatment, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, or similar methods or combinations thereof. However, any suitable activation method may be used. After the activation process, the redistribution structure 120 and / or the electronic die 122 may be cleaned, for example, by a chemical rinse. The electronic die 122 is then aligned with the redistribution structure 120 and brought into physical contact with the redistribution structure 120.The electronic die 122 may be placed on the redistribution structure 120, for example, using a pick-and-place process. The redistribution structure 120 and the electronic die 122 may then be heat-treated and / or pressed against each other (for example, by applying contact pressure) to bond the redistribution structure 120 and the electronic die 122. For example, the redistribution structure 120 and the electronic die 122 may be subjected to a pressure of about 200 kPa or less at a temperature between about 200°C and about 400°C. The redistribution structure 120 and the electronic die 122 may then be exposed to a temperature at or above the eutectic point of the material of the conductive pads 116 and the die connectors 124 (for example, between about 150°C and about 650°C) to fuse the conductive pads 116 and the die connectors 124.In this way, the dielectric connection and / or the metal-to-metal connection between the redistribution structure 120 and the electronic die 122 forms a bonded structure. In some embodiments, the bonded structure is baked, annealed, pressed, or otherwise treated to strengthen or complete the connections.

[0031] In Fig. 9, a dielectric material 126 is formed over the electronic die 122 and the redistribution structure 120 according to some embodiments. The dielectric material 126 may be formed from silicon oxide, silicon nitride, a polymer, or the like, or a combination thereof. The dielectric material 126 may be formed by CVD, PVD, ALD, a spin-on dielectric process, or the like, or a combination thereof. In some embodiments, the dielectric material 126 may be formed by HDP-CVD, FCVD, or the like, or a combination thereof. The dielectric material 126 may, in some embodiments, be a gap fill material, which may include one or more of the example materials mentioned above.In some embodiments, the dielectric material 126 may be a material (e.g., silicon oxide) that is substantially transparent to light at wavelengths suitable for transmitting optical signals or optical power between the grating coupler 107 and a vertically mounted optical fiber (see, for example, 217B in FIG. Fig. 25A). In some embodiments where no grating coupler 107 is present, the dielectric material 126 may be formed from a relatively opaque material, such as an encapsulant material, a molding material, or the like. Other dielectric materials formed by any acceptable method may also be used. The dielectric material 126 may be planarized by a planarization process, such as a CMP process, a grinding process, or the like. In some embodiments, the planarization process may expose the electronic dies 122 such that the surfaces of the electronic dies 122 and the surfaces of the dielectric material 126 are coplanar.

[0032] The use of dielectric-to-dielectric bonding may allow materials that are transparent at the relevant light wavelengths to be deposited over the redistribution structure 120 and / or around the electronic die 122, instead of opaque materials such as an encapsulation material or a molding material. For example, the dielectric material 126 may be formed from a suitably transparent material such as silicon oxide, instead of an opaque material such as a molding material. Using a suitably transparent material for the dielectric material 126 in this way enables the transmission of optical signals through the dielectric material 126, for example, the transmission of optical signals between a grating coupler 107 and a vertically mounted optical fiber (see, for example, FIG. 217B in Fig. 25A) over the dielectric material 126. Furthermore, by bonding the electronic die 122 to the redistribution structure 120 in this manner, the thickness of the resulting photonics package 100 can be reduced and the optical coupling between a grating coupler 107 and a vertically mounted optical fiber can be improved. In some cases, this can reduce the size or processing cost of a photonics package and improve the optical coupling to external components.

[0033] In Fig. 10, an optional support body 128 is attached to the structure according to some embodiments. The support body 128 is a rigid structure attached to the structure to provide structural or mechanical stability. The use of a support 128 can reduce deformation or bending, which can improve the performance of optical structures such as the waveguides 104 or the photonic components 106. The support body 128 can be formed from one or more materials such as silicon (e.g., a silicon wafer, bulk silicon, or the like), a silicon oxide, a metal, an organic core material, or the like, or another type of material. The support body 128 can be attached to the structure (e.g., to the dielectric material 126 and / or the electronic dies 122) using an adhesive layer 127, as shown in Fig. 10, or the support body 128 may be attached by direct bonding or another suitable technique. In some embodiments, the support body 128 may have a thickness of about 500 µm to about 700 µm. The support body 128 may also have lateral dimensions (e.g., length, width, and / or area) that are larger than, approximately equal to, or smaller than those of the structure. In other embodiments, the support body 128 is attached in a later process step than shown in the fabrication of the photonics package 100.

[0034] In the example of Fig. 10, a microlens 131 is embedded in the support body 128 at the top of the carrier 128. In some embodiments, an etching process is performed to remove a portion of the carrier 128 to form a recess at the location of the microlens 131, then a preformed microlens 131 is inserted into the recess in the support body 128. In other embodiments, the microlens 131 is formed in situ in the recess by depositing a suitable material in the recess after the recess is formed in the support body 128. Subsequently, a dielectric layer 129 is formed over the support body 128, and an index matching material 133 is formed in the dielectric layer 129 over (e.g., directly over) the microlens 131.The dielectric layer 129 may be formed from a suitable material, such as silicon oxide, silicon nitride, a polymer material, or the like, by a suitable deposition process. An etching process is then performed to remove a portion of the dielectric layer 129 and form a recess above the microlens 131. The index matching material 133 is then deposited into the recess in the dielectric layer 129. A planarization process, such as CMP, may be performed to obtain a coplanar top surface between the dielectric layer 129 and the index matching material 133. In some embodiments, the index matching material 133 is used to reduce light loss for light coming from or entering a vertically mounted optical fiber (see, for example, FIG. 217B in FIG. Fig. 25A), and has a refractive index of, for example, about 1.4 to match the refractive index of silicon oxide. In some embodiments, the dielectric layer 129 and the index matching material 133 are omitted.

[0035] In Fig. 11 the structure is Fig. 10, according to some embodiments, is inverted and attached to a carrier 130. The carrier 140 may be, for example, a wafer (e.g., a silicon wafer), a plate, a glass substrate, a ceramic substrate, or the like. The structure may be attached to the carrier 140 using, for example, an adhesive or a release liner (not shown).

[0036] In Fig. 12, the substrate 102C is removed according to some embodiments. The substrate 102C may be removed by a planarization process (e.g., a CMP or grinding process), an etching process, a combination thereof, or the like. In some embodiments, the oxide layer 102B may also be thinned. The oxide layer 102B may be thinned as part of the removal process of the substrate 102C, or the oxide layer 102B may be thinned in a separate step. The oxide layer 102B may be thinned, for example, by a planarization process, an etching process, a combination thereof, or the like. In some embodiments, the oxide layer 102B may have a thickness of about 0.1 μm to about 1.0 μm after thinning. Other thicknesses are conceivable. In some cases, thinning the oxide layer 102B may improve the optical coupling between a waveguide 104 and a nitride waveguide 134 (see Fig. 14).

[0037] In the Fig. 13 and Fig. 14, nitride waveguides 134A are formed over the oxide layer 102B according to some embodiments. In Fig. 13, a silicon nitride layer 132 is deposited on the oxide layer 102B. The silicon nitride layer 132 may be formed by a suitable deposition process, such as CVD, PECVD, LPCVD, PVD, or the like. In some embodiments, the silicon nitride layer 132 is formed with a thickness of about 0.2 µm to about 1.0 µm, although other thicknesses are also contemplated.

[0038] In Fig. 14, the silicon nitride layer 132 is patterned to form the nitride waveguides 134A according to some embodiments. For simplicity, the nitride waveguides 134A and the subsequently formed nitride waveguides 134B, 134C, and 134D (see, for example, Fig. 16) collectively referred to as nitride waveguide 134. Nitride waveguide 134 may be patterned using acceptable photolithography and etching techniques. For example, in some embodiments, a hard mask layer may be formed and patterned over silicon nitride layer 132. The pattern of the hard mask layer may then be transferred to silicon nitride layer 132 by an etching process. The etching process may be, for example, a dry etching process and / or a wet etching process. The etching process may be selectively applied to silicon nitride, as opposed to silicon oxide or other materials. Silicon nitride layer 132 may be etched to form recesses that define nitride waveguides 134, with the sidewalls of the remaining unetched portions defining the sidewalls of nitride waveguides 134.In some embodiments, more than one photolithography and etch sequence may be used to pattern the silicon nitride layer 132. One or more nitride waveguides 134 may be patterned from the silicon nitride layer 132. When multiple nitride waveguides 134 are formed, the multiple nitride waveguides 134 may be individual, separate nitride waveguides 134 or connected as a single continuous structure. In some embodiments, one or more of the nitride waveguides 134 form a continuous loop. In some embodiments, the nitride waveguides 134 may include photonic structures such as grating couplers, edge couplers, or couplers (e.g., mode converters) that enable the transmission of optical signals between two nitride waveguides 134 and / or between a nitride waveguide 134 and a waveguide 104.

[0039] In some cases, a waveguide formed from silicon nitride (e.g., nitride waveguide 134) may have advantages over a waveguide formed from silicon (e.g., waveguide 104). For example, silicon nitride has a higher dielectric constant than silicon, and thus a nitride waveguide may have greater light confinement than a silicon waveguide. This may also make the performance or leakage of nitride waveguides less sensitive to process variations, less sensitive to dimensional uniformity, and less sensitive to surface roughness (e.g., edge roughness or linewidth roughness). In some cases, the lower process sensitivity may make nitride waveguides easier or less costly to process than silicon waveguides.These properties can result in a nitride waveguide having lower propagation loss than a silicon waveguide. In some cases, the propagation loss (dB / cm) of a nitride waveguide can range from about 0.1% to about 50% of that of a silicon waveguide. In some cases, a nitride waveguide can also be less sensitive to ambient temperature than a silicon waveguide. For example, a nitride waveguide can have a temperature sensitivity that is only about 1% of that of a silicon waveguide. In this way, the embodiments described herein can enable the formation of a photonics package that includes both nitride waveguides (e.g., nitride waveguide 134) and silicon waveguides (e.g., waveguide 104).

[0040] With further reference to Fig. 14, a reflector 145 is formed on the oxide layer 102B above the grating coupler 107. The reflector 145 may be configured to reflect the light from a photonic component, such as a vertically mounted optical fiber 217B, and may enable more efficient coupling between the grating coupler 107 and the photonic component. The reflector 145 may be formed from one or more dielectric materials, metal materials, or the like, which may be deposited using suitable deposition techniques. After the deposition of the reflector material 145, the reflector 145 may be formed using suitable techniques, for example, photolithographic patterning and etching techniques. Other techniques for fabricating a reflector 145 are conceivable.

[0041] With reference to Fig. 15, a dielectric layer 135 is shown over the nitride waveguides 134 according to some embodiments. The dielectric layer 135 may be formed from one or more materials similar to those described above with respect to the dielectric layer 108 or the dielectric layer 115. For example, the dielectric layer 135 may be formed from silicon oxide, spin-on glass, or the like. The dielectric layer 135 may be formed by a technique similar to that described above with respect to the dielectric layer 108 or the dielectric layer 115, or by a different technique. For example, the dielectric layer 135 may be formed by CVD, PVD, spin-on coating, or the like, but another method may also be used.In some embodiments, a planarization process (e.g., a CMP or grinding process) is used to remove excess material of the dielectric layer 135. After planarization, the dielectric layer 135 may, in some embodiments, have a thickness of about 0.5 μm to about 2 μm. Other thicknesses are conceivable.

[0042] Next, Fig. 16, a dielectric layer 138A is formed over the dielectric layer 135, a nitride waveguide 134B is formed over the dielectric layer 138A, and a dielectric layer 148A is then formed over the nitride waveguide 134B and the dielectric layer 138A. The dielectric layers 138A / 1,48A and the nitride waveguide 134B may be formed from the same or a similar material by a same or a similar manufacturing process as described with respect to the dielectric layer 135 and the nitride waveguide 134A, so details are not repeated here. The same processing may be repeated to form additional dielectric layers (e.g., 138B, 148B) and additional nitride waveguides (e.g., 134C, 134D). The number of nitride waveguides and the number of dielectric layers above the dielectric layer 135 in Fig. 16 is merely a non-limiting example. Other numbers are also possible and are fully within the scope of the present disclosure.

[0043] Subsequently, vias 152 are formed, which extend through the dielectric layers (e.g., 102B, 135, 138A, 148A, 138B, and 148B) and are connected to the vias 112. Conductive pads 153 are formed in the dielectric layer 148B over the respective vias 152. The vias 152 and the conductive pads 153 may be formed by the same or similar methods as described above with respect to the vias 112 and the conductive pads 116, so details are not repeated here. While in Fig. 16, one skilled in the art will recognize that ten, hundreds, or more identical photonic packages may be formed simultaneously on the carrier 140. In some embodiments, a singulation process is performed to divide the multiple photonic packages into individual photonic packages 100.

[0044] Fig. 17 shows the photonics package 100 after the carrier 140 is removed. In the example of Fig. 17, the structure below the electronic die 122 is referred to as photonic die 151, which includes the redistribution structure 120, the dielectric layers 115, 108, 102B, 135, 138A, 138B, 148A and 148B, and components formed in the dielectric layers such as the waveguide 104, the photonic component 106, the grating coupler 107, the reflector 145, and the nitride waveguides 134 (e.g., 134A, 134B, 134C, and 134D). Therefore, the photonics package 100 includes an electronic die 122 bonded to a photonic die 151 and may optionally include a support body 128, the microlens 131, the dielectric layer 129, and the index matching material 133.

[0045] It should be noted that the waveguides (e.g., 104, 134A, 134B, and 134C) are located in adjacent (e.g., immediately adjacent) dielectric layers in Fig. 17 overlap laterally. In Fig. 17, for example, the nitride waveguide 134A lies within the lateral extent of the waveguide 104, at least a portion of the nitride waveguide 134A lies within the lateral extent of the nitride waveguide 134B, and at least a portion of the nitride waveguide 134B lies within the lateral extent of the nitride waveguide 134C. Since optical coupling can occur between closely spaced waveguides, an “optical pass-through” (see, for example, 160 in Fig. 25B) formed by these waveguides (e.g. 104, 134A, 134B, 134C), which enables optical signals to be transmitted in the vertical direction from Fig. 17 to transmit (e.g., forward) the signal through optical coupling between adjacent waveguides. Details of the optical transmission are explained below.

[0046] Fig. Figure 18 shows a cross-sectional view of a photonics package 100A according to another embodiment. The photonics package 100A is similar to the photonics package 100 of Fig. 17, but has a photonic die 161 bonded to the photonic die 151. As in Fig. 18, the photonic die 161 is similar to the photonic die 151, but additionally includes nitride waveguides 134 formed in the dielectric layer 115 of the photonic die 161. In some embodiments, the vertical distance between the waveguide 104 of the photonic die 161 and the bottommost nitride waveguide 134 of the photonic die 151 may be too large to allow optical coupling, and therefore the nitride waveguides 134 are formed in the dielectric layer 115 of the photonic die 161 as an intermediate optical medium to break up the large vertical distance and allow optical coupling between the photonic dies 151 and 161. While in Fig. 18, two photonic dies are shown, the number of photonic dies in the photonics package 100A may be any. These and other variations are intended to be fully incorporated within the scope of the present disclosure.

[0047] In the following discussion, the Photonics Package 100 in Fig. 17 is used in various embodiments to form semiconductor packages. One skilled in the art will readily recognize that variations of the photonics package 100, such as photonics package 100A, may be substituted for the photonics package 100 in the various embodiments to form semiconductor packages. These and other variations are intended to be fully incorporated within the scope of the present disclosure.

[0048] Fig. 19 to 22 show cross-sectional views of an interposer 50 with a waveguide at various stages of fabrication according to one embodiment. In various embodiments discussed below, the photonics package described above (e.g., 100 or 100A) is bonded to the interposer 50 (or its variants) to form various semiconductor packages.

[0049] Fig. 19 shows a substrate 11 having TSVs (through substrate vias) 13. The substrate 11 can be, for example, a doped or undoped silicon substrate or an active layer of a SOI (silicon-on-insulator) substrate. However, the substrate 11 can also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that provides a suitable protection and / or connection function. These and any other suitable materials can alternatively be used for the substrate 11.

[0050] The TSVs 13 may be formed by etching the substrate 11 to create TSV openings and lining the TSV openings with conductive material(s), such as a liner (in Fig. 19 not shown separately), a barrier layer (in Fig. 19 also not separately shown) and a conductive material. In one embodiment, the liner may be a dielectric material such as silicon nitride, silicon oxide, a dielectric polymer, combinations of these materials, or the like, produced by a process such as chemical vapor deposition, oxidation, physical vapor deposition, ALD, or the like. The barrier layer may be an electrically conductive material such as titanium nitride, tantalum nitride, titanium, tantalum, or the like, produced by a CVD process (e.g., PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), ALD, or the like. The conductive material may be formed of copper, although other suitable materials such as aluminum, tungsten, alloys, doped polysilicon, combinations thereof, or the like may also be used.The conductive material can be formed by depositing a seed layer and then electroplating copper onto the seed layer, filling and overfilling the TSV openings. After the TSV openings are filled, excess liner / barrier layers and excess conductive material outside the TSV openings can be removed by an abrasive process, such as chemical mechanical polishing (CMP). Any suitable removal method can be used.

[0051] Next, Fig. 20, a redistribution structure 12 is formed over the substrate 11. The redistribution structure 12 comprises one or more dielectric layers 15 (e.g., silicon oxide layers) and conductive features such as conductive lines 17 and vias 19. The redistribution structure 12 may be formed by a same or similar method using the same or similar materials as described above with reference to the redistribution structure 120 of the photonics package 100, so details are not repeated here.

[0052] Next, Fig. 21, a nitride waveguide 21 is formed over the redistribution structure 12. The nitride waveguide 21 is formed by forming a silicon nitride layer over the redistribution structure 12 and patterning the silicon nitride layer. The details are the same or similar to those for the formation of the nitride waveguides 134 of the photonics package 100 and are therefore not repeated here. The nitride waveguide 21 may include photonic structures such as an edge coupler 24, which allows optical signals and / or optical power to be transmitted between the nitride waveguide 21 and a photonic component mounted horizontally near a sidewall of the interposer 50, such as an edge-mounted optical fiber (see, for example, FIG. 217A in Fig. 25A).

[0053] Next, Fig. 22, a dielectric layer 23 is formed over the nitride waveguide 21 and over the redistribution structure 12, and conductive pads 25 are formed that extend through the dielectric layer 23 to connect to the conductive features of the redistribution structure 12. The dielectric layer 23 may be formed from the same or similar material (e.g., silicon oxide) as the dielectric layer 15. In some embodiments, the refractive index of the dielectric layers 23 and 15 is lower than the refractive index of the nitride waveguide 21 to ensure that the nitride waveguide 21 has high internal reflections, so that the light is substantially confined within the nitride waveguide 21. The conductive pads 25 may be formed by a same or similar method as the conductive pads 153 of the photonics package 100, and the details are therefore not repeated here.Conductive connectors 27, also referred to as external connectors, are formed on the bottom surface of the interposer 50 to connect to the TSVs 13. The conductive connectors 27 may be, for example, BGA (Ball Grid Array) connectors, solder balls, metal pillars, C4 (Controlled Collapse Chip Connection) bumps, microbumps, ENEPIG (Electroless Nickel-Electroless Palladium-Immersion Gold Technique) bumps, or the like.

[0054] Fig. Figure 23 shows a cross-sectional view of an interposer 50A with multiple layers of waveguides according to one embodiment. The interposer 50A is similar to the interposer 50 of Fig. 22, but has multiple layers of nitride waveguides, such as nitride waveguides 21A, 21B, and 21C, formed over the redistribution structure 12. Each of the nitride waveguides 21A, 21B, and 21C may have a different thickness, measured along the vertical direction in Fig. 23. The nitride waveguides 21A, 21B, and 21C with different thicknesses can fulfill different functions in the fabricated photonics package. Furthermore, at least one of the nitride waveguides, for example, the nitride waveguide 24B, is formed such that it has different thicknesses in different sections. For example, the central section of the nitride waveguide 21B is Fig. 23 thicker than other portions of the nitride waveguide 21B. In some embodiments, the same nitride waveguide 21 (e.g., 21A, 21B, or 21C) may have thicknesses of, for example, 800 nm, 300 nm, and 150 nm at different portions of the nitride waveguide.

[0055] Fig. Figure 24 shows a cross-sectional view of an interposer 50B according to an embodiment comprising a waveguide and an organic substrate. The interposer 50B is similar to the interposer 50 in Fig. 22, however, the substrate 11 and the TSVs 13 are replaced by a redistribution structure 14 comprising one or more layers of an organic material 31 and conductive features (e.g., conductive lines 33 and vias 35) in the organic material 31. The interposer 50B may be formed by: forming a structure similar to the interposer 50 of Fig. 22, but without the TSVs 13 and the conductive connectors 27, removing the substrate 11, then forming the redistribution structure 14 on the lower side 12L of the redistribution structure 12.

[0056] To form the redistribution structure 14, a layer of organic material 31, such as a polymer material (e.g., polyimide) or the like, is formed on the bottom surface 12L of the redistribution structure 12. Openings are then formed in the layer of organic material 31 to expose the conductive features of the redistribution structure 12. A seed layer is formed over the layer of organic material 31 and in the openings. A patterned photoresist layer is then formed on the seed layer, with the pattern (e.g., openings) of the patterned photoresist layer corresponding to the positions of the conductive lines 33 and the vias 35. A conductive material (e.g., copper or the like) is then formed in the patterns of the patterned photoresist layer, for example, by a plating process.The photoresist layer is then removed (e.g., by an ashing process), and portions of the seed layer on which no conductive material is formed are removed by an etching process. The process can be repeated to form additional layers of the organic material 31 and additional layers with conductive features for the redistribution structure 14.

[0057] It should be noted that due to the available methods for deposition, patterning, and curing of the organic dielectric 31 (which may be softer than dielectric materials such as oxide and nitride and may have a different thermal regime), the dimensions of the conductive features 33 / 35 of the redistribution structure 14 differ from those of the conductive features 17 / 19 of the redistribution structure 12. For example, the smallest dimensions of the conductive features, such as the line width and / or the line spacing (e.g., the distance between adjacent conductive lines) of the conductive lines 33 are larger than those of the conductive lines 17. While the redistribution structure 14 may have a lower line density than the redistribution structure 12, the use of the organic material 31 offers certain advantages.The advantages of using the organic material 31 include lower material costs and the ease of covering the entire wafer surface during manufacturing. Another advantage is the ability to embed LSI (local silicon interconnect) chips into the organic material 31, providing greater die-to-die routing capacity. Examples of interposers with embedded LSI chips are described below with reference to FIG. Fig. 31-33 described.

[0058] In the following discussion, the photonics package 100 is bonded to the interposer 50 to form semiconductor packages in various embodiments. One of ordinary skill in the art will recognize that variations of the interposer 50, such as the interposer 50A or the interposer 50B, may be substituted for the interposer 50 in the various embodiments to form semiconductor packages. These and other variations are fully within the scope of the present disclosure.

[0059] Fig. 25A-25D show various views (e.g., cross-sectional, top view) of a semiconductor package 500 according to one embodiment. To form the semiconductor package 500, the photonics package 100 is bonded to the interposer 50 by dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, or the like). In such embodiments, covalent bonds may be formed between oxide layers, such as the dielectric layer 23 of the interposer 50 and the dielectric layers 148B of the photonics package 100. During bonding, a metal connection may also be formed between the conductive pads 153 of the photonics package 100 and the conductive pads 25 of the interposer 50.

[0060] As in Fig. 25A, in addition to the photonics package 100, the semiconductor devices 200 and 300 and a laser diode 400 are bonded to the interposer 50. In some embodiments, the semiconductor device 200 includes, for example, a processing die, a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a high-performance computing (HPC) chip, or the like, or a combination thereof. Fig. 25A shows the substrate 201 of the semiconductor device 200, on which electrical components such as transistors, resistors, capacitors, inductors, or the like are formed, and an interconnect structure 203 of the semiconductor device 200, which includes conductive structural elements formed in multiple dielectric layers for interconnecting the electrical components to form functional circuits of the semiconductor device 200. Conductive pads 207 of the semiconductor device 200 are connected to the conductive pads 25 of the interposer 50.

[0061] In some embodiments, the semiconductor device 300 includes, for example, a memory die, a high-bandwidth memory (HBM) device, a volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), another type of memory, or the like. Fig. Figure 25A shows the substrate 301 of the semiconductor device 300, on which memory cells and other electrical components are formed, as well as an interconnect structure 303 comprising conductive features formed in multiple dielectric layers to interconnect the electrical components and form functional circuits of the semiconductor device 300. The conductive pads 307 of the semiconductor device 300 are connected to the conductive pads 25 of the interposer 50.

[0062] Fig. 25A further shows a substrate 401, a light-emitting layer 403, a contact layer 405 (e.g., a doped semiconductor layer), and a dielectric layer 406 (e.g., silicon oxide) of the laser diode 400. The contact layer 405 and the dielectric layer 406 may be transparent or nearly transparent to light in the wavelength range of the laser diode 400, such that the nitride waveguide 21 of the interposer 50 is optically coupled to the light-emitting layer 403 of the laser diode 400. The conductive pads 407 of the laser diode are bonded to the conductive pads 25 of the interposer 50. In some embodiments, the laser diode 400 generates light signals (e.g., laser signals) controlled, for example, by the semiconductor device 200 and transmits the light signals through the nitride waveguide 21 of the interposer 50 to the photonics package 100.The laser diode 400 is used by way of example and not limitation, and other III-V devices may also be used in the photonics package 100, as will be appreciated by those skilled in the art.

[0063] In Fig. 25A, a mold material 211 is formed over the interposer 50 around the photonics package 100, the semiconductor devices 200 and 300, and the laser diode 400. The mold material 211 may be cured through a curing process. After the mold material 211 is formed, a planarization process, such as CMP, is performed to create a coplanar top surface between the photonics package 100, the semiconductor devices 200 and 300, and the laser diode 400.

[0064] With further reference to Fig. 25A, the photonics package 100 is coupled to a vertically mounted optical fiber 217B and an edge-mounted optical fiber 217A. In other embodiments, only vertically mounted optical fibers 217B or only edge-mounted optical fibers 217A are coupled to the photonics package 100, or a different number of vertically mounted optical fibers 217B or edge-mounted optical fibers 217A are coupled to the photonics package 100. The optical fibers 217 (e.g., 217A and 217B) may be mounted to the photonics package 100 with an optical adhesive 215 or the like.

[0065] In some embodiments, the vertically mounted optical fiber 217B may be configured to optically couple to a grating coupler, such as the grating coupler 107, within the photonics package 100. The vertically mounted optical fiber 217B may be mounted at an angle with respect to the vertical axis or may be laterally offset from the grating coupler 107. The optical signals and / or optical power transmitted between the vertically mounted optical fiber 217B and the grating coupler 107 are transmitted through the dielectric layer 108, the dielectric layer 115, the dielectric material 126, the adhesive layer 127, and the support body 128 formed over the grating coupler 107, as represented by the light path 164.Optical signals may be transmitted from the optical fiber 217B to the grating coupler 107 and into the waveguides 104, where the optical signals may be detected by a photonic component 106 including a photodetector and transmitted as electrical signals into the electronic die 122. Optical signals generated in the waveguides 104 by a photonic component 106 including a modulator may similarly be transmitted from the grating coupler 107 to the vertically mounted optical fiber 217B. Mounting the optical fiber 217B in a vertical orientation may enable improved optical coupling, lower processing costs, or greater design flexibility of the photonics package 100 or the semiconductor package 500.

[0066] In some embodiments, the edge-mounted optical fiber 217A is configured to optically couple to an edge coupler, such as the edge coupler 24, within the interposer 50. The edge coupler 24 may be disposed near an edge or sidewall of the interposer 50. The edge-mounted optical fiber 217A may be mounted at an angle with respect to the horizontal axis or vertically offset from the edge coupler 24. The optical signals and / or optical power transmitted between the edge-mounted optical fiber 217A and the edge coupler 24 may be transmitted through a dielectric layer (e.g., the dielectric layer 15). For example, optical signals may be transmitted from the edge-mounted optical fiber 217A to the edge coupler 24 and into the nitride waveguide 21.In some embodiments, a single optical fiber 217A may be coupled into more than one nitride waveguide 21 (see, for example, 21A, 21B, and 21C in FIG. Fig. 23). In this way, the photonics package 100 or the semiconductor package 500 described herein can be coupled to the optical fibers 217 in various configurations, allowing for greater design flexibility.

[0067] In the example of Fig. 25A, a portion of the molding material 211 near the edge-mounted optical fiber 217A is replaced by an index-matching material 213. In some embodiments, the index-matching material 213 is used to reduce or prevent light losses for light coming from or entering the edge-mounted optical fiber 217A. For example, the dielectric layers 15 / 23 may be oxide layers with a refractive index of 1.4, the molding material 211 may be a SOG material or an organic material with a refractive index other than 1.4 (e.g., greater than 1.4). To prevent light losses into the molding material 211, the index-matching material 213 is used with a refractive index (e.g., 1.4) corresponding to that of the dielectric layers 15 / 23. In some embodiments, the thickness of the index-matching material 213, measured along the vertical direction of Fig. 25A, at least 6 µm. The thickness T of the portion of the dielectric layer 15 beneath the nitride waveguide 21 may, for example, be up to 7 µm. In some embodiments where the refractive index of the mold material 211 matches that of the dielectric layer 15, the index matching material 213 is omitted. The semiconductor package 500 may be bonded to another substrate (e.g., a PCB board) via the conductive connectors 27 of the interposer 50.

[0068] Fig. 25B shows an enlarged view of a portion of the semiconductor package 500, showing a portion of the photonics package 100 and a portion of the interposer 50 in Fig. 25A shows. As in Fig. 25B, an optical through-via 160 is formed in the semiconductor package 500, which includes the silicon waveguides 104 and the nitride waveguides 134 of the photonics package 100, as well as the nitride waveguide 21 of the interposer 50. When the horizontal distances between adjacent waveguides (e.g., 104, 134, 21) are small, for example, when there is a lateral overlap, and when the vertical distances D1, D2, and D3 between adjacent waveguides (e.g., 104, 134, 21) are also small, the light can optically couple between the adjacent waveguides (e.g., 104, 134, 21). Thus, the light in the nitride waveguide 21 can be optically coupled into the overlying silicon waveguides 104 via the nitride waveguides 134 along the light path 162.

[0069] To effectively couple the light, the adjacent waveguides (e.g., 104, 134, and 21) in the optical through-via 160 have small pitches to achieve effective optical coupling and low light loss. For example, the vertical pitch D1 between the silicon waveguide 104 and its neighboring nitride waveguides 134 may be less than about 2000 Å. The vertical pitch D2 between adjacent nitride waveguides 134 may be less than about 2 µm. The vertical pitch D3 between the nitride waveguide 134C and the nitride waveguide 21 may be less than about 2 µm. For effective light transmission, all materials in the light paths, including the dielectric layers, may be transparent and have a refractive index lower than that of silicon nitride. For example, some or all of these dielectric layers may be formed of or contain silicon oxide.

[0070] Fig. 25C and Fig. 25D show top views of parts of the semiconductor package 500. Fig. 25C particularly shows the sidewalls of the laser diode 400, the light-emitting layer 403 of the laser diode 400, and the nitride waveguide 21 of the interposer 50. Fig. Figure 25D shows the side walls of the photonics package 100, the conductive pads 153 of the photonics package 100, the bottom nitride waveguide 134C of the photonics package 100, and the nitride waveguide 21 of the interposer 50. For simplicity, Fig. 25C and Fig. 25D not all features are shown. As in Fig. 25C, the light-emitting layer 403 of the laser diode 400 overlaps with at least a portion of the underlying nitride waveguide 21. Similarly, Fig. 25D that the lowermost nitride waveguide 134C of the photonics package 100 overlaps with the nitride waveguide 21 of the interposer 50.

[0071] Fig. Figure 26 shows a cross-sectional view of a semiconductor package 500A according to an embodiment. The semiconductor package 500A is similar to the semiconductor package 500 of Fig. 25A, except that multiple photonics packages 100 are bonded to the interposer 50. Each photonics package 100 includes a semiconductor device 200 (e.g., a CPU or a controller), a semiconductor device 300 (e.g., a memory device), and a laser diode 400 attached to the interposer 50. The Fig. The semiconductor device 300 shown in Figure 26 is a memory device. Fig. 26 shows memory cells 315 formed in / on the substrate of the semiconductor device 300 and the interconnect structure 303 of the semiconductor device 300. For simplicity, the laser diodes 400 in Fig. 26 with less detail than in Fig. 25A.

[0072] In the example of Fig. 26, the photonics packages 100 and the laser diodes 400 in the semiconductor package 500A are optically coupled to the nitride waveguide 21 of the interposer 50, so that optical signals can be transmitted between the photonics packages 100, between a photonics package 100 and a laser diode 400, and between the semiconductor package 500A and an external device (not shown) via the optical fibers 217 (e.g., 217A or 217B). Therefore, the nitride waveguide 21 serves as a data bus optically coupled to all optical components (e.g., 100, 400) of the semiconductor package 500A to facilitate optical communication between the optical components of the semiconductor package 500A.

[0073] Fig. Figure 27 shows a cross-sectional view of a semiconductor package 500B according to another embodiment. The semiconductor package 500B is similar to the semiconductor package 500 in Fig. 25A, but the interposer 50 is replaced by the interposer 50B from Fig. 24 is replaced.

[0074] Fig. Figure 28 shows a cross-sectional view of a semiconductor package 500C according to another embodiment. The semiconductor package 500C is similar to the semiconductor package 500 of Fig. 25A, except that semiconductor device 300 is replaced by semiconductor device 300A. Semiconductor device 300A is a memory device including memory cells 315, a first electronic die 311 (e.g., a CPU) and a second electronic die 313 (e.g., a memory controller) above memory cells 315, and a photonic die 317 below memory cells 315. Photonic die 317 is similar to photonic die 151 of photonics package 100. Photonic die 317 includes, for example, a redistribution structure, a silicon waveguide 304, a photonic component 306 (e.g., a photodetector or modulator), and nitride waveguides 334A and 334B. The lowermost nitride waveguide 334B is optically coupled to the nitride waveguide 21 of the interposer 50.The nitride waveguides 21, 334A, 334B and the silicon waveguide 304 form an optical through-via that optically couples the nitride waveguide 21 and the silicon waveguide 304.

[0075] Fig. 29 shows a cross-sectional view of a semiconductor package 500D according to another embodiment. In Fig. 29, the photonics package 100 and a laser diode 400 are bonded to the interposer 50 to form a semiconductor structure, which in turn is bonded to an interposer 60 via conductive connectors 27 of the interposer 50. The interposer 60 is similar to the interposer 50, but without the nitride waveguide 21. The interposer 60 includes, for example, a substrate 61, TSVs 63, and a redistribution structure 65 over the substrate 61. In Fig. 29 illustrates a semiconductor device 200 (e.g., a processor) and a semiconductor device 300 (e.g., a memory device) bonded to the interposer 60. An underfill material 404 is formed between the interposer 50 and the interposer 60, and between the semiconductor devices 200 / 300 and the interposer 60. A mold material 402 is formed over the interposer 60 around the semiconductor devices 200 / 300 and around the semiconductor structure including the interposer 50, the laser diode 400, and the photonics package 100.

[0076] Fig. 30 shows a cross-sectional view of a semiconductor package 500E according to another embodiment. The semiconductor package 500E is similar to the semiconductor package 500 of Fig. 25A, but the interposer 50 has multiple separate nitride waveguides. In the example of Fig. 30, two separate nitride waveguides 21A and 21B are shown on the top surface of the redistribution structure 12. In some embodiments, the lateral distance between the nitride waveguides 21A and 21B is too large for direct optical coupling. Note that the nitride waveguide 134C of the photonics package 100 is close to the two nitride waveguides 21A and 21B and laterally overlaps both nitride waveguides 21A and 21B. Thus, the nitride waveguide 134C is optically coupled to the two nitride waveguides 21A and 21B. A light signal in the nitride waveguide 21B can be indirectly coupled to the nitride waveguide 21A by first traveling upward to the nitride waveguide 134C and then traveling downward from the nitride waveguide 134C to the nitride waveguide 21A, as illustrated by the light path 167. Thus, Fig. 30 that the nitride waveguide 21 of the interposer 50 does not have to extend continuously over the entire length (or width) of the interposer 50, but can have several separate segments.

[0077] Fig. Figure 31 shows a cross-sectional view of an optical local silicon interconnect (OLSI) 610 according to one embodiment. The OLSI 610 includes a substrate 619 that is the same as or similar to the substrate 102C in Fig. 1. The substrate 619 may be formed, for example, from glass, ceramic, dielectric, a semiconductor material (e.g., Si), or a combination thereof. A dielectric layer 611 (e.g., a silicon oxide layer) is formed over the substrate 619, and a waveguide 613 (e.g., a silicon waveguide) is formed over the dielectric layer 611. Additional optical components, such as photodetectors, modulators, grating couplers, and the like, may also be formed in the same layer with the waveguide 613. One or more dielectric layers 615 (e.g., silicon oxide layers) are formed over the waveguide 613. Conductive features 617, including conductive lines and vias, are formed in the one or more dielectric layers 615 to form a redistribution structure 614 with a waveguide 613.In some embodiments, the OLSI 610 is formed by the same process used to form the interconnect structure of a semiconductor chip in a back-end-of-line (BEOL) process, and therefore the critical dimension (e.g., line width or line pitch) of the OLSI 610 is the same as that of the interconnect structure to enable high-density routing.

[0078] Fig. Figure 32 shows a cross-sectional view of a local silicon interconnect (LSI) 620 according to one embodiment. The LSI 620 is similar to the OLSI 610 in Fig. 31, but without the waveguide 613 being formed. The LSI 620 includes a substrate 629 (e.g., Si), a dielectric layer 621 (e.g., silicon oxide), and a redistribution structure 624 comprising one or more dielectric layers 625 (e.g., silicon oxide) and conductive features 627. The details are the same or similar to those described above with respect to the OLSI 610 and are therefore not repeated here.

[0079] Fig. 33 shows a cross-sectional view of a semiconductor package 600 according to one embodiment. The semiconductor package 600 includes the photonics package 100, the semiconductor device 200 (e.g., a processor), the semiconductor device 300 (e.g., a memory device), and the laser diode 400 bonded to an interposer 70. The interposer 70 includes a substrate 71 with TSVs 73 extending through the substrate 71. The substrate 71 is the same as or similar to the substrate 11 in Fig. 25A, so details are not repeated here. One or more layers of an organic material 75 (e.g., a polymer material such as polyimide) are formed over the substrate 71, and conductive features 79 (e.g., conductive lines and vias) are formed in the one or more layers of organic material 75 to form a redistribution structure 81. Specifically, two preformed LSIs 620 and an OLSI 610 are embedded (e.g., encapsulated) in the organic material 75 at the top surface of the redistribution structure 81. The OLSI 610 is disposed below the laser diode 400 and the photonics package 100. The laser diode 400 and the photonics package 100 are both optically coupled to the waveguide 613 of the OLSI 610 to enable optical communication.Furthermore, the laser diode 400 and the photonics package 100 are electrically coupled to the redistribution structure 614 of the OLSI 610 via conductive connectors 635.

[0080] As in Fig. 33, one of the LSIs 620 is arranged below the photonics package 100 and the semiconductor device 200, and the redistribution structure 624 of the LSI 620 is electrically connected to the photonics package 100 and the semiconductor device 200 via the conductive connectors 635. Another LSI 620 is arranged below the semiconductor device 200 and the semiconductor device 300, and the redistribution structure 624 of the other LSI 620 is electrically coupled to the semiconductor devices 200 and 300 via the conductive connectors 635. The LSIs 620 and the OLSI 610 have smaller feature sizes (e.g., line widths, line pitches) than the conductive feature elements 79 (because processes of the organic material 75 have larger critical dimensions) of the redistribution structure 81, thereby enabling higher density routing than the redistribution structure 81.

[0081] As in Fig. 33, an underfill material 631 is formed to fill the gap between the interposer 70 and the semiconductor devices 200 / 300, the laser diode 400, and the photonics package 100. A molding material 633 is formed over the interposer 70 around the semiconductor devices 200 / 300, the laser diode 400, and the photonics package 100. In some embodiments, the index matching material 213 is formed on the interposer 70 between the laser diode 400 and the photonics package 100, between the interposer 70 and the laser diode 400, and between the interposer 70 and the photonics package 100. The semiconductor package 600 may be bonded to another substrate (e.g., a PCB board) via the conductive interconnects 27 of the interposer 70.

[0082] The embodiments can achieve advantages. For example, the interposer (e.g., 50, 50A, 50B) comprising the nitride waveguide 21 supports the routing of both electrical and optical signals and enables the easy integration of various types of devices into the semiconductor package. Without the nitride waveguide 21 on the interposer, the photonics package 100 would have to communicate with the semiconductor devices 200 / 300 exclusively via electrical signals. As the data rate and routing density increase, the electrical signals transmitted between the photonics package 100 and the semiconductor devices 200 / 300 are degraded by the conductive connectors and copper lines. In the embodiments proposed herein, the interposer with built-in integrated waveguide enables high-speed optical signal transmission with increased power and performance.The interposers disclosed herein enable the use of highly efficient edge couplers in optical systems and enable the heterogeneous integration of III-V devices or devices made from other material systems. With the precision of die-to-wafer bonding, the integration structure can provide very low coupling loss for the heterogeneous integration of III-V devices into silicon photonic dies. Furthermore, the use of organic material in the interposer not only reduces costs but also enables the integration of LSI and / or OLSI for high-density, high-speed routing between devices bonded to the interposer.

[0083] Fig. 34 shows a flowchart of a method 1000 for manufacturing a semiconductor package according to some embodiments. It should be noted that the Fig. 34 is merely one example of many possible implementation methods. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, various steps as described in Fig. 34 are added, removed, replaced, rearranged or repeated.

[0084] With reference to Fig.34, in block 1010, a photonics package is attached to a first side of an interposer, the interposer comprising a first substrate, a first redistribution structure over a first side of the first substrate, and a first waveguide over the first redistribution structure and proximate the first side of the interposer, the photonics package comprising an electronic die and a photonic die comprising a plurality of dielectric layers and a second waveguide in the plurality of dielectric layers, a first side of the photonic die being attached to the electronic die and an opposite second side of the photonic die being attached to the first side of the interposer, the second waveguide being proximate the second side of the photonic die and optically coupled to the first waveguide.In block 1020, a laser diode is attached to the first side of the interposer, the laser diode being optically coupled to the first waveguide. In block 1030, a molding material is formed on the first side of the interposer around the laser diode and the photonics package.

[0085] According to one embodiment, a semiconductor package comprises a first interposer comprising: a first substrate; a first redistribution structure over a first side of the first substrate; and a first waveguide over the first redistribution structure and proximate a first side of the first interposer, the first redistribution structure being between the first substrate and the first waveguide.The semiconductor package further comprises a photonics package attached to the first side of the first interposer, the photonics package comprising: an electronic die; and a photonic die comprising a plurality of dielectric layers and a second waveguide in one of the plurality of dielectric layers, wherein a first side of the photonic die is attached to the electronic die and an opposite second side of the photonic die is attached to the first side of the first interposer, the second waveguide being proximate the second side of the photonic die. In one embodiment, the first waveguide of the first interposer is optically coupled to the second waveguide of the photonic die.In one embodiment, the first interposer further comprises a dielectric layer over the first waveguide, the first waveguide being located between the dielectric layer and the first redistribution structure, wherein a refractive index of the dielectric layer is lower than that of the first waveguide.In one embodiment, the photonic die further comprises: a second redistribution structure between the plurality of dielectric layers and the electronic die, the second redistribution structure electrically coupled to the electronic die; a third waveguide in a topmost dielectric layer of the plurality of dielectric layers closest to the second redistribution structure, the third waveguide optically coupled to the second waveguide; a photonic device in the topmost dielectric layer optically coupled to the third waveguide, the photonic device electrically coupled to the second redistribution structure; and conductive vias in the plurality of dielectric layers electrically coupled to the second redistribution structure.In one embodiment, the first waveguide and the second waveguide are nitride waveguides and the third waveguide is a silicon waveguide. In one embodiment, the photonic die further comprises a fourth waveguide in the plurality of dielectric layers disposed between the second waveguide and the third waveguide, wherein the third waveguide is optically coupled to the second waveguide via the fourth waveguide. In one embodiment, the photonics package further comprises: a support substrate over the electronic die, the electronic die being between the support substrate and the photonic die; and a microlens in the support substrate, wherein the semiconductor package further comprises an optical fiber attached to the support substrate over the microlens.In one embodiment, the semiconductor package further comprises a laser diode attached to the first side of the first interposer, the laser diode being optically coupled to the first waveguide of the first interposer. In one embodiment, the semiconductor package further comprises: a second interposer, wherein a first side of the second interposer is attached to a second side of the first interposer opposite the first side of the first interposer; a memory device attached to the first side of the second interposer; and a second electronic die attached to the first side of the second interposer.In one embodiment, the semiconductor package further comprises: a memory device attached to the first side of the first interposer, wherein the memory device is electrically coupled to the first redistribution structure of the first interposer; and a second electronic die attached to the first side of the first interposer, wherein the second electronic die is electrically coupled to the first redistribution structure of the first interposer. In one embodiment, the memory device has a third waveguide proximate a first side of the memory device facing the first interposer, wherein the third waveguide is optically coupled to the first waveguide. In one embodiment, the semiconductor package further comprises an optical fiber attached to a sidewall of the first interposer, wherein the optical fiber is optically coupled to the first waveguide of the first interposer.In one embodiment, the photonics package further comprises a second photonic die between the electronic die and the photonic die, wherein the photonic die is attached to the electronic die by the second photonic die.

[0086] According to one embodiment, a semiconductor package comprises an interposer comprising: a substrate; a first redistribution structure over a first side of the substrate; a first waveguide over the first redistribution structure; and a dielectric layer over the first waveguide.The semiconductor package further comprises a photonics package attached to a first side of the interposer, the photonics package comprising: an electronic die; and a photonic die, wherein a first side of the photonic die is attached to the dielectric layer of the interposer, and a second side of the photonic die is attached to the electronic die, the photonic die comprising: a second redistribution structure attached to the electronic die; a plurality of dielectric layers between the second redistribution structure and the interposer; a second waveguide in the plurality of dielectric layers proximate the interposer, the second waveguide optically coupled to the first waveguide; and vias in the plurality of dielectric layers, the vias electrically coupling the second redistribution structure to the first redistribution structure.In one embodiment, the semiconductor package further comprises an optical fiber attached to a sidewall of the interposer, the optical fiber optically coupled to the first waveguide of the interposer. In one embodiment, the semiconductor package further comprises a laser diode attached to the first side of the interposer, the laser diode optically coupled to the first waveguide of the interposer. In one embodiment, the substrate of the interposer comprises an organic material. In one embodiment, the photonics package further comprises a third waveguide in the plurality of dielectric layers proximate the electronic die, the third waveguide optically coupled to the second waveguide.

[0087] According to one embodiment, a method of manufacturing a semiconductor package comprises: attaching a photonics package to a first side of an interposer, the interposer comprising a first substrate, a first redistribution structure over a first side of the first substrate, and a first waveguide over the first redistribution structure and proximate the first side of the interposer, the photonics package comprising an electronic die and a photonic die comprising a plurality of dielectric layers and a second waveguide in the plurality of dielectric layers, a first side of the photonic die being attached to the electronic die and an opposite second side of the photonic die being attached to the first side of the interposer, the second waveguide being proximate the second side of the photonic die and optically coupled to the first waveguide;Attaching a laser diode to the first side of the interposer, the laser diode being optically coupled to the first waveguide; and forming a molding material over the first side of the interposer around the laser diode and the photonics package. In one embodiment, the method further comprises: prior to forming the molding material, attaching a memory device to the first side of the interposer; and attaching a second electronic die to the first side of the interposer.

Claims

[1] Semiconductor package comprising: a first interposer (50) comprising: - a first substrate (11); - a first redistribution structure (12) over a first side of the first substrate (11); and - a first waveguide (21A, 21B, 21C) above the first redistribution structure (12) and near a first side of the first interposer (50), the first redistribution structure (12) being located between the first substrate (11) and the first waveguide (21A, 21B, 21C); and a photonics package (100) attached to the first side of the first interposer (50), the photonics package (100) comprising: - an electronic die (122); and - a photonic die (151) having a plurality of dielectric layers (135, 148A, 148B) and a second waveguide (134A, 134B, 134C) in one of the plurality of dielectric layers, wherein a first side of the photonic die (151) is attached to the electronic die (122) and an opposite second side of the photonic die (151) is attached to the first side of the first interposer (50), wherein the second waveguide (134A, 134B, 134C) is proximate to the second side of the photonic die. [2] The semiconductor package of claim 1, wherein the first waveguide (21A, 21B, 21C) of the first interposer (50) is optically coupled to the second waveguide (134A, 134B, 134C) of the photonic die (151). [3] The semiconductor package of claim 1 or 2, wherein the first interposer (50) further comprises a dielectric layer over the first waveguide (21A, 21B, 21C), the first waveguide (21A, 21B, 21C) being located between the dielectric layer and the first redistribution structure (12), a refractive index of the dielectric layer being lower than that of the first waveguide (21A, 21B, 21C). [4] Semiconductor package according to one of the preceding claims, wherein the photonic (151) further comprises: a second redistribution structure (120) between the plurality of dielectric layers and the electronic die (122), the second redistribution structure (120) being electrically coupled to the electronic die (122); a third waveguide (104) in a topmost dielectric layer (108) of the plurality of dielectric layers closest to the second redistribution structure (120), the third waveguide (104) being optically coupled to the second waveguide (134A, 134B, 134C); a photonic device (106) in the uppermost dielectric layer (108) optically coupled to the third waveguide (104), the photonic device (106) being electrically coupled to the second redistribution structure (120); and conductive vias (152) in the plurality of dielectric layers electrically connected to the second redistribution structure (120). [5] The semiconductor package of claim 4, wherein the first waveguide (134A) and the second waveguide (134B) are nitride waveguides and the third waveguide (104) is a silicon waveguide. [6] The semiconductor package of claim 4 or 5, wherein the photonic die (151) further comprises a fourth waveguide (134A) disposed in the plurality of dielectric layers and between the second waveguide (134B) and the third waveguide (104), the third waveguide (104) being optically coupled to the second waveguide (134B) by the fourth waveguide (134A). [7] Semiconductor package according to one of the preceding claims, wherein the photonics package (100) further comprises: a carrier substrate (128) over the electronic die (122), wherein the electronic die (122) is located between the carrier substrate (128) and the photonic die (151); and a microlens (131) in the carrier substrate (128), wherein the semiconductor package further comprises an optical fiber (217A) attached to the carrier substrate (128) above the microlens. [8] Semiconductor package according to one of the preceding claims, further comprising: a laser diode (400) mounted on the first side of the first interposer (50), the laser diode (400) being optically coupled to the first waveguide (21A, 21B, 21C) of the first interposer (50). [9] The semiconductor package of claim 8, further comprising: a second interposer (60), wherein a first side of the second interposer (60) is attached to a second side of the first interposer (50) opposite the first side of the first interposer (50); a memory device (300) attached to the first side of the second interposer (60); and a second electronic die (200) attached to the first side of the second interposer (60). [10] Semiconductor package according to one of claims 1 to 8, further comprising: a memory device (300) attached to the first side of the first interposer (50), the memory device being electrically coupled to the first redistribution structure (65) of the first interposer (50); and a second electronic die (200) attached to the first side of the first interposer (50), the second electronic die (200) being electrically coupled to the first redistribution structure (65) of the first interposer (50). [11] The semiconductor package of claim 10, wherein the memory device (300) includes a third waveguide (104) near a first side of the memory device opposite the first interposer (50), the third waveguide (104) being optically coupled to the first waveguide (21A, 21B, 21C). [12] Semiconductor package according to one of the preceding claims, further comprising: an optical fiber (217B) attached to a sidewall of the first interposer (50), the optical fiber (217B) being optically coupled to the first waveguide (21A, 21B, 21C) of the first interposer (50). [13] The semiconductor package of any preceding claim, wherein the photonics package (100) further comprises a second photonic die (161) between the electronic die (122) and the photonic die (151), the photonic die (151) being attached to the electronic die (122) by the second photonic die (161). [14] Semiconductor package comprising: having an interposer: - a substrate; - a first redistribution structure (12) over a first side of the substrate; - a first waveguide (21A, 21B, 21C) above the first redistribution structure; and - a dielectric layer over the first waveguide (21A, 21B, 21C); and a photonics package (100) attached to a first side of the interposer, the photonics package (100) comprising: - an electronic die (122); and - a photonic die (151), wherein a first side of the photonic die (151) is attached to the dielectric layer of the interposer, and a second side of the photonic die (151) is attached to the electronic die (122), the photonic die (151) comprising: - a second redistribution structure (120) attached to the electronic die (122); - a plurality of dielectric layers between the second redistribution structure (120) and the interposer; - a second waveguide (134A, 134B, 134C) in the plurality of dielectric layers near the interposer, the second waveguide (134A, 134B, 134C) being optically coupled to the first waveguide (21A, 21B, 21C); and - vias (152) in the plurality of dielectric layers, wherein the vias (152) electrically connect the second redistribution structure (120) to the first redistribution structure (12). [15] The semiconductor package of claim 14, further comprising: an optical fiber (217B) attached to a side wall of the interposer, the optical fiber (217B) being optically coupled to the first waveguide (21A, 21B, 21C) of the interposer. [16] Semiconductor package according to claim 14 or 15, further comprising: a laser diode (400) mounted on the first side of the interposer, the laser diode (400) being optically coupled to the first waveguide (21A, 21B, 21C) of the interposer. [17] Semiconductor package according to one of claims 14 to 16, wherein the substrate of the interposer contains an organic material. [18] The semiconductor package of any one of claims 14 to 17, wherein the photonics package (100) further comprises a third waveguide (104) in the plurality of dielectric layers proximate the electronic die (122), the third waveguide (104) being optically coupled to the second waveguide (134A, 134B, 134C). [19] A method of manufacturing a semiconductor package, the method comprising: Attaching a photonics package (100) to a first side of an interposer, the interposer comprising a first substrate (11), a first redistribution structure (12) over a first side of the first substrate (11), and a first waveguide (21A, 21B, 21C) over the first redistribution structure (12) and proximate the first side of the interposer, the photonics package (100) comprising an electronic die (122) and a photonic die (151) having a plurality of dielectric layers and a second waveguide (134A, 134B, 134C) in the plurality of dielectric layers, a first side of the photonic die (151) being attached to the electronic die (122) and an opposite second side of the photonic die (151) being attached to the first side of the interposer, the second waveguide (134A, 134B, 134C) being proximate the second side of the photonic die (151) and is optically coupled to the first waveguide (21A, 21B, 21C); Attaching a laser diode (400) to the first side of the interposer, the laser diode (400) being optically coupled to the first waveguide (21A, 21B, 21C); and Forming a molding material over the first side of the interposer around the laser diode (400) and the photonics package (100). [20] The method of claim 19, further comprising, prior to forming the molding material: Attaching a memory device to the first side of the interposer; and Attaching a second electronic die (122) to the first side of the interposer.

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