ELECTROLUMINESCENT INDICATOR DEVICE AND CONTROL METHOD FOR IT

Abstract

Electroluminescent display device comprising: a pixel (PXL) connected to a data line (140) and a reference voltage line (150), wherein the pixel (PXL) includes a driver element (DT) configured to generate a driver current (Isen) based on a sample data voltage (VSEN) supplied via the data line (140) and a reference voltage (Vref) supplied via the reference voltage line (150), and wherein a level of the driver current (Isen) is proportional to a level of the sample data voltage (VSEN); a digital-to-analog converter (DAC) configured to set a level of the sample data voltage (VSEN) proportional to a magnitude of the current tracking data (TDATA) supplied to the digital-to-analog converter (DAC) and supplying the level-adjusted sample data voltage (VSEN) to the data line (140);a comparator and tracer circuit (CTS) configured to first determine a target current range between a low reference current (REF-LOW) and a high reference current (REF-HIGH) and modify the current trace data (TDATA) to set a level of the sample data voltage (VSEN) until the driver current (Isen) input via the reference voltage line (150) is within the target current range; and wherein, when the driver current (Isen) has a first value within the target current range, the comparator and tracer circuit (CTS) stops an operation to modify the current trace data (TDATA) and calculates a threshold voltage (Vth) of the driver element (DT) based on the driver current (Isen) with the first value.

Description

TECHNICAL AREA The present disclosure relates to an electroluminescence display device and a control method therefor. BACKGROUND In active-matrix electroluminescent displays, a plurality of pixels, each containing a light-emitting device and a driver element, are arranged in a matrix. The luminance of an image implemented by the pixels is set based on a grayscale value of the image data. The driver element controls a pixel current flowing in the light-emitting device based on a voltage (hereafter referred to as the gate-source voltage) applied between a gate electrode and a source electrode. The amount of light emitted by the light-emitting device and the luminance of a screen are determined based on this pixel current. Since the threshold voltage of a driver element determines the drive characteristic of a pixel, the threshold voltage should be constant across all pixels. However, the drive characteristic between pixels can vary due to various factors, such as processing characteristics and degradation characteristics. Such a difference in the drive characteristic leads to luminance deviation, which limits the implementation of an image. Compensation technologies for correcting luminance deviations between pixels have been proposed, but these do not exhibit high compensation performance due to noise in the sampling process. US 2018 / 0190192 A1 discloses an OLED display device capable of simplifying the configuration of an external compensation circuit and reducing the compensation time. SUMMARY To overcome the aforementioned problem of related prior art, the present disclosure can provide an electroluminescence display device for improving the scanning performance and the compensation performance, as well as a control method for it. To achieve these objectives and other advantages, and in accordance with the purpose of the disclosure as embodied and generally described herein, an electroluminescent display device according to the present invention comprises the features according to claim 1. In another aspect of the present disclosure, a control method for an electroluminescent display device according to the present invention has the features of claim 12. Additional features for advantageous embodiments of the present invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which serve to further understand the disclosure and are included in and form part of this application, illustrate the embodiment(s) of the disclosure and, together with the description, serve to explain the principle of the disclosure. In the drawings: Fig. 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure; Fig. 2 is a diagram showing an example of a pixel array in the display panel of Fig. 1; Fig. 3 is a diagram showing a drive system for reducing the threshold voltage sampling time of a driver element in an electroluminescent display device according to an embodiment of the present disclosure; Fig. 4 is a diagram describing the principle that a threshold voltage of a driver element is reduced based on a specific driver current within a target current range in the driver system of Fig.3 is calculated; Fig. 5 is a diagram showing the driver system of Fig. 3 in detail; Fig. 6 is a diagram showing an operating waveform of the driver system of Fig. 5; Fig. 7 is a diagram showing a first source voltage and a second source voltage for driving the display and the sampling drive in the driver system of Fig. 5; Fig. 8 is a diagram showing an example of a current-tracing feedback operation performed in the driver system of Fig. 5; Fig. 9 is a diagram showing an example of a current buffer in the driver system of Fig. 5; and Fig. 10 is a diagram showing a result obtained by comparing the time required to detect a threshold voltage of a driver element in the driver system of Fig. 5 with the prior art. DETAILED DESCRIPTION OF DISCLOSURE The present disclosure is described in more detail below with reference to the accompanying drawings, which illustrate exemplary embodiments of the disclosure. However, the disclosure can be embodied in many different forms and should not be interpreted as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the concept of the disclosure to the person skilled in the art. The advantages and features of the present disclosure and its implementation methods are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the present disclosure can be embodied in various forms and should not be understood as being limited to the embodiments presented here. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and fully conveys the scope of the present disclosure to the person skilled in the art. Furthermore, the present disclosure is defined only by the scope of the claims. The shapes, sizes, ratios, angles, numbers, and the like indicated in the drawings to describe various embodiments of the present disclosure are merely examples, and the present disclosure is not limited to them. The same reference numerals consistently refer to the same elements. Throughout the entire description, the same elements are designated by the same reference numerals. The expressions "have," "have," "contain," and the like used herein indicate that further parts may be added unless the term "only" is used. The singular forms "a," "an," and "the" used herein also include the plural forms unless the context clearly indicates otherwise. Elements in various embodiments of the present disclosure are to be interpreted as including the possibility of errors even without explicit indication. When describing a positional relationship, for example, when a positional relationship between two parts is described as "on~", "above~", "below~" and "next to~", one or more other parts may be located between the two parts unless "immediately" or "directly" is used. It goes without saying that while the terms "first," "second," etc., may be used here to describe different elements, these elements should not be restricted by these terms. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and similarly, a second element could be called a first element, without this deviating from the scope of the present disclosure. Identical numbers consistently refer to the same elements. The description states that a pixel circuit implemented on a display panel substrate can be implemented using a thin-film transistor (TFT) with an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure, but is not limited to this and can also be implemented using a TFT with a p-type MOSFET structure. A TFT can be a three-electrode element comprising a gate, a source, and a drain. The source can be an electrode that supplies a carrier to the transistor. Within the TFT, a carrier can flow from the source. The drain can be an electrode that allows the carrier to flow out of the TFT. Thus, in a MOSFET, the charge carrier flows from the source to the drain. Since the charge carrier in an n-type TFT (NMOS) is an electron, the source voltage can be lower than the drain voltage, allowing the electron to flow from the source to the drain.In an n-type TFT, the electron flows from the source to the drain, allowing current to flow from the drain to the source. In a p-type TFT (PMOS), however, the source voltage can be higher than the drain voltage because the charge carrier is a hole, allowing current to flow from the source to the drain. It's important to note that the source and drain of a MOSFET are not fixed but can switch between them. For example, the source and drain of a MOSFET can alternate between these states. Furthermore, in the present disclosure, a semiconductor layer of a TFT can be implemented with at least one oxide element, one amorphous silicon element and one polysilicon element. In the following description, a detailed description of the respective known function or configuration is omitted if it is determined that this would unnecessarily obscure the essential point of the present disclosure. Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Fig. 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure. Fig. 2 is a diagram showing an example of a pixel array in the display panel of Fig. 1. Referring to Figures 1 and 2, the electroluminescent display device according to one embodiment of the present disclosure can comprise a timing controller 1, a display panel 10, an integrated driver circuit (IC) 20, a compensation IC 30, a host system 40, a memory 50, and a power circuit 60. A gate driver circuit 15 contained in the display panel 10 and a data driver circuit 25 embedded in the driver IC 20 can control pixels PXL contained in the display panel 10. The display panel 10 can contain a plurality of pixel rows PNL1 to PNL4, and each of the pixel rows PNL1 to PNL4 can contain a plurality of pixels PXL and a plurality of signal lines. A "pixel row" as described here need not be a physical signal line and can denote a set of signal lines and pixels PXL adjacent to one another in one direction of extension of a gate line. The signal lines can include a plurality of data lines 140 for supplying the pixels PXL with a display data voltage and a sampling data voltage, a plurality of reference voltage lines 150 for supplying the pixels PXL with a reference voltage, a plurality of gate lines 160 for supplying the pixels PXL with a gate signal SCAN, and a plurality of first supply lines PWL for supplying the pixels PXL with a first source voltage EVDD. The pixels PXL of the display panel 10 can be arranged in a matrix configuration to form a pixel array. Each pixel PXL in the pixel matrix of Fig. 2 can be connected to one of the data lines 140, one of the reference voltage lines 150, one of the first power lines PWL, and one of the gate lines 160. Each pixel PXL in the pixel matrix of Fig. 2 can be connected to multiple gate lines 160. Furthermore, each pixel PXL in the pixel array of Fig. 2 can be supplied with a second source voltage by the power circuit 60. The power circuit 60 can supply the second source voltage to the pixel PXL via a low-level power line or a pad. The timing controller 1 can generate a gate timing control signal for controlling an operating timing of the gate driver circuit 15 and a data timing control signal for controlling an operating timing of the data driver circuit 25 with reference to timing signals (e.g. a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a point clock signal DCLK and a data release signal DE) that are input from a host system 40. The data timing control signal can include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse can control the start time of data sampling for the driver voltage generation circuit 23. The gate timing control signal can include, but is not limited to, a gate start pulse and a gate shift clock. The gate start pulse can be applied to a gate stage, which generates an initial gate output and can enable operation of the gate stage. The gate shift clock can be applied to all gate stages and can be a clock signal for shifting the gate start pulse. The timing controller 1 can control a sampling timing and a display timing of the pixel rows PNL1 to PNL4 of the display panel 10 based on a predetermined sequence, thus performing a display control operation and a sampling control operation. The display control operation and the sampling control operation can be executed differently by operations of the gate driver circuit 15 and the data driver circuit 25, which are performed based on the control by the timing controller 1. Sampling control can refer to an operation that applies the sampling data voltage to pixels PXL contained in a sampling target pixel array to sample a threshold voltage variation of each of the corresponding pixels PXL, and that updates a compensation value to compensate for a threshold voltage variation of each of the corresponding pixels PXL based on the sampling result data. Display control can also refer to an operation that corrects digital image data to be input into corresponding pixels PXL based on an updated compensation value and applies the display data voltage corresponding to the corrected image data to the corresponding pixels PXL to display an input image on a screen (hereinafter referred to as screen display). The display drive operation can be performed during a vertically active period, in which the data release signal is shifted between a logic high level and a logic low level within a frame. The sample drive operation can be performed during a vertically idle period, other than the vertically active period within a frame. During the vertically idle period, the data release signal can continuously maintain a logic low level. The sample drive operation can be performed during a power-on period until just before screen playback begins, after the system's main power supply is applied, or during a power-off period until just before the system's main power supply is released after the screen playback has ended. The gate driver circuit 15 can be embedded in the display panel 10. The gate driver circuit 15 can be located in a non-display area outside the display area where the pixel array is located. The gate driver circuit 15 can have a plurality of gate stages connected to the gate lines 160 of the pixel array. The gate stages can generate the gate signal SCAN for controlling switching elements of the pixels PXL and supply the gate signal SCAN to the gate lines 160. The data driver circuit 25 embedded in the driver IC 20 can include a plurality of comparator and tracker units and a plurality of digital-to-analog converters. During display control, each of the comparator and tracker units can supply the reference voltage to the reference voltage line 150, and each of the digital-to-analog converters can generate a display data voltage and supply the display data voltage to the data line 140. During display control, a display driver current can flow in a driver element of a pixel PXL based on a display data voltage and the reference voltage, and a light-emitting device of the pixel PXL can emit light with the display driver current, thereby displaying an image on a screen. In sample-driven operation, each of the comparator and tracker units can supply the reference voltage to the reference voltage line 150. Then, when a driver current input via the reference voltage line 150 is within a predetermined target current range, a gate-source voltage of a driver element contained in a corresponding pixel can be calculated as the threshold voltage of the driver element. In sample-driven operation, each of the digital-to-analog converters can adjust the level of a sample data voltage based on current-tracking data until the driver current input via the reference voltage line 150 is within the target current range, and can then transmit a level-adjusted sample data voltage to the data line 140. In sample-driven operation, because the level of the driver current that meets the target current range is much lower than that of the display driver current, the sampling time can be significantly reduced. Each of the comparator and tracker units of the data driver circuit 25 can convert a detected threshold voltage of the driver element into digital sample result data and deliver the digital sample result data to the memory 50. The memory 50 can be implemented as flash memory, but is not limited to this. The compensation IC 30 can include a compensation circuit 31 and a compensation memory 32. The compensation memory 32 can transfer the digital sample result data read from the memory 50 to the compensation circuit 31. The compensation memory 32 can be random access memory (RAM) (e.g., a synchronous dynamic RAM with double data rate (DDR SDRAM)), but is not limited to this. The compensation circuit 31 can calculate a compensation offset and compensation gain for each pixel based on the digital sample result data, correct the digital image data input from the host system 40 based on the calculated compensation offset and compensation gain, and deliver the corrected image data to the driver IC 20. The power circuit 60 can generate various types of source voltages required for driving the electroluminescent display device. The power circuit 60 can generate the reference voltage to be supplied to the pixels PXL. The power circuit 60 can include a pixel power adjustment circuit that generates different first and second source voltages to be supplied to the pixels PXL during display and scanning operation. Fig. 3 is a diagram illustrating a drive system for reducing the threshold voltage sampling time of a driver element in an electroluminescent display device according to an embodiment of the present disclosure. Fig. 4 is a diagram describing the principle that a threshold voltage of a driver element is calculated in the driver system of Fig. 3 based on a specific driver current within a target current range. Referring to Figures 3 and 4, the electroluminescent display device according to an embodiment of the present disclosure can adaptively adjust a data voltage based on a tracking operation of a driver current during sampling, thereby reducing the threshold voltage sampling time of a driver element. For this purpose, the driver system can comprise a pixel PXL, a comparator and tracker CTS, and a digital-to-analog converter DAC. The Pixel PXL can be connected via a data line 140 and a reference voltage line 150 and can include a driver element and a light-emitting device. During scanning, the driver element can be supplied with a scanning data voltage via the data line 140 and with a reference voltage via the reference voltage line 150, generating a driver current proportional to the differential voltage between the scanning data voltage and the reference voltage. This driver current can be supplied to the comparator and tracker (CTS) via the reference voltage line 150 instead of being supplied to the light-emitting device. Furthermore, when controlling the display, the driver element can be supplied with a display data voltage via data line 140 and with the reference voltage via reference voltage line 150, generating a display driver current proportional to the differential voltage between the display data voltage and the reference voltage. This display driver current can then be supplied to the light-emitting device, enabling it to emit light. The Comparator & Tracker (CTS) unit can be connected to the Pixel PXL via the reference voltage line 150. The CTS unit can first determine a target current range between a low and a high reference current and perform a rapid tracking feedback operation based on a current comparison until a driver current of the Pixel PXL, input via the reference voltage line 150, is within the target current range, thereby modifying the current tracking data TDATA. As in Fig. 4, for example, a horizontal axis represents a gate-source voltage Vgs of the driver element and a vertical axis represents a drain-source current Ids of the driver element. In a current characteristic where a drain-source voltage Vds of the driver element is Y (where Y is a positive real number), the target current range can have a drain-source current Ids with a level of X (where X is a positive real number) nA. In this case, if the drain-source current Ids of the driver element is X nA, the gate-source voltage Vgs of the driver element can be a threshold voltage Vth of the driver element. The driver element can be an analog element. Therefore, the driver element cannot be switched off even when the gate-source voltage Vgs is the threshold voltage Vth, and as shown in Fig. 4, the driver current of X nA can flow through the driver element. Since the magnitude of the driver current is much smaller than that of the display driver current, the time of the fast tracking feedback operation (i.e., a current comparison and feedback operation) performed by the comparator and tracker (CTS) can be greatly reduced. Accordingly, the time (hereafter referred to as the sample-attach time) required to detect the threshold voltage of the driver element can be significantly reduced. The digital-to-analog converter (DAC) can adjust the level of a sampling data voltage to be proportional to the level of the current tracking data (TDATA) and can supply the level-adjusted sampling data voltage to data line 140. The electroluminescent display device according to one embodiment of the present disclosure may further include a pixel power adjustment circuit (PCT) to prevent a light-emitting device contained in each pixel (PXL) from emitting unwanted light during scanning. This is described below with reference to Fig. 5. Fig. 5 is a diagram showing the driver system of Fig. 3 in detail. Fig. 6 is a diagram showing an operating waveform of the driver system of Fig. 5. Fig. 7 is a diagram showing a first source voltage and a second source voltage for driving the display and the sampling drive in the driver system of Fig. 5. Fig. 8 is a diagram showing an example of a current-tracing feedback operation performed in the driver system of Fig. 5. With reference to Fig. 5, Fig. 6, Fig. 7 to Fig. 8, the electroluminescence display device according to an embodiment of the present disclosure can include a pixel PXL, a comparator & tracker unit CTS and a digital-to-analog converter DAC and can further include a pixel power adjustment circuit PCT. The Pixel PXL can contain a light-emitting element EL, a driver element DT, switching elements ST1 and ST2, and a storage capacitor Cst. The driver element DT and the switching elements ST1 and ST2 can each be implemented with an NMOS transistor, but are not limited to this. The light-emitting device EL can emit light with a display driver current Iel supplied by the driver element DT. The light-emitting device EL can only emit light when the display is driven and must not emit light during scanning. The light-emitting device EL can be implemented with an organic light-emitting diode with an organic light-emitting layer or with an inorganic light-emitting diode with an inorganic light-emitting layer. An anode electrode of the light-emitting device EL can be connected to a second node N2, and a cathode electrode of this can be connected to an input terminal for a second source voltage EVSS. In display drive mode, the driver element DT can generate a first drain-source current Idt based on a first gate-source voltage (i.e., VDIS - Vref), and this first drain-source current Idt can be the display driver current Iel. In sample drive mode, the driver element DT can generate a second drain-source current Idt based on a second gate-source voltage (i.e., VSEN - Vref), and this second drain-source current Idt can be a driver current Isen. A gate electrode of the driver element DT can be connected to a first node N1, a drain electrode of this can be connected to a first power line PWL via a first source voltage input terminal EVDD, and a source electrode of this can be connected to the second node N2. Switching elements ST1 and ST2 can be activated during display or scanning control and can connect the gate electrode of driver element DT to data line 140, connect the source electrode of driver element DT to reference voltage line 150, and set a gate-source voltage of driver element DT. Switching elements ST1 and ST2 can be activated based on the same SCAN gate signal. Switching elements (e.g., the first and second switching elements) ST1 and ST2 can continuously maintain an on state during scanning control. The first switching element ST1 can be connected between data line 140 and the first node N1 and can be switched on based on the gate signal SCAN from gate line 160. The first switching element ST1 can be switched on during programming for display control and can also be switched on during sampling control. When the first switching element ST1 is switched on, a sampling data voltage VSEN or a display data voltage VDIS can be applied to the first node N1. One gate electrode of the first switching element ST1 can be connected to gate line 160, one source electrode can be connected to data line 140, and one drain electrode can be connected to the first node N1. The second switching element ST2 can be connected between the reference voltage line 150 and the second node N2 and can be switched on based on the gate signal SCAN from the gate line 160. During programming for display control, the second switching element ST2 can be switched on and can apply a reference voltage Vref (see Fig. 9), which is loaded into the reference voltage line 150, to the second node N2. During scanning control, the second switching element ST2 can be switched on, apply the reference voltage Vref (see Fig. 9), which is loaded into the reference voltage line 150, to the second node N2, and transmit a driver current generated by the driver element DT to the reference voltage line 150.A gate electrode of the second switching element ST2 can be connected to the gate line 160, a drain electrode of the same can be connected to the second node N2 and a source electrode of the same can be connected to the reference voltage line 150. The storage capacitor Cst can be connected between the first node N1 and the second node N2 and can store a gate-source voltage of the driver element DT. The pixel power matching circuit PCT can generate the first source voltage EVDD and supply the first source voltage EVDD via the first power line PWL to a first source voltage input terminal, and can also generate the second source voltage EVSS and supply the second source voltage EVSS to a second source voltage input terminal contained in the pixel PXL. When the display is driven, the pixel power matching circuit (PCT) can generate the first source voltage (EVDD) with a first value (EVDD1) and the second source voltage (EVSS) with a second value (EVSS1). As shown in Figures 6 and 7, because the first value (EVDD1) is higher than the second value (EVSS1), the light-emitting device (EL) of each pixel (PXL) can emit light when the display is driven with the display driver current (Iel). During scan control, the pixel power adjustment circuit (PCT) can generate the first source voltage EVDD with a third value EVDD2 and the second source voltage EVSS with a fourth value EVSS2. As shown in Figures 6 and 7, the third value EVDD2 can be higher than the reference voltage Vref and can be lower than the fourth value EVSS2. Since the third value EVDD2 is higher than the reference voltage Vref, the driver current Isen can be generated during scan control. Since the third value EVDD2 is lower than the fourth value EVSS2, the driver current Isen cannot flow to the light-emitting device EL, but can instead flow to the reference voltage line 150 during scan control, thus preventing the light-emitting device EL from emitting unwanted light. The Comparator & Trace Unit (CTS) can operate during sampling but cannot operate during display driving. The CTS can compare the driver current Isen, input from the reference voltage line 150, with a predetermined low reference current REF-LOW and a predetermined high reference current REF-HIGH, thus checking whether the driver current Isen lies within one current period (i.e., a target current range) between the low reference current REF-LOW and the high reference current REF-HIGH. Furthermore, the CTS can perform a rapid tracking feedback operation until the driver current Isen is within the target current range, and can therefore modify the current tracking data TDATA to set a level of the sampling data voltage VSEN. For example, if, as in Fig. 6, a first driver current Is1, corresponding to the first sample data voltage VSEN1, is higher than the target current range, the comparator and tracker (CTS) can reduce the current tracking data TDATA so that the second sample data voltage VSEN2 can be applied to pixel PXL. Subsequently, if a second driver current Is2, corresponding to the second sample data voltage VSEN2, is lower than the target current range, the CTS can increase the current tracking data TDATA so that the third sample data voltage VSEN3 can be applied to pixel PXL. If the driver current Isen is within the target current range as a result of the fast tracking feedback operation, the comparator and tracker (CTS) can stop an operation to modify the current tracking data TDATA and calculate a threshold voltage of the driver element DT based on the driver current Isen at that specific value. In other words, the CTS can calculate a gate-source voltage (VSEN-Vref) of the driver element DT that corresponds to the driver current Isen at that specific value, as the threshold voltage of the driver element DT. For example, if, as in Fig. 6, a third driver current Is3, corresponding to the third sample data voltage VSEN3, is within the target current range, the comparator & tracker unit CTS can calculate a gate-source voltage (VSEN3-Vref) of the driver element DT, corresponding to the third driver current Is3, as the threshold voltage of the driver element DT. Here, the gate-source voltage (VSEN3-Vref) of the driver element DT can be a differential voltage between the third sampling data voltage VSEN3, which is applied to the gate electrode of the driver element DT via data line 140, and the reference voltage Vref, which is applied to the source electrode of the driver element DT via reference voltage line 150. The third sampling data voltage VSEN3 can be the sampling data voltage VSEN whose level is set for the third driver current Is3, and the reference voltage Vref can have a fixed level independent of the level of the driver current Isen. To perform the fast feedback operation, the Comparator & Trace Unit (CTS) can include a current buffer (CBuF), a first current comparator (COMP1), a second current comparator (COMP2), a logic circuit (CP), and an application-specific integrated circuit (ASIC). The current buffer CBuF can supply the reference voltage Vref (see Fig. 9) to the reference voltage line 150 and mirror the driver current Isen input via the reference voltage line 150 to output the mirrored driver current to a node Nx. The current buffer CBuF can prevent a direct connection between the reference voltage line 150 and node Nx, thus preventing the panel noise contained in the driver current Isen from being transmitted to the first current comparator COMP1 and the second current comparator COMP2. The current buffer CBuF can increase the noise immunity of the driver current Isen, which is a super-low current. The first current comparator COMP1 can compare the high reference current REF-HIGH with the driver current Isen input via node Nx to output a first comparison result signal C1. The first current comparator COMP1 can have a first non-inverting input (+) connected to node Nx, a first inverting input (-) connected to a first current source A1 that generates the high reference current REF-HIGH, and a first output that outputs the first comparison result signal C1. Since the first current comparator COMP1 compares the high reference current REF-HIGH of the first inverting input terminal (-) with the driver current Isen input via the first non-inverting input terminal (+), the first current comparator COMP1 can output the first comparison result signal C1 as a high logic value "1" if the driver current Isen is greater than the high reference current REF-HIGH, as shown in Fig. 8, and if the driver current Isen is less than or equal to the high reference current REF-HIGH, the first current comparator COMP1 can output the first comparison result signal C1 as a low logic value "0". Because the low reference current REF-LOW is lower than the high reference current REF-HIGH, a region where the driver current Isen is lower than the low reference current REF-LOW can be contained within a region where the driver current Isen is lower than the high reference current REF-HIGH.Even in this case, the first current comparator COMP1, as shown in Fig. 8, can output the first comparison result signal C1 as a low logical value “0”. The second current comparator COMP2 can compare the low reference current REF-LOW with the driver current Isen input via node Nx to output a second comparison result signal C2. The second current comparator COMP2 can have a second inverting input terminal (-) connected to node Nx, a second non-inverting input terminal (+) connected to a second current source A2 that generates the low reference current REF-LOW, and a second output terminal that outputs the second comparison result signal C2. Since the second current comparator COMP2 compares the low reference current REF-LOW of the second non-inverting input (+) with the driver current Isen input via the second inverting input (-), the second current comparator COMP2 can output the second comparison result signal C2 as a high logic value "1" if the driver current Isen is less than the low reference current REF-LOW, as shown in Fig. 8, and if the driver current Isen is greater than or equal to the low reference current REF-LOW, the second current comparator COMP2 can output the second comparison result signal C2 as a low logic value "0". Because the low reference current REF-LOW is lower than the high reference current REF-HIGH, a region where the driver current Isen is higher than the high reference current REF-HIGH can be contained within a region where the driver current Isen is higher than the low reference current REF-LOW. Even in this case, as shown in Fig.8 , the second current comparator COMP2 can output the second comparison result signal C2 as a low logical value “0”. The logic circuit CP can be connected to the first output terminal of the first current comparator COMP1 and the second output terminal of the second current comparator COMP2. The logic circuit CP can generate a data matching signal FO based on a logical value of the first comparison result signal C1 and a logical value of the second comparison result signal C2. If the logical value of the first comparison result signal C1 differs from the logical value of the second comparison result signal C2, the logic circuit CP can output either a downward control signal DN or an upward control signal UP as a data adjustment signal FO, and if the logical value of the first comparison result signal C1 is equal to the logical value of the second comparison result signal C2, the logic circuit CP can output a hold control signal HOLD as a data adjustment signal FO. In the embodiment of Fig. 8, if the first comparison result signal C1 has a high logical value "1" and the second comparison result signal C2 has a low logical value "0", the logic circuit CP can output the downward control signal DN as the data adjustment signal FO. If the first comparison result signal C1 has a low logical value "0" and the second comparison result signal C2 has a high logical value "1", the logic circuit CP can output the upward control signal UP as the data adjustment signal FO. If both the first comparison result signal C1 and the second comparison result signal C2 have a low logical value "0", the logic circuit CP can output the hold control signal HOLD as the data setting signal FO. The application-specific integrated circuit (ASIC) can decrease, increase, or hold the current tracking data (TDATA) based on the data adjustment signal (FO) input by the logic circuit (CP). The ASIC can decrease the value of the current tracking data (TDATA) based on the downward control signal (DN), increase the value of the current tracking data (TDATA) based on the upward control signal (UP), and hold the value of the current tracking data (TDATA) unchanged based on the hold control signal (HALTEN). The current tracking data TDATA can be supplied by the application-specific integrated circuit ASIC to the digital-to-analog converter DAC. Based on a reduction of the current tracking data TDATA, as shown in Fig. 6, the digital-to-analog converter DAC can generate the second sample data voltage VSEN2, which is lower than the first sample data voltage VSEN1, which is a previous value, and can supply the second sample data voltage VSEN2 to data line 140. Accordingly, the driver current Isen output by the driver element DT to the reference voltage line 150 can be the second driver current Is2, which is lower than the first driver current Is1. Based on an increase in the current tracking data TDATA, as shown in Fig. 6, the digital-to-analog converter DAC can generate the third sample data voltage VSEN3, which is greater than the second sample data voltage VSEN2, which is a previous value, and can supply the third sample data voltage VSEN3 to data line 140. Accordingly, the driver current Isen output by the driver element DT to the reference voltage line 150 can be the third driver current Is3, which is higher than the second driver current Is2. Based on holding the current tracking data TDATA, as shown in Fig. 6, the digital-to-analog converter DAC can generate the third sample data voltage VSEN3, which is a previous value, and can supply the third sample data voltage VSEN3 to data line 140. Accordingly, the driver current Isen output by the driver element DT to the reference voltage line 150 can hold the third driver current Is3, which is a previous value. Since the HOLD control signal is generated when a driver current of a corresponding pixel is within a target current range, the application-specific integrated circuit ASIC can detect a gate-source voltage of a driver element contained in the corresponding pixel based on a sample data voltage corresponding to the HOLD control signal and calculate the gate-source voltage as the threshold voltage of the driver element. Fig. 9 is a diagram showing an example of the CbuF current buffer in the driver system of Fig. 5. As shown in Fig. 9, the CbuF current buffer can have an input unit, a mirror unit, and an output unit. The input unit can supply a reference voltage Vref to a reference voltage line 150 and receive a driver current Isen via the reference voltage line 150. The input unit can include an input amplifier AMP and an input transistor T1. The input amplifier AMP can have a non-inverting input terminal (+) through which the reference voltage Vref is applied, an inverting input terminal (-) connected to the reference voltage line 150, and an output terminal connected to node Na. The input transistor T1 can have a gate electrode connected to node Na, a drain electrode connected to the reference voltage line 150, and a source electrode connected to node Nb. The driver current Isen can be buffered in the input unit and supplied to the mirror unit. The input unit may further include a start switch SW, which is connected between the inverting input terminal (-) and the output terminal of the input amplifier AMP. The start switch SW can be turned on in a first period to supply the reference voltage Vref to the reference voltage line 150, and it can be turned off in a second period to receive the driver current Isen via the reference voltage line 150. When the start switch SW is turned on in the first period, the time required to load the reference voltage Vref into the reference voltage line 150 can be shorter than in a case where no start switch SW is present, and thus the sampling time can be further reduced. The mirror unit can be connected to the input unit via node Nb and mirror the driver current Isen so that the driver current Isen can flow in node Nc. The mirror unit can have a first mirror transistor T2 and a second mirror transistor T3. A gate electrode and a drain electrode of the first mirror transistor T2 can be connected to node Nb, and a source electrode of it can be connected to a ground voltage source GND. A gate electrode of the second mirror transistor T3 can be connected to node Nb, a drain electrode of the same to node Nc, and a source electrode of the same to the ground voltage source GND. The output unit can be connected to the mirror unit via node Nc and output the mirrored driver current Isen to node Nx. The output unit can have a first output transistor T4 and a second output transistor T5. A gate electrode and a source electrode of the first output transistor T4 can be connected to node Nc. A gate electrode of the second output transistor T5 can be connected to node Nc, and a source electrode of the same can be connected to node Nx. A drain electrode of the first output transistor T4 can be connected to a drain electrode of the second output transistor T5. Fig. 10 is a diagram showing a result obtained by comparing the time required to detect a threshold voltage of a driver element in the driver system of Fig. 5 with the prior art. As shown in Fig. 6, the level of a first source voltage EVDD and the level of a data voltage can be relatively lower during display drive than during sample drive. With respect to the first source voltage EVDD, EVDD2 for sample drive can be lower than EVDD1 for display drive. With respect to a data voltage Vdata, a sample data voltage VSEN can be lower than a display data voltage VDIS. Therefore, the driver current for sample drive can be lower than the driver current for display drive. Since, in the present embodiment, a driver current that is significantly lower than the display driver current is a benchmark for detecting a threshold voltage of the driver element, the sample attachment time can be easily reduced. Furthermore, to detect the threshold voltage of the driver element, a prior art technique is known in which a gate voltage of the driver element is set to a sampling data voltage DRG, and a source voltage DRS of the driver element is increased by using a source follower based on a driver current. In this technique, the source voltage DRS of the driver element and the voltage of a reference voltage line are increased until the gate-source voltage of the driver element corresponds to a threshold voltage φ of the driver element. However, due to a parasitic capacitance of the reference voltage line connected to a source electrode of the driver element, real-time sampling based on a vertical idle period is not possible with this technology, as the time (i.e., the sampling tack time TA) for detecting the threshold voltage of the driver element is long. On the other hand, according to the present disclosure, the control system can rapidly detect the threshold voltage of the driver element in a state where the influence of a parasitic capacitance of the reference voltage line is excluded, based on a fast tracking feedback configuration that relies on a current comparison operation. Thus, the sampling time TB can be significantly reduced compared to the prior art. With the sampling time TB reduced, sampling and compensation can be performed in real time, and the update period of a compensation value can be short, thereby significantly improving the threshold voltage compensation performance of the driver element. According to the embodiments of the present disclosure, a threshold voltage of a driver element in a state where a parasitic capacitance influence of a reference voltage line is excluded can be rapidly detected based on a fast tracking feedback configuration based on a current comparison operation, and thus a sampling time can be greatly reduced. With the sampling time reduced, real-time sampling and compensation can be performed, and the update period of a compensation value can be short, so that the threshold voltage compensation performance of the driver element can be greatly improved. The effects according to the present disclosure are not limited to the examples above, and other various effects may be included in the description. Although the present disclosure has been shown and described in particular by means of exemplary embodiments, it will be understandable to the person skilled in the art that various changes in form and details can be made without departing from the scope of the present disclosure as defined by the following claims.

Claims

Electroluminescent display device comprising: a pixel (PXL) connected to a data line (140) and a reference voltage line (150), wherein the pixel (PXL) includes a driver element (DT) configured to generate a driver current (Isen) based on a sample data voltage (VSEN) supplied via the data line (140) and a reference voltage (Vref) supplied via the reference voltage line (150), and wherein a level of the driver current (Isen) is proportional to a level of the sample data voltage (VSEN); a digital-to-analog converter (DAC) configured to set a level of the sample data voltage (VSEN) proportional to a magnitude of the current tracking data (TDATA) supplied to the digital-to-analog converter (DAC) and supplying the level-adjusted sample data voltage (VSEN) to the data line (140);a comparator and tracer circuit (CTS) configured to first determine a target current range between a low reference current (REF-LOW) and a high reference current (REF-HIGH) and modify the current trace data (TDATA) to set a level of the sample data voltage (VSEN) until the driver current (Isen) input via the reference voltage line (150) is within the target current range; and wherein, when the driver current (Isen) has a first value within the target current range, the comparator and tracer circuit (CTS) stops an operation to modify the current trace data (TDATA) and calculates a threshold voltage (Vth) of the driver element (DT) based on the driver current (Isen) with the first value. Electroluminescent display device according to claim 1, wherein the comparator and tracker circuit (CTS) calculates a gate-source voltage (Vgs) of the driver element (DT) corresponding to the driver current (Is1) with the first value as the threshold voltage (Vth) of the driver element (DT), the gate-source voltage (Vgs) of the driver element (DT) is a voltage difference between a first sampling data voltage (VSEN1) applied to a gate electrode of the driver element (DT) via the data line (140) and the reference voltage (Vref) applied to a source electrode of the driver element (DT) via the reference voltage line (150), the first sampling data voltage (VSEN1) is the sampling data voltage (VSEN) whose level is set such that the driver current (Is1) has the first value, and the reference voltage (Vref) has a fixed value independent of the magnitude of the driver current (Isen). Electroluminescent display device according to claim 1 or 2, wherein the comparator and tracker (CTS) circuit comprises: a current buffer (CBuf) configured to supply the reference voltage (Vref) to the reference voltage line (150) and to mirror the driver current (Isen) input via the reference voltage line (150) to output a mirrored driver current (Isen) to a first node (NX); a first current comparator (COMP1) configured to compare the high reference current (REF-HIGH) with the driver current (Isen) input via the first node (NX) to output a first comparator result signal (C1); a second current comparator (COMP2) configured to compare the low reference current (REF-LOW) with the driver current (Isen) input via the first node (NX) to output a second comparator result signal (C2);a logic circuit (CP) configured to output a data adjustment signal (FO) based on a logical value of the first comparison result signal (C1) and a logical value of the second comparison result signal (C2); and an application-specific integrated circuit (ASIC) configured to decrease (DN), increase (UP), or hold (HOLD) the current tracking data (TDATA) based on the data adjustment signal (FO). Electroluminescent display device according to claim 3, wherein the first current comparator (COMP1) has a first non-inverting input terminal (+) connected to the first node (NX) and a first inverting input terminal (-) connected to a first current source (A1) generating the high reference current (REF-HIGH), and the second current comparator (COMP2) has a second inverting input terminal (-) connected to the first node (NX) and a second non-inverting input terminal (+) connected to a second current source (A2) generating the low reference current (REF-LOW). Electroluminescent display device according to claim 3 or 4, wherein, if the logical value of the first comparison result signal (C1) differs from the logical value of the second comparison result signal (C2), the logic circuit (CP) outputs either a downward control signal (DN) or an upward control signal (UP) as a data adjustment signal (FO), and if the logical value of the first comparison result signal (C1) is the same as the logical value of the second comparison result signal (C2), the logic circuit (CP) outputs a hold control signal (HOLD) as a data adjustment signal (FO). Electroluminescent display device according to claim 5, wherein, when the logical value of the first comparison result signal (C1) is logically high and the logical value of the second comparison result signal (C2) is logically low, the downward control signal (DN) is output as the data adjustment signal (FO), when the logical value of the first comparison result signal (C1) is logically low and the logical value of the second comparison result signal (C2) is logically high, the upward control signal (UP) is output as the data adjustment signal (FO), and when both the logical value of the first comparison result signal (C1) and the logical value of the second comparison result signal (C2) are logically low, the hold control signal (HOLD) is output as the data adjustment signal (FO). Electroluminescent display device according to claim 6, wherein the application-specific integrated circuit (ASIC) decreases a value of the current tracking data (TDATA) based on the down control signal (DN), increases the value of the current tracking data (TDATA) based on the up control signal (UP), and holds the current tracking data (TDATA) unchanged based on the hold control signal (HOLD). Electroluminescent display device according to any one of claims 3 to 7, wherein the current buffer (CBuF) comprises: an input circuit configured to supply the reference voltage (Vref) to the reference voltage line (150) and to receive the driver current (Isen) via the reference voltage line (150); a mirror circuit connected to the input circuit via a second node (Nb) to mirror the driver current (Isen); and an output circuit connected to the mirror circuit via a third node to output a mirrored driver current (Isen) to the first node (NX). Electroluminescent display device according to claim 8, wherein the input circuit comprises: an input amplifier (AMP) with a non-inverting input terminal (+) through which the reference voltage (Vref) is input, an inverting input terminal (-) connected to the reference voltage line (150), and an output terminal connected to a fourth node (Na); and an input transistor (T1) with a gate electrode connected to the fourth node (Na), a drain electrode connected to the reference voltage line (150), and a source electrode connected to the second node (Nb). Electroluminescent display device according to claim 9, wherein the input circuit further comprises a start switch (SW1) which is connected between the inverting input terminal (-) and the output terminal of the input amplifier (AMP), and the start switch (SW1) is turned on in a first period to supply the reference voltage (Vref) to the reference voltage line (150), and is turned off in a second period to receive the driver current (Isen) via the reference voltage line (150). Electroluminescent display device according to any one of claims 1 to 10, wherein the pixel (PXL) further comprises a first source voltage terminal (EVDD) connected to a drain electrode of the driver element (DT), a light-emitting device (EL) with an anode electrode connected to a source electrode of the driver element (DT), and a second source voltage terminal (EVSS) connected to a cathode electrode of the light-emitting device (EL), a first source voltage applied to the first source voltage terminal (EVDD) being higher than the reference voltage (Vref) and lower than a second source voltage applied to the second source voltage terminal (EVSS), and the driver current (Isen) not flowing to the light-emitting device (EL) but flowing to the reference voltage line (150). Control method for an electroluminescent display device with one pixel (PXL) connected to a data line (140) and a reference voltage line (150) and comprising a driver element (DT) configured to generate a driver current (Isen) based on a sampling data voltage (VSEN) supplied via the data line (140) and a reference voltage (Vref) supplied via the reference voltage line (150), wherein a level of the driver current (Isen) is proportional to a level of the sampling data voltage (VSEN), wherein the control method comprises: adjusting by a digital-to-analog converter (DAC) a level of the sampling data voltage (VSEN) such that it is proportional to a magnitude of the current tracking data (TDATA), and supplying the level-adjusted sampling data voltage (VSEN) to the data line (140);Predetermine a target current range between a low reference current (REF-LOW) and a high reference current (REF-HIGH) and modify current tracking data (TDATA) to adjust the level of the sampled data voltage (VSEN) until the driver current (Isen) input by the driver element (DT) via the reference voltage line (150) is within the target current range; and when the driver current (Isen) is within the target current range with a first value, stop an operation to modify the current tracking data (TDATA) and calculate a threshold voltage (Vth) of the driver element (DT) based on the driver current (Isen) with the first value. Control method according to claim 12, wherein the calculation of the threshold voltage (Vth) of the driver element (DT) comprises the calculation of a gate-source voltage (Vgs) of the driver element (DT) corresponding to the driver current (Is1) with the first value, as the threshold voltage (Vth) of the driver element (DT), the gate-source voltage (Vgs) of the driver element (DT) being a voltage difference between a first sampling data voltage (VSEN1) applied to a gate electrode of the driver element (DT) via the data line (140) and the reference voltage (Vref) applied to a source electrode of the driver element (DT) via the reference voltage line (150), the first sampling data voltage (VSEN1) being the sampling data voltage (VSEN) whose level is set such that the driver current (Is1) has the first value, and the reference voltage (Vref) being independent of the magnitude of the driver current (Isen) has a fixed value.

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