CAPACITOR STRUCTURE

Abstract

Capacitor structure (100a), comprising: a first metal conduit (140a); a second metal conduit (142a); a plurality of first capacitor cells (10a, 10b) connected in parallel between the first metal conductor (140a) and the second metal conductor (142a), each of the first capacitor cells (10a, 10b) having the following: a first lower electrode (130a) which is connected to the first metal conductor (140a); a first dielectric (133) above the first lower electrode (130a); and a first upper electrode (135a) above the first dielectric (133), which is connected to the second metal conductor (142a); and a plurality of second capacitor cells (20a, 20b) connected in parallel between the first metal conductor (140a) and the second metal conductor (142a), each of the second capacitor cells (20a, 20b) having the following: a second lower electrode (132a) which is connected to the second metal conductor (142a); a second dielectric (133) above the second lower electrode (132a); and a second upper electrode (137a) above the second dielectric (133), which is connected to the first metal conductor (140a); characterized in that the first capacitor cells (10a, 10b) and the second capacitor cells (20a, 20b) overlap the first and the second metal conductor (140a, 142a), and the first capacitor cells (10a, 10b) and the second capacitor cells (20a, 20b) are arranged alternately under the first and the second metal conductor (140a, 142a).

Description

BACKGROUND OF THE INVENTIONField of Invention

[0001] The invention relates to a capacitor array and in particular to a capacitor array with low equivalent series inductance (ESL). Description of the state of the art

[0002] Integrated circuits (ICs) have become increasingly important. Applications that use ICs are used by millions of people. These applications include mobile phones, smartphones, tablets, laptops, notebook computers, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless web browsers. Integrated circuits increasingly feature powerful and efficient onboard data storage and logic circuitry for signal control and processing.

[0003] As high-performance ICs require more power at higher frequencies with lower supply voltages, power system design becomes increasingly challenging. It becomes increasingly important to use a decoupling capacitor to reduce power noise when a digital circuit such as a microprocessor contains numerous transistors that alternate between on and off states.

[0004] A capacitor structure according to the preamble of patent claim 1 is known from US 2012 / 0 211 868 A1. Further capacitor structures are known from US 2020 / 0 279 908 A1 and US 2021 / 0 074 629 A1. BRIEF SUMMARY OF THE INVENTION

[0005] The invention relates to a capacitor structure according to claim 1.

[0006] Furthermore, the invention relates to a capacitor structure according to claim 10.

[0007] A detailed description is given in the following embodiments with reference to the accompanying drawings. Preferred embodiments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention can be better understood by reading the following detailed description and examples with reference to the accompanying drawings, in which: Fig. 1 is a schematic showing a capacitor array according to some embodiments of the invention. Fig. Figure 2 shows the capacitor structure of the region in the capacitor array of Fig. 1 according to some embodiments of the invention. Fig. Figure 3A shows a cross-sectional view of the capacitor cell along the line A-AA in Fig. 2 according to some embodiments of the disclosure. Fig. Figure 3B shows a cross-sectional view of the capacitor cell along the line B-BB in Fig. 2 according to some embodiments of the disclosure. Fig. Figure 3C shows a cross-sectional view of the capacitor cell along the line C-CC in Fig. 2 according to some embodiments of the disclosure. Fig. 4 shows a cross-sectional view of the capacitor cell according to some embodiments of the disclosure. Fig. 5 shows a circuit diagram of row ROW2 in Fig. 2 according to some embodiments of the invention. Fig. 6 is a schematic showing a capacitor array according to some embodiments of the invention. Fig. Figure 7 shows a capacitor structure of the region in the capacitor array of Fig. 6 according to some embodiments of the invention. Fig. 8 is a schematic showing a capacitor array according to some embodiments of the invention. Fig. Figure 9 shows the capacitor structure of the region in the capacitor array of Fig. 8 according to some embodiments of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following description concerns the most preferred embodiment of the invention. This description is intended to describe the general principles of the invention. The scope of the invention is best determined by reference to the appended claims.

[0010] Some variations of the embodiments are described. Like reference numerals are used to refer to like elements throughout the various views and exemplary embodiments. It is understood that additional operations may be provided before, during, and / or after a disclosed method, and that some of the described operations may be substituted or omitted for further embodiments of the method.

[0011] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures.

[0012] Fig. 1 is a schematic diagram illustrating a capacitor array 100A according to some embodiments of the invention. The capacitor array 100A includes a plurality of capacitor cells 10 and a plurality of capacitor cells 20. In the capacitor array 100A, the capacitor cells 10 and 20 are arranged alternately in each row. Furthermore, the columns formed by the capacitor cells 10 and the columns formed by the capacitor cells 20 are arranged alternately. In some embodiments, the capacitor cells 10 are arranged in odd columns, and the capacitor cells 20 are arranged in even columns. In some embodiments, the capacitor cells 20 are arranged in odd columns, and the capacitor cells 10 are arranged in even columns.

[0013] In some embodiments, capacitor cells 10 and capacitor cells 20 have the same capacitance. In some embodiments, capacitor cells 10 and capacitor cells 20 have a similar structure. For example, the upper electrodes of capacitor cells 10 and 20 are formed in the same upper metal layer (i.e., on the same plane), and the lower electrodes of capacitor cells 10 and 20 are formed in the same lower metal layer (i.e., on the same plane). In addition, the difference between capacitor cells 10 and capacitor cells 20 is that the connection configuration of capacitor cells 10 and 20 is different. For example, each upper electrode of capacitor cells 10 is connected to a power line (e.g., VDD) via the corresponding metal lines, and each upper electrode of capacitor cells 20 is connected to a ground line (e.g.,VSS / GND). Furthermore, each lower electrode of the capacitor cells 10 is connected to a ground line via the corresponding metal lines, and each lower electrode of the capacitor cells 20 is connected to a power line via the corresponding metal lines. The capacitor array 100A acts as a decoupling capacitor between the power line and the ground line.

[0014] Fig. Figure 2 shows the capacitor structure of region 102A in the capacitor array 100A of Fig. 1 according to some embodiments of the invention. In region 102A, capacitor cells 10a, 20a, 10b, and 20b are arranged alternately in row ROW2. Capacitor cell 10a has bottom electrode 130a and top electrode 135a, with bottom electrode 130a having a larger area than top electrode 135a. Capacitor cell 20a has bottom electrode 132a and top electrode 137a, with bottom electrode 132a having a larger area than top electrode 137a. Capacitor cell 10b has bottom electrode 130b and top electrode 135b, with bottom electrode 130b having a larger area than top electrode 135b. Capacitor cell 20b includes lower electrode 132b and upper electrode 137b, with lower electrode 132b having a larger area than upper electrode 137b. Furthermore, in capacitor array 100A, the number of capacitor cells 10 is equal to the number of capacitor cells 20.

[0015] The bottom electrodes of capacitor cells 10 and 20 have the same area. For example, bottom electrode 130a of capacitor cell 10a and bottom electrode 132a of capacitor cell 20a have the same area. Furthermore, the top electrodes of capacitor cells 10 and 20 have a first area. For example, top electrode 135a of capacitor cell 10a and top electrode 137a of capacitor cell 20a have a second area. In some embodiments, the bottom electrode of capacitor cell 10 / 20 is connected to the corresponding signal line via the top connection structure, and the first area is larger than the second area. In some embodiments, the bottom electrode of capacitor cell 10 / 20 is connected to the corresponding signal line via the bottom connection structure, and the first area is less than or equal to the second area.

[0016] In some embodiments, the lower electrodes 130a and 130b and the lower electrodes 132a and 132b are formed in a first metal layer, and the upper electrodes 135a and 135b and the upper electrodes 137a and 137b are formed in a second metal layer above the first metal layer. In some embodiments, the lower electrodes 130a, 130b, 132a, and 132b have the same area, and the upper electrodes 135a, 135b, 137a, and 137b have the same area. Additionally, the lower electrodes 130a, 130b, 132a, and 132b and the upper electrodes 135a, 135b, 137a, and 137b are formed from the same conductive material, e.g., tungsten (W).

[0017] Capacitor cells 10c, 20c, 10d, and 20d are arranged alternately in row ROW1. Similarly, bottom electrodes 130c and 130d and bottom electrodes 132c and 132d are formed in the first metal layer, and top electrodes 135c and 135d and top electrodes 137c and 137d are formed in the second metal layer. In some embodiments, bottom electrodes 130c, 130d, 132c, and 132d have the same area, and top electrodes 135c, 135d, 137c, and 137d have the same area, which is smaller than bottom electrodes 130c, 130d, 132c, and 132d.

[0018] The upper electrodes 135a to 135d and 137a to 137d extend in the Y direction. Furthermore, the upper electrodes arranged in the same column are separated from each other. For example, the upper electrode 135a is separated from the upper electrode 135c, and the upper electrode 137a is separated from the upper electrode 137c.

[0019] The lower electrodes 130a to 130d and 132a to 132d extend in the Y direction. Furthermore, the lower electrodes arranged in the same column are separated from each other. For example, the lower electrode 130a is separated from the lower electrode 130c, and the lower electrode 132a is separated from the lower electrode 132c. In some embodiments, the lower electrodes arranged in the same column are integrated into the same lower electrode. In other words, the lower electrodes arranged in the same column share the same lower electrode.

[0020] In Fig. 2, metal lines 140a to 140c and metal lines 142a to 142c are formed in the same metal layer and above capacitor cells 10a to 10d and 20a to 20d. Metal lines 140a to 140c and 142a to 142c extend in the X direction and are arranged alternately. For example, metal line 142a is arranged parallel to and between metal lines 140a and 140b, and metal line 140b is arranged parallel to and between metal lines 142a and 142b. The metal lines 140a to 140c are configured to supply the capacitor cells 10 and 20 with a first voltage signal, and the metal lines 142a to 142c are configured to supply the capacitor cells 10 and 20 with a second voltage signal, wherein the first voltage signal is different from the second voltage signal.In some embodiments, metal lines 140a to 140c are the ground lines, and metal lines 142a to 142c are the power lines. In some embodiments, metal lines 140a to 140c are the power lines, and metal lines 142a to 142c are the ground lines.

[0021] In row ROW2, metal lines 140a and 140b are connected to the lower electrodes 130a and 130b via vias (contacts or connection features) 148. Furthermore, metal lines 140a and 140b are connected to the upper electrodes 137a and 137b via vias (contacts or connection features) 145. Metal line 142a is connected to the lower electrodes 132a and 132b via vias 148. Furthermore, metal line 142a is connected to the upper electrodes 135a and 135b via vias 145. In row ROW1, metal line 140c is connected to the lower electrodes 130c and 130d via vias 148. Furthermore, the metal line 140c is connected to the upper electrodes 137c and 137d via the vias 145. The metal lines 142b and 142c are connected to the lower electrodes 132c and 132d via the vias 148.Furthermore, the metal lines 142b and 142c are connected to the upper electrodes 135c and 135d via the vias 145. It should be noted that the number of vias 145 and 148 is used as an example and does not limit the invention.

[0022] As described above, capacitor cells 10 and 20 have similar structures. The structure of capacitor cells 10 and 20 will be described below, taking capacitor cell 20a as an example. Furthermore, it is assumed that metal lines 140a to 140c are configured to provide ground signal VSS, and metal lines 142a to 142c are configured to provide power signal VDD.

[0023] Fig. 3A shows a cross-sectional view of the capacitor cell 20a along the line A-AA in Fig. 2 according to some embodiments of the disclosure. The bottom electrode 132a is formed over a semiconductor substrate 110. Metal lines 140a, 142a, and 140b are formed in a metal layer Mx over the bottom electrode 132a. The metal line 142a is connected to the bottom electrode 132a via vias 148. Thus, the current signal VDD is applied to the bottom electrode 132a via the vias 148 and the metal line 142a. The via 148 has a height (thickness or depth) H1.

[0024] Fig. 3B shows a cross-sectional view of the capacitor cell 20a along the line B-BB in Fig. 2 according to some embodiments of the disclosure. The bottom electrode 132a is formed over the semiconductor substrate 110. A dielectric 133 is formed over the bottom electrode 132a. The top electrode 137a is formed over the dielectric 133. Thus, the capacitor cell 20a consists of the bottom electrode 132a, the dielectric 133, and the top electrode 137a. Metal lines 140a, 142a, and 140b are formed over the top electrode 137a and in the metal layer Mx. The metal lines 140a and 140b are connected to the top electrode 137a via the vias 145. Thus, the ground signal VSS is applied to the top electrode 137a via the vias 145 and the metal lines 140a and 140b. The via 145 has a height (or thickness or depth) H2, and the via 145 is shorter than the via 148, ie the height H2 is smaller than the height H1 (H2 < H1).In the capacitor array 100A, the dielectrics of the capacitor cells 10 and 20 are formed by the same dielectric.

[0025] Fig. Figure 3C shows a cross-sectional view of the capacitor cell 20a along the line C-CC in Fig. 2 according to some embodiments of the disclosure. The bottom electrode 132a is formed over the semiconductor substrate 110. The dielectric 133 is formed over the bottom electrode 132a, and the top electrode 137a is formed over the dielectric 133. The metal line 140a is connected to the top electrode 137a via the vias 145. Thus, the ground signal VSS is applied to the top electrode 137a via the vias 145 and the metal line 140a. The metal line 142a is connected to the bottom electrode 132a via the vias 148. Thus, the power signal VDD is applied to the bottom electrode 132a via the vias 148 and the metal line 142a.

[0026] In the Fig. 3A to 3C, the capacitor cell 20a is formed over the semiconductor substrate 110, and the lower electrode 132a is in direct contact with the semiconductor substrate 110. In other words, no other device is formed between the lower electrode 132a and the semiconductor substrate 110. The respective voltages are applied to the upper electrode and the lower electrode of each capacitor cell via the metal lines above the capacitor cell.

[0027] In some embodiments, some devices (e.g., passive devices or active devices) are formed over the semiconductor substrate 110, and the capacitor array is formed over the devices. Therefore, the respective voltages are applied to the top electrode and the bottom electrode of a capacitor cell via the metal lines above the capacitor and / or the metal lines below the capacitor.

[0028] Fig. Figure 4 shows a cross-sectional view of the capacitor cell 20a according to some embodiments of the disclosure. In one such embodiment, the capacitor cell 20a is a metal-insulator-metal (MIM) capacitor. The capacitor cell 20a is formed over the devices (e.g., the passive devices, the active devices, or the memory cells). Fig. 4, the current signal VDD is applied from the metal line 142a via the via 125, the metal line 120b, and the via 122, and from the metal line 120a via the via 122 to the bottom electrode 132a. In some embodiments, the metal lines 120a and 120b are formed in the lowest metal layer. Furthermore, the via 125 has a height (or thickness, or depth) H3, and the via 125 is longer than the via 148, i.e., the height H1 is less than the height H3 (H1 < H3). Furthermore, the via 122 has a height (or thickness, or depth) H4, and the via 122 is shorter than the via 148, i.e., the height H4 is less than the height H1 (H4 < H1). In some embodiments, vias 122 and 145 have the same height, ie, height H4 is equal to height H2 (H4 = H2).

[0029] Fig. 5 shows a circuit diagram of row ROW2 in Fig. 2 according to some embodiments of the invention. Referring together to the Fig. 2 and Fig. 5, capacitor cells 10a, 20a, 10b, and 20b are connected in parallel between metal line 142a (VDD) and metal line 140a / 140b (i.e., VSS). Capacitor cell 10a is connected to metal line 142a via upper electrode 135a. Furthermore, capacitor cell 20a is further connected to metal line 142a (VDD) via lower electrode 132a. Furthermore, capacitor cell 10b is further connected to metal line 142a (VDD) via upper electrode 135b. Furthermore, capacitor cell 20b is further connected to metal line 142a (VDD) via lower electrode 132b. Capacitor cell 10a is connected to metal line 140a / 140b (VSS) via lower electrode 130a. Furthermore, the capacitor cell 20a is further connected to the metal line 140a / 140b (VSS) via the upper electrode 137a. Furthermore, the capacitor cell 10b is further connected to the metal line 140a / 140b (VSS) via the lower electrode 130b.In addition, the capacitor cell 20b is further connected to the metal line 140a / 140b (VSS) via the upper electrode 137b.

[0030] Capacitor cells 10a and 10b are separated by capacitor cell 20a, i.e., capacitor cell 20a is arranged between capacitor cells 10a and 10b. Capacitor cells 20a and 20b are separated by capacitor cell 10b, i.e., capacitor cell 10b is arranged between capacitor cells 20a and 20b. In the same row, capacitor cells 10 and 20 are arranged to overlap the corresponding metal lines. For example, capacitor cells 10a, 20a, 10b, and 20b overlap metal lines 140a, 142a, and 140b. Furthermore, capacitor cells 10a and 10b and capacitor cells 20a and 20b are arranged alternately under metal lines 140a, 142a, and 140b.

[0031] A magnetic field 210a forms in capacitor cell 10a because the current flows from the upper electrode 135a to the lower electrode 130a. A magnetic field 220a forms in capacitor cell 20a because the current flows from the lower electrode 132a to the upper electrode 137a. A magnetic field 210b forms in capacitor cell 10c because the current flows from the upper electrode 135b to the lower electrode 130b. A magnetic field 220b forms in capacitor cell 20b because the current flows from the lower electrode 132b to the upper electrode 137b.

[0032] In Fig. 5, the magnetic fields 210a and 210b and the magnetic fields 220a and 220b may exhibit inductive cancellation because the charges on the top electrode and bottom electrode of the capacitor cells 10 and the charges on the top electrode and bottom electrode of the capacitor cells 20 move in opposite directions, allowing the magnetic fields 210a and 210b and the magnetic fields 220a and 220b to cancel each other out rather than reinforcing each other.

[0033] Compared to conventional capacitor cells, where all upper electrodes are connected to the power signal VDD and all lower electrodes are connected to the ground signal VSS, the equivalent series inductance (ESL) does not increase as the number of capacitor cells in the capacitor array 100A increases. In some embodiments, the capacitor array 100A can act as a decoupling capacitor to reduce power noise caused by digital circuits that have numerous transistors switching between ON and OFF states.

[0034] Fig. Figure 6 is a schematic diagram showing a capacitor array 100B according to some embodiments of the invention. The capacitor array 100B includes a plurality of capacitor cells 10 and a plurality of capacitor cells 20. Compared to the capacitor array 100A of Fig. 1, capacitor cells 10 and 20 are arranged alternately in each row and each column in capacitor array 100B. Therefore, in capacitor array 100B, each capacitor cell 10 is surrounded by capacitor cells 20, and each capacitor cell 20 is surrounded by capacitor cells 10. Furthermore, in capacitor array 100B, the number of capacitor cells 10 is equal to the number of capacitor cells 20.

[0035] Fig. 7 shows a capacitor structure of the region 102B in the capacitor array 100B of Fig. 6 according to some embodiments of the invention. In region 102B, the capacitor cells 10a, 20a, 10b, and 20b are arranged alternately in the upper row. Furthermore, the connection configuration between the capacitor cells 10a, 20a, 10b, and 20b and the metal lines 140a, 142a, and 140b in row ROW4 is similar to the related configuration in row ROW2 of Fig. 2.

[0036] In Fig. 7, capacitor cells 20c, 10c, 20d, and 10d are arranged alternately in row ROW3. Capacitor cell 20c and capacitor cell 10a are arranged in the same column, and capacitor cell 10c and capacitor cell 20a are arranged in the same column. Furthermore, capacitor cell 20d and capacitor cell 10b are arranged in the same column, and capacitor cell 10d and capacitor cell 20b are arranged in the same column.

[0037] Similar to Fig. 2, metal lines 140a to 140c and metal lines 142a to 142c are formed over capacitor cells 10a to 10d and 20a to 20d. Metal lines 140a to 140c and 142a to 142c extend in the X direction and are arranged alternately. Furthermore, assume that metal lines 140a to 140c are configured to provide ground signal VSS, and metal lines 142a to 142c are configured to provide power signal VDD. Note that the lower electrodes arranged in the same column are separated from each other.

[0038] In row ROW3, ​​metal line 140c is connected to the lower electrodes 130c and 130d via vias 148, and metal line 140c is connected to the upper electrodes 137c and 137d via vias 145. Metal lines 142b and 142c are connected to the lower electrodes 132c and 132d via vias 148, and metal lines 142b and 142c are connected to the upper electrodes 135c and 135d via vias 145. Thus, capacitor cells 10 and capacitor cells 20 can be arranged in the capacitor array (e.g., 100A or 100B) in any known manner by determining the order of the power lines and ground lines and determining the arrangement of vias 145 and 148.

[0039] Fig. 8 is a schematic diagram showing a capacitor array 200 according to some embodiments of the invention. The capacitor array 200 includes a plurality of capacitor cells 30 and a plurality of capacitor cells 40. In the capacitor array 200, the columns formed by the capacitor cells 30 and the columns formed by the capacitor cells 40 are arranged alternately. In some embodiments, the capacitor cells 30 are arranged in odd columns, and the capacitor cells 40 are arranged in even columns. In some embodiments, the capacitor cells 40 are arranged in odd columns, and the capacitor cells 30 are arranged in even columns. In some embodiments, the capacitor cells 30 and the capacitor cells 40 have the same capacitance. In some embodiments, the capacitor cells 30 and the capacitor cells 40 have a similar structure.For example, each upper electrode of capacitor cells 30 and 40 is formed in the same upper metal layer, and each lower electrode of capacitor cells 30 and 40 is formed in the same lower metal layer. In addition, the difference between capacitor cells 30 and capacitor cells 40 is that the connection configuration of capacitor cells 30 and 40 is different. For example, each upper electrode of capacitor cells 30 is connected to a power line (e.g., VDD) via the corresponding metal lines, and each upper electrode of capacitor cells 40 is connected to a ground line (e.g., VSS / GND) via the corresponding metal lines. Furthermore, each lower electrode of capacitor cells 30 is connected to a ground line via the corresponding metal lines, and each lower electrode of capacitor cells 40 is connected to a power line via the corresponding metal lines.Furthermore, in the capacitor array 200, the number of capacitor cells 30 is equal to the number of capacitor cells 40.

[0040] Fig. Figure 9 shows the capacitor structure of region 202 in the capacitor array 200 of Fig. 8 according to some embodiments of the invention. In region 202, capacitor cells 30a, 30b, and 30c are arranged in column COL1. Capacitor cell 30a consists of bottom electrode 230a, top electrode 235a (indicated by a dashed line), and the dielectric (not shown) between electrodes 230a and 235a. In such an embodiment, the top electrode of each capacitor cell 30 / 40 is indicated by a dashed line. Top electrode 235a is connected to metal line 242a via vias (contacts or connection features) 245. Capacitor cell 30b consists of bottom electrode 230a, top electrode 235b, and the dielectric (not shown). Top electrode 235b is connected to metal line 242b via vias 245. In addition, the capacitor cell 30c consists of the lower electrode 230a, the upper electrode 235c and the dielectric (not shown).The upper electrode 235c is connected to the metal line 242c via the vias 245. It should be noted that the capacitor cells 30a, 30b, and 30c share the lower electrode 230a. The lower electrode 230a is connected to the metal lines 240a and 240b via the vias 248. In such an embodiment, the metal lines 242a to 242c are configured to provide the power signal VDD, and the metal lines 240a and 240b are configured to provide the ground signal VSS. Furthermore, the via 245 is shorter than the via 248.

[0041] Capacitor cells 40a and 40b are arranged in column COL2. Capacitor cell 40a consists of the bottom electrode 232a, the top electrode 237a, and the dielectric (not shown) between the electrodes 232a and 237a. The top electrode 237a is connected to the metal line 240a via vias 245. Capacitor cell 40b consists of the bottom electrode 232a, the top electrode 237b, and the dielectric (not shown). The top electrode 237b is connected to the metal line 240b via vias 245. Similarly, capacitor cells 40a and 40b arranged in the same column share the same bottom electrode 232a. The lower electrode 232a is connected to the metal lines 242a, 242b, and 242c via the vias 248. Furthermore, the dielectric of the capacitor cells 30 and 40 is formed by the same dielectric.

[0042] Capacitor cells 30d, 30e, and 30f are arranged in column COL3. Capacitor cell 30d consists of the lower electrode 230b, the upper electrode 235d, and the dielectric (not shown) between electrodes 230b and 235d. The upper electrode 235d is connected to the metal line 242a via vias 245. Capacitor cell 30e consists of the lower electrode 230b, the upper electrode 235e, and the dielectric (not shown). The upper electrode 235e is connected to the metal line 242b via vias 245. Capacitor cell 30f consists of the lower electrode 230b, the upper electrode 235f, and the dielectric (not shown). The upper electrode 23fe is connected to the metal line 242c via vias 245. Similarly, capacitor cells 30d, 30e, and 30f arranged in the same column share the same lower electrode 230b.The lower electrode 230b is connected to the metal lines 240a and 240b via the vias 248.

[0043] Capacitor cells 40d and 40e are arranged in column COL4. Capacitor cell 40d consists of the bottom electrode 232b, the top electrode 237d, and the dielectric (not shown) between the electrodes 232b and 237d. The top electrode 237d is connected to the metal line 240a via vias 245. Capacitor cell 40e consists of the bottom electrode 232b, the top electrode 237e, and the dielectric (not shown). The top electrode 237e is connected to the metal line 240b via vias 245. Similarly, capacitor cells 40d and 40e arranged in the same column share the same bottom electrode 232b. The lower electrode 232b is connected to the metal lines 242a, 242b and 242c via the vias 248.

[0044] The upper electrodes of capacitor cells 30 and 40 have the same area. For example, the upper electrode 235b of capacitor cell 30b and the upper electrode 237a of capacitor cell 40a have the same area. Furthermore, the lower electrodes of capacitor cells 30 and 40 have a larger area than the upper electrodes of capacitor cells 30 and 40. For example, the area of ​​the lower electrode 230a is larger than that of the upper electrodes 235a, 235b, and 235c.

[0045] Compared to the 100A capacitor array from Fig. 2 and the capacitor array 100B of Fig. 7, in which the metal lines 140a to 140c and the metal lines 142a to 142c have a fixed width, the metal lines 240a and 240b and the metal lines 242a to 242c in the capacitor array 200 have multiple widths. For example, the metal lines 240a and 240b have a width W1 in the columns COL1 and COL3 and a width W2 in the columns COL2 and COL4, and the width W1 is smaller than the width W2 (i.e., W1 < W2). The width W2 is large enough to completely cover the top electrodes 237a, 237b, 237d, and 237e of the capacitor cells 40a, 40b, 40d, and 40e. Similarly, the metal lines 242a to 242c have the narrower width (e.g., width W1) in the columns COL2 and COL4 and the larger width (e.g., width W2) in the columns COL1 and COL3.

[0046] Taking the metal line 242a (VDD) and the metal line 240a (VSS) as an example, the capacitor cells 30a, 40a, 30d, and 40d are connected in parallel between the power line (i.e., the metal line 242a) and the ground line (i.e., the metal line 240a). The capacitor cells 30a and 30d are separated by the capacitor cell 40a, and the capacitor cells 40a and 40d are separated by the capacitor cell 30d. The magnetic fields of the capacitor cells 30a and 30d are opposite to the magnetic fields of the capacitor cells 40a and 40d, thereby causing inductive cancellation. Compared to the capacitor array 100A of Fig. 2 and the capacitor array 100B of Fig.7, in which the upper electrodes in capacitor cells 10 and 20 are connected to the corresponding metal lines via the different number of vias 145, the upper electrodes in capacitor cells 30 and 40 are connected to the corresponding metal lines via the same number of vias 245. For example, the upper electrode 135a of capacitor cell 10a is connected to the metal line 142a via nine vias 145, and the upper electrode 135c of capacitor cell 10c is connected to the metal lines 142b and 142c via eighteen vias 145, whereby the arrangement of vias 145 in capacitor arrays 100A and 100B is non-uniform.In the capacitor array 200, each upper electrode of the capacitor cells 30 and 40 is connected to the corresponding metal line via twelve vias 245, whereby the arrangement of the vias 245 is uniform, making it more suitable for induction cancellation.

Claims

[1] Capacitor structure (100a), comprising: a first metal line (140a); a second metal line (142a); a plurality of first capacitor cells (10a, 10b) connected in parallel between the first metal line (140a) and the second metal line (142a), each of the first capacitor cells (10a, 10b) comprising: a first lower electrode (130a) connected to the first metal line (140a); a first dielectric (133) over the first lower electrode (130a); and a first upper electrode (135a) over the first dielectric (133) connected to the second metal line (142a); and a plurality of second capacitor cells (20a, 20b) connected in parallel between the first metal line (140a) and the second metal line (142a), each of the second capacitor cells (20a, 20b) comprising: a second lower electrode (132a) connected to the second metal line (142a); a second dielectric (133) over the second lower electrode (132a); and a second upper electrode (137a) over the second dielectric (133) connected to the first metal line (140a); characterized by that the first capacitor cells (10a, 10b) and the second capacitor cells (20a, 20b) overlap the first and second metal lines (140a, 142a), and the first capacitor cells (10a, 10b) and the second capacitor cells (20a, 20b) are arranged alternately under the first and second metal lines (140a, 142a). [2] The capacitor structure according to claim 1, wherein two adjacent first capacitor cells (10a, 10b) are separated by one of the second capacitor cells (20a) and two adjacent second capacitor cells (20a, 20b) are separated by one of the first capacitor cells (10b). [3] The capacitor structure according to claim 1 or 2, wherein the first lower electrodes (130a, 130b) of the first capacitor cells (10a, 10b) and the second lower electrodes (132a, 132b) of the second capacitor cells (20a, 20b) are formed on the same plane, and wherein the first upper electrodes (135a, 135b) of the first capacitor cells (10a, 10b) and the second upper electrodes (137a, 137b) of the second capacitor cells (20a, 20b) are formed on the same plane. [4] A capacitor structure according to any one of the preceding claims, wherein the first and second metal lines (140a, 142a) are formed in the same metal layer (Mx) over the first and second capacitor cells (10, 20). [5] The capacitor structure of claim 4, wherein the first lower electrode (130a, 130b) of each of the first capacitor cells (10a, 10b) is connected to the first metal line (140a) via a plurality of first connection features (148), and the first upper electrode (135a, 135b) of each of the first capacitor cells (10a, 10b) is connected to the second metal line (142a) via a plurality of second connection features (145), wherein a first height (H1) of the first connection features (148) is greater than a second height (H2) of the second connection features (145). [6] The capacitor structure of claim 5, wherein the second lower electrode (132a, 132b) of each of the second capacitor cells (20a, 20b) is connected to the second metal line (142a) via the first connection features (148), and the second upper electrode (137a, 137b) of each of the second capacitor cells (20a, 20b) is connected to the first metal line (140a) via the second connection features (145). [7] A capacitor structure according to any one of the preceding claims, wherein each of the first capacitor cells (10) and each of the second capacitor cells (20) has the same capacitance, and the number of first capacitor cells (10) is equal to the number of second capacitor cells (20). [8] A capacitor structure according to any one of the preceding claims, wherein the first and second lower electrodes (130a, 132a, 130b, 132b) have the same first area, and the first and second upper electrodes (135a, 137a, 135b, 137b) have the same second area. [9] The capacitor structure of claim 8, wherein the first area is larger than the second area. [10] Capacitor structure, comprising: a capacitor array 102A comprising: a plurality of first metal lines (140a, 140b, 140c); a plurality of second metal lines (142a, 142b, 142c) parallel to the first metal lines (140a, 140b, 140c), the first and second metal lines being arranged alternately; a plurality of first capacitor cells (10a, 10b, 10d, 10c) arranged in odd and even columns of the capacitor array (102A), respectively; and a plurality of second capacitor cells (20a, 20b, 20c, 20d) arranged in even and odd columns of the capacitor array (102A), wherein first lower electrodes (130a, 130b, 130c, 130d) of the first capacitor cells (10a, 10b, 10c, 10d) are connected to the first metal lines (140a, 140b, 140c) and first upper electrodes (135a, 135b, 135c, 135d) of the first capacitor cells (10a, 10b, 10c, 10d) are connected to the second metal lines (142a, 142b, 142c), wherein second lower electrodes (132a, 132b, 132c, 132d) of the second capacitor cells (20a, 20b, 20c, 20d) are connected to the second metal line (142a, 142b, 142c) and second upper electrodes (137a, 137b, 137c, 137d) of the second capacitor cells (20a, 20b, 20c, 20d) are connected to the first metal line (140a, 140b, 140c), wherein a first voltage (VSS) applied to the first metal lines (140a, 140b, 140c) is different from a voltage (VDD) applied to the second metal lines (142a, 142b, 142c). [11] The capacitor structure of claim 10, wherein in each row of the capacitor array (102A), the first capacitor cells (10a, 10b, 10c, 10d) of two adjacent columns are separated by one of the second capacitor cells (20a, 20c), and the second capacitor cells (20a, 20b, 20c, 20d) of two adjacent columns are separated by one of the first capacitor cells (10b, 10d). [12] The capacitor structure according to claim 10 or 11, wherein the first lower electrodes (130a, 130b, 130c, 130d) of the first capacitor cells (10a, 10b, 10c, 10d) and the second lower electrodes (132a, 132b, 132c, 132d) of the second capacitor cells (20a, 20b, 20c, 20d) are formed on the same plane, and the first upper electrodes (135a, 135b, 135c, 135d) of the first capacitor cells (10a, 10b, 10c, 10d) and the second upper electrodes (137a, 137b, 137c, 137d) of the second capacitor cells (20a, 20b, 20c, 20d) are formed on the same plane. [13] A capacitor structure according to any one of claims 10 to 12, wherein the number of first capacitor cells (10a, 10b, 10c, 10d) is equal to the number of second capacitor cells (20a, 20b, 20c, 20d), and each of the first capacitor cells and each of the second capacitor cells has the same capacitance. [14] The capacitor structure of claim 13, wherein the first lower electrode (130a, 130b, 130c, 130d) of each of the first capacitor cells (10a, 10b, 10c, 10d) is connected to one of the first metal lines (140a, 140b, 140c) via a plurality of first connection features (148), and the first upper electrode (135a, 135b, 135c, 135d) of each of the first capacitor cells (10a, 10b, 10c, 10d) is connected to one of the second metal lines (142a, 142b, 142c) via a plurality of second connection features (145), wherein a first height (H1) of the first connection features (148) is greater than a second height (H2) of the second connection features (145). [15] The capacitor structure of claim 14, wherein the second lower electrode (132a, 132b, 132c, 132d) of each of the second capacitor cells (20a, 20b, 20c, 20d) is connected to one of the second metal lines (142a, 142b, 142c) via the first connection features (148), and wherein the second upper electrode (137a, 137b, 137c, 137d) of each of the second capacitor cells (20a, 20b, 20c, 20d) is connected to one of the first metal lines (140a, 140b, 140c) via the second connection features (145). [16] The capacitor structure according to any one of claims 10 to 15, wherein the first capacitor cells (10a, 10c) arranged in the same column share the same first lower electrode (130a, 130c), and the second capacitor cells (20, 20c) arranged in the same column share the same second lower electrode (132a, 132c). [17] The capacitor structure according to any one of claims 10 to 16, wherein the first and second lower electrodes (130a, 130b, 130c, 130d, 132a, 132b, 132c, 132d) have the same first area, and the first and second upper electrodes (135a, 135b, 135c, 135d, 137a, 137b, 137c, 137d) have the same second area, the first area being larger than the second area. [18] The capacitor structure of any one of claims 10 to 17, wherein the first and second metal lines (140a, 140b, 140c, 142a, 142b, 142c) have a fixed width. [19] The capacitor structure of any one of claims 10 to 17, wherein the first and second metal lines (140a, 140b, 140c, 142a, 142b, 142c) have a different width in odd columns and in even columns of the capacitor array.

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