MICROELECTRONIC DEVICES AND ASSOCIATED STORAGE DEVICES AND ELECTRONIC SYSTEMS

Abstract

A microelectronic device (100, 200) comprising: a base structure (106; 206) comprising a logic area (130, 230) including logic devices; a memory array overlying the base structure (106; 206) and comprising vertically extending chains of memory cells (142) within a horizontal region of the logic region (130, 230) of the base structure (106; 206); and a conductive pad plane (122) overlying the memory array and comprising: first conductive pads (124A, 224A) substantially outside the horizontal surface of the logic area (130, 230) of the base structure (106; 206); and second conductive pads (124B, 224B) horizontally adjacent to the first conductive pads (124A, 224A) and within the horizontal surface of the logic area (130, 230) of the base structure (106; 206); wherein at least one of the second conductive pads (124B, 224B) is offset from two of the first conductive pads (124A, 224A) that are closest in the first horizontal direction and is disposed at least partially between the two first conductive pads (124A, 224A) in a second horizontal direction perpendicular to the first horizontal direction.

Description

FIELD OF TECHNOLOGY

[0001] The disclosure, in various embodiments, generally relates to the field of designing and manufacturing microelectronic devices. More specifically, the disclosure relates to methods of forming microelectronic devices and to associated microelectronic devices, memory devices, and electronic systems. STATE OF THE ART

[0002] Microelectronic device designers often seek to increase the level of integration or density of components within a microelectronic device by reducing the dimensions of individual components and the distance between adjacent components. Furthermore, microelectronic device designers often desire architectures that are not only compact but also offer performance advantages and are easier and more cost-effective to manufacture.

[0003] An example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices, including, but not limited to, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to use vertical memory arrays (also called "three-dimensional (3D) memory array" architectures). A conventional vertical memory array includes chains of memory cells that extend vertically through a stack structure that includes layers of conductive and insulating materials. Each chain of memory cells may include at least one select device coupled in series to a serial combination of vertically stacked memory cells.Such a configuration makes it possible to accommodate a larger number of switching devices (e.g., transistors) in a unit of die area (e.g., length and width of the consumed active area) by building the array upwards (e.g., vertically) on a die compared to structures with conventional planar (e.g., two-dimensional (2D)) arrangements of transistors.

[0004] In a conventional non-volatile memory device (e.g., a conventional 3D NAND flash memory device), a die (e.g., a semiconductor die) including a vertical memory array and associated internal circuitry is electrically connected to external circuitry of a relatively larger package (e.g., an electronic package such as an integrated circuit (IC) package) via bond pads positioned along a perimeter of the die and via bond wires extending between the bond pads and conductive contacts (e.g., leads) coupled to the external circuitry. However, conventional bond pad configurations may hinder improving the performance of the non-volatile memory device and / or prevent reducing the size (e.g., horizontal areas) of the non-volatile memory device's features.

[0005] US 2021 / 0 134 819 A1 discloses a method for forming a device structure comprising forming a memory plane structure containing a three-dimensional memory device over a front surface of a semiconductor substrate, forming memory-side dielectric material layers over the memory plane structure and bonding a handle substrate thereto, the memory-side dielectric material layers, thinning the semiconductor substrate while attaching the handle substrate to the memory-side dielectric material layers, forming a driver circuit including field-effect transistors on a backside semiconductor surface of the semiconductor substrate after thinning the semiconductor substrate, and removing the handle substrate from the memory-side dielectric material layers.

[0006] CN 1 12 614 853 A discloses a three-dimensional memory device and a manufacturing method thereof. A memory unit is connected to a control unit, and then another memory unit is bonded to the backside of a substrate of the control unit, thus realizing a connection of at least three units. This realizes wafer-level bonding, simplifies the process, and effectively solves the stress problem, while increasing the number of memory layers, making the structure more stable, and reducing the risk of structural collapse.After the storage unit and the control unit are connected, the bonding pads on both sides are led out. The bonding pads can be led out from the sides of the two storage units, and the bonding pads can also be led out from the two sides of one storage unit and the two sides of the control unit. A control circuit of the control unit is used to control the storage unit accessed during storage. The pad outing mode is added and the number of bonding pads per unit area is increased. By increasing the number of bonding pads per unit area, the access hit rate of the storage unit can be improved, and therefore the storage period of the storage unit can be significantly shortened.

[0007] US 2019 / 0 157 280 A1 discloses embodiments of 3D memory structures and methods for forming them. A method for forming a three-dimensional (3D) memory structure includes forming a dielectric layer on a substrate and forming a first plurality of openings in the dielectric layer in a stair-step region of the 3D memory structure. The method also includes forming a second plurality of openings in the dielectric layer in a peripheral device region of the 3D memory structure and forming at least one hard mask layer in the first plurality of openings of the stair-step region and in the second plurality of openings of the peripheral device region.The method further comprises etching the dielectric layer using the at least one hard mask layer to form first and second pluralities of via extension regions in upper portions of the respective first and second pluralities of openings. The method further comprises disposing a first conductive material in the first and second pluralities of openings to form first and second pluralities of contact wires, respectively. The method also comprises disposing a second conductive material in the first and second pluralities of via extension regions to form first and second pluralities of contact pads, and forming first and second pluralities of lead wires on the first and second pluralities of contact pads, respectively. SUMMARY

[0008] In some embodiments, a microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad level overlying the memory array. The base structure includes a logic region including logic devices. The memory array includes vertically extending chains of memory cells in a horizontal surface of the logic region of the base structure. The conductive pad level includes first conductive pads lying substantially outside the horizontal surface of the logic region of the base structure and second conductive pads horizontally adjacent to the first conductive pads and lying within the horizontal surface of the logic region of the base structure.

[0009] In further embodiments, a memory device comprises a base structure, a conductive routing plane, a stack structure, a memory array, an additional conductive routing plane, conductive contacts, first conductive pads, and second conductive pads. The base structure comprises a region of complementary metal-oxide-semiconductor (CMOS) circuitry and an additional region horizontally adjacent to the region and substantially free of CMOS circuitry. The conductive routing plane lies above the base structure. The stack structure lies above the conductive routing plane and comprises conductive material and insulating material alternating vertically with the conductive material. The memory array comprises chains of memory cells extending through the stack structure. The memory array is located in a horizontal surface of the base structure region.The additional conductive routing level lies above the stack structure. The conductive contacts are horizontally offset from the memory array and extend between the conductive routing level and the additional conductive routing level. The first conductive pads lie above the additional conductive routing level and lie in a horizontal area of ​​the additional area of ​​the base structure. The first conductive pads are in electrical connection with some of the conductive contacts. The second conductive pads lie above the additional conductive routing level and are arranged horizontally between the first conductive pads and at least some of the chains of memory cells of the memory array. The second conductive pads are in electrical connection with another of the conductive contacts.

[0010] In further embodiments, an electronic system comprises an input device, an output device, a processor device operatively connected to the input device and the output device, and a memory device operatively connected to the processor device. The memory device comprises a stack structure, a base structure, a memory array, and bond pads. The stack structure comprises conductive structures vertically interleaved with insulating structures. The base structure lies vertically below the stack structure and includes a logic region containing logic circuitry. The memory array includes chains of memory cells extending vertically through the stack structure. The memory array is located in a horizontal region of the logic region of the base structure. The bond pads, which lie vertically above the stack structure, are in electrical connection with the logic circuitry.The bond pads include first bond pads and second bond pads. The first bond pads are located outside the horizontal surface of the logic area of ​​the base structure. The second bond pads are located within the horizontal surface of the logic area of ​​the base structure. BRIEF DESCRIPTION OF THE DIFFERENT VIEWS OF THE DRAWINGS Fig. 1A is a simplified, partial cross-sectional view of a microelectronic device according to embodiments of the present disclosure. Fig. 1B is a simplified, partial plan view of a portion of the Fig. 1A shown microelectronic device. Fig. 2 is a simplified, partial plan view of a portion of a microelectronic device in accordance with further embodiments of the disclosure. Fig. 3 is a schematic block diagram of an electronic system in accordance with embodiments of the disclosure. WAY(S) OF CARRYING OUT THE INVENTION

[0011] The following description provides specific details, such as material compositions, shapes, and sizes, to provide a comprehensive description of embodiments of the disclosure. However, one skilled in the art would understand that embodiments of the disclosure may be practiced without the use of these specific details. Embodiments of the disclosure may be used in conjunction with methods commonly used in the industry for fabricating microelectronic devices. Furthermore, the following description does not represent a complete process for fabricating a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device). The structures described below do not represent a complete microelectronic device.Only the processes and structures necessary to understand the embodiments of the disclosure are described in detail below. Further steps for fabricating a complete microelectronic device from the structures can be performed using conventional manufacturing techniques.

[0012] The drawings presented in this document are for illustrative purposes only and are not to be construed as actual views of any particular material, component, structure, device, or system. Deviations from the shapes shown in the drawings, for example, due to manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments described in this document are not limited to the shapes or regions shown, but include variations in shapes that arise, for example, from manufacturing. For example, an area shown or described as box-shaped may have rough and / or non-linear features, and an area shown or described as round may include some rough and / or linear features. Furthermore, sharp angles shown may be rounded, and vice versa.The regions depicted in the figures are therefore schematic, and their shapes are not intended to represent the exact shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Furthermore, common elements of figures may be given the same numerical designation.

[0013] In this document, the term "memory device" means and includes microelectronic devices with memory functionality, but is not necessarily limited to memory functionality. In other words, and only as a non-limiting example, the term "memory device" includes not only conventional memories (e.g., conventional non-volatile memories such as conventional NAND memory; conventional volatile memories such as conventional DRAM), but also an application-specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device that combines logic and memory, and a graphics processing unit (GPU) that includes memory.

[0014] As used herein, the term "configured" refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that performs the operation of one or more of the structures and devices in a predetermined manner.

[0015] As used in this document, the terms "vertical," "longitudinal," "horizontal," and "lateral" refer to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to the principal plane of the structure, whereas a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by a surface of the structure that has a relatively large area compared to other surfaces of the structure.With reference to the figures, a "horizontal" or "lateral" direction may be perpendicular to a specified "Z" axis and parallel to a specified "X" axis and / or parallel to a specified "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to a specified "Z" axis, perpendicular to a specified "X" axis, and perpendicular to a specified "Y" axis.

[0016] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other mean and include features of the disclosed nature (or qualities) that are closest to each other (e.g., closest to each other). Additional features (e.g., additional regions, additional structures, additional devices) that do not correspond to the disclosed nature (or qualities) of the "adjacent" features may be located between the "adjacent" features. In other words, the "adjacent" features may be directly adjacent to each other, such that no other feature is located between the "adjacent" features; or the "adjacent" features may be indirectly adjacent, such that at least one feature having a different nature than that associated with at least one of the "adjacent" features is located between the "adjacent" features.Accordingly, the description of features that are "vertically adjacent" to each other means and includes the features of the disclosed condition (or conditions) that are closest vertically to each other (e.g., closest vertically). Furthermore, the description of features that are "horizontally adjacent" to each other means and includes the features of the disclosed condition (or conditions) that are closest horizontally to each other (e.g., closest horizontally).

[0017] Throughout this specification, spatially relative terms such as "under," "beneath," "lower," "underneath," "above," "upper," "top," "front," "back," "left," "right," and the like may be used to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Unless otherwise noted, the spatially relative terms are intended to include other orientations of materials in addition to the orientation shown in the figures. For example, if materials are inverted in the figures, elements described as being "below" or "under" or "beneath" or "on the underside of" other elements or features would then be oriented "above" or "on top of" the other elements or features.For example, the term "below" can encompass both an upward and downward orientation, depending on the context in which the term is used, which would be obvious to a person of ordinary skill in the art. The materials may be oriented differently (e.g., rotated 90 degrees, inverted, mirrored), and the spatially relative descriptors used in this document should be interpreted accordingly.

[0018] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0019] In this context, “and / or” includes any and all combinations of one or more of the related items listed.

[0020] As used in this document, the term “coupled to” refers to structures that are operatively connected to each other, such as electrically connected by a direct ohmic connection or by an indirect connection (e.g., via another structure).

[0021] As used in this document, the term "substantially," with respect to a particular parameter, characteristic, or condition, means and includes, to the extent that one of ordinary skill in the art would understand that the particular parameter, characteristic, or condition is satisfied with some variation, such as within acceptable tolerances. For example, depending on the parameter, characteristic, or condition that is substantially satisfied, the parameter, characteristic, or condition may be at least 90.0 percent satisfied, at least 95.0 percent satisfied, at least 99.0 percent satisfied, at least 99.9 percent satisfied, or even 100.0 percent satisfied.

[0022] As used herein, "about" or "approximately," with respect to a numerical value for a particular parameter, includes the numerical value and a degree of deviation from the numerical value that is within acceptable tolerances for the particular parameter to one skilled in the art. For example, "about" or "approximately," with respect to a numerical value, may include additional numerical values ​​within a range of 90.0 percent to 110.0 percent of the numerical value, such as within a range of 95.0 percent to 105.0 percent of the numerical value, within a range of 97.5 percent to 102.5 percent of the numerical value, within a range of 99.0 percent to 101.0 percent of the numerical value, within a range of 99.5 percent to 100.5 percent of the numerical value, or within a range of 99.9 percent to 100.1 percent of the numerical value.

[0023] As used in this document, “conductive material” means and includes electrically conductive material such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-base alloy, an Fe-base alloy, a Ni-base alloy, an Fe and Ni-base alloy, a Co and Ni-base alloy, a Fe and Co-base alloy, a Co and Ni and Fe-base alloy, an Al-base alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g.a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)). Furthermore, a "conductive structure" means and includes a structure consisting of and including conductive material.

[0024] As used herein, “insulating material” means and includes electrically insulating material, such as one or more of at least one dielectric oxide material (e.g., one or more of silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, boronphosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlO x ), a hafnium oxide (HfO x ), a niobium oxide (NbO x ), a titanium oxide (TiO x ), a zirconium oxide (ZrO x ), a tantalum oxide (TaO x) and a magnesium oxide (MgO x )), at least one dielectric nitride material (e.g. a silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g. a silicon oxynitride (SiO x N y )), to at least one dielectric oxycarbide material (e.g. silicon oxycarbide (SiO x C y )), at least one hydrogenated dielectric oxycarbide material (e.g. hydrogenated silicon oxycarbide (SiC x O y H z )) and at least one dielectric carboxynitride material (e.g. a silicon carboxynitride (SiO x C z N y Formulas that contain one or more of “x”, “y” and “z” in this document (e.g. SiO x , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C y , SiC x O y H z , SiO x C z N y) represent a material that contains an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the formulas represent relative atomic ratios rather than a strict chemical structure, an insulating material may comprise one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x," "y," and "z" (if any) may be integers or non-integers. As used in this document, the term "non-stoichiometric compound" means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and that violates the law of definite proportions.In addition, an “insulating structure” means and includes a structure consisting of and including insulating material.

[0025] Unless the context indicates otherwise, the materials described in this document may be formed by any suitable technique, including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for deposition or growth of the material may be selected by a person having the appropriate expertise.In addition, unless the context indicates otherwise, the removal of the materials described in this document may be performed by any suitable technique, including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization (CMP)) or other known methods.

[0026] Fig. 1A is a simplified, partial cross-sectional view of a microelectronic device 100 (e.g., a semiconductor device; a memory device such as a 3D NAND flash memory device), according to embodiments of the disclosure. Fig. Figure 1B is a simplified partial plan view of a section A of the Fig. 1A. For the sake of clarity and better understanding of the drawings and the associated description, not all components (e.g., features, structures, devices) of the microelectronic device 100 shown in Fig. 1A shown microelectronic device 100 in Fig. 1B. For example, some components of the microelectronic device 100 that are vertically above other components of the microelectronic device 100 are shown in Fig. 1B not shown to provide a clearer top view of the other components.

[0027] According to Fig. 1A, the microelectronic device 100 includes a die 101 including a memory array region 102 and a contact region 104 (e.g., a deep contact region) in horizontal proximity (e.g., in the X direction) to the memory array region 102. In some embodiments, the contact region 104 is positioned at or near an outer horizontal boundary (e.g., a peripheral boundary, an outer perimeter) of the die 101, and the memory array region 102 is positioned horizontally within the contact region 104. The memory array region 102 may be arranged horizontally (e.g., in the X direction) between the contact region 104 and one or more other regions (e.g., an additional contact region, such as a contact region for the access line) of the chip 101. As described in detail below, the die 101 of the microelectronic device 100 includes various features (e.g.Materials, structures, devices) within the horizontal surfaces of the various horizontal regions (e.g., the memory array region 102, the contact region 104) thereof.

[0028] As in Fig. 1A, the die 101 of the microelectronic device 100 may include a base structure 106, at least one first conductive routing level 108 including first conductive routing structures 110 vertically above the base structure 106 (e.g., in the Z direction), a stack structure 112 vertically above the first conductive routing level 108, at least one second conductive routing level 114 including second conductive routing structures 116 vertically above the stack structure 112, at least one third conductive routing level 118 including third conductive routing structures 120 vertically above the second conductive routing level 114, and at least one conductive pad level 122 including conductive pads 124 (e.g., bond pads) vertically above the third conductive routing level 118 lie.Die 101 of microelectronic device 100 may also include cell column structures 126 within its memory array region 102 and contact structures 128 (e.g., deep contact structures) within its contact region 104. The aforementioned features of microelectronic device 100 are described in more detail below. Microelectronic device 100 also includes other features, which are also described in detail below.

[0029] The base structure 106 includes a base material or construction upon which additional features (e.g., materials, structures, devices) of the microelectronic device 100 are formed. The base structure 106 may include a semiconductor structure (e.g., a semiconductor wafer) or a base material on a support structure. For example, the base structure 106 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or other substrate including semiconductor material. In some embodiments, the base structure 106 includes a silicon wafer. The base structure 106 may be configured to include various regions, materials, structures, and / or devices therein and / or thereon.

[0030] As in Fig. 1A, the base structure 106 may include at least one logic region 130 (also referred to herein as at least one "active region" or at least one "first region") and at least one additional region 132 (also referred to herein as at least one "inactive region" or at least one "second region") horizontally adjacent to the logic region 130. The logic region 130 may include logic devices and may be arranged at least partially within the horizontal boundaries (e.g., within a horizontal surface) of the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, the logic region 130 of the base structure 106 also extends horizontally into the contact region 104 of the die 101 of the microelectronic device 100. The additional region 132 may be free of logic devices therein and may be at least partially within the horizontal boundaries (e.g.,within a horizontal surface) of the contact area 104 of the die 101 of the microelectronic device 100. In some embodiments, the additional area 132 of the base structure 106 is substantially limited to the contact area 104 of the die 101 of the microelectronic device 100.

[0031] The logic devices within the logic region 130 of the base structure 106 are configured to control various operations of the microelectronic device 100. The logic devices consist of and include logic circuits. In some embodiments, at least some of the logic devices within the logic region 130 are formed of and include complementary metal-oxide-semiconductor (CMOS) circuits. As a non-limiting example, the logic devices included in the logic region 130 of the base structure 106 may include one or more (e.g., each) charge pumps (e.g., V CCP -Charge pumps, VNEGWL -charge pumps, DVC2 charge pumps), DLL circuits (e.g. ring oscillators), drain supply voltage regulators (V dd), chain drivers, page buffers, and various chip / deck control circuits. As a further non-limiting example, the logic devices included in the logic region 130 of the basic structure 106 may include devices configured to control column operations for arrays (e.g., memory arrays) within the memory array region 102 of the die 101 of the microelectronic device 100, such as one or more (e.g., each) decoders (e.g., local deck decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuits (e.g., column repair circuits), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), and error checking and correction (ECC) devices.As another non-limiting example, the logic devices included in logic region 130 of base structure 106 may include devices configured to control row operations for arrays (e.g., memory arrays) within memory array region 102 of die 101 of microelectronic device 100, such as one or more (e.g., each) of decoders (e.g., local deck decoders, row decoders), drivers (e.g., word line (WL) drivers), repair circuits (e.g., row repair circuits), memory test devices, MUX, ECC devices, and self-refresh / wear leveling devices.

[0032] The logic region 130 of the basic structure 106 may be divided into several (e.g., a plurality of) logic subregions 134. At least some of the logic subregions 134 may include different types of logic devices than at least some other of the logic subregions 134. As a non-limiting example, one or more of the logic subregions 134 may be a pump subregion that includes charge pumps (e.g., V CCP -Charge pumps, V NEGWL-charge pumps, DVC2 charge pumps). At least some other of the logic sub-regions 134 may be free of charge pumps. As a further non-limiting example, one or more of the logic sub-regions 134 may be a driver sub-region that includes driver devices (e.g., chain driver devices). At least some other of the logic sub-regions 134 may be free of driver devices located therein. As an additional non-limiting example, one or more of the logic sub-regions 134 may be a memory cache sub-region that includes memory devices (e.g., page buffer devices) therein. At least some other of the logic sub-regions 134 may be free of buffer devices located therein. As a further non-limiting example, one or more of the logic sub-regions 134 may be a decoder sub-region that includes decoder devices.At least some other of the logic sub-regions 134 may be free of decoder devices. Another non-limiting example is that one or more of the logic sub-regions 134 may be a sense amplifier sub-region that includes sense amplifier devices therein. At least some other of the logic sub-regions 134 may be free of sense amplifier devices included therein.

[0033] With further reference to Fig. 1A, the first conductive routing plane 108 may be arranged vertically between the base structure 106 and the stack structure 112. The first conductive routing structures 110 of the first conductive routing plane 108 may include at least one source structure 110A (e.g., a source plate) within the memory array region 102 of the die 101 of the microelectronic device 100 and contact pads 110B within the contact region 104 of the die 101 of the microelectronic device 100. The source structure(s) 110A and the contact pads 110B may be horizontally adjacent to each other within the first conductive routing plane 108 (e.g., in the X direction, in the Y direction). The source structure(s) 110A may be electrically isolated from the contact pads 110B and may be arranged in substantially the same vertical position (e.g., in the Z direction) as the contact pads 110B.At least one insulating material may be inserted between the source structure(s) 110A and the contact pads 110B of the first conductive routing level 108.

[0034] The first conductive routing levels 110 (including the source structure(s) 110A and the contact pads 110B) of the first conductive routing level 108 may each be formed from and include conductive material. In some embodiments, the first conductive structures 110 are formed from and include one or more of a metal, an alloy, and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). As a non-limiting example, the first conductive structures 110 may be formed from and include W.In further embodiments, the first conductive structures 110 are formed from and include conductively doped semiconductor material, such as a conductively doped form of one or more silicon materials, such as monocrystalline silicon or polycrystalline silicon; a silicon-germanium material; a germanium material; a gallium arsenide material; a gallium nitride material; and an indium phosphide material. As a non-limiting example, the first conductive structures 110 may be formed from and include silicon (e.g., polycrystalline silicon) doped with at least one dopant (e.g., one or more of at least one n-type dopant, at least one p-type dopant, and at least one other dopant).

[0035] At least some of the first conductive routing planes 110 of the first conductive routing plane 108 may be individually coupled to logic devices within the logic region 130 of the base structure 106. Furthermore, at least some of the first conductive routing structures 110 (e.g., the source structure(s) 110A) may also be individually coupled to the cell column structures 126 within the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, the source structure(s) 110A of the first conductive routing level 108 are in direct physical contact with the cell pillar structures 126 in the region of the memory array 102 of the die 101 of the microelectronic device 100. In further embodiments, contact structures are located vertically between the source structure(s) 110A and at least some of the cell pillar structures 126. Furthermore, at least some of the first conductive structures 110 (e.g.At least some of the contact pads 110B may be individually coupled to at least some of the contact structures 128 within the contact area 104 of the die 101 of the microelectronic device 100. In some embodiments, the contact pads 110B of the first conductive routing level 108 are in direct physical contact with the contact structures 128 coupled thereto. In further embodiments, additional contact structures are located vertically between at least some of the contact pads 110B and at least some of the contact structures 128 coupled thereto.

[0036] As in Fig. 1A, the stack structure 112 of the die 101 of the microelectronic device 100 may be configured to vertically overlie the first conductive routing plane 108 and include a vertically alternating (e.g., in the Z-direction) sequence of conductive structures 136 and insulating structures 138 arranged in levels 140. Each of the levels 140 of the stack structure 112 may include at least one of the conductive structures 136 vertically adjacent to at least one of the insulating structures 138. The stack structure 112 may be configured to include any number of levels 140, such as greater than or equal to sixteen (16) of the levels 140, greater than or equal to thirty-two (32) of the levels 140, greater than or equal to sixty-four (64) of the levels 140, greater than or equal to one hundred twenty-eight (128) of the levels 140, or greater than or equal to two hundred fifty-six (256) of the levels 140.

[0037] The conductive structures 136 of the levels 140 of the stack structure 112 may be formed from and include conductive material. As a non-limiting example, the conductive structures 136 may each individually be formed from and include a metallic material comprising at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the conductive structures 136 are formed from and include W. Each of the conductive structures 136 may individually be substantially homogeneous, or one or more of the conductive structures 136 may individually be substantially heterogeneous. In some embodiments, each of the conductive structures 136 is substantially homogeneous.In further embodiments, each of the conductive structures 136 is heterogeneous. For example, each conductive structure 136 may consist of and include a stack of at least two different conductive materials.

[0038] At least one vertically lower (e.g., in the Z-direction) conductive structure 136 of the stack structure 112 may be used as at least one first select gate (e.g., at least one source-side select gate (SGS)) within the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, a first conductive structure 136 of a vertically lowest level 140 of the stack structure 112 is used as a first select gate (e.g., an SGS) within the memory array region 102. Furthermore, one or more vertically upper (e.g., in the Z-direction) conductive structure(s) 136 of the stack structure 112 may be used as second select gates (e.g., drain-side select gate(s) (SGD)) in the region of the memory array 102 of the die 101 of the microelectronic device 100. In some embodiments, horizontally (e.g.,in the Y direction) conductive structures 136 of a vertically uppermost level 140 of the stack structure 112 are used as second selection gates (e.g., SGDs) within the memory array area 102.

[0039] Optionally, one or more lining materials (e.g., insulating lining material, conductive wire material) may also be formed around the conductive structures 136. The lining material may, for example, consist of and include one or more metals (e.g., titanium, tantalum), an alloy, a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), and a metal oxide (e.g., aluminum oxide). In some embodiments, the lining material(s) comprise(s) at least one conductive material used as a seed material for forming the conductive structures 136. In some embodiments, the lining material(s) comprise(s) titanium nitride. In further embodiments, the lining material(s) comprise(s) aluminum oxide.As a non-limiting example, aluminum oxide may be formed directly adjacent to the insulating structures 138, titanium nitride may be formed directly adjacent to the aluminum oxide, and tungsten may be formed directly adjacent to the titanium nitride. For clarity and ease of understanding of the description, the lining material(s) are shown in FIG. Fig. 1A, but it is understood that the lining material(s) may be disposed around the conductive structures 136.

[0040] The insulating structures 138 of the levels 140 of the stack structure 112 may be formed of and include at least one insulating material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx , HfO x , NbO x , TiO x , ZrO x , TaO x and MgO x ), at least one dielectric nitride material (e.g. SiN y ), at least one dielectric oxynitride material (e.g. SiO x N y ) and at least one dielectric carboxynitride material (e.g. SiO x C z N y ). In some embodiments, each of the insulating structures 138 is made of a dielectric oxide material such as SiO x(e.g., SiO2) and includes it. Each of the insulating structures 138 may be substantially homogeneous in itself, but may also be substantially heterogeneous. In some embodiments, each of the insulating structures 138 is substantially homogeneous. In further embodiments, at least one of the insulating structures 138 is substantially heterogeneous. One or more of the insulating structures 138 may, for example, be formed from and include a stack (e.g., laminate) of at least two different insulating materials.

[0041] As in Fig. 1A, in some embodiments, the stack structure 112 does not extend substantially horizontally into the contact region 104 of the die 101 of the microelectronic device 100. In other words, the contact region 104 may be substantially free of the stack structure 112 within a horizontal region. In such embodiments, the contact structures 128 may extend vertically within the contact region 104 by at least one additional insulating material (e.g., at least one dielectric oxide material, such as SiO x , at least one dielectric nitride material, such as SiN y) may extend horizontally adjacent to and be horizontally surrounded by the stack structure 112. Within the contact area 104, the additional insulating material may, for example, extend vertically from and between the first conductive routing level 108 and the second conductive routing level 114. In further embodiments, the stack structure 112 extends horizontally into the contact area 104 of the die 101 of the microelectronic device 100. In some embodiments, at least some of the contact structures 128 within the contact area 104 may extend vertically through the stack structure 112 and be horizontally surrounded by it.

[0042] With further reference to Fig. 1A, the cell column structures 126 may extend vertically through the levels 140 of the stack structure 112. The cell column structures 126 may each be individually formed from and include a stack of materials. As a non-limiting example, each of the cell column structures 126 may be configured to include a charge-barrier material, such as a first dielectric oxide material (e.g., SiO x , such as SiO2; AlO x , such as Al2O3); a charge-trapping material, such as a dielectric nitride material (e.g. SiN y , such as Si3N4); a dielectric tunneling material, such as a second dielectric oxide material (e.g. SiO x, such as SiO2); a channel material, such as a semiconducting material (e.g., silicon, such as polycrystalline Si); and a dielectric fill material (e.g., a dielectric oxide, a dielectric nitride, air). The charge-barrier material may be formed on or over surfaces of the conductive structures 136 and the insulating structures 138 of the levels 140 of the stack structure 112 that at least partially define horizontal boundaries of the cell column structures 126; the charge-barrier material may be horizontally surrounded by the charge-barrier material; the tunneling dielectric material may be horizontally surrounded by the charge-barrier material; the channel material may be horizontally surrounded by the tunneling dielectric material; and the dielectric fill material may be horizontally surrounded by the channel material.

[0043] The intersections of the cell column structures 126 and the conductive structures 136 of the levels 140 of the stack structure 112 can define vertically extending chains of memory cells 142 that are coupled in series within the stack structure 112. In some embodiments, the memory cells 142 formed at the intersections of the conductive structures 136 and the cell column structures 126 within the various levels 140 of the stack structure 112 comprise so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In further embodiments, the memory cells 142 comprise so-called "TANOS" (tantalum nitride - aluminum oxide - nitride - oxide - semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, which are each subsets of MONOS memory cells.In further embodiments, the memory cells 142 comprise so-called "floating gate" memory cells, which include floating gates (e.g., metallic floating gates) as charge storage structures. The floating gates can engage horizontally between the central structures of the cell column structures 126 and the conductive structures 136 of the various levels 140 of the stack structure 112. The vertically extending chains of memory cells 142 together form a memory array within the stack structure 112.

[0044] As in Fig. 1A, the contact structures 128 within the contact area 104 of the die 101 of the microelectronic device 100 may be configured and positioned to electrically connect one or more features (e.g., structure(s), material(s), device(s)) of the microelectronic device 100 that are vertically above the stack structure 112 to one or more additional features of the microelectronic device 100 that are vertically below the stack structure 112. For example, the contact structures 128 within the contact area 104 may electrically connect at least some of the first conductive routing planes 110 of the first conductive routing plane 108 that are vertically below the stack structure 112 to at least some of the second conductive routing structures 116 of the second conductive routing plane 114 that are vertically above the stack structure 112.The contact structures 128 may individually be formed from and include at least one conductive material. In some embodiments, the contact structures 128 are formed from and include W. In further embodiments, the contact structures 128 are formed from and include conductively doped polycrystalline silicon.

[0045] In embodiments where the stack structure 112 extends horizontally into the contact area 104 of the die 101 of the microelectronic device 100, insulating structures of the liner extend substantially continuously over and substantially cover the side surfaces of at least some of the contact structures 128. The insulating liner structures may be inserted horizontally between the contact structures 128 and the conductive structures 136 (and the insulating structures 138) of the levels 140 of the stack structure 112. The insulating structures of the liner materials may consist of and include at least one insulating material, such as at least one dielectric oxide material (e.g., one or more of SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaOx and MgO x ), at least one dielectric nitride material (e.g. SiN y ), at least one dielectric oxynitride material (e.g. SiO x N y ) and at least one dielectric carboxynitride material (e.g. SiO x C z N y ). In embodiments where the stack structure 112 extends horizontally into the contact area 104 of the die 101 of the microelectronic device 100, insulating structures of the liner extend substantially continuously over and substantially cover the side surfaces of at least some of the contact structures 128. In some embodiments, the contact structures 128 are in direct physical contact and extend vertically through additional insulating material horizontally adjacent to the stack structure 112.

[0046] As in Fig. 1A, the second conductive routing level 114 may be arranged vertically between the stack structure 112 and the third conductive routing level 118. The second conductive routing structures 116 of the second conductive routing level 114 may include digit line structures 116A (e.g., bit line structures, data line structures) within the memory array region 102 of the die 101 of the microelectronic device 100 and additional contact pads 116B within the contact region 104 of the die 101 of the microelectronic device 100. The digit line structures 116A and the additional contact pads 116B may be horizontally adjacent to each other within the second conductive routing level 114 (e.g., in the X direction, in the Y direction). The digit line structures 116A may be electrically isolated from the additional contact pads 116B and may be in substantially the same vertical position (e.g.,in the Z direction) as the additional contact pads 116B. At least one insulating material can be inserted between the source structure(s) 110A and the contact pads 110B of the second conductive routing level 114.

[0047] The second conductive routing structures 116 (including the digit line structures 116A and the additional contact pads 116B) of the second conductive routing level 114 may each be formed from and include conductive material. In some embodiments, the second conductive routing structures 116 are formed from and include one or more of a metal, an alloy, and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). As a non-limiting example, the second conductive routing structures 116 may be formed from and include W.

[0048] Some of the second conductive routing structures 116 (e.g., the digit line structures 116A) may be individually coupled to the cell column structures 126 within the memory array region 102 of the die 101 of the microelectronic device 100. In some embodiments, the digit line structures 116A of the second conductive routing level 114 are in electrical communication with the cell column structures 126 within the memory array region 102 of the die 101 of the microelectronic device 100. Conductive contact structures may be vertically disposed between and electrically connect the digit line structures 116A and at least some of the cell column structures 126. Furthermore, some of the second conductive routing structures 116 (e.g., at least some of the additional contact pads 116B) may be individually coupled to at least some of the contact structures 128 within the contact area 104 of the die 101 of the microelectronic device 100.In some embodiments, the additional contact pads 116B of the second conductive routing level 114 are in electrical connection with the contact structures 128 within the contact area 104 of the die 101 of the microelectronic device 100. The additional contact pads 116B may be directly physically in contact with the contact structures 128 coupled thereto, or further conductive contact structures may be located vertically between the additional contact pads 116B and at least some of the contact structures 128 and electrically connect them.

[0049] With continued reference to Fig. 1A, within the third conductive routing level 118, which is vertically above the second conductive routing level 114, some of the third conductive routing structures 120 may be positioned at least partially within the memory array area 102 of the die 101 of the microelectronic device 100, and some other of the third conductive routing structures 120 may be positioned within the contact area 104 of the die 101 of the microelectronic device 100. As in Fig. 1A, at least some of the third conductive routing structures 120 may be electrically connected to at least some of the second conductive routing structures 116 (e.g., the digit line structures 116A, the additional contact pads 116B) of the second conductive routing level 114 via contact structures 144.

[0050] The third conductive routing structures 120 of the third conductive routing level 118 may each be formed from and include conductive material. In some embodiments, the third conductive routing structures 120 are formed from and include one or more of a metal, an alloy, and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). As a non-limiting example, the third conductive routing structures 120 may be formed from and include Cu. As a further non-limiting example, the third conductive routing structures 120 may be formed from and include W.

[0051] While Fig. 1A illustrates die 101 of microelectronic device 100 as including a single (e.g., only one) third conductive routing level 118 with third conductive routing structures 120, die 101 of microelectronic device 100 may be configured to include multiple (e.g., more than one) third routing levels 118, each individually including a desired arrangement (e.g., a pattern) of third conductive routing structures 120. As a non-limiting example, die 101 of microelectronic device 100 may be configured to include two or more (e.g., three or more) third routing levels 118, wherein different third routing levels 118 are vertically offset from one another and each individually including a desired arrangement of third conductive routing structures 120 therein.At least some of the third conductive routing structures 120 within at least one of the third routing levels 118 may be coupled to at least some of the third conductive routing structures 120 within at least one other of the third routing levels 118 via conductive interconnect structures.

[0052] Still referring to Fig. 1A, the conductive pads 124 (e.g., bond pads) within the conductive pad level 122 that lies vertically above the third conductive routing level 118 may include first conductive pads 124A (e.g., first bond pads) arranged outside horizontal boundaries (e.g., outside a horizontal surface) of the memory array area 102 of the die 101 of the microelectronic device 100, and second conductive pads 124B (e.g., second bond pads) arranged at and / or at least partially within the horizontal boundaries (e.g., at or at least partially within the horizontal surface) of the memory array area 102 of the die 101 of the microelectronic device 100.Configurations and positions of the conductive pads 124 of the pad level 122, including configurations and positions of the first conductive pads 124A and the second conductive pads 124B, relative to each other and relative to other features of the microelectronic device 100 are described in more detail below.

[0053] As in Fig. 1A, the conductive pads 124 may be coupled to at least some of the third conductive routing structures 120 of the third conductive routing level 118. At least some of the conductive pads 124, including at least some of the first conductive pads 124A and at least some of the second conductive pads 124B, may be configured to receive global signals from conductive wires 146 (e.g., bond pads) coupled thereto and to forward the global signals to the third conductive routing structures 120 coupled thereto. As a non-limiting example, the global signals may include one or more of the following signals: power supply signals (e.g., supply voltage signals (V cc ), ground signals (V ss)), data signals (e.g., input / output (I / O) signals), and control signals. In some embodiments, at least some of the conductive pads 124, including at least some of the first conductive pads 124A and at least some of the second conductive pads 124B, are configured as power pads (e.g., V cc -Pads, V ss pads) that are configured and positioned to transmit current signals (e.g. V cc -signals, V ss-signals) from at least some of the conductive wires 146. In further embodiments, one or more of the conductive pads 124 are used as one or more data signal pads (e.g., I / O pads) configured and positioned to receive data signals (e.g., I / O signals) from one or more of the conductive wires 146. In further embodiments, one or more of the conductive pads 124 are used as one or more control pads configured and positioned to receive control signals from one or more of the conductive wires 146. The conductive wires 146 may be coupled to additional conductive contact structures 148 (e.g., leads) operatively associated with additional circuitry (e.g., external circuitry, such as external bus circuitry). In some embodiments, the additional conductive contact structures 148 are portions of a lead frame of a package (e.g.,an electronics package, such as an integrated circuit (IC) package, that includes the microelectronic device 100 and additional features (e.g., a protective housing with non-conductive encapsulation materials). Although the microelectronic device 100 is described herein as part of a package, the microelectronic device 100 may include the entire package.

[0054] The conductive pads 124 (including the first conductive pads 124A and the second conductive pads 124B) of the conductive pad level 122 may each be formed from and include conductive material. In some embodiments, the conductive pads 124 are formed from and include one or more of a metal, an alloy, and a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). As a non-limiting example, the conductive pads 124 may be formed from and include Al. As a further non-limiting example, the conductive pads 124 may be formed from and include W.

[0055] As in Fig. 1A, the first conductive pads 124A, which are arranged outside the horizontal boundaries (e.g., outside the horizontal surface) of the memory array region 102 of the die 101 of the microelectronic device 100, may be located within the horizontal boundaries of the additional region 132 of the base structure 106 of the die 101 of the microelectronic device 100. In some embodiments, the first conductive pads 124A are substantially confined to the horizontal surface of the additional region 132 of the base structure 106, such that the first conductive pads 124A are located entirely outside the horizontal surface of the logic region 130 of the base structure 106.

[0056] With reference to Fig. 1B, configurations and operational functions of the first conductive pads 124A may be selected based at least in part on the logic sub-region(s) 134 of the logic region 130 that are located relatively horizontally (e.g., in the X-direction) proximate the first conductive pads 124A. If the Fig. 1B, the logic section 134 includes a pump section that provides charge pumps (V CCP -Charge pumps, V NEGWL -charge pumps, DVC2 charge pumps), at least some of the first conductive pads 124A positioned horizontally in proximity (e.g., in the X direction) thereto may be power supply pads (e.g., V cc -Pads, V ss pads) that are configured and positioned to transmit current signals (e.g. V cc -signals, V ss signals) from some of the conductive wires 146. For example, at least one of the first conductive pads 124A may be a V cc-Pad, and at least one other of the first conductive pads 124A may comprise a V ss -Pad. One or more of the first conductive pads 124A, designated as V cc Pads may be electrically connected to a voltage regulator device 150 (e.g., a linear direct current (DC) regulator, such as a low-dropout (LDO) regulator). Conductive routing structures 152 may be used to electrically connect at least some of the first conductive pads 124A to other features (e.g., structures, devices) of the microelectronic device 100 and / or a package including the microelectronic device 100, as desired. As a non-limiting example, as shown in Fig. 1B, some conductive routing structures 152 may be located between one or more of the first conductive pads 124A, which may be referred to as V ccpads are used, and be coupled to the voltage regulator device 150.

[0057] The first conductive pads 124A can each individually have a desired horizontal cross-sectional shape. As shown in Fig. 1B, in some embodiments, each of the first conductive pads 124A has a substantially regular (e.g., square) horizontal cross-sectional shape. In additional embodiments, one or more (e.g., each) of the first conductive pads 124A has an irregular horizontal cross-sectional shape, such as a circular cross-sectional shape, an oblong cross-sectional shape, an elliptical cross-sectional shape, a teardrop cross-sectional shape, a semicircular cross-sectional shape, a tombstone cross-sectional shape, a crescent cross-sectional shape, a triangular cross-sectional shape, a kite cross-sectional shape, and an irregular cross-sectional shape. Furthermore, each of the first conductive pads 124A may have substantially the same horizontal cross-sectional dimensions (e.g.,substantially the same horizontal width in the X-direction and substantially the same horizontal length in the Y-direction), or at least one of the first conductive pads 124A may have one or more different horizontal cross-sectional dimensions (e.g., a different horizontal width in the X-direction and / or a different horizontal length in the Y-direction) than at least one other of the first conductive pads 124A. In some embodiments, all of the first conductive pads 124A have substantially the same horizontal cross-sectional dimensions.

[0058] The first conductive pads 124A may be spaced apart from each other in a horizontal direction (e.g., in the Y direction) by at least a pad pitch distance B1. The pad pitch distance B1 between two (2) first conductive pads 124A that are horizontally adjacent to each other may depend at least in part on the configurations and functions of the two (2) first conductive pads 124A, as well as the configurations and positions of the second conductive pad(s) 124B and the conductive wire(s) 146 that are horizontally (e.g., in the Y direction) between the two (2) first conductive pads 124A. In some embodiments, the pad pitch B1 is greater than or equal to about 15 micrometers (µm), such as greater than or equal to about 20 µm, within a range of about 15 µm to about 50 µm, within a range of about 15 µm to about 30 µm, within a range of about 15 µm to about 25 µm, or within a range of about 15 µm to about 20 µm.Each pair of horizontally adjacent first conductive pads 124A may be horizontally separated by substantially the same pad pitch distance B1, or at least one pair of horizontally adjacent first conductive pads 124A may be horizontally separated by a different pad pitch distance B1 (e.g., a larger pad pitch distance B1, a smaller pad pitch distance B1) than at least one other pair of horizontally adjacent first conductive pads 124A.

[0059] As in Fig. 1B, at least some (e.g., all) of the first conductive pads 124A may be substantially horizontally aligned with each other. For example, the first conductive pads 124A within a row of the first conductive pads 124A may be substantially horizontally aligned with each other. The row of first conductive pads 124A may extend horizontally in the Y-direction, and the horizontal center point of the first conductive pads 124A within the row may be substantially horizontally aligned with each other in the X-direction perpendicular to the Y-direction. In further embodiments, at least one of the first conductive pads 124A is at least partially horizontally offset (e.g., at least partially horizontally misaligned) from at least one other of the first conductive pads 124A in the X-direction.For example, a horizontal center point of at least one of the first conductive pads 124A in the X direction may be horizontally offset from a horizontal center point of at least one other of the first conductive pads 124A in the X direction.

[0060] Each of the first conductive pads 124A may be individually coupled to one of the conductive wires 146, or at least one of the first conductive pads 124A may not be coupled to one of the conductive wires 146. When a single first conductive pad 124A is coupled to a single conductive wire 146, the first conductive pads 124A may be physically attached (e.g., bonded) to the conductive wire 146 in any desired manner. In some embodiments, at least some of the first conductive pads 124A are connected to at least some of the conductive wires 146 through conductive interconnect structures 154 therebetween. The conductive interconnect structures 154 may, for example, include solder structures such as one or more solder balls and solder bumps.

[0061] As in Fig. 1B, the second conductive pads 124B, which are arranged on and / or at least partially within the horizontal boundaries (e.g., on or at least partially within the horizontal surface) of the memory array region 102 of the chip 101 of the microelectronic device 100, may be arranged at least partially within the horizontal boundaries of the logic region 130 of the base structure 106 of the chip 101 of the microelectronic device 100. In some embodiments, the second conductive pads 124B are substantially confined to the horizontal surface of the logic region 130 of the base structure 106, such that the second conductive pads 124B are located entirely outside the horizontal surface of the additional region 132 of the base structure 106. Horizontal boundaries (e.g., in the X-direction) of the second conductive pads 124B that are closest to the first conductive pads 124A may be at or relatively close to (e.g.,relatively close to) horizontal boundaries (e.g., in the X-direction) of the logic area 130. In some embodiments, the second conductive pads 124B are substantially confined to a horizontal surface of the memory array area 102 of the die 101. As shown in FIG. Fig. As shown in Figure 1A, the second conductive pads 124B may at least partially (e.g., substantially) horizontally overlap the stack structure 112 (e.g., in the X direction). In some embodiments, the second conductive pads 124B at least partially horizontally overlap (e.g., in the X direction) some of the cell column structures 126 that extend vertically through the stack structure 112.

[0062] Again referring to Fig. 1B, at least some of the second conductive pads 124B may individually be disposed at least partially (e.g., substantially) within horizontal surface(s) of one or more logic sub-regions 134 of the logic region 130 that are relatively horizontally proximate the additional region 132 of the base structure 106. In some embodiments, one or more (e.g., each) of the second conductive pads 124B is substantially confined to a horizontal surface of at least one logic sub-region 134 that is proximate an outer horizontal boundary (e.g., in the X-direction) of the logic region 130. In additional embodiments, at least one (e.g., each) of the second conductive pads 124B has a portion of the second conductive pad 124B positioned within a horizontal surface of a logic sub-region 134 that is proximate an outer horizontal boundary (e.g.,in the X direction) of the logic region 130, and another portion of the second conductive pad 124B is positioned outside the horizontal surface of the logic sub-region 134. The additional portion of the second conductive pad 124B may be further disposed within a horizontal surface of the logic region 130 containing the logic sub-region 134 or outside the horizontal surface of the logic region 130.

[0063] Configurations and operational functions of the second conductive pads 124B may be selected based at least in part on the logic sub-region(s) 134 of the logic region 130 with which the second conductive pads 124B horizontally overlap or are arranged relatively horizontally in proximity (e.g., in the X-direction). Fig. 1B, the logic subsection 134 includes a pump subsection that includes charge pumps (V CCP -Charge pumps, V NEGWL-charge pumps, DVC2 charge pumps), at least some of the second conductive pads 124B that overlap horizontally and / or are arranged relatively horizontally near the logic subsection 134 may be power supply pads (e.g., V cc -Pads, V ss pads) that are configured and positioned to transmit current signals (e.g. V cc -signals, V ss signals) from some of the conductive wires 146. For example, at least one of the second conductive pads 124B may have a V cc -Pad, and at least one other of the second conductive pads 124B may comprise a V ss -Pad. One or more of the second conductive pads 124B, which are designated as V ccPads may be electrically connected to the voltage regulator device 150. Some of the conductive routing structures 152 may be used to electrically connect at least some of the second conductive pads 124B to other features (e.g., structures, devices) of the microelectronic device 100 and / or a package including the microelectronic device 100, as desired. As a non-limiting example, as shown in Fig. 1B, some conductive routing structures 152 may be located between one or more of the second conductive pads 124B, which may be referred to as V cc pads are used, and be coupled to the voltage regulator device 150.

[0064] In some embodiments, the operational functions of at least some of the second conductive pads 124B correspond to the operational functions of at least some of the first conductive pads 124A that are in their closest horizontal proximity (e.g., they are substantially identical to them). If one or more of the first conductive pads 124A are power supply pads (e.g., V cc -Pads, V ss -Pads), one or more of the second conductive pads 124B that are in the greatest horizontal proximity to one or more of the first conductive pads 124A may also include power supply pads (e.g., V cc -Pads, V ss -Pads), to give a non-limiting example. In some embodiments, one or more of the second conductive pads 124B, designated as V ccpads are used, positioned relatively horizontally near one or more of the first conductive pads 124A, which are also designated as V cc -pads are used; and one or more of the second conductive pads 124B, which are used as V ss pads are positioned relatively horizontally near one or more of the first conductive pads 124A, which are also designated as V ss Pads may be used. Positioning the first conductive pad(s) 124A and the second conductive pad(s) 124B, which have corresponding operational functions, in relatively horizontal proximity to each other can provide redundancy in performing the operational functions to ensure the reliability of the device.

[0065] The second conductive pads 124B can each individually have a desired horizontal cross-sectional shape. As shown in Fig. 1B, in some embodiments, each of the second conductive pads 124B has a substantially regular (e.g., square) horizontal cross-sectional shape. In further embodiments, one or more (e.g., each) of the second conductive pads 124B have an irregular horizontal cross-sectional shape, such as a circular cross-sectional shape, an oblong cross-sectional shape, an elliptical cross-sectional shape, a teardrop cross-sectional shape, a semicircular cross-sectional shape, a tombstone cross-sectional shape, a crescent cross-sectional shape, a triangular cross-sectional shape, a kite cross-sectional shape, and an irregular cross-sectional shape. Furthermore, each of the second conductive pads 124B may have substantially the same horizontal cross-sectional dimensions (e.g.,substantially the same horizontal width in the X-direction and substantially the same horizontal length in the Y-direction), or at least one of the second conductive pads 124B may have one or more different horizontal cross-sectional dimensions (e.g., a different horizontal width in the X-direction and / or a different horizontal length in the Y-direction) than at least one other of the second conductive pads 124B. In some embodiments, all of the second conductive pads 124B have substantially the same horizontal cross-sectional dimensions.

[0066] A horizontal cross-sectional shape of each of the second conductive pads 124B may be substantially the same as a horizontal cross-sectional shape of each of the first conductive pads 124A, or one or more horizontal cross-sectional shapes of the second conductive pads 124B may be different from one or more horizontal cross-sectional shapes of the first conductive pads 124A. Furthermore, the horizontal cross-sectional dimensions of each of the second conductive pads 124B may be substantially the same as the horizontal cross-sectional dimensions (e.g., substantially the same horizontal width in the X-direction and substantially the same horizontal length in the Y-direction) of each of the first conductive pads 124A, or one or more of the second conductive pads 124B may have one or more different horizontal cross-sectional dimensions (e.g.,a different horizontal width in the X-direction and / or a different horizontal length in the Y-direction) than one or more of the first conductive pads 124A.

[0067] The second conductive pads 124B may be spaced apart from each other in the horizontal direction (e.g., in the Y direction) by at least one additional pad pitch distance C1. The additional pad pitch distance C1 between two (2) horizontally adjacent second conductive pads 124B may depend at least in part on the configurations and functions of the two (2) second conductive pads 124B, as well as the configurations and positions of the first conductive pad(s) 124A and the conductive wire(s) 146 located horizontally (e.g., in the Y direction) between the two (2) second conductive pads 124B.In some embodiments, the additional pad pitch distance C1 is greater than or equal to about 15 µm, such as greater than or equal to about 20 µm, within a range of about 15 µm to about 50 µm, within a range of about 15 µm to about 30 µm, within a range of about 15 µm to about 25 µm, or within a range of about 15 µm to about 20 µm. Each pair of horizontally adjacent second conductive pads 124B may be horizontally separated by substantially the same additional pad pitch distance C1, or at least one pair of horizontally adjacent second conductive pads 124B may be horizontally separated by a different additional pad pitch distance C1 (e.g., a larger additional pad pitch distance C1, a smaller additional pad pitch distance C1) than at least one other pair of horizontally adjacent second conductive pads 124B.The additional pad pitch distance C1 between all horizontally adjacent second conductive pads 124B may be substantially equal (e.g., substantially equal) to the pad pitch distance B1 between all horizontally adjacent first conductive pads 124A, or the additional pad pitch distance C1 between at least two (2) horizontally adjacent second conductive pads 124B may be different (e.g., smaller or larger) than the pad pitch distance B1 between at least two (2) horizontally adjacent first conductive pads 124A. Conductive routing structures (e.g., signal routing structures) of the microelectronic device 100 may be disposed within the space between horizontally adjacent second conductive pads 124B (e.g., partially within) and extend through this space (e.g., extending horizontally, extending vertically).

[0068] Still referring to Fig. 1B, the second conductive pads 124B may be horizontally spaced from the first conductive pads 124A (e.g., in the X direction) by at least one further pad pitch distance D1. The further pad pitch distance D1 between at least one of the second conductive pads 124B and at least one of the first conductive pads 124A that is horizontally adjacent (e.g., in the X direction) to the second conductive pad 124B may be greater than or equal to the pad pitch distance B1 between the at least one of the first conductive pads 124A and at least one other of the first conductive pads 124A that is horizontally adjacent (e.g., in the Y direction) to the at least one of the first conductive pads 124A.In some embodiments, the further pad pitch distance D1 is greater than or equal to about 15 µm, such as greater than or equal to about 20 µm, within a range of about 15 µm to about 50 µm, within a range of about 15 µm to about 30 µm, within a range of about 15 µm to about 25 µm, or within a range of about 15 µm to about 20 µm. Each second conductive pad 124B may be horizontally separated from each first conductive pad 124A horizontally adjacent to the second conductive pad 124B by substantially the same further pad pitch distance D1, or at least one of the second conductive pads 124B may be horizontally separated from at least one of the first conductive pads 124A horizontally adjacent to the at least one of the second conductive pads 124B by a different further pad pitch distance D1 (e.g.,a larger further pad pitch distance D1, a smaller further pad pitch distance D1) than that between at least one other of the second conductive pads 124B and at least one other of the first conductive pads 124A that is horizontally adjacent to the at least one other of the second conductive pads 124B.

[0069] As in Fig. 1B, at least some (e.g., all) of the second conductive pads 124B may be substantially horizontally aligned with each other. For example, the second conductive pads 124B within a row of the second conductive pads 124B may be substantially horizontally aligned with each other. The row of second conductive pads 124B may extend horizontally in the Y-direction, and the horizontal centers of the second conductive pads 124B within the row may be substantially horizontally aligned with each other in the X-direction perpendicular to the Y-direction. The row of second conductive pads 124B may extend horizontally substantially parallel to a row of the first conductive pads 124A. In further embodiments, at least one of the second conductive pads 124B is at least partially horizontally offset from at least one other of the second conductive pads 124B in the X-direction (e.g.,at least partially horizontally disaligned therewith). For example, a horizontal center point of at least one of the second conductive pads 124B may be horizontally offset in the X direction from a horizontal center point of at least one other of the second conductive pads 124B in the X direction.

[0070] One or more (e.g., each) of the second conductive pads 124B may be at least partially horizontally offset in the Y direction from one or more (e.g., each) of the first conductive pads 124A that are horizontally closest thereto (e.g., horizontally closest). For example, a horizontal center point of at least one of the second conductive pads 124B that is horizontally offset in the Y direction may be distant from a horizontal center point of at least one first conductive pad 124A that is in close proximity. The horizontal centers of all of the second conductive pads 124B may be horizontally offset in the Y direction from the horizontal centers of all of the first conductive pads 124A, or a horizontal center point of at least one of the second conductive pads 124B may be substantially aligned in the Y direction with a horizontal center point of at least one of the first conductive pads 124A.As in . Fig. 1B, in some embodiments, at least one (e.g., each) of the second conductive pads 124B partially overlaps horizontally in the Y-direction with at least one (e.g., each) of the first conductive pads 124A that is horizontally adjacent to at least one of the second conductive pads 124B. In further embodiments, at least one (e.g., each) of the second conductive pads 124B does not overlap horizontally in the Y-direction with at least one (e.g., each) of the first conductive pads 124A that is horizontally adjacent to at least one of the second conductive pads 124B. In other words, the at least one of the second conductive pads 124B may be completely horizontally offset in the Y-direction from the at least one of the first conductive pads 124A that is horizontally adjacent to the at least one of the second conductive pads 124B.

[0071] Each of the second conductive pads 124B may be individually coupled to one of the conductive wires 146, or at least one of the second conductive pads 124B may not be coupled to one of the conductive wires 146. When a single second conductive pad 124B is coupled to a single conductive wire 146, the second conductive pads 124B may be physically connected (e.g., bonded) to the conductive wire 146 in any manner. In some embodiments, at least some of the second conductive pads 124B are connected to at least some of the conductive wires 146 by at least some of the conductive connection structures 154 (e.g., solder structures, such as one or more of solder balls and solder bumps).

[0072] As in Fig. 1B, the conductive wires 146 (e.g., bond pads) coupled to the conductive pads 124 (e.g., including the first conductive pads 124A and the second conductive pad 124B) may be spaced apart horizontally (e.g., in the Y direction) by at least a pad pitch distance E1. The pad pitch distance E1 between two (2) conductive wires 146 in horizontal proximity may depend at least in part on the configurations of the two (2) conductive wires 146 as well as on the configurations and positions of the two (2) conductive pads 124 (e.g., one (1) first conductive pad and one (1) second conductive pad 124B, two (2) first conductive pads 124A, two (2) first conductive pads 124A) connected to the two (2) conductive wires 146 (e.g., via two (2) of the conductive connection structures 154).Each pair of horizontally adjacent conductive wires 146 may be horizontally separated by substantially the same distance E1, or at least one pair of horizontally adjacent conductive wires 146 may be horizontally separated by a different distance E1 (e.g., a greater distance E1, a lesser distance E1) than at least one other pair of horizontally adjacent conductive wires 146.In some embodiments, the pad pitch distance E1 between one of the conductive wires 146 coupled to one of the first conductive pads 124A and another of the conductive wires 146 coupled to one of the second conductive pads 124B that is horizontally adjacent to the one of the first conductive pads 124A is about half (1 / 2) of a relatively greater distance between the one of the conductive wires 146 and yet another of the conductive wires 146 coupled to another of the first conductive pads 124A that is horizontally adjacent to the one of the first conductive pads 124A.

[0073] As previously described, the microelectronic device 100 may be designed to have a different configuration than that shown in Fig. 1A and Fig. 1B. As a non-limiting example, Fig. 2 shows a simplified, partial top view of a portion A of a microelectronic device 200 according to further embodiments of the disclosure. The portion A of the microelectronic device 200 may correspond to the portion A of the microelectronic device 100 previously described with reference to Fig. 1A and Fig. 1B, however, may have different configurations of features within a horizontal surface thereof compared to section A of the microelectronic device 100. In Fig. 2 and the associated description, functionally similar features (e.g., materials, structures, devices) are referred to with similar reference numbers incremented by 100. To avoid repetition, not all of the Fig. 2 described in detail. Unless otherwise described below, a feature in Fig. 2, which is designated by a reference number which is a 100-fold increase of the reference number of a feature previously designated by reference to one or more of the Fig. 1A and Fig. 1B shall be understood to be substantially similar to the previously described feature. By way of non-limiting example, unless otherwise described below, the features shown in Fig. 2 with the reference number 224A are to be understood as corresponding to the first conductive pads 124A, which are described in this document with reference to the Fig. 1A and Fig. 1B are substantially similar. As a further non-limiting example, unless otherwise described below, the Fig. 2 with the reference number 224B are to be understood as corresponding to the second conductive pads 124B, which are described in this document with reference to the Fig. 1A and Fig. 1B are substantially similar. In addition, unless otherwise described below, features of the devices described previously with reference to Fig. 1A in substantially the same manner (e.g., having substantially similar configurations and positions) in the embodiment described herein with reference to Fig. 2 described microelectronic device 200.

[0074] As in Fig. 2, a configuration of the microelectronic device 200 may be similar to the configuration of the microelectronic device 100 previously described with reference to Fig. 1A and Fig. 1B, except that the microelectronic device 200 may have different configurations and / or positions of one or more of at least some of the first conductive pads 224A (e.g., first bond pads), at least some of the second conductive pads 224B (e.g., second bond pads), and at least some of the conductive wires 246 (e.g., bond wires) compared to configurations and / or positions of the first conductive pads 124A ( Fig. 1A and Fig. 1B), the second conductive pads 124B ( Fig. 1A and Fig. 1B) or the conductive wires 146 ( Fig. 1A and Fig. 1B). The first conductive pads 224A, the second conductive pads 224B, and the conductive wires 246 of the microelectronic device 200, including non-limiting examples of possible configurations and possible positions thereof, are described in more detail below.

[0075] As in Fig. 2, one or more of the second conductive pads 224B may be arranged at different locations in the X-direction than one or more other of the second conductive pads 224B. For example, one or more of the second conductive pads 224B may be positioned horizontally in the X-direction relatively farther away from the additional region 232 (and thus relatively farther into the logic region 230) of the base structure 206. For example, one or more (e.g., two or more) of the second conductive pads 224B may be arranged at one or more different positions in the X-direction within one or more of the logic sub-regions 234 (e.g., a pump sub-region, a driver sub-region, a memory cache sub-region, a decoder sub-region, a sense amplifier sub-region) of the logic region 230 than one or more other of the second conductive pads 224B. In some embodiments, one or more (e.g.,two or more) of the second conductive pads 224B are offset horizontally in the X-direction from one or more other of the second conductive pads 224B such that the one or more second conductive pads 224B are positioned relatively closer to a horizontal midpoint in the X-direction of an individual logic sub-region 234 of the logic region 230 than the one or more other of the second conductive pads 224B.

[0076] The horizontal centers of at least two of the second conductive pads 224B may be substantially horizontally aligned with each other in the X-direction and may each be horizontally offset in the X-direction from a horizontal center of at least one other of the second conductive pads 224B. In some embodiments, at least two of the second conductive pads 224B that are substantially horizontally aligned with each other in the X-direction are horizontally adjacent in the Y-direction. In further embodiments, at least two of the second conductive pads 224B that are substantially horizontally aligned with each other in the X-direction are not horizontally adjacent in the Y-direction.For example, at least one further second conductive pad 224B, whose horizontal center point in the X direction is offset from the horizontal centers of the at least two second conductive pads 224B, may be arranged horizontally between the at least two second conductive pads 224B in the Y direction. In further embodiments, a horizontal center point of each of the second conductive pads 224B is offset horizontally in the X direction from a horizontal center point of any other of the second conductive pads 224B.

[0077] As in Fig. 2, at least one of the second conductive pads 224B may be spaced horizontally (e.g., in the Y-direction) from at least one other of the second conductive pads 224B by a first additional pad spacing distance C2 that is different (e.g., greater or lesser) than a second additional pad spacing distance C3 between the at least one of the second conductive pads 224B and at least one other of the second conductive pads 224B. For example, a horizontal center point in the Y-direction of the at least one of the second conductive pads 224B may be relatively closer to a horizontal center point in the Y-direction of the at least one other of the second conductive pads 224B than to a horizontal center point in the Y-direction of the at least one other of the second conductive pads 224B, such that the first additional pad spacing distance C2 is greater than the second additional pad spacing distance C3. As shown in Fig. 2, in some such embodiments, at least one of the second conductive pads 224B horizontally overlaps in the Y-direction a pair of horizontally adjacent first conductive pads 224A to a greater extent than another of the pair of horizontally adjacent first conductive pads 224A. In additional embodiments, the at least one of the second conductive pads 224B does not overlap in the Y-direction a pair of horizontally adjacent first conductive pads 224A that is horizontally proximate to the at least one of the second conductive pads 224B to a greater extent than another of the pair of horizontally adjacent first conductive pads 224A.In some embodiments, the first additional pad pitch distance C2 and the second additional pad pitch distance C3 are each individually greater than or equal to about 15 µm, such as greater than or equal to about 20 µm, within a range of about 15 µm to about 50 µm, within a range of about 15 µm to about 30 µm, within a range of about 15 µm to about 25 µm, or within a range of about 15 µm to about 20 µm.

[0078] With further reference to Fig. 2, one or more of the first conductive pads 224A may be arranged at different locations in the X-direction than one or more other first conductive pads 224A. For example, one or more of the first conductive pads 224A may be arranged horizontally in the X-direction relatively closer to the logic region 230 of the base structure 206. In some embodiments, the first conductive pads 224A are each arranged within a horizontal surface of the additional region 232 of the base structure 206, but one or more of the first conductive pads 224A are located relatively closer to a horizontal boundary of the logic region 230 of the base structure 206 than one or more other of the first conductive pads 224A.In additional embodiments, one or more of the first conductive pads 224A are partially disposed within a horizontal surface of the additional region 232 of the base structure 206 and also partially within a horizontal surface of the logic region 230 of the base structure 206; and one or more other of the first conductive pads 224A are not partially disposed within the horizontal surface of the logic region 230 of the base structure 206 (e.g., they are bounded by the horizontal surface of the additional region 232 of the base structure 206). If a single first conductive pad 224A extends horizontally into the horizontal region of the logic region 230 of the base structure 206, the first conductive pad 224A may be partially disposed within a horizontal surface of a logic sub-region 234 (e.g.,a pump portion, a driver portion, a memory cache portion, a decoder portion, a sense amplifier portion) within the logic portion 230, or may not be partially positioned within a horizontal surface of a logic sub-portion 234 within the logic portion 230. In some embodiments, one or more of the first conductive pads 224A are horizontally offset in the X-direction from one or more other of the first conductive pads 224A such that the one or more first conductive pads 224A are positioned relatively closer to a horizontal midpoint in the X-direction of an individual logic sub-portion 234 of the logic portion 230 than the one or more other of the first conductive pads 224A. As shown in FIG. Fig. 2, in some such embodiments, one or more of the second conductive pads 224B that are horizontally adjacent to one or more of the first conductive pads 224A are arranged relatively closer to the horizontal X-direction midpoint of the single logic sub-region 234 of the logic region 230 than one or more other of the second conductive pads 224B.

[0079] The horizontal centers of some of the first conductive pads 224A may be substantially horizontally aligned with each other in the X-direction and may be horizontally offset in the X-direction from the horizontal centers of one or more other first conductive pads 224A. In some embodiments, at least two of the first conductive pads 224A that are substantially horizontally aligned with each other in the X-direction are horizontally adjacent in the Y-direction. In further embodiments, at least two of the first conductive pads 224A that are substantially horizontally aligned with each other in the X-direction are not horizontally adjacent in the Y-direction.For example, at least one further one of the first conductive pads 224A, whose horizontal center point in the X direction is offset from the horizontal centers of the at least two first conductive pads 224A, may be arranged horizontally between the at least two first conductive pads 224A in the Y direction. In further embodiments, a horizontal center point of each of the first conductive pads 224A is horizontally offset in the X direction from a horizontal center point of each other of the first conductive pads 224A. In still further embodiments, a horizontal center point of each of the first conductive pads 224A is horizontally aligned in the X direction with the horizontal center point of each other of the first conductive pads 224A.

[0080] As from Fig. 2, at least one of the first conductive pads 224A may be spaced horizontally in the X-direction from at least one of the second conductive pads 224B by a first further pad spacing distance D2 that is different (e.g., greater or smaller than) a second further pad spacing distance D3 between at least one other of the first conductive pads 224A and the at least one of the second conductive pads 224B. For example, a horizontal center point in the X-direction of the at least one other of the first conductive pads 224A may be relatively closer to a horizontal center point in the X-direction of the at least one of the second conductive pads 224B than to a horizontal center point in the X-direction of the at least one of the first conductive pads 224A, such that the first further pad spacing distance D2 is greater than the second further pad spacing distance D3. As shown in Fig. 2, in some embodiments, at least one of the first conductive pads 224A is horizontally spaced in the X-direction from at least one other of the second conductive pads 224B by the second further pad spacing distance D3. In some embodiments, the first further pad spacing distance D2 and the second further pad spacing distance D3 are each individually greater than or equal to about 15 µm, such as greater than or equal to about 20 µm, within a range of about 15 µm to about 50 µm, within a range of about 15 µm to about 30 µm, within a range of about 15 µm to about 25 µm, or within a range of about 15 µm to about 20 µm.

[0081] As in Fig. 2, in some embodiments, at least one (but not each) of the second conductive pads 224B is not coupled to any of the conductive wires 246. At least one of the second conductive pads 224B may be free of a conductive connection structure 254 thereon. A first pad pitch distance E2 between a pair of horizontally adjacent conductive wires 246 operatively associated with one of the first conductive pads 124A and one of the second conductive pads 224B may be different (e.g., smaller or larger) than a second pad pitch distance E3 between another pair of horizontally adjacent conductive wires 246 operatively associated with a pair of the first conductive pads 124A. In further embodiments, at least one (but not each) of the first conductive pads 224A is not coupled to any of the conductive wires 246.At least one of the first conductive pads 224A may be free of a conductive connection structure 254 located thereon.

[0082] Thus, a microelectronic device according to embodiments of the disclosure comprises a base structure, a memory array overlying the base structure, and a conductive pad level overlying the memory array. The base structure comprises a logic region containing logic devices. The memory array comprises vertically extending chains of memory cells within a horizontal surface of the logic region of the base structure. The conductive pad level comprises first conductive pads lying substantially outside the horizontal surface of the logic region of the base structure and second conductive pads horizontally adjacent to the first conductive pads and lying within the horizontal surface of the logic region of the base structure.

[0083] Furthermore, a memory device according to embodiments of the disclosure includes a base structure, a conductive routing plane, a stack structure, a memory array, an additional conductive routing plane, conductive contacts, first conductive pads, and second conductive pads. The base structure includes a region with complementary metal-oxide-semiconductor (CMOS) circuitry and an additional region horizontally adjacent to the region and substantially free of the CMOS circuitry. The conductive routing plane lies above the base structure. The stack structure lies above the conductive routing plane and includes conductive material and insulating material alternating vertically with the conductive material. The memory array includes chains of memory cells extending through the stack structure. The memory array is located in a horizontal area of ​​the base structure region.The additional conductive routing level lies above the stack structure. The conductive contacts are horizontally offset from the memory array and extend between the conductive routing level and the additional conductive routing level. The first conductive pads lie above the additional conductive routing level and lie in a horizontal area of ​​the additional area of ​​the base structure. The first conductive pads are in electrical connection with some of the conductive contacts. The second conductive pads lie above the additional conductive routing level and are arranged horizontally between the first conductive pads and at least some of the chains of memory cells of the memory array. The second conductive pads are in electrical connection with another of the conductive contacts.

[0084] Microelectronic devices (e.g., microelectronic devices 100, 200) according to embodiments of the disclosure may be used in electronic systems of the disclosure. For example, Fig. 3 is a block diagram of an exemplary electronic system 300 according to embodiments of the disclosure. Electronic system 300 may include, for example, a computer or computer hardware component, a server or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media player (e.g., music), a Wi-Fi or cellular-enabled tablet such as an iPad® or a SURFACE® tablet, an electronic book, a navigation device, etc. Electronic system 300 includes at least one storage device 302. Storage device 302 may include, for example, a microelectronic device (e.g., microelectronic devices 100, 200 previously described herein).The electronic system 300 may also include at least one electronic signal processing device 304 (often referred to as a "microprocessor"). The electronic signal processing device 304 may optionally include a microelectronic device (e.g., the microelectronic devices 100, 200 described previously herein). While the memory device 302 and the electronic signal processing device 304 are shown in FIG. Fig.3 are shown as two (2) separate devices, in further embodiments, a single (e.g., only one) memory / processor device with the functions of the memory device 302 and the electronic signal processor device 304 is included in the electronic system 300. In such embodiments, the memory / processor device may include a microelectronic device (e.g., the microelectronic devices 100, 200 previously described herein). The electronic system 300 may further include one or more input devices 306 for inputting information into the electronic system 300 by a user, such as a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 300 may further include one or more output devices 308 for outputting information (e.g.,visual or audio output) to a user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 306 and the output device 308 may comprise a single touchscreen device that can be used to both input information into the electronic system 300 and output visual information to a user. The input device 306 and the output device 308 may electrically communicate with the storage device 302 or the electronic signal processor device 304.

[0085] Thus, an electronic system according to embodiments of the disclosure comprises an input device, an output device, a processor device operatively connected to the input device and the output device, and a memory device operatively connected to the processor device. The memory device comprises a stack structure, a base structure, a memory array, and bond pads. The stack structure comprises conductive structures vertically interleaved with insulating structures. The base structure lies vertically below the stack structure and includes a logic region containing logic circuitry. The memory array comprises chains of memory cells extending vertically through the stack structure. The memory array is located in a horizontal region of the logic region of the base structure. The bond pads, which lie vertically above the stack structure, are in electrical connection with the logic circuitry.The bond pads include first bond pads and second bond pads. The first bond pads are located outside the horizontal surface of the logic area of ​​the base structure. The second bond pads are located within the horizontal surface of the logic area of ​​the base structure.

[0086] The structures and devices of the disclosure advantageously perform one or more of the following: improved microelectronic device performance, lower costs (e.g., manufacturing costs, material costs), greater component miniaturization, and higher packaging density compared to conventional structures, conventional devices, and conventional methods. The structures and devices of the disclosure may also improve scalability, efficiency, and simplicity compared to conventional structures and devices.

[0087] Further non-limiting embodiments of the disclosure are set forth below.

[0088] Embodiment 1: A microelectronic device comprising: a base structure comprising a logic region with logic devices; a memory array overlying the base structure and comprising vertically extending chains of memory cells within a horizontal surface of the logic region of the base structure; and a conductive pad level overlying the memory array and comprising: first conductive pads substantially outside the horizontal surface of the logic region of the base structure; and second conductive pads horizontally adjacent to the first conductive pads and within the horizontal surface of the logic region of the base structure.

[0089] Embodiment 2: The microelectronic device of Embodiment 1, wherein: the second conductive pads each lie at least partially within a horizontal surface of a memory array region including the memory array therein; and the first conductive pads each lie substantially outside the horizontal surface of the memory array region.

[0090] Embodiment 3: The microelectronic device of embodiment 2, further comprising conductive contact structures overlying the base structure and within a horizontal surface of a contact region horizontally adjacent to the memory array region, the conductive contact structures being in electrical communication with at least some of the first conductive pads and at least some of the second conductive pads.

[0091] Embodiment 4: The microelectronic device of embodiment 3, wherein at least some of the second conductive pads are partially located within the horizontal surface of the memory array region and partially within the horizontal surface of the contact region.

[0092] Embodiment 5: The microelectronic device of any of embodiments 3 and 4, wherein at least some of the conductive contact structures are in electrical connection with charge pumps within the logic region of the base structure.

[0093] Embodiment 6: The microelectronic device according to any one of Embodiments 1 to 5, wherein: the first conductive pads comprise a row of the first conductive pads; and the second conductive pads comprise a row of the second conductive pads extending horizontally parallel to the row of the first conductive pads.

[0094] Embodiment 7: The microelectronic device according to any one of Embodiments 1 to 5, further comprising conductive wires attached to the first conductive pads and the second conductive pads.

[0095] Embodiment 8: The microelectronic device of embodiment 7, wherein at least some of the first conductive pads and at least some of the second conductive pads are configured and positioned to receive power signals from at least some of the conductive wires.

[0096] Embodiment 9: The microelectronic device of Embodiment 8, wherein one or more of the first conductive pads and one or more of the second conductive pads are electrically connected to a voltage regulating device.

[0097] Embodiment 10: The microelectronic device of any one of embodiments 1 to 9, wherein at least some of the first conductive pads are offset from at least some of the second conductive pads in a first horizontal direction by at least a distance within a range of about 15 µm to about 50 µm.

[0098] Embodiment 11: The microelectronic device of embodiment 10, wherein at least one of the first conductive pads is offset from at least one other of the first conductive pads in a second horizontal direction orthogonal to the first horizontal direction by at least an additional distance of greater than or equal to about 15 µm.

[0099] Embodiment 12: The microelectronic device of embodiment 11, wherein at least one of the second conductive pads is offset from at least one other of the second conductive pads in the second horizontal direction by at least a further distance of greater than or equal to about 15 µm.

[0100] Embodiment 13: The microelectronic device of any one of embodiments 1 to 12, wherein at least one of the second conductive pads is offset from two of the first conductive pads closest thereto in the first horizontal direction and is at least partially disposed between the two first conductive pads in a second horizontal direction perpendicular to the first horizontal direction.

[0101] Embodiment 14: A memory device comprising: a base structure comprising a region comprising complementary metal oxide semiconductor (CMOS) circuitry and an additional region horizontally adjacent to the region and substantially free of the CMOS circuitry; a conductive routing plane overlying the base structure; a stack structure overlying the conductive routing plane and comprising conductive material and insulating material alternating vertically with the conductive material; a memory array comprising chains of memory cells extending through the stack structure, the memory array being located within a horizontal surface of the region of the base structure; an additional conductive routing plane overlying the stack structure; an additional conductive routing plane overlying the stack structure;conductive contacts horizontally offset from the memory array and extending between the conductive routing plane and the additional conductive routing plane; first conductive pads located above the additional conductive routing plane and within a horizontal surface of the additional region of the base structure, the first conductive pads being in electrical communication with some of the conductive contacts; and second conductive pads located above the additional conductive routing plane and arranged horizontally between the first conductive pads and at least some of the chains of memory cells of the memory array, the second conductive pads being in electrical communication with some other of the conductive contacts.

[0102] Embodiment 15: The memory device of Embodiment 14, wherein the second conductive pads are positioned with the horizontal surface of the region of the base structure.

[0103] Embodiment 16: The memory device of Embodiment 15, wherein: some of the conductive contacts that are in electrical connection with the first conductive pads are arranged within the horizontal surface of the additional region of the base structure; and some other of the conductive contacts that are in electrical connection with the second conductive pads are arranged within the horizontal surface of the region of the base structure.

[0104] Embodiment 17: The memory device of any of Embodiments 14 to 16, wherein: the second conductive pads are arranged horizontally between the first conductive pads and the memory array in a first horizontal direction; and horizontal centers of at least some of the second conductive pads are substantially aligned with each other in a second horizontal direction orthogonal to the first horizontal direction.

[0105] Embodiment 18: The memory device of any one of Embodiments 14 to 16, wherein: the second conductive pads are horizontally disposed between the first conductive pads and the at least some of the chains of memory cells of the memory array in a first horizontal direction; and a horizontal center of each of the second conductive pads is horizontally offset in a second horizontal direction orthogonal to the first horizontal direction from a horizontal center of each of the first conductive pads.

[0106] Embodiment 19: The memory device of any one of Embodiments 14 to 18, wherein the second conductive pads are arranged in a row disposed between the first conductive pads and the at least some of the chains of memory cells of the memory array in a first horizontal direction, the row extending in a second horizontal direction perpendicular to the first horizontal direction.

[0107] Embodiment 20: The memory device of any one of embodiments 14 to 19, wherein at least one of the second conductive pads horizontally overlaps at least one of the chains of memory cells of the memory array.

[0108] Embodiment 21: The memory device of any one of Embodiments 14 to 20, further comprising conductive wires connected to at least some of the first conductive pads and at least some of the second conductive pads, wherein the conductive wires are coupled to the leads of a lead frame.

[0109] Embodiment 22: The memory device according to any one of Embodiments 14 to 21, wherein: at least one of the second conductive pads comprises a supply voltage pad (V cc ); and at least one other of the second conductive pads comprises a ground pad (V ss ) includes.

[0110] Embodiment 23: An electronic system comprising: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device and comprising: a stack structure comprising conductive structures vertically interleaved with insulating structures; a base structure lying vertically beneath the stack structure and comprising a logic region containing logic circuitry; a memory array comprising chains of memory cells extending vertically through the stack structure, the memory array being positioned in a horizontal region of the logic region of the base structure;and bond pads arranged vertically above the stack structure and in electrical connection with the logic circuit, the bond pads comprising: first bond pads arranged outside the horizontal surface of the logic area of ​​the base structure; and second bond pads arranged within the horizontal surface of the logic area of ​​the base structure.

[0111] Embodiment 24: The electronic system of embodiment 23, wherein the logic circuit of the base structure comprises a complementary metal oxide semiconductor (CMOS) circuit.

[0112] Embodiment 25: The electronic system of any of embodiments 23 and 24, wherein the memory device comprises a 3D NAND flash memory device.

[0113] While the disclosure allows for various modifications and alternative embodiments, certain embodiments are shown by way of example in the drawings and described in detail herein. However, the disclosure is not limited to these particular forms. Rather, the disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the scope of the following appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment may be combined with elements and features disclosed with respect to other embodiments of the disclosure.

Claims

[1] A microelectronic device (100, 200) comprising: a base structure (106; 206) comprising a logic area (130, 230) including logic devices; a memory array overlying the base structure (106; 206) and comprising vertically extending chains of memory cells (142) within a horizontal region of the logic region (130, 230) of the base structure (106; 206); and a conductive pad plane (122) overlying the memory array and comprising: first conductive pads (124A, 224A) substantially outside the horizontal surface of the logic area (130, 230) of the base structure (106; 206); and second conductive pads (124B, 224B) horizontally adjacent to the first conductive pads (124A, 224A) and within the horizontal surface of the logic area (130, 230) of the base structure (106; 206); wherein at least one of the second conductive pads (124B, 224B) is offset from two of the first conductive pads (124A, 224A) that are closest in the first horizontal direction and is disposed at least partially between the two first conductive pads (124A, 224A) in a second horizontal direction perpendicular to the first horizontal direction. [2] Microelectronic device (100, 200) according to claim 1, wherein: the second conductive pads (124B, 224B) each lie at least partially within a horizontal surface of a memory array region (102, 202) containing the memory array; and the first conductive pads (124A, 224A) each lie substantially outside the horizontal surface of the memory array region (102, 202). [3] The microelectronic device (100, 200) of claim 2, further comprising conductive contact structures (128) overlying the base structure (106; 206) and within a horizontal surface of a contact region (104, 204) horizontally adjacent to the memory array region (102, 202), the conductive contact structures (128) being in electrical communication with at least some of the first conductive pads (124A, 224A) and with at least some of the second conductive pads (124B, 224B). [4] The microelectronic device (100, 200) of claim 3, wherein at least some of the second conductive pads (124B, 224B) are partially within the horizontal surface of the memory array region (102, 202) and partially within the horizontal surface of the contact region (104, 204). [5] The microelectronic device (100, 200) of claim 3, wherein at least some of the conductive contact structures (128) are in electrical communication with charge pumps within the logic region (130, 230) of the base structure (106; 206). [6] Microelectronic device (100, 200) according to one of claims 1 to 5, wherein: the first conductive pads (124B, 224B) comprise a row of the first conductive pads (124A); and the second conductive pads (124B, 224B) comprise a row of the second conductive pads (124B, 224B) extending horizontally parallel to the row of the first conductive pads (124A). [7] The microelectronic device (100, 200) of any one of claims 1 to 5, further comprising conductive wires (146, 246) attached to the first conductive pads (124A, 224A) and the second conductive pads (124B, 224B). [8] The microelectronic device (100, 200) of claim 7, wherein at least some of the first conductive pads (124A, 224A) and at least some of the second conductive pads (124B, 224B) are configured and positioned to receive power signals from at least some of the conductive wires (146, 246). [9] The microelectronic device (100, 200) of claim 8, wherein one or more of the first conductive pads (124A, 224A) and one or more of the second conductive pads (124B, 224B) are electrically connected to a voltage regulating device. [10] The microelectronic device (100, 200) of any one of claims 1 to 5, wherein at least some of the first conductive pads (124A, 224A) are offset from at least some of the second conductive pads (124B, 224B) in a first horizontal direction by at least a distance within a range of 15 µm to 50 µm. [11] The microelectronic device (200) of claim 10, wherein at least one of the first conductive pads (224A) is offset from at least one other of the first conductive pads (224A) in a second horizontal direction orthogonal to the first horizontal direction by at least an additional distance of greater than or equal to 15 µm. [12] The microelectronic device (200) of claim 11, wherein at least one of the second conductive pads (224B) is offset from at least one other of the second conductive pads (224B) in the second horizontal direction by at least a further distance greater than or equal to 15 µm. [13] A storage device (100, 200, 302) comprising: a base structure (106; 206) comprising a region (130, 230) comprising a complementary metal oxide semiconductor, CMOS, circuitry, and an additional region (132, 232) horizontally adjacent to the region and substantially free of the CMOS circuitry; a conductive routing layer (108) lying above the base structure (106; 206); a stack structure (112) overlying the conductive routing plane (108) and comprising conductive material and insulating material alternating vertically with the conductive material; a memory array comprising chains of memory cells (142) extending through the stack structure (112), the memory array being located within a horizontal surface of the region of the base structure (106; 206); an additional conductive routing layer (114) lying above the stack structure (112); conductive contact structures (128) that are horizontally offset from the memory array and extend between the conductive routing plane (108) and the additional conductive routing plane (114); first conductive pads (124A, 224A) located above the additional conductive routing plane (114) and within a horizontal surface of the additional portion of the base structure (106; 206), the first conductive pads (124A, 224A) being in electrical connection with some of the conductive contact structures (128); and second conductive pads (124B, 224B) overlying the additional conductive routing plane (114) and arranged horizontally between the first conductive pads (124A, 224A) and at least some of the chains of memory cells (142) of the memory array, the second conductive pads (124B, 224B) being positioned within the horizontal surface of the region of the base structure (106; 206) and being in electrical connection with some other of the conductive contact structures (128). [14] The storage device (100, 200, 302) of claim 13, wherein: some of the conductive contact structures (128) that are in electrical connection with the first conductive pads (124A, 224A) are arranged within the horizontal surface of the additional region of the base structure (106; 206); and the several other conductive contact structures (128) which are in electrical connection with the second conductive pads are arranged in the horizontal surface of the region of the base structure (106; 206). [15] Storage device (100, 302) according to one of claims 13 to 14, wherein: the second conductive pads (124B, 224B) are arranged horizontally between the first conductive pads (124A) and the memory array in a first horizontal direction; and the horizontal centers of at least some of the second conductive pads (124B) are substantially aligned with each other in a second horizontal direction orthogonal to the first horizontal direction. [16] Storage device (200, 302) according to one of claims 13 to 14, wherein: the second conductive pads (224B) are arranged horizontally between the first conductive pads (224A) and the at least some of the chains of memory cells (142) of the memory array in a first horizontal direction; and a horizontal center of each of the second conductive pads (224B) is horizontally offset from a horizontal center of each of the first conductive pads (224A) in a second horizontal direction orthogonal to the first horizontal direction. [17] The memory device (100, 200, 302) of any one of claims 13 to 14, wherein the second conductive pads (124B, 224B) are arranged in a row that lies between the first conductive pads (124A, 224A) and the at least some of the chains of memory cells (142) of the memory array in a first horizontal direction, the row extending in a second horizontal direction perpendicular to the first horizontal direction. [18] The memory device (100, 200, 302) of any one of claims 13 to 14, wherein at least one of the second conductive pads (224B) horizontally overlaps at least one of the chains of memory cells (142) of the memory array. [19] The memory device (100, 200, 302) of any one of claims 13 to 14, further comprising conductive wires (146, 246) connected to at least some of the first conductive pads (124A, 224A) and at least some of the second conductive pads (124B, 224B), the conductive wires (146, 246) being coupled to leads of a lead frame. [20] Storage device (100, 200, 302) according to one of claims 13 to 14, wherein: at least one of the second conductive pads (124B, 224B) has a supply voltage, V cc ,-Pad; and at least one other of the second conductive pads (124B, 224B) is a ground contact point, V ss , includes. [21] Electronic system (300) comprising: an input device (306); an output device (308); a processor device (304) operatively connected to the input device (306) and the output device (308); and a memory device (302) operatively connected to the processor device (304) and comprising: a base structure (106; 206) comprising a region (130, 230) comprising a complementary metal oxide semiconductor, CMOS, circuitry, and an additional region (132, 232) horizontally adjacent to the region and substantially free of the CMOS circuitry; a conductive routing layer (108) lying above the base structure (106; 206); a stack structure (112) overlying the conductive routing plane (108) and comprising conductive material and insulating material alternating vertically with the conductive material; a memory array comprising chains of memory cells (142) extending through the stack structure (112), the memory array being located within a horizontal surface of the region of the base structure (106; 206); an additional conductive routing layer (114) lying above the stack structure (112); conductive contact structures (128) that are horizontally offset from the memory array and extend between the conductive routing plane (108) and the additional conductive routing plane (114); first conductive pads (124A, 224A) located above the additional conductive routing plane (114) and within a horizontal surface of the additional portion of the base structure (106; 206), the first conductive pads (124A, 224A) being in electrical connection with some of the conductive contact structures (128); and second conductive pads (124B, 224B) overlying the additional conductive routing plane (114) and arranged horizontally between the first conductive pads (124A, 224A) and at least some of the chains of memory cells (142) of the memory array, the second conductive pads (124B, 224B) being positioned within the horizontal surface of the region of the base structure (106; 206) and being in electrical connection with some other of the conductive contact structures (128). [22] The electronic system (300) of claim 21, wherein the memory device comprises a 3D NAND flash memory device.

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