SEMICONDUCTOR DEVICE, METHOD FOR TESTING THE SAME

Abstract

Semiconductor device comprising: a variety of electrode pads; a first input-output block (111) coupled to the plurality of electrode pads (121, 122); a second input-output block (112) coupled to the plurality of electrode pads; a third input-output block (113) coupled to the plurality of electrode pads (121, 122); a first functional block (101) coupled to each of the plurality of electrode pads via the first input-output block (111); a second functional block (102) coupled to each of the plurality of electrode pads via the second input-output block (112); and a third functional block (103) coupled to each of the plurality of electrode pads via the third input-output block (113), wherein the first and second functional blocks (101, 102) are arranged at positions opposite to each other to sandwich the first, second and third input-output blocks (111, 112, 113).

Description

BACKGROUND

[0001] The present disclosure relates to a semiconductor device and a method for testing and designing the semiconductor device, and relates, for example, to a semiconductor device having a plurality of functional blocks, a method for testing and designing such a semiconductor device.

[0002] A disclosed technique is listed below. [Patent Document 1] JP 2001-034 650 A [Patent document 2] US 2021 / 0 066 171 A1 [Patent document 3] US 2008 / 0 013 376 A1 [Patent document 4] US 2021 / 0 043 602 A1 [Patent Document 5] US 6,356,095 B1

[0003] As a related art, Patent Document 1 discloses a method for designing a semiconductor device. In Patent Document 1, the semiconductor device combines a plurality of macrocells by arranging various element circuits on the semiconductor chip. The semiconductor device has a plurality of pads arranged at predetermined intervals along its outer periphery. Furthermore, the semiconductor device includes an analog-to-digital (AD) converter arranged in the center of the chip and an input-output buffer cell arranged on the outer periphery of the chip. The AD converter and the input-output buffer cell are connected to each other, and the input-output buffer cell and the pad are connected to each other. Patent Document 2 discusses a semiconductor chip, a semiconductor wafer, a semiconductor device including the semiconductor chip, and a manufacturing method of the semiconductor device.Patent Document 3 describes memory units, memory compilation systems, and a corresponding method. Patent Document 4 discloses an integrated electronic element module, a semiconductor package, and a corresponding manufacturing method. Finally, Patent Document 5 describes a semiconductor integrated circuit with three input / output elements for wafer testing and a plurality of input / output terminals. SUMMARY

[0004] Recently, with the increasing performance and functionality of electronic devices, a plurality of functional blocks are often mounted on a semiconductor chip. In such a semiconductor chip, in order to reduce the number of pads mounted on the semiconductor chip, one pad for inputting and outputting the signal of each functional block to the outside may be shared by a plurality of functional blocks. Patent Document 1 does not consider that one pad is shared by a plurality of functional blocks. In Patent Document 1, when one pad is shared by a plurality of functional blocks, the length of wiring from the pad to one functional block is longer than the length of wiring from the pad to the other functional block.

[0005] Other tasks and novel features will become apparent from the description of this specification and the accompanying drawings.

[0006] According to one embodiment, a semiconductor device is provided. The semiconductor device includes first and second input / output blocks, a first functional block, and a second functional block. The first functional block is connected to each of a plurality of electrode pads via the first input / output block. The second functional block is connected to each of the plurality of electrode pads via the second input / output block. In the semiconductor device, the first functional block and the second functional block are arranged at opposite positions to sandwich the first and second input / output blocks.

[0007] According to one embodiment, in the signal path from the electrode pad to the first functional block via the first input-output block and in the signal path from the electrode pad to the second functional block via the second input-output block, it is possible to reduce the resistance and capacitance associated with each signal path. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a part of a semiconductor device according to a first numbered example of the present disclosure. Fig. 2 is a circuit diagram showing a circuit configuration of the semiconductor device. Fig. 3 is a cross-sectional diagram showing an AA cross-section of Fig. 1 shows. Fig. 4 is a plan view showing a layout example of a semiconductor chip. Fig. 5 is a plan view showing another layout example of a semiconductor chip. Fig. 6 is a plan view showing yet another layout example of a semiconductor chip. Fig. 7 is a flowchart showing a method of designing a semiconductor device. Fig. Figure 8 is a block diagram showing a configuration example of a computer. Fig. 9 is a block diagram showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 10 is a block diagram showing a semiconductor device according to a third numbered example of the present disclosure. Fig. 11 is a block diagram schematically showing a test for a semiconductor device. Fig. 12 is a plan view showing an example of a layout of a semiconductor device used in the study. Fig. Figure 13 is a block diagram showing part of a semiconductor chip. DETAILED DESCRIPTION

[0008] Before describing the embodiments, the background leading to the following embodiments is described. Fig. Figure 12 shows an example of a layout of a semiconductor device (semiconductor chip) used in the study. This semiconductor chip 200 includes a plurality of electrode pads 201, an input-output block (input-output circuit) 202, and an internal logic forming region 203. The plurality of electrode pads 201 at the peripheral part of the semiconductor chip 200 are arranged side by side in the X direction and the Y direction. In the semiconductor chip 200, the plurality of electrode pads 201 are stacked and arranged on the input-output circuit 202 to reduce the chip area.

[0009] A plurality of functional blocks are arranged in the internal logic forming area 203. The plurality of functional blocks includes, but is not limited to, a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM), and peripheral circuits. In the example of Fig. 12, a functional block (functional block A) 211 and a functional block (functional block B) 212 are arranged in the internal logic forming area 203. At least a portion of the plurality of electrode pads 201 is shared by the plurality of functional blocks.

[0010] Fig. Figure 13 shows a portion of the semiconductor chip mentioned above. In this case, the two electrode pads 251 and 252 are shared by the functional block A 211 and the functional block B 212. The electrode pads 251 and 252 correspond to the Fig. 12. The electrode pads 251 and 252 are connected to the input-output circuit (input-output circuit A) 221 of the functional block A 211 and the input-output circuit (input-output circuit B) 222 of the functional block B 212, respectively. The input-output circuit A 221 and the input-output circuit B 222 include a block connected to the electrode pad 251 and a block connected to the electrode pad 252, respectively. The input-output circuit A 221 and the input-output circuit B 222 at the peripheral part of the semiconductor chip 200 are arranged side by side in the X direction.

[0011] In Fig. 13, the electrode pads 251 are stacked on the input-output circuit A 221, and the electrode pad 252 is stacked on the input-output circuit B 222. The electrode pad 251 is connected to the input-output circuit A 221 via a contact and is connected to the input-output circuit B 222 via a wiring 261. On the other hand, the electrode pad 252 is connected to the input-output circuit B 222 via a contact and is connected to the input-output circuit A 221 via a wiring 262. The functional block A 211 is connected to the input-output circuit 221. The functional block B 212 is connected to the input-output circuit 222.

[0012] Here, a voltage drop, a change in the signal change timing, and noise may occur in the wiring connecting the electrode pad and the input-output circuit, and the wiring connecting the functional block and the input-output circuit in the semiconductor chip. In the design of the semiconductor chip 200, in order to reduce noise or the like, the design is carried out so that the wiring has no resistance and no capacitance. In the example of Fig. 13, the electrode pad 251 is stacked on the input-output circuit A 221, and the electrode pad 251 and the input-output circuit A 221 are connected on the input-output circuit A 221. Further, the electrode pad 252 is stacked on the input-output circuit B 222, and the electrode pad 252 and the input-output circuit B 222 are connected on the input-output circuit B 222.

[0013] However, in order to avoid short-circuiting of the electrode pad 252, the electrode pad 251 and the input-output circuit B 222 are connected using the wiring 261 passing through the outer portion of the input-output circuit A 221 and the input-output circuit B. The electrode pad 252 and the input-output circuit A 221 are also connected using the wiring 262 passing through the outer portion of the input-output circuit A 221 and the input-output circuit B 222. In the example of Fig. 13, the block connected to the electrode pad 251 and the block connected to the electrode pad 252 of the input-output circuit A 221 are arranged in the X direction. Therefore, it is particularly impossible to shorten the wiring length of the wiring 261, and a voltage drop and noise also occur in the wiring 261. When the input-output circuit A 221 and the input-output circuit B 222 are arranged side by side in the Y direction, the wiring lengths of the wirings 261 and 262 are shorter than the wiring length in the case of the example of Fig. 13. However, in this case, the wiring length between the input-output circuit B222 and the functional block B212 becomes longer. The present inventor, focusing on the problems described above, has come up with the following embodiments.

[0014] Embodiments to which means for solving the above problems are applied will be described in detail below with reference to the drawings. For clarity of explanation, the following description and the drawings are omitted and simplified as appropriate. In each drawing, the same elements are designated by the same reference numerals, and repeated descriptions thereof are omitted as necessary.

[0015] In the following embodiments, when necessary for convenience, description will be made by dividing it into a plurality of sections or embodiments, but unless specifically stated, these are not independent of each other, and one refers to the modified example, detail, additional description, or the like of part or all of the other. Furthermore, in the following embodiments, when reference is made to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), except in the case where it is specifically stated or in the case where it is obviously limited to the specific number in principle, the number is not limited to the specific number and may be larger or smaller than the specific number.

[0016] Furthermore, it is needless to say that in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are specifically specified and in the case where they are considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of components and the like, the shapes and the like are assumed to be substantially approximate or similar to the shapes and the like except in the case where they are specifically specified and in the case where they are considered to be obviously essential in principle. The same applies to the number and the like recited above (including number, numerical value, quantity, and range). First numbered example

[0017] Fig. 1 shows a portion of a semiconductor device according to a first numbered example of the present disclosure for a better understanding of the following embodiment. A semiconductor device 100 includes a functional block A 101, a functional block B 102, an input / output block A 111, an input / output block B 112, an electrode pad 121, and an electrode pad 122. The functional block A 101 and the functional block B 102 are circuit blocks for each performing a predetermined function. The functional block A 101 and the functional block B 102 each include circuit elements such as logic elements, active elements, and memory elements.

[0018] The input / output block A 111 includes an input / output circuit for the functional block A 101. The input / output block B 112 includes an input / output circuit for the functional block B 102. The electrode pads 121 and 122 are pads for a signal input and output, which are shared by the functional block A 101 and the functional block B 102, respectively. Both the input / output block A 111 and the input / output block B 112 include a block connected to the electrode pad 121 and a block connected to the electrode pad 122. The electrode pad 121 is connected to a block of the input / output block A 111 and a block of the input / output block B 112. Furthermore, the electrode pad 122 is connected to the other block of the input-output block A 111 and the other block of the input-output block B 112. The input-output block A 111 is connected to the functional block A 101.The input-output block B 112 is connected to the functional block B 102. The electrode pads 121 and 122 are connected to the input-output block A 111 and the input-output block B 112 on the input-output block, respectively.

[0019] Fig. 2 shows a circuit configuration of the semiconductor device 100. Signals input from the electrode pads 121 and 122 are distributed to the input / output block A 111 and the input / output block B 112, respectively. The signal input from the electrode pad 121 is input to the functional block A 101 via the input / output block A 111 and is input to the functional block B 102 via the input / output block B 112. The signal input from the electrode pad 122 is input to the functional block A 101 via the input / output block A 111 and is input to the functional block B 102 via the input / output block B 112.

[0020] A selector 115 selectively outputs a signal output from functional block A 101 and a signal output from functional block B 102 in response to a control signal. The selector 115 selects the signal output from functional block A 101 when the signals input from electrode pads 121 and 122 are used by functional block A 101. The selector 115 selects the signal output from functional block B 102 when the signals input from electrode pads 121 and 122 are used by functional block B 102.

[0021] The example described above is that the signals input from the electrode pads 121 and 122 are input to the function block A 101 and the function block B 102, and the selector 115 selects one of the outputs of the function block A 101 and the output of the function block B 102. However, the present example is not limited to this. For example, the selection of signals may be performed on the input sides of the function blocks, and a selector may be arranged between the electrode pads 121 and 122 and the function blocks A 101 and B 102. In this case, the selector selectively outputs the signal inputs from the electrode pads 121 and 122 to the function block A 101 or the function block B 102.

[0022] The electrode pads 121 and 122 are formed at positions overlapping with one of the input-output block A 111 and the input-output block B 112. As shown in Fig. 1, in the present example, the electrode pad 121 is arranged on the upper layer of the input-output block A 111. Further, the electrode pad 122 is arranged on the upper layer of the input-output block B 112. In other words, the electrode pad 121 is stacked and arranged on the input-output block A 111, and the electrode pad 122 is stacked and arranged on the input-output block B 112. The input-output block A 111 and the input-output block B 112 are arranged side by side in the Y direction. Further, the functional block A 101 and the functional block B 102 are arranged to sandwich the input-output block A 111 and the input-output block B 112 from the Y direction.In other words, the functional block A 101 and the functional block B 102 are arranged to oppose each other in the Y direction and sandwich the input-output block A 111 and the input-output block B 112.

[0023] Fig. 3 shows an AA cross section of Fig. 1. The electrode pad 122 is formed, for example, in an aluminum (AL) layer, which is the uppermost layer of the wiring layer. A wiring 151 is formed in the AL layer, drawing a signal input from the electrode pad 122 to a region where the input / output block A 111 is formed. The input / output block A 111 includes a gate 152 and a diffusion layer 155. The wiring 151 is connected to the gate 152 via a contact formed in the wiring layer. The output of the input / output block A 111 is connected to a wiring 161 formed in the AL layer via a contact formed in the wiring layer. The functional block A 101 includes a gate 171 and a diffusion layer 175. The wiring 161 is connected to the gate 171 via a contact.

[0024] The input / output block B 112 includes a gate 153 and a diffusion layer 156. The electrode pad 122 is connected to the gate 153 via a contact formed in the wiring layer in a region where the input / output block B 112 is formed. The output of the input / output block B 112 is connected to a wiring 162 formed in the AL layer via a contact formed in the wiring layer. The functional block B 102 includes a gate 172 and a diffusion layer 176. The wiring 162 is connected to the gate 172 via a contact.

[0025] The following is a layout example of the semiconductor chip with the Fig. 1 shown structure. Fig. 4 shows a layout example of a semiconductor chip that has the Fig. 1 shown part of the semiconductor device. In the example of Fig. 4, a semiconductor chip 150a comprises the functional block A 101, the functional block B 102, CPU0 - CPU3 (130 - 133), and RAMs 135 and 136. Further, the semiconductor chip 150a comprises a plurality of electrode pads 140 arranged at the peripheral part in the X-direction and the Y-direction, and an input-output block 141. In the semiconductor chip 150a, the electrode pads 140 are arranged on the upper layer of the input-output block 141, similar to the semiconductor chip 200 shown in Fig. 12. The electrode pads 121 and 122 for the functional block A 101 and the functional block B 102 are arranged inside the chip. In the example of Fig. 4, the functional block A 101, the functional block B 102, the input-output block A 111 and the input-output block B 112 are arranged in an area on the semiconductor chip 150a which is located in the middle part in the X direction and the end part in the Y direction.

[0026] Fig. Figure 5 shows another layout example of a semiconductor chip that contains the part of the Fig. 1. In a semiconductor chip 150b, which is shown in Fig. As shown in Figure 5, functional block A 101, functional block B 102, input / output block A 111, and input / output block B 112 are arranged in the corner portion of the semiconductor chip. The arrangement of CPU0 - CPU3 (130 - 133) and RAMs 135 and 136 in semiconductor chip 150b may be similar to their arrangement in semiconductor chip 150a.

[0027] In comparison to the Fig. 4 shown semiconductor chips 150a with the in Fig. Compared with the semiconductor chip 150b shown in FIG. 5, the semiconductor chip 150a is capable of increasing the number of electrodes 140 and input / output blocks 141 arranged at the peripheral part of the chip compared to the semiconductor chip 150b. Therefore, when a large number of electrode pads 140 are to be arranged, as in the semiconductor chip 150a, the functional block A 101, the functional block B 102, the input / output block A 111, and the input / output block B 112 can be arranged at the end part of the central part of the chip.

[0028] However, in the semiconductor chip 150a, the functional block A 101, the input-output block A 111, and the input-output block B 112 are arranged between the CPU 1 (131) and the RAM 136. Therefore, when forming wiring (digital signal wiring) connecting the CPU 1 (131) and the RAM 136, it is difficult to form the wiring linearly. In many cases, the digital signal wiring must bypass the functional block A 101, the input-output block A 111, and the input-output block B 112. Therefore, wiring congestion occurs in the semiconductor chip 150a, and the degree of freedom of the layout decreases. In contrast, in the semiconductor chip 150b, there is no influence of the detour of the digital signal wiring and a high degree of freedom of the layout in the semiconductor chip 150b.Therefore, when the degree of freedom of the layout is prioritized, as in the semiconductor chip 150b, the functional block A 101, the functional block B 102, the input-output block A 111 and the input-output block B 112 can be arranged in the corner region of the chip.

[0029] As in the Fig. 4 and Fig. As shown in Figure 5, in semiconductor chips 150a and 150b, electrode pads 121 and 122 are formed within the chip. When semiconductor chip 150a or 150b is connected to a package substrate by wires, the lengths of the wires connected to electrode pads 121 and 122 are longer than the length of the wire connected to the electrode pad located at the peripheral portion. In this case, for example, the risk of wire flow during molding increases, and a short circuit between wires may occur.

[0030] Fig. 6 shows another layout example of a semiconductor chip including the semiconductor device 100. A Fig. The semiconductor chip 150c shown in Figure 6 is a semiconductor chip that is flip-chip connected to a package substrate. The semiconductor chip 150c includes a plurality of electrode pads 140 evenly arranged over the entire surface of the chip. When a semiconductor chip has flip-chip packaging, there is no risk of wire flow even if the electrode pads 121 and 122 are arranged inside the chip. Therefore, the structure of the present embodiment is compatible with flip-chip packaging.

[0031] Furthermore, in the case of flip-chip packaging, if the pads are not evenly arranged, the resin filling the semiconductor chip and the package frame cannot be injected evenly, and the chip and the package cannot be brought into close contact. Therefore, as shown in Fig. As shown in Figure 6, the electrode pad may be arranged at a position where the electrode pad overlaps the functional block A 101 or the functional block B 102. The electrode pads 145-147 arranged at the positions overlapping the functional block A 101 or the functional block B 102 may be dummy electrode pads that are not connected anywhere.

[0032] Fig. 7 shows a method for designing the semiconductor device 100. In a functional block arrangement process, the functional blocks are arranged to conform to the layout of the semiconductor chip (step S1). Then, each input-output block is arranged to be sandwiched between the plurality of functional blocks that share the same electrode pads, and the positions of the input-output blocks are adjusted so that the input-output blocks are aligned in one direction, for example, the Y direction (step S2). Subsequently, the electrode pads shared by the plurality of functional blocks are arranged on one of the input-output blocks (step S3). The electrode pads and the input-output blocks are connected by the shortest path (step S4), and the functional blocks and the input-output blocks are connected by the shortest path (step S5).

[0033] It should be noted that the Fig. 7 shown design process can be carried out by a computer. Fig. Figure 8 shows an example configuration of a computer. A computer 500 includes one or more processors 501 and one or more memories 502. The memory 502 stores a program. The program includes instructions (or software code) that cause the computer 500 to perform each step of the design method described in Fig. 7. In the computer 500, the processor 501 executes each step of the Fig. 7 by reading the program from the memory 502 and executing the processing according to the read program.

[0034] The above program may be stored on a non-transitory computer-readable medium or a tangible storage medium. By way of example, but not limitation, a computer-readable medium or a tangible storage medium includes RAM, ROM, flash memory, solid-state drive (SSD), other storage technologies, compact disc (CD)-ROM, DVD (Digital Versatile Disc), Blu-ray (registered trademark) disc, other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage, and other magnetic storage devices. The program may be transmitted on a non-transitory computer-readable medium or a communications medium. By way of example, and not limitation, a non-transitory computer-readable medium or a communications medium may include electrical, optical, acoustic, or other forms of propagating signals. Effect

[0035] In the present example, functional block A 101 and functional block B 102 are arranged to oppose each other and sandwich input / output block A 111 and input / output block B 112. In the present example, the electrode pads 121 and 122 shared by the two functional blocks may be connected to input / output block A 111 and input / output block B 112 by short-distance wiring. Further, input / output block A 111 and input / output block B 112 may be connected to functional block A 101 and functional block B 102 by short-distance wiring. Therefore, it is possible to optimize the resistance and capacitance of the wirings from the electrode pads 121 and 122 to the functional block A 101 and the functional block B 102, and thus it is possible to reduce a voltage drop and noise in the signal path.Furthermore, in the present example, the electrode pads 121 and 122 are stacked on one of the input-output blocks. Therefore, in the present example, it is possible to suppress an increase in the wiring area of ​​the semiconductor chip. Embodiment of the invention (hereinafter also referred to as “second embodiment”)

[0036] Fig. Figure 9 shows a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device 100a according to the present embodiment includes a functional block C103 and an input / output block C113 in addition to the configuration of the semiconductor device 100 shown in the Fig. 1. Input-output block C 113 includes an input-output circuit for functional block C 103. In the present embodiment, electrode pads 121 and 122 are shared by functional block A 101, functional block B 102, and functional block C 103. Other configurations may be the same as the configuration of semiconductor device 100 described in the first numbered example.

[0037] The input / output block A 111, the input / output block B 112, and the input / output block C 113 are arranged in a row along the Y direction. The input / output block C 113 is arranged, for example, between the input / output block A 111 and the input / output block B 112. The electrode pad 121 is formed on one of the three input / output blocks, for example, the input / output block A 111. The electrode pad 122 is formed on one of the three input / output blocks, for example, the input / output block B 112. The functional block A 101 and the functional block B 102 are arranged to face each other and sandwich the input / output block in the Y direction. The function block C103 is arranged side by side in the X direction with respect to the input-output block C113.

[0038] Electrode pad 121 is provided in a region where input / output block B 112 and input / output block C 113 are formed, for example, using wiring of the uppermost layer of the wiring layer. Electrode pad 122 is provided in a region where input / output block A 111 and input / output block C 113 are formed, for example, using wiring of the uppermost layer of the wiring layer. Electrode pads 121 and 122 are connected to a gate in each input / output block via a contact provided in the wiring layer.

[0039] In the present embodiment, wiring to functional block C 103 is slightly longer than the wiring to functional block A 101 and functional block B 102. However, the length of the wiring to each functional block can be shortened compared to the case where three functional blocks and three input-output blocks are arranged side by side in the X direction. Thus, in the present embodiment, even if the number of functional blocks is increased to more than 2, similar to the first numbered example, it is possible to optimize the resistance and capacitance of the wiring, and it is possible to reduce such voltage drop and noise in the signal path.

[0040] The number of functional blocks connected to the electrode pads 121 and 122 is not particularly limited to the number described above. For example, a semiconductor device may include four functional blocks. In this case, the input-output block for the fourth functional block (functional block D) may be arranged between the input-output block A 111 and the input-output block B 112. The functional block D may be arranged on the opposite side in the X direction, for example, with the input-output block of the functional block C 103 sandwiched therebetween. Third numbered example

[0041] Fig. 10 shows a semiconductor device according to a third example of the present disclosure for better understanding. A semiconductor device 100b according to the present example includes test electrode pads (test pads) 125 and 126 in addition to the configuration of the semiconductor device 100 shown in the Fig. 1. Test pads 125 and 126 are electrically connected to electrode pads 121 and 122, respectively. Test pad 125 is formed on input / output block B 112, and test pad 126 is formed on input / output block A 111. Other configurations may be the same as the configuration of semiconductor device 100 described in the first numbered example.

[0042] Generally, during semiconductor chip testing, a probe needle can damage the electrode pads. For example, if electrode pads 121 and 122 are damaged, adhesion failure is likely to occur during bonding of the bond wires. To prevent this, test pads 125 and 126 are used during testing in the present example. Test pads 125 and 126 are damaged by the probe needle. However, since electrode pads 121 and 122 are not damaged, it is possible to avoid such adhesion failure of the bond wire.

[0043] In the following, it is assumed that electrode pad 121 and test pad 125 are an electrode pad for a signal input, and that electrode pad 122 and test pad 126 are an electrode pad for a signal output. In input-output block A 111, electrode pad 121 and test pad 125 are connected to the input buffer, and electrode pad 122 and test pad 126 are connected to the output buffer. In input-output block B 112, electrode pad 121 and test pad 125 are connected to the input buffer, and electrode pad 122 and test pad 126 are connected to the output buffer.

[0044] Fig. Figure 11 schematically shows a test for the semiconductor device 100b. In the case of an alternating current (AC) scan test, the test needles 401 and 402 are contacted with the test pad 125 for the input circuit and the test pad 126 for the output circuit, respectively, to perform the test. Fig.11, it is assumed that the functional block to be tested is functional block A101. A sample pattern (test signal) is input from test probe 401 to test pad 125. The sample pattern is input to functional block A101 via input-output block A111. The logic circuit of functional block A101 operates at the frequency of the product and outputs the operation result. The operation result (output signal) of functional block A101 is output from test pad 126 via input-output block A111. A tester 400 acquires the operation result (signal pattern) via probe 402. Tester 400 determines whether functional block A101 is operating normally or not by determining whether the signal pattern (signal value) obtained from test pad 126 and the expected value match or not.

[0045] If the resistance and capacitance of the wiring in the signal path from test pad 125 to function block A 101 are large, a delay occurs in the input sampling pattern. As a result, the expected value cannot be stored in the flip-flops in function block A 101, which operate at the product's frequency. In this case, the result ultimately detected by the tester deviates from the expected value, and the result degrades.

[0046] Furthermore, if the resistance and capacitance of the wiring in the signal path from functional block A 101 to test pad 126 are large, a delay occurs in the signal output from test pad 126. In this case, the result finally detected by the tester deviates from the expected value, and the result deteriorates. Furthermore, although the sampling period can be adjusted in the tester, adjusting the sampling time is not easy because the manufacturing variation is different for each semiconductor chip.

[0047] In the present example, regarding the test pads 125 and 126, similar to the electrode pads 121 and 122, the test pads 125 and 126 can be connected to the input / output block A 111 and the input / output block B 112 by short-distance wiring. Furthermore, the input / output block A 111 and the input / output block B 112 can be connected to the functional block A 101 and the functional block B 102 by short-distance wiring. Therefore, it is possible to optimize the resistance and capacitance of the wiring from the test pads 125 and 126 to the functional block A 101 and the functional block B 102, and it is possible to reduce the voltage drop and noise in the signal path for testing. As a result, it is possible to reduce the probability that the semiconductor device is determined to be defective in the test, and it is possible to suppress the deterioration of the result.

Claims

[1] Semiconductor device comprising: a variety of electrode pads; a first input-output block (111) coupled to the plurality of electrode pads (121, 122); a second input-output block (112) coupled to the plurality of electrode pads; a third input-output block (113) coupled to the plurality of electrode pads (121, 122); a first functional block (101) coupled to each of the plurality of electrode pads via the first input-output block (111); a second functional block (102) coupled to each of the plurality of electrode pads via the second input-output block (112); and a third functional block (103) coupled to each of the plurality of electrode pads via the third input-output block (113), wherein the first and second functional blocks (101, 102) are arranged at positions opposite to each other to sandwich the first, second and third input-output blocks (111, 112, 113). [2] The semiconductor device according to claim 1, wherein each of the plurality of electrode pads is formed at a position overlapping with one of the first and second input-output blocks (111, 112). [3] The semiconductor device according to claim 1, wherein the first functional block (101), the second functional block (102), the first input-output block (111) and the second input-output block (112) are arranged in an area on a semiconductor chip which is located in a central part in a first direction and an end part in a second direction orthogonal to the first direction. [4] The semiconductor device according to claim 1 or 2, wherein the first functional block (101), the second functional block (102), the first input-output block (111) and the second input-output block (112) are arranged in a corner part of a semiconductor chip. [5] The semiconductor device according to claim 1, wherein the plurality of electrode pads comprises a first electrode pad and a second electrode pad, wherein the first electrode pad is formed at a position overlapping with one of the first and second input-output blocks (111, 112), and wherein the second electrode pad is formed at a position overlapping with the other of the first and second input-output blocks (111, 112). [6] The semiconductor device according to claim 1, wherein the plurality of electrode pads is a part of a plurality of electrode pads formed on an entire surface of a semiconductor chip. [7] The semiconductor device according to claim 6, wherein the plurality of electrode pads formed on the entire surface of the semiconductor chip comprises dummy electrode pads that are not coupled to the first and second input-output blocks (111, 112), and wherein the dummy electrode pads are formed at positions overlapping with the first functional block (101) or the second functional block (102). [8] The semiconductor device according to claim 1, further comprising a plurality of test electrode pads used during testing, and wherein each of the plurality of test electrode pads is coupled to the plurality of electrode pads. [9] The semiconductor device according to claim 8, wherein the plurality of electrode pads comprises an electrode pad for a signal input and an electrode pad for a signal output, and wherein the plurality of test electrode pads comprises a test electrode pad coupled to the signal input electrode pad and a test electrode pad coupled to the signal output electrode pad. [10] A method for testing the semiconductor device according to claim 9, comprising: Contacting a first test needle with the test electrode pad coupled to the signal input electrode pad; Inputting a test signal from the first needle into the first or second functional block (101, 102) via the first and second input-output blocks (111, 112); Contacting a second test needle with the test electrode pad coupled to the signal output electrode pad; Receiving, from the second needle, an output signal output from the first or second functional block (101, 102) via the first and second input-output blocks (111, 112); and Comparing the output signal with an expected value of the test signal to determine whether the first or second functional block (101, 102) is operating normally.

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