Embedded housing with electrically insulating dielectric lining and method for forming a semiconductor housing

Abstract

A semiconductor package (100) comprising: a package substrate comprising an inner laminate layer (102), a first metallization layer (108) disposed beneath the inner laminate layer (102), and a second metallization layer (110) disposed above the inner laminate layer (102); a first semiconductor die (122) having a first load terminal (126) arranged on a first surface (124) of the first semiconductor die (122) and a second load terminal (130) arranged on a second surface of the first semiconductor die (122) opposite the first surface (124) of the first semiconductor die (122); and a liner of dielectric material (158) on the first semiconductor die (122); wherein the first semiconductor die (122) is embedded in the inner laminate layer (102) such that the first surface (124) of the first semiconductor die (122) faces the second metallization layer (110), and wherein the lining of dielectric material (158) is arranged at a corner of the first semiconductor die (122) which lies between the first load terminal and the second load terminal (126, 130) of the first semiconductor die (122); wherein the lining of dielectric material (158) has a portion extending from the corner only along a portion of the first edge side (160) of the first semiconductor die (122) extending between the first surface (124) and the second surface (132) of the first semiconductor die (122); and wherein the dielectric material (158) comprises an epoxy or an epoxy mixture.

Description

[0001] Power stage circuits such as half-bridge and full-bridge circuits are used in many applications, such as automotive and industrial applications. These power stage circuits may include power devices rated for controlling large voltages and / or currents, e.g., MOSFETs (metal-oxide-semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), diodes, etc., and driver devices configured to control the power devices. Generally speaking, it is desirable to provide a power stage circuit with high performance, e.g., low power dissipation, high current density, and high efficiency, while maintaining a small physical footprint and having robust electrical connections.Conventional semiconductor packaging solutions, such as lead-frame and metal-clip-based semiconductor packages, have reached physical limits in terms of parameters such as power dissipation, current density, and efficiency. In particular, the solder joints of these semiconductor packages impose practical limitations that are not easily overcome.

[0002] US 2016 / 0 071 819 A1 discloses a method for manufacturing a semiconductor device, comprising: providing a semiconductor wafer, the wafer including an upper layer of a semiconductor material, an inner etch stop layer, and a lower layer; forming a plurality of functional regions in the upper layer; performing a selective first etching process on the upper layer to separate the plurality of functional regions from each other by trenches etched through the upper layer, wherein the first etching process is substantially stopped by the inner etch stop layer; and removing the lower layer by a second etching process, wherein the second etching process is substantially stopped by the inner etch stop layer.

[0003] US 2020 / 0 219 846 A1 discloses a multi-chip package power module comprising: a plurality of chips, including a first chip and a second chip, arranged side by side; a first conductive element arranged at least partially between the first chip and the second chip; and a second conductive element arranged at least partially between the first chip and the second chip, wherein the first conductive element is electrically connected to a power supply pin of the first chip, the second conductive element is electrically connected to a power supply pin of the second chip, and the plurality of chips, the first conductive element, and the second conductive element are all embedded in an insulating package material.

[0004] DE 10 2015 113 208 A1 discloses an integrated power module comprising an embedded power semiconductor module with one or more power semiconductor chips embedded in a dielectric material, a multilayer logic circuit board with one or more logic chips attached to a surface of the logic circuit board, and an elastic connection integrally formed between the embedded power semiconductor module and the logic circuit board.

[0005] DE 10 2021 101 747 A1 discloses semiconductor packages containing a thermal capacitor designed to absorb transient heat pulses from a power semiconductor chip and subsequently dissipate the transient heat pulses to an environment.

[0006] US 2021 / 0 066 495 A1 discloses a power semiconductor device comprising a semiconductor body with a front surface and a first passivation layer disposed over the front surface. The first passivation layer is a polycrystalline diamond layer.

[0007] A semiconductor package according to claim 1 and a method of forming a semiconductor package according to claim 17 are provided. Further embodiments are described in the subclaims.

[0008] A semiconductor device is disclosed. According to one embodiment, the semiconductor device comprises: a package substrate having an inner laminate layer, a first metallization layer disposed below the inner laminate layer, and a second metallization layer disposed above the inner laminate layer; a first semiconductor die having a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die opposite the first surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die, wherein the first semiconductor die is embedded in the inner laminate layer such that the first surface of the first semiconductor die faces the second metallization layer.and wherein the lining of dielectric material is arranged at a corner of the first semiconductor die which lies between the first load terminal and the second load terminal of the first semiconductor die.,

[0009] Individually or in combination, the corner of the first semiconductor die is located between the first surface of the first semiconductor die and a first edge side of the first semiconductor die extending between the first surface and the second surface of the first semiconductor die, and wherein the liner of dielectric material has a first portion disposed on the first surface of the first semiconductor die and extending from the first load terminal to the corner.

[0010] Individually or in combination, the first part of the lining of dielectric material extends from the corner along only a portion of the first edge side of the first semiconductor die.

[0011] Individually or in combination, the lining of dielectric material has a second part which is arranged on the first edge side and extends from the corner along only a portion of the first edge side.

[0012] Individually or in combination, the liner of dielectric material comprises a second portion disposed at a second corner of the first semiconductor die located between the first surface of the first semiconductor die and a second edge side of the first semiconductor die extending between the first surface and the second surface of the first semiconductor die and opposite the first surface of the first semiconductor die.

[0013] Alone or in combination, the second liner of dielectric material extends along only a portion of the second edge side of the first semiconductor die, and wherein the second liner of dielectric material is an epoxy layer.

[0014] Alone or in combination, the semiconductor package further comprises a second semiconductor die having a first load terminal arranged on a first surface of the second semiconductor die and a second load terminal arranged on a second surface of the second semiconductor die opposite the first surface of the second semiconductor die, and a liner made of dielectric material on the second semiconductor die, wherein the second semiconductor die is embedded in the inner laminate layer such that the first surface of the second semiconductor die faces the first metallization layer, and wherein the liner made of dielectric material is arranged at a corner of the second semiconductor die that lies between the first load terminal and the second load terminal of the second semiconductor die.

[0015] Individually or in combination, the semiconductor package is configured as an integrated half-bridge circuit, wherein the first semiconductor die and the second semiconductor die are each configured as discrete power transistor dies, wherein the first semiconductor die is a high-side switch of the integrated half-bridge circuit, and wherein the second semiconductor die is a low-side switch of the integrated half-bridge circuit.

[0016] Individually or in combination, the semiconductor package further comprises a third semiconductor die embedded in the inner laminate layer, wherein the third semiconductor die is a logic die having I / O terminals arranged on a first surface of the third semiconductor die facing the second metallization layer, wherein the third semiconductor die is configured to control a switching operation of the first semiconductor die and the second semiconductor die by means of the I / O terminals, and wherein the third semiconductor die is laterally electrically insulated from the first semiconductor die by the liner made of dielectric material arranged at a first edge region of the first semiconductor die.

[0017] Individually or in combination, the first load terminal of the first semiconductor die is a source terminal of the high-side switch, wherein the second load terminal of the second semiconductor die is a drain terminal of the low-side switch, and wherein the first load terminal of the first semiconductor die is electrically connected to the second load terminal of the second semiconductor die through the second metallization layer.

[0018] Individually or in combination, the second semiconductor die further comprises a control terminal arranged on the first surface of the first semiconductor die.

[0019] Individually or in combination, the second semiconductor die further comprises a control terminal arranged on the second surface of the first semiconductor die.

[0020] Alone or in combination, the semiconductor package further comprises a central dielectric structure disposed between the first semiconductor die and the second semiconductor die, wherein a first portion of the inner laminate layer is disposed between the second liner of dielectric material disposed at the second edge region of the first semiconductor die and the central dielectric structure, and wherein a second portion of the inner laminate layer is disposed between the liner of dielectric material disposed at the first edge region of the second semiconductor die and the central dielectric structure.

[0021] Individually or in combination, the dielectric material of the central portion differs from the material of the inner laminate layer.

[0022] Individually or in combination, the dielectric material of the central portion differs from the dielectric material of the dielectric material liners on the first semiconductor die and the second semiconductor die.

[0023] Individually or in combination, the semiconductor package further comprises a first structured contact pad comprising a structured portion of the first metallization layer and arranged on the second load terminal of the first semiconductor die, wherein a thickness of the first structured contact pad is at least 50% of a vertical height of the first semiconductor die.

[0024] A method for forming a semiconductor package is disclosed. According to one embodiment, the method comprises: fabricating a package substrate having an inner laminate layer, a first metallization layer disposed below the inner laminate layer, and a second metallization layer disposed above the inner laminate layer; providing a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die opposite the first surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die;Embedding the first semiconductor die in the inner laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is arranged at a corner of the first semiconductor die that lies between the first load terminal and the second load terminal of the first semiconductor die;

[0025] Individually or in combination, the first semiconductor die is provided with the lining of dielectric material, which is arranged at the corner of the first semiconductor die, before embedding the first semiconductor die.

[0026] Individually or in combination, the corner of the first semiconductor die is located between the first surface of the first semiconductor die and a first edge side of the first semiconductor die extending between the first surface and the second surface of the first semiconductor die, and wherein the liner of dielectric material has a first portion disposed on the first surface of the first semiconductor die and extending from the first load terminal to the corner.

[0027] Individually or in combination, the lining of dielectric material has a second part which is arranged on the first edge side and extends from the corner along only a portion of the first edge side.

[0028] Individually or in combination, embedding the first semiconductor die into the inner laminate layer comprises: providing a core structure having a plurality of openings; disposing the first semiconductor die, which has the liner of dielectric material disposed at the corner of the first semiconductor die, within one of the openings; and filling gaps in the openings between the first semiconductor die and the core structure with dielectric material.

[0029] Individually or in combination, the method further comprises: providing a second semiconductor die having a first load terminal disposed on a first surface of the second semiconductor die and a second load terminal disposed on a second surface of the second semiconductor die opposite the first surface of the second semiconductor die; providing a liner of dielectric material on the second semiconductor die;and embedding the second semiconductor die in the inner laminate layer such that the first surface of the second semiconductor die faces the first metallization layer, wherein the lining of dielectric material is arranged at a corner of the second semiconductor die which lies between the first load terminal and the second load terminal of the second semiconductor die, and wherein the second semiconductor die is provided with the lining of dielectric material which is arranged at the corner of the second semiconductor die prior to embedding the second semiconductor die;

[0030] Individually or in combination, the semiconductor package is configured as an integrated half-bridge circuit, wherein the first semiconductor die and the second semiconductor die are each configured as discrete power transistor dies, wherein the first semiconductor die is a high-side switch of the integrated half-bridge circuit and wherein the second semiconductor die is a low-side switch of the integrated half-bridge circuit.

[0031] Individually or in combination, the first load terminal of the first semiconductor die is a source terminal of the high-side switch, wherein the second load terminal of the second semiconductor die is a drain terminal of the low-side switch, and wherein the first load terminal of the first semiconductor die is electrically connected to the second load terminal of the second semiconductor die through the second metallization layer.

[0032] The elements of the drawings are not necessarily to scale. Like reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive. Embodiments are illustrated in the drawings and described in detail in the following description. Fig. 1 shows a semiconductor package according to one embodiment. Fig. 2 shows a semiconductor package according to another embodiment. Fig. 3 shows a semiconductor package according to another embodiment. Fig. 4, which the Fig. 4A-4F illustrates selected steps in a method of forming a semiconductor package, according to one embodiment. Fig. 5, which the Fig. 5A-5F illustrates selected steps in a method of forming a semiconductor package, according to one embodiment.

[0033] Embodiments of an embedded semiconductor package comprising one or more semiconductor dies embedded in a laminate layer and having advantageous voltage breakdown characteristics are disclosed herein. The semiconductor package comprises a laminate layer that protects and electrically insulates the semiconductor die(s) and comprises contact pads that form externally accessible electrical contact points with the terminals of the semiconductor die(s). At least one of the semiconductor dies may be a power device rated for sensing voltages on the order of 600V, 1200V, or more. The power device may comprise a liner of dielectric material, such as an epoxy material, on an edge surface of the semiconductor die.In particular, the lining of dielectric material may be provided at a corner of the semiconductor die and partially along an edge side of the semiconductor die located between the device's load terminals. This strengthens the semiconductor package against high-voltage breakdown by mitigating breakdown mechanisms, including electromigration. The semiconductor package may further include dielectric structures between a plurality of the semiconductor dies, which improve the lateral electrical isolation between high-voltage devices.

[0034] Referring to Fig. 1, a semiconductor package 100 includes an inner laminate layer 102, a second laminate layer 104 disposed above the inner laminate layer 102, and a third laminate layer 106 disposed below the inner laminate layer 102. The inner laminate layer 102 and the first and second laminate layers 104, 106 may comprise a dielectric material suitable for semiconductor device encapsulation. Examples of these dielectric materials include epoxy materials, mixed epoxy and glass fiber materials such as FR-4, FR-5, CEM-4, etc., and resin materials such as bismaleimidetrazine (BT) resin. The inner laminate layer 102, the second laminate layer 104, and the third laminate layer 106 may each have the same material composition.Alternatively, at least one of the inner laminate layer 102, the second laminate layer 104, and the third laminate layer 106 may have a different material composition than the other layers.

[0035] The semiconductor package 100 includes a first metallization layer 108 disposed beneath the inner laminate layer 102, a second metallization layer 110 disposed above the inner laminate layer 102, a third metallization layer 112 disposed above the second laminate layer 104, and a fourth metallization layer 114 disposed beneath the third laminate layer 104. The first metallization layer, the second metallization layer, the third metallization layer, and the fourth metallization layer 108, 110, 112, and 114 may each comprise electrically conductive metals such as copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), etc., and alloys or combinations thereof.The first metallization layer, the second metallization layer, the third metallization layer, and the fourth metallization layer 108, 110, 112, and 114 may each have the same material composition, or at least one of these layers may have a different material composition than other layers. A surface plating 116, such as an ENEPIG (electroless nickel electroless palladium immersion gold) layer, may be provided on the outer surfaces of the third metallization layers and the fourth metallization layer 112, 114 to improve adhesion and / or provide corrosion protection. The semiconductor package 100 may further include a solder resist 118, such as a polymer material, disposed between patterned regions of the fourth metallization layer 114.

[0036] The semiconductor package 100 further comprises vias 120 extending through the laminate layer. These vias 120 are configured to provide a vertical electrical connection between the metallization layers and the embedded components of the semiconductor package 100 and / or between two vertically separated metallization layers. These vias 120 may comprise so-called blind vias, which form electrical connections to the outermost metallization layers, i.e., in this embodiment, the third metallization layer and the fourth metallization layer 112, 114. These vias 120 may additionally comprise so-called buried vias, which form electrical connections within the substrate. The vias 120 may comprise electrically conductive metals such as copper, aluminum, tungsten, nickel, etc.and alloys or combinations thereof.

[0037] The semiconductor package 100 includes a first semiconductor die 122. The first semiconductor die 122 is embedded in the inner laminate layer 102 such that a first surface 124 of the first semiconductor die 122 faces the second metallization layer 110. In this context, the term "embedded" means that the first semiconductor die 122 is surrounded on all sides by the inner laminate layer 102 and is contained within a vertical space defined by the planes of the top surface and the bottom surface of the inner laminate layer 102. The first semiconductor die 122 includes a first load terminal 126 and a control terminal 128 disposed on the first surface 124 of the first semiconductor die 122, and a second load terminal 130 disposed on a second surface 132 of the first semiconductor die 122 opposite the first surface 124 of the first semiconductor die 122.

[0038] The semiconductor package 100 includes a second semiconductor die 134. The second semiconductor die 134 is embedded in the inner laminate layer 102 such that a second surface 132 of the second semiconductor die 134 faces the second metallization layer 110. In this context, the term "embedded" means that the second semiconductor die 134 is surrounded on all sides by the inner laminate layer 102 and is contained within a vertical space defined by the planes of the top surfaces and the bottom surface of the inner laminate layer 102. The second semiconductor die 134 includes a first load terminal 126 and a control terminal 128 disposed on the first surface 124 of the second semiconductor die 134, and a second load terminal 130 disposed on a second surface 132 of the second semiconductor die 134 opposite the first surface 124 of the second semiconductor die 134.

[0039] Generally speaking, the first semiconductor die and the second semiconductor die 122, 134 may be any type of device configured to block a voltage, e.g., a diode, a transistor, a thyristor, etc. The first load terminal and the second load terminal 126, 130 may be the voltage-blocking terminals of the device, i.e., the terminals that receive operating voltages in an OFF or blocking state of the device. For example, the first load terminal and the second load terminal 126, 130 may be the source and drain terminals in the case of a MOSFET, the collector and emitter terminals in the case of an IGBT, or the anode and cathode terminals in the case of a diode (in this case, the control terminal 128 may be omitted from the die). The first semiconductor die and the second semiconductor die 122, 134 may comprise IV semiconductor materials, e.g., silicon, silicon germanium, silicon carbide, etc., and / or III-V type semiconductor materials, e.g.,Gallium nitride, gallium arsenide, etc.

[0040] According to one embodiment, the first semiconductor die and the second semiconductor die 122, 134 are configured as discrete power transistors. A discrete power transistor is a switching device rated for accommodating voltages of at least 100 V (volts), and more typically on the order of 600 V, 1200 V, or more, and / or rated for accommodating currents of at least 1 A (amperes), and more typically on the order of 10 A, 50 A, 100 A, or more. Examples of discrete power transistors include, for example, MOSFETs (metal oxide semiconductor field-effect transistors), IGBTs (insulated gate bipolar transistors), and HEMTs (high electron mobility transistors). The first semiconductor die and the second semiconductor die 122, 134 may internally comprise a plurality of transistors or transistor cells connected in parallel with one another.

[0041] According to one embodiment, the semiconductor package 100 is configured as an integrated half-bridge circuit. A half-bridge circuit refers to a type of circuit topology used in a power conversion circuit, such as a DC-to-DC converter, a DC-to-AC converter, etc. A half-bridge circuit includes a high-side switch connected in series with a low-side switch. A load terminal of the high-side switch (e.g., the drain) is connected to a first DC voltage (e.g., a positive potential), a load terminal of the low-side switch (e.g., the source) is connected to a second DC voltage (e.g., a negative potential or ground), and the remaining two load terminals (e.g., the source of the high-side switch and the drain of the low-side switch) are connected to each other to form the output of the half-bridge circuit.The control terminals of the high-side and low-side switches (e.g., the gate terminals) can be switched according to a power control scheme (e.g., pulse width modulation) to generate a desired voltage and frequency at the output of the half-bridge circuit.

[0042] In an embodiment in which the semiconductor package 100 is configured as an integrated half-bridge circuit, the first semiconductor die 122 may be a high-side switch of the half-bridge circuit, and the second semiconductor die 134 may be a low-side switch of the half-bridge circuit. In this case, the first semiconductor die and the second semiconductor die 122, 134 may each be identically configured discrete power transistors, with the second semiconductor die 134 flipped upside down compared to the first semiconductor die 122.In one particular example, the first semiconductor die and the second semiconductor die 122, 134 are each vertical MOSFET devices, where the first load terminal 126 of the first semiconductor die 122 is a source terminal of the high-side switch, the second load terminal 130 of the second semiconductor die 134 is a drain terminal of the low-side switch, the second load terminal 130 of the first semiconductor die 122 is a drain terminal of the high-side switch, and the first load terminal 126 of the second semiconductor die 134 is a source terminal of the low-side switch. A similar half-bridge circuit topology can be achieved by the first semiconductor die and the second semiconductor die 122, 134 being each vertical IGBT devices, except that the source and drain terminals become the collector and emitter terminals, respectively.

[0043] The semiconductor package 100 may have the following electrical connection. A first contact pad 136 formed in the fourth metallization layer 114 may be electrically connected to the first load terminal 126 of the first semiconductor die 122 and to the second load terminal 130 of the second semiconductor die 134. A second contact pad 138 formed in the fourth metallization layer 114 may be electrically connected directly to the first load terminal 124 of the second semiconductor die 134. A third contact pad 140 formed in the fourth metallization layer 114 may be electrically connected directly to the second load terminal 130 of the first semiconductor die 122.The semiconductor package 100 may further include an upper contact pad 142 formed in the third metallization layer 112, which forms an additional electrical contact point with the first load terminal 126 of the first semiconductor die 122 and with the second load terminal 130 of the second semiconductor die 134. In any case, the electrical connections between the various terminals of the semiconductor dies and the contact pads formed in the fourth metallization layer 114 may be achieved through the vias 120 and patterned portions of the first metallization layer, the second metallization layer, the third metallization layer, and the fourth metallization layer 108, 110, 112, 114.As shown, the semiconductor package 100 includes a patterned portion 144 of the second metallization layer 110 disposed over the first semiconductor die and the second semiconductor die 122, 134 and in direct electrical contact with the first load terminal 126 of the first semiconductor die 122 and the second load terminal 130 of the second semiconductor die 134. In this context, direct electrical contact refers to direct physical contact or an arrangement in which an intervening conductive element such as solder, sinter, conductive adhesive, etc., or a seed layer is disposed between the two structures. Similarly, a first patterned contact pad 146 is in direct electrical contact with the second load terminal 130 of the first semiconductor die 122, and a second patterned contact pad 148 is in direct electrical contact with the first load terminal 124 of the second semiconductor die 134.The first patterned contact pad and the second patterned contact pad 146, 148 may be composite structures comprising patterned portions of the first metallization layer 108 and an intermediate metallization formed between the first metallization layer and the fourth metallization layer 108, 114.

[0044] According to one embodiment, a thickness T1 of the first structured contact pad 146 is at least 50% of a vertical height of the first semiconductor die 122, wherein the vertical height of the first semiconductor die 122 is a shortest distance between the first surface and the second surfaces 124, 132 of the first semiconductor die 122. Likewise, a thickness T2 of the second structured contact pad 148 can be at least 50% of a vertical height of the second semiconductor die 134, wherein the vertical height of the second semiconductor die 134 is a shortest distance between the first surface and the second surface 124, 132 of the second semiconductor die 134. By making these structured contact pads very thick in this way, improved thermal conduction and / or electrical conduction can be achieved.

[0045] The semiconductor package 100 may further include a fourth contact pad 150 formed in the fourth metallization layer 114. The fourth contact pad 150 may be an I / O pad used to control the switching of the first semiconductor die and the second semiconductor die 122, 134. According to the illustrated embodiment, the semiconductor package 100 further includes a third semiconductor die 152 embedded in the inner laminate layer 102. The third semiconductor die 152 may be a logic or driver device, e.g., a silicon-based device, with I / O (input / output) terminals 154 arranged on a main surface of the third semiconductor die 152 facing the second metallization layer 110. One or more of the I / O terminals 154 may be electrically connected to the fourth contact pad 150 via the vias 120 and patterned metallization regions in a manner similar to that previously described.One or more of the I / O terminals 154 may be electrically connected to the control terminals 128 of the first semiconductor die and the second semiconductor die 122, 134 through a patterned portion of the second metallization layer 110. An imide layer 156 may be provided on the main surface of the third semiconductor die 152 to electrically isolate the I / O terminals 154 from each other. In one embodiment in which the semiconductor package 100 is configured as an integrated half-bridge circuit, the third semiconductor die 152 may be a driver die configured to control a switching operation of the high-side switch and the low-side switch of the half-bridge circuit. In another embodiment, the third semiconductor die 152 may be omitted from the semiconductor package 100.In this case, the control terminals 128 can be directly connected to externally accessible contact pads, and thus the switching of the first semiconductor die and the second semiconductor die 122, 134 can be controlled externally.

[0046] The semiconductor package 100 further includes a liner of dielectric material 158 on the first semiconductor die 122. The liner of dielectric material 158 may be disposed at a corner of the first semiconductor die 122 that lies between the first load terminal and the second load terminal 126, 130. The corner of the first semiconductor die 122 may be an intersection point between a first edge side 160 of the first semiconductor die 122 that extends between the first surface and the second surface 124, 132 of the first semiconductor die 122.As shown, the liner of dielectric material 158 has a first portion extending between the first load terminal 126 of the first semiconductor die 122 and a corner of the first semiconductor die 122 located between the first surface 124 of the first semiconductor die 122 and a first edge side 160 of the first semiconductor die 122 extending between the first surface and the second surface 124, 132 of the first semiconductor die 122.The liner of dielectric material 158 additionally has a second part which extends from the corner only along a portion of the first edge side 160 of the first semiconductor die 122, which means that the liner of dielectric material 158 does not completely cover the first edge side 160, so that a lower part of the first edge side 160, which extends to the second surface 132 of the first semiconductor die 122, is exposed by the liner of dielectric material 158.The liner of dielectric material 158 may also be arranged at a second corner of the first semiconductor die 122, which is located between the first surface 124 of the first semiconductor die 122 and a second edge side 162 of the first semiconductor die 122, which extends between the first surface and the second surface 124, 132 of the first semiconductor die 122 and is opposite the first surface 124 of the first semiconductor die 122. As shown, the liner of dielectric material 158, which is arranged at both corners of the first semiconductor die 122, is a continuous structure. However, this is not required. In other embodiments, the liner of dielectric material 158 may be discontinuous on the first semiconductor die 122, as is the case, for example, with the second semiconductor die 134.

[0047] According to one embodiment, the dielectric material liner 158 has a different material composition than the inner laminate layer 102. For example, the dielectric material liner 158 may comprise an epoxy or mixed epoxy material (please provide examples), whereas the inner laminate layer 102 may comprise a resin material such as bismaleimidetrazine (BT) resin. In a particular embodiment, the material composition of the dielectric material liner 158 is such that the dielectric material liner 158 has a higher dielectric strength (i.e., the applied voltage at which dielectric breakdown occurs) than the material of the inner laminate layer 102.

[0048] By providing the dielectric material liner 158 at at least one corner of the first semiconductor die 122, which lies between the first load terminal and the second load terminal 126, 130, the high-voltage robustness of the semiconductor package 100 is increased. Among other things, the material composition and arrangement of the dielectric material liner 158 mitigates the possibility of voids or gaps forming between the edge surfaces of the first semiconductor die 122 and the inner laminate layer 102. This mitigates the risk of breakdown failures, such as electromigration.

[0049] The semiconductor package 100 may further include a liner of dielectric material 158 on the second semiconductor die 134. The liner of dielectric material 158 on the second semiconductor die 134 may be disposed at the corners of the second semiconductor die 134 in a similar manner as previously described with respect to the first semiconductor die 122. The liner of dielectric material 158 on the second semiconductor die 134 may provide at least some of the same voltage breakdown advantages as the liner of dielectric material 158 on the first semiconductor die 122, as previously described.

[0050] The semiconductor package 100 further includes a central dielectric structure 164 disposed between the first semiconductor die and the second semiconductor die 122, 134. As shown, the central dielectric structure 164 may be disposed such that a first portion of the inner laminate layer 102 is disposed between the liner of dielectric material 158 on the first semiconductor die 122 and the central dielectric structure 164, such that a second portion of the inner laminate layer 102 is disposed between the liner of dielectric material 158 on the second semiconductor die 134 and the central dielectric structure 164.According to one embodiment, the material composition of the central dielectric structure 164 differs from the material composition of the inner laminate layer 102 and / or differs from the composition of the dielectric material liners 158 on the first semiconductor die and the second semiconductor die 122, 134. Thus, three different types of dielectric structures may be laterally interposed between the first semiconductor die and the second semiconductor die. As a result, the lateral electrical isolation between the first semiconductor die and the second semiconductor die 122, 134 may be improved. In one particular example, the central dielectric structure 164 comprises a prepreg (pre-impregnated fiber material) material, such as FR-4, FR-5, CEM-4, etc., the inner laminate layer 102 comprises a resin material, such as bismaleimidetrazine (BT) resin, and the dielectric material liners 158 on the first semiconductor die and the second semiconductor die 122, 134 comprise an epoxy material.

[0051] Referring to Fig. 2, a semiconductor package 100 according to another embodiment is shown. The semiconductor package 100 of Fig. 2 differs from the semiconductor package 100 of Fig. 1 in that the terminal configuration of the second semiconductor die 134 is changed such that the control terminal 128 and the second load terminal 128 are arranged on the same surface of the second semiconductor die 134, which is designated in the figure as the second surface 132 of the second semiconductor die 134. In other words, the second surface 132 of the second semiconductor die 134, which faces the second layer of metallization 110, becomes the main surface of the die. Thus, unlike the embodiment of Fig. 1, which uses a first semiconductor die and a second semiconductor die 122, 134 that are identical to each other, uses the semiconductor package 100 of Fig. 2 shows a first and a second semiconductor die 122, 134, which differ from one another. This first semiconductor die and this second semiconductor die 122, 134 can form the high-side switch and the low-side switch, respectively, of a half-bridge circuit in a manner similar to that described above. In this case, providing the lining of dielectric material 158 on the second semiconductor die 134 can be particularly advantageous, as it provides electrical insulation between the control terminal 128 and the metallization connected to the drain potential.

[0052] Referring to Fig. 3, a semiconductor package 100 according to another embodiment is shown. In this embodiment, the semiconductor package 100 includes only a first semiconductor die 122 embedded in an inner laminate layer 102. The semiconductor package 100 may be configured as a discrete power device, such as a power MOSFET, with the inner laminate layer 102 protecting the first semiconductor die 122 and the semiconductor package 100 including contact pads formed in the first metallization layer and the second metallization layer 108, 110, providing electrical contact points to the various terminals of the first semiconductor die 122.The first semiconductor die 122 includes the liner of dielectric material 158 between the first load terminal and the second load terminal 126, 130 of the respective semiconductor die in a manner similar to that described above, thereby providing the advantageous voltage breakdown capability as described above.

[0053] Referring to Fig. 4, a method of forming the semiconductor package 100 according to another embodiment is illustrated. Referring to Fig. 4A, a core structure 202 is provided on a first carrier 204. The first carrier 204 may be, for example, an adhesive laminating tape. The core structure 202 may be a frame-like structure formed from an organic insulating material, e.g., a mixed epoxy and fiberglass materials such as FR-4, FR-5, CEM-4, etc. The core structure 202 has a plurality of openings 206 sized to receive the various semiconductor dies to be embedded in the semiconductor package 100. The core structure 202 is additionally provided to include a plurality of metallic via structures 208 extending through the core structure 202, thereby forming the buried via structures. The first semiconductor die, the second semiconductor die, and the third semiconductor die 122, 134, 152 are provided and arranged in one of the openings 206.The first semiconductor die 122 is provided to include the liner of dielectric material 158 disposed at the corner or corners of the first semiconductor die 122 in a manner previously described, prior to the subsequent step of embedding the first semiconductor die 122 into the inner laminate. Likewise, the second semiconductor die 134 is provided to include the liner of dielectric material 158 disposed at the corner or corners of the second semiconductor die 134 in a manner previously described, prior to the subsequent step of embedding the second semiconductor die 134 into the inner laminate.

[0054] Referring to Fig. 4C, the inner laminate layer 102 is formed such that the first semiconductor die, the second semiconductor die, and the third semiconductor die 122, 134, 152 are embedded in the inner laminate layer 102. The inner laminate layer 102 may be, for example, an ABF (Ajinomoto Build-Up Film). Referring to Fig. 4D, the first carrier 204 is removed, and outer openings 208 are formed in the inner laminate layer 102. The outer openings 208 can be formed, for example, using a laser etching process. The outer openings 208 expose the terminals of the first semiconductor die and the second semiconductor die 122, 134, which are to be connected to the first metallization layer 108, along with the buried via structures 120. Referring to Fig. 4E, a plating process is performed to form the first metallization layer and the second metallization layer 108, 110. The plating process may, for example, be an electroplating process. Referring to Fig. 4F, conductive pillars 210 are provided on the patterned portions of the first metallization layers and the second metallization layer 108, 110. These conductive pillars 210 form the blind via structures together with the intermediate metal structure of the first patterned contact pad and the second patterned contact pad 146, 148, as previously described. The conductive pillars 210 may be formed, for example, by means of a further plating process. Subsequently, a process sequence of further lamination, polishing, laser drilling, plating, and solder mask formation may be performed to form the further layers of the semiconductor package 100, e.g., the third layer of metallization and the fourth layer of metallization 112, 114, the second laminate layer and the third laminate layer 104, 106, the solder mask 118, and so on.

[0055] Referring to Fig. 5 illustrates a method of forming the semiconductor package 100 according to another embodiment. Referring to Fig. 5A, a core structure 202 is provided, which has a plurality of openings 206. According to one embodiment, the core structure 202 is a metal structure, such as a copper or aluminum structure, and thus provides buried via structures in the finished semiconductor package 100. The core structure 202 is arranged on a first carrier 204, which may, for example, be an adhesive laminating tape. As shown in Fig. As shown in Figure 5B, the inner laminate layer 102 is formed by a lamination process that fills each of the openings 206 of the core structure 202 with a dielectric material. The dielectric material may, for example, be a prepreg material. Subsequently, as shown in Fig. 5C, the first carrier 204 is removed and an etching process is performed to form another opening 212 in the inner laminate layer 102.

[0056] Referring to Fig. 5D, the structure comprising the core and the inner laminate layer 102 is placed on a second carrier 214, which may be, for example, a carrier tape. The first semiconductor die 122 is provided and has the liner of dielectric material 158 arranged at the corner or corners of the first semiconductor die 122 in a manner previously described, prior to the subsequent step of embedding the first semiconductor die 122 into the inner laminate. The first semiconductor die 122 is arranged on the second carrier 214 within the further opening 212 in the inner laminate layer 102. As shown in Fig. As shown in Figure 5E, a second lamination process is performed to fill each gap in the opening between the first semiconductor die 122 and the inner laminate layer 102 with a dielectric material 216. The second lamination process may be, for example, an ABF (Ajinomoto Build-Up Film) process.

[0057] Referring to Fig. 5F, the second carrier 214 is removed and a further opening 218 is formed in the inner laminate layer 102 to expose the second load terminal 130 of the first semiconductor die 122. The further opening 218 in the inner laminate layer 102 can be formed, for example, by means of a laser process. Subsequently, as shown in Fig.5G, the first metallization layer and the second metallization layer 108, 110 are formed. This can be done, for example, using a plating process. A seed layer can be applied to the exposed conductive surfaces prior to the plating surface. After forming the first metallization layer and the second metallization layer 108, 110, subsequent layers, such as a solder mask and an ENEPIG layer, can be formed.

[0058] The semiconductor package 100 described herein may be a so-called "die-embedded" package. A die-embedded package includes an encapsulant housing formed from multiple individual layers of dielectric material laminated (stacked) atop one another. This type of package differs from an overmolded package, where the encapsulant housing is provided by a monolithic region of electrically insulating material, such as a molding compound, that encapsulates the semiconductor die and associated electrical terminals, e.g., bond wires, clips, etc. In a die-embedded package, each individual laminate layer may generally comprise any dielectric material suitable for semiconductor device encapsulation. Examples of these dielectric materials include epoxy materials, mixed epoxy, and fiberglass materials such as FR-4, FR-5, CEM-4, etc.and resin materials such as bismaleimidetrazine (BT). A die-embedded package may also have multiple layers of metallization, e.g., copper, aluminum, etc., and their alloys, formed on at least some of the individual laminate layers. These layers of metallization may be patterned to form both the internal interconnect lines within the package body and the bond pads exposed on the outer surfaces of the package body. Due to the electrical connection provided by the internal patterned metallization, a die-embedded package does not require a lead frame or electrical connectors such as bond wires or clips. Therefore, the semiconductor package 100 may omit a die pad that houses the semiconductor dies and / or conductive lines formed from the same lead frame structure as a die pad.

[0059] Spatially relative terms such as "below," "beneath," "bottom," "above," "upper," and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass various orientations of the device in addition to those illustrated in the figures. Furthermore, terms such as "first," "second," and the like are used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.

[0060] As used herein, the terms "with," "containing," "including," "having," and the like are open-ended terms that indicate the presence of the specified elements or features but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and singular, unless the context clearly indicates otherwise.

Claims

[1] A semiconductor package (100) comprising: a package substrate comprising an inner laminate layer (102), a first metallization layer (108) disposed beneath the inner laminate layer (102), and a second metallization layer (110) disposed above the inner laminate layer (102); a first semiconductor die (122) having a first load terminal (126) arranged on a first surface (124) of the first semiconductor die (122) and a second load terminal (130) arranged on a second surface of the first semiconductor die (122) opposite the first surface (124) of the first semiconductor die (122); and a liner of dielectric material (158) on the first semiconductor die (122); wherein the first semiconductor die (122) is embedded in the inner laminate layer (102) such that the first surface (124) of the first semiconductor die (122) faces the second metallization layer (110), and wherein the lining of dielectric material (158) is arranged at a corner of the first semiconductor die (122) which lies between the first load terminal and the second load terminal (126, 130) of the first semiconductor die (122); wherein the lining of dielectric material (158) has a portion extending from the corner only along a portion of the first edge side (160) of the first semiconductor die (122) extending between the first surface (124) and the second surface (132) of the first semiconductor die (122); and wherein the dielectric material (158) comprises an epoxy or an epoxy mixture. [2] The semiconductor package (100) of claim 1, wherein the corner of the first semiconductor die (122) is located between the first surface (124) of the first semiconductor die (122) and a first edge side (160) of the first semiconductor die (122) extending between the first surface and the second surface of the first semiconductor die (122), and wherein the liner of dielectric material (158) has a first portion disposed on the first surface (124) of the first semiconductor die (122) and extending from the first load terminal (126) to the corner. [3] The semiconductor package (100) of claim 2, wherein the first portion of the liner of dielectric material (158) extends from the corner along only a portion of the first edge side of the first semiconductor die (122). [4] The semiconductor package (100) of claim 3, wherein the liner of dielectric material (158) has a second portion disposed on the first edge side and extending from the corner along only a portion of the first edge side. [5] The semiconductor package (100) of any one of claims 2 to 4, wherein the lining of dielectric material (158) has a second portion disposed at a second corner of the first semiconductor die (122) that is located between the first surface (124) of the first semiconductor die (122) and a second edge side (162) of the first semiconductor die (122) that extends between the first surface and the second surface of the first semiconductor die (122) and is opposite the first edge side (160) of the first semiconductor die (122). [6] The semiconductor package (100) of claim 5, wherein the second liner of dielectric material (158) extends along only a portion of the second edge side of the first semiconductor die (122), and wherein the second liner of dielectric material (158) is an epoxy layer. [7] The semiconductor package (100) according to any one of claims 4 to 6, further comprising a second semiconductor die (134) having a first load terminal (126) disposed on a first surface of the second semiconductor die (134) and a second load terminal (130) disposed on a second surface (132) of the second semiconductor die (134) opposite the first surface of the second semiconductor die (134); and a liner of dielectric material on the second semiconductor die (134); wherein the second semiconductor die (134) is embedded in the inner laminate layer (102) such that the first surface (124) of the second semiconductor die (134) faces the first metallization layer (108), and wherein the lining of dielectric material is arranged at a corner of the second semiconductor die (134) which lies between the first load terminal and the second load terminal (126, 130) of the second semiconductor die (134). [8] The semiconductor package (100) of claim 7, wherein the semiconductor package (100) is configured as an integrated half-bridge circuit, wherein the first semiconductor die and the second semiconductor die (122, 134) are each configured as discrete power transistor dies, wherein the first semiconductor die (122) is a high-side switch of the integrated half-bridge circuit, and wherein the second semiconductor die (134) is a low-side switch of the integrated half-bridge circuit. [9] The semiconductor package (100) according to one of claims 7 or 8, further comprising a third semiconductor die embedded in the inner laminate layer (102), wherein the third semiconductor die is a logic die having I / O terminals arranged on a first surface of the third semiconductor die facing the second metallization layer (110), wherein the third semiconductor die is configured to control a switching operation of the first semiconductor die and the second semiconductor die (122, 134) by means of the I / O terminals, and wherein the third semiconductor die is laterally electrically insulated from the first semiconductor die (122) by the liner made of dielectric material (158) arranged at a first edge region of the first semiconductor die (122). [10] The semiconductor package (100) according to any one of claims 7 to 9, wherein the first load terminal (126) of the first semiconductor die (122) is a source terminal of the high-side switch, wherein the second load terminal (130) of the second semiconductor die (134) is a drain terminal of the low-side switch, and wherein the first load terminal (126) of the first semiconductor die (122) is electrically connected to the second load terminal (130) of the second semiconductor die (134) through the second metallization layer (110). [11] The semiconductor package (100) according to one of claims 9 or 10, wherein the second semiconductor die (134) further comprises a control terminal (128) arranged on the first surface (124) of the second semiconductor die (134). [12] The semiconductor package (100) according to any one of claims 9 to 11, wherein the second semiconductor die (134) further comprises a control terminal (128) arranged on the second surface of the second semiconductor die (134). [13] The semiconductor package (100) of any one of claims 6 to 12, further comprising a central dielectric structure (164) disposed between the first semiconductor die and the second semiconductor die (122, 134), wherein a first portion of the inner laminate layer (102) is disposed between the second liner of dielectric material disposed at the second edge region of the first semiconductor die (122) and the central dielectric structure, and wherein a second portion of the inner laminate layer (102) is disposed between the liner of dielectric material disposed at the first edge region of the second semiconductor die (134) and the central dielectric structure. [14] The semiconductor package (100) of claim 13, wherein the dielectric material of the central dielectric structure is different from the material of the inner laminate layer (102). [15] The semiconductor package (100) of claim 13 or 14, wherein the dielectric material of the central dielectric structure is different from the dielectric material of the dielectric material liners on the first semiconductor die and the second semiconductor die (122, 134). [16] The semiconductor package (100) according to any one of claims 1 to 15, further comprising a first structured contact pad comprising a structured portion of the first metallization layer (108) and arranged on the second load terminal (130) of the first semiconductor die (122), wherein a thickness of the first structured contact pad is at least 50% of a vertical height of the first semiconductor die (122). [17] A method of forming a semiconductor package (100), the method comprising: Producing a package substrate comprising an inner laminate layer (102), a first metallization layer (108) disposed beneath the inner laminate layer (102), and a second metallization layer (110) disposed above the inner laminate layer (102); Providing a first load terminal (126) arranged on a first surface (124) of the first semiconductor die (122) and a second load terminal (130) arranged on a second surface of the first semiconductor die (122) opposite the first surface (124) of the first semiconductor die (122); and Providing a liner of dielectric material (158) on the first semiconductor die (122); Embedding the first semiconductor die (122) in the inner laminate layer (102) such that the first surface (124) of the first semiconductor die (122) faces the second metallization layer (110), and wherein the lining of dielectric material (158) is arranged at a corner of the first semiconductor die (122) which lies between the first load terminal and the second load terminal (126, 130) of the first semiconductor die (122); wherein the lining of dielectric material (158) has a portion extending from the corner only along a portion of the first edge side (160) of the first semiconductor die (122) extending between the first surface (124) and the second surface (132) of the first semiconductor die (122); and wherein the dielectric material (158) comprises an epoxy or an epoxy mixture. [18] The method according to any one of claims 16 or 17, wherein the first semiconductor die (122) is provided with the lining of dielectric material (158) arranged at the corner of the first semiconductor die (122) prior to embedding the first semiconductor die (122). [19] The method of claim 18, wherein the corner of the first semiconductor die (122) is located between the first surface (124) of the first semiconductor die (122) and a first edge side of the first semiconductor die (122) extending between the first surface and the second surface of the first semiconductor die (122), and wherein the liner of dielectric material (158) has a first portion disposed on the first surface (124) of the first semiconductor die (122) and extending from the first load terminal (126) to the corner. [20] The method of claim 19, wherein the lining of dielectric material (158) has a second part disposed on the first edge side and extending from the corner along only a portion of the first edge side. [21] The method of any one of claims 17 to 20, wherein embedding the first semiconductor die (122) into the inner laminate layer (102) comprises: Providing a core structure having a plurality of openings; Disposing the first semiconductor die (122) having the liner of dielectric material (158) disposed at the corner of the first semiconductor die (122) within one of the openings; and Filling gaps in the openings between the first semiconductor die (122) and the core structure with dielectric material. [22] The method according to any one of claims 19 to 21, further comprising: Providing a second semiconductor die (134) having a first load terminal (126) disposed on a first surface of the second semiconductor die (134) and a second load terminal (130) disposed on a second surface (132) of the second semiconductor die (134) opposite the first surface of the second semiconductor die (134); Providing a lining of dielectric material on the second semiconductor die (134); and Embedding the second semiconductor die (134) in the inner laminate layer (102) such that the first surface (124) of the second semiconductor die (134) faces the first metallization layer (108), wherein the lining of dielectric material is arranged at a corner of the second semiconductor die (134) which lies between the first load terminal and the second load terminal (126, 130) of the second semiconductor die (134), and wherein the second semiconductor die (134) is provided with the lining of dielectric material arranged at the corner of the second semiconductor die (134) prior to embedding the second semiconductor die (134). [23] The method of claim 22, wherein the semiconductor package (100) is configured as an integrated half-bridge circuit, wherein the first semiconductor die and the second semiconductor die (122 134) are each configured as discrete power transistor die, wherein the first semiconductor die (122) is a high-side switch of the integrated half-bridge circuit and wherein the second semiconductor die (134) is a low-side switch of the integrated half-bridge circuit. [24] The method of claim 23, wherein the first load terminal (126) of the first semiconductor die (122) is a source terminal of the high-side switch, wherein the second load terminal (130) of the second semiconductor die (134) is a drain terminal of the low-side switch, and wherein the first load terminal (126) of the first semiconductor die (122) is electrically connected to the second load terminal (130) of the second semiconductor die (134) through the second metallization layer (110).

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