GATE STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Abstract

Procedure, comprehensive: Forming a fin (52) extending from a substrate (50); Forming a dummy gate (72) over the fin (52), wherein the dummy gate (72) extends along side walls and a top surface of the fin (52); Removing the dummy gate (72) to form a recess (90); and Forming a replacement gate in the recess (90), wherein forming the replacement gate includes: Forming a boundary layer (92) along side walls and a bottom of the depression (90); Forming a dipole layer (94) above the interface layer (92), wherein the dipole layer (94) contains metal atoms; Insertion of fluorine atoms into the dipole layer (94); Driving the fluorine atoms and the metal atoms from the dipole layer (94) into the interface layer (92); and Removal of the dipole layer (94).

Description

BACKGROUND

[0001] Semiconductor devices are used in numerous electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and structuring the various material layers using lithography to create circuit components and elements.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, thus enabling the integration of more components into a given area. However, reducing the minimum component size introduces additional problems that need to be addressed.

[0003] Publication CN 113 764 411 A discloses in Fig. 17A to 23B a method for manufacturing a FinFET in which a metal layer 105 is treated with fluorine 109 in order to subsequently effect annealing to dope a layer stack of interface layer 101 and gate dielectric 103.

[0004] From the publication US 2020 / 0 119 164 A1, see its Fig. In documents 4A to 7D, a method for fabricating a FinFET is known in which a metal layer 236 containing fluorine 310 is deposited on a stack of gate dielectric 234 and interface layer 232, and an aluminum layer 238 is formed over it. During this process, annealing causes the diffusion of aluminum into the gate dielectric 234 and the interface layer 232, and an aluminum oxide dipole forms at the interface between these two layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates an example of a FinFET in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 23A and Fig. Figure 23B shows cross-sectional views of intermediate stages in the manufacture of a FinFET device according to some embodiments. Fig. Figure 14 is a flowchart illustrating a method for forming gate stacks according to some embodiments. Fig. Figure 17 is a flowchart illustrating a method for forming a dipole layer according to some embodiments. Fig. 24A and Fig. Figure 24B shows cross-sectional views of a FinFET device according to some embodiments. Fig. 25A and Fig. Figure 25B shows cross-sectional views of an NSFET device according to some embodiments. Fig. 26A and Fig. Figure 26B shows cross-sectional views of an NSFET device according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "underlying", "below", "under", "overlying", "above", and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0008] Embodiments are described in relation to a specific context, namely a gate structure of a semiconductor device and a method for forming it. Several embodiments presented here are described in the context of a fin field-effect transistor (FinFET) device formed using a gate-last process. In other embodiments, a gate-first process may be used. However, various embodiments can be applied to dies featuring other types of transistors, such as planar FETs, gate-all-around transistors (GAA transistors) (for example, nanostructured (e.g., nanosheet, nanowire, or the like) field-effect transistors (NSFETs)), or the like, instead of or in combination with the FinFETs.Several embodiments discussed here enable an improvement (or reduction) of the threshold voltage (Vt) of a semiconductor device, a reduction in interfacial trap density, an improvement in reliability, and a reduction or elimination of gate leakage current. In some embodiments, the threshold voltage (Vt) of a semiconductor device can be improved by forming a dipole layer (containing metal atoms) over an interfacial layer, performing a fluorine insertion process on the dipole layer, and performing an annealing process to drive metal and fluorine atoms from the dipole layer into the interfacial layer.

[0009] Fig. Figure 1 illustrates an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET has a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Insulating regions 56 are arranged in the substrate 50, and the fin 52 projects over and between adjacent insulating regions 56. Although the insulating regions 56 are shown separately from the substrate 50 in the description / illustration, the term "substrate," as used here, can refer to the semiconductor substrate alone or to a semiconductor substrate including insulating regions. Additionally, although the fin 52 is illustrated as a single continuous material like the substrate 50, the fin 52 and / or the substrate 50 may contain a single material or multiple materials. In this context, the fin 52 refers to the portion that extends between the adjacent insulating regions 56.

[0010] A dielectric gate layer 98 extends along side walls and over a top surface of the fin 52, and a gate electrode 100 is located above the dielectric gate layer 98. Source / drain regions 82 are arranged on opposite sides of the fin 52 with respect to the dielectric gate layer 98 and the gate electrode 100. Source / drain region(s) can refer to a source or a drain, individually or jointly, depending on the context. Fig. Figure 1 further illustrates reference cross-sections that will be used in later figures. Cross-section AA runs along a longitudinal axis of the gate electrode 100 and in a direction, for example, perpendicular to a current flow direction between the source / drain regions 82 of the FinFET. Cross-section BB runs perpendicular to cross-section AA and along a longitudinal axis of the fin 52 and in a direction, for example, of the current flow between the source / drain regions 82 of the FinFET. Cross-section CC runs parallel to cross-section AA and extends through the source / drain region 82 of the FinFET. Subsequent figures refer to these reference cross-sections for clarity.

[0011] Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 23A and Fig. Figure 23B shows cross-sectional views of intermediate stages in the manufacture of a FinFET device according to some embodiments. Fig. Figures 2-7, 8A-13A, 15A, 16A and 18A-23A illustrate cross-sectional views along the reference cross-section AA, which is shown in Fig. 1 is illustrated, with the exception of several fins / FinFETs. Fig. Figures 8B-13B, 15B, 16B, 18B-23B, 21C and 21D illustrate cross-sectional views along the reference cross-section BB, which is in Fig. 1 is illustrated, with the exception of several fins / FinFETs. Fig. 10C and Fig. 10D illustrates cross-sectional views along the reference cross-section CC, which is in Fig. 1 is illustrated, with the exception of several fins / FinFETs.

[0012] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor containing silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor containing SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0013] The substrate 50 has a region 50N and a region 50P. Region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-FinFETs. Region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. Region 50N can be physically separated from region 50P (as illustrated by a divider 51), and any number of device structure elements (e.g., other active devices, doped regions, insulating structures, etc.) can be placed between region 50N and region 50P.

[0014] In Fig. 3. Fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 in the substrate 50 can be formed by etching grooves in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like. The etching process can be anisotropic.

[0015] The fins 52 can be formed by any suitable method. For example, the fins 52 can be formed using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, thereby producing structures that, for example, have smaller pitches than would otherwise be obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask for forming the fins 52.

[0016] In Fig. 4 An insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide such as silicon dioxide, a nitride, a combination thereof, or the like, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert to another material such as an oxide), a combination thereof, or the like. Other insulating materials formed by an acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon dioxide formed by an FCVD process. An annealing process can be performed once the insulating material has formed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52.Although the insulating material 54 is illustrated as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a lining (not shown) can first be formed along the surfaces of the substrate 50 and the fins 52. Then, a filler material, such as those discussed above, can be formed over the lining.

[0017] In Fig. 5. A removal process is applied to the insulation material 54 to remove excess sections of the insulation material 54 above the fins 52. In some embodiments, a planarization process, such as a chemical-mechanical polishing process (CMP process), a back-etching process, a combination thereof, or the like, may be used. The planarization process exposes the fins 52 so that, after completion of the planarization process, the covering surfaces of the fins 52 and the covering surface of the insulation material 54 are flush within process variations of the planarization process.

[0018] In Fig. 6 the insulation material 54 (see Fig. 5) Deepened to form isolation areas 56. The isolation areas 56 may also be referred to as trench isolation areas (STI areas). The isolation material 54 is deepened such that upper portions of fins 52 project in areas 50N and 50P between adjacent isolation areas 56. Furthermore, the surface coverings of the isolation areas 56 may have a flat surface, as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The surface coverings of the isolation areas 56 may be formed flat, convex, and / or concave by suitable etching. The isolation areas 56 may be deepened using an acceptable etching process, such as one that is selective for the material of the isolation material 54 (e.g., etching the material of the isolation material 54 at a faster rate than the material of the fins 52).For example, chemical oxide removal can be achieved using a suitable etching process, such as dilute hydrofluoric acid (dHF acid).

[0019] The process relating to Fig. The description in Figures 2 to 6 is only one example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be allowed to grow epitaxially in the trenches, and the dielectric layer can be deepened such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins. For example, the fins 52 can be formed in Fig. The recesses 52 are deepened, and a material different from the fins 52 can be epitaxially grown over them. In such embodiments, the fins contain both the recessed material and the epitaxially grown material deposited over the recessed material. In a further embodiment, a dielectric layer can be formed over a surface of the substrate 50, and grooves can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the grooves using a material different from the substrate 50, and the dielectric layer can be deepened such that the heteroepitaxial structures protrude from the dielectric layer to form the fins.In some embodiments where homoepitactic or heteroepitactic structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, which can avoid prior or subsequent implantations, although in situ and implantation doping can be used together.

[0020] Furthermore, it can be advantageous to epitaxially grow a material in region 50N that differs from a material in region 50P. In various embodiments, upper sections of the fins 52 can be made of silicon germanium (Si₂). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0021] Further information can be found in Fig. Six suitable wells (not shown) are formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well can be formed in region 50N and an N-well can be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P. In embodiments with different types of wells, the various implantation steps for region 50N and region 50P can be achieved using a photoresist or other masks (not shown). For example, a first photoresist can be formed over the fins 52 and the insulating regions 56 in both region 50N and region 50P. The first photoresist is structured to expose region 50P of the substrate 50. The first photoresist can be formed using a spin-on technique and can be structured using acceptable photolithography techniques.Once the first photoresist is structured, an n-impurity implantation is performed in area 50P, while the remaining portion of the first photoresist acts as a mask to essentially prevent n-impurities from being implanted into area 50N. The n-impurities can be phosphorus, arsenic, antimony, or the like, present in the area at a dose equal to or less than 10. 15 cm -2 , as between about 10 12 cm -2 and about 10 15 cm -2 , are implanted. In some embodiments, the n-defect sites can be implanted at an implantation energy of approximately 1 keV to approximately 10 keV. After implantation, the first photoresist is removed, for example by an acceptable ashing process, followed by a wet cleaning process.

[0022] Following the implantation of region 50P, a second photoresist is formed over the fins 52 and the insulating regions 56 in both region 50P and region 50N. The second photoresist is patterned to expose region 50N of the substrate 50. The second photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the second photoresist is patterned, p-defect implantation can be performed in region 50N, while the remaining portion of the second photoresist acts as a mask to essentially prevent p-defects from being implanted into region 50P. The p-defects can be boron, BF2, indium, or the like, implanted in the region at a dose equal to or less than 10 15 cm -2 , as between about 10 12 cm -2 and about 10 15 cm -2, are implanted. In some embodiments, the p-defect sites can be implanted at an implantation energy of approximately 1 keV to approximately 10 keV. After implantation, the second photoresist can be removed, for example by an acceptable ashing process followed by a wet cleaning process.

[0023] After implantation of region 50N and region 50P, a tempering process can be performed to activate the p- and / or n-defects that were implanted. In some embodiments, the grown materials of epitaxial fins can be doped in situ during growth, which can eliminate the need for implantation, although in situ doping and implantation doping can be used together.

[0024] In Fig. A dielectric dummy layer 60 is formed on the fins 52. The dielectric dummy layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dielectric dummy layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dielectric dummy layer 60 and then planarized using, for example, a CMP process. After performing the planarization process, the mask layer 64 can be deposited over the dummy gate layer 62.The dummy gate layer 62 can be a conductive material and can be selected from a group containing amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), continuous vapor deposition (CVD), sputtering, or other techniques known and used in the technology for depositing conductive materials. The dummy gate layer 62 can be made of materials other than those of the insulating regions 56, provided they exhibit high etch selectivity. The mask layer 64, for example, can contain one or more layers of silicon dioxide, SiN, SiON, a combination thereof, or the like.In some embodiments, the mask layer 64 may comprise a layer of silicon nitride and a layer of silicon oxide over the silicon nitride layer. In some embodiments, a single dummy gate layer 62 and a single mask layer 64 are formed over region 50N and region 50P. It should be noted that, for illustrative purposes only, the dielectric dummy layer 60 covers only the fins 52 in the illustration. In some embodiments, the dielectric dummy layer 60 may be deposited such that it covers the insulating regions 56, extending between the dummy gate layer 62 and the insulating regions 56.

[0025] Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 23A and Fig. Figure 23B illustrates various additional steps in the manufacture of a FinFET device according to some embodiments. Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 23A and Fig. 23B illustrates structural elements in one of the areas 50N and 50P. For example, the ones in Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 23A and Fig. The structures illustrated in Figure 23B are applicable to both Area 50N and Area 50P. Differences (if any) between the structures of Area 50N and Area 50P are described in the text accompanying each figure.

[0026] In Fig. 8A and Fig. 8B can be used for mask layer 64 (see Fig. 7) are structured using acceptable photolithography and etching techniques to form masks 74. In some embodiments, the etching techniques may include one or more anisotropic etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like. Subsequently, the structure of the masks 74 can be transferred to the dummy gate layer 62 (see Fig. 7) to form dummy gates 72. In some embodiments, the structure of the masks 74 can also be transferred to the dielectric dummy layer 60 by an acceptable etching technique. The dummy gates 72 cover channel regions 58 of the fins 52. The structure of the masks 74 can be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The dummy gates 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of a corresponding fin 52. As described in more detail below, the dummy gates 72 are sacrificial gates and are subsequently replaced by replacement gates. Therefore, dummy gates 72 can also be referred to as sacrificial gates. In other embodiments, some of the dummy gates 72 are not replaced and remain in the finished structure of the resulting FinFET device.

[0027] Further information can be found in Fig. 8A and Fig. 8B Gate sealing spacers 80 are formed on exposed surfaces of the dummy gates 72, masks 74, and / or fins 52. The gate sealing spacers 80 can be formed by heat oxidation or deposition followed by anisotropic etching. The gate sealing spacers 80 can contain silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. After the formation of the gate sealing spacers 80, implantations for lightly doped source / drain regions (LDD regions) (not specifically illustrated) can be performed. In embodiments with different types of devices, similar to the above in Fig. As discussed in the 6 implantation procedures, a mask, such as a photoresist, is formed over region 50N while region 50P remains exposed, and a suitable type (e.g., p-) of defect can be implanted into the exposed fins 52 in region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over region 50P while region 50N remains exposed, and a suitable type (e.g., n-) of defect can be implanted into the exposed fins 52 in region 50N. The mask can then be removed. The n-defects can be any of the previously discussed n-defects, and the p-defects can be any of the previously discussed p-defects. The lightly doped source / drain regions can accommodate a dose of defects of approximately 10 12 cm -2 up to about 10 16 cm -2In some embodiments, suitable defects can be implanted at an implantation energy of approximately 1 keV to approximately 10 keV. Annealing can be used to activate the implanted defects.

[0028] In Fig. 9A and Fig. In 9B, gate spacers 86 are formed on the gate sealing spacers 80 along the side walls of the dummy gates 72 and the masks 74. The gate spacers 86 can be formed by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gate spacers 86 can contain silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. In some embodiments, the gate spacers 86 can have multiple layers (not shown) such that the layers contain different materials. In some embodiments, the gate spacers 86 and the gate sealing spacers 80 contain the same material. In other embodiments, the gate spacers 86 and the gate sealing spacers 80 contain different materials.

[0029] It is noted that the above disclosure describes a process for forming spacers and LDD regions in general. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be employed (e.g., the gate sealing spacers 80 may not be etched before the formation of the gate spacers 86, resulting in "L-shaped" gate sealing spacers; spacers may be formed and removed, and / or the like). Furthermore, the n- and p-devices may be formed using different structures and steps. For example, LDD regions for n-devices may be formed before the formation of the gate sealing spacers 80, while the LDD regions for p-devices may be formed after the formation of the gate sealing spacers 80.

[0030] In Fig. 10A and Fig. In 10B, epitaxial source / drain regions 82 are formed in the fins 52 to exert voltage in the corresponding channel regions 58, thereby improving the performance of the device. The epitaxial source / drain regions 82 are formed in the fins 52 such that each dummy gate 72 is located between corresponding adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into and penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 at a suitable lateral distance, so that the epitaxial source / drain regions 82 do not short-circuit subsequently formed gates of the resulting FinFET device.

[0031] The epitaxial source / drain regions 82 in region 50N can be formed by masking region 50P and etching source / drain regions of the fins 52 in region 50N to create depressions in the fins 52. The epitaxial source / drain regions 82 in region 50N are then allowed to grow epitaxially within these depressions. The epitaxial source / drain regions 82 can contain any acceptable material, as is suitable for n-FinFETs. For example, if the fin 52 contains silicon, the epitaxial source / drain regions 82 in region 50N can contain materials that exert a tensile load in the channel region 58, such as silicon, SiC, SiCP, SiP, a combination thereof, or the like. The epitaxial source / drain areas 82 in area 50N may have surfaces that are distinct from corresponding surfaces of the fins 52 and may exhibit facets.

[0032] The epitaxial source / drain regions 82 in region 50P can be formed by masking region 50N and etching source / drain regions of the fins 52 in region 50P to create depressions in the fins 52. The epitaxial source / drain regions 82 in region 50P are then allowed to grow epitaxially within these depressions. The epitaxial source / drain regions 82 can contain any acceptable material suitable for p-FinFETs. For example, if the fin 52 contains silicon, the epitaxial source / drain regions 82 in region 50P can contain materials that exert a pressure load in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, a combination thereof, or the like. The epitaxial source / drain areas 82 in area 50P may also have surfaces that are distinct from corresponding surfaces of the fins 52 and may have facets.

[0033] The epitaxial source / drain regions 82 and / or the fins 52 can be implanted with dopants, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The epitaxial source / drain regions 82 can accommodate an impurity concentration of approximately 10 19 cm -3 and about 10 21 cm -3 exhibit. The n- and / or p-defect sites for the epitaxial source / drain regions 82 can be any of the defects discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0034] As a result of the epitaxial processes used to form the epitaxial source / drain regions 82 in region 50N and region 50P, the upper surfaces of the epitaxial source / drain regions exhibit facets that extend laterally outward beyond the sidewalls of the fins 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 82 of the same FinFET to merge, as described by Fig. Figure 10C illustrates this. In other embodiments, adjacent epitaxial source / drain regions 82 remain separated after completion of the epitaxial process, as shown by Fig. Illustrated in 10D. In the embodiments shown in Fig. 10C and Fig. As illustrated in Figure 10D, the gate spacers 86 are formed, covering a section of the sidewalls of the fins 52 that extend over the insulating areas 56, thereby blocking epitaxial growth. In other embodiments, the spacer etching used to form the gate spacers 86 can be adjusted to remove the spacer material from the sidewalls of the fins 52, allowing the epitaxially grown area to extend to the surface of the insulating area 56.

[0035] In Fig. 11A and Fig. 11B will be a first interlayer dielectric (ILD) 88 over the in Fig. 10A and Fig. The structure illustrated in Figure 10B is deposited. The first ILD 88 can be formed from a dielectric material and can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), FCVD, a combination thereof, or the like. Dielectric materials can include phosphosilicate glass (PSG), boron-silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by an acceptable process can also be used. In some embodiments, a contact etch stop layer (CESL) 87 is arranged between the first ILD 88 and the epitaxial source / drain regions 82, the masks 74, and the gate spacers 86. The CESL 87 may contain a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, a combination thereof or the like, with a different etch rate than the material of the overlying first ILD 88.

[0036] In Fig. 12A and Fig. 12B, a planarization process, such as a CMP process, can be carried out to make the cover surface of the first ILD 88 flush with the cover surfaces of the dummy gates 72 or the masks 74 (see Fig. 11A and Fig. 11B). The planarization process can also remove the masks 74 on the dummy gates 72 and sections of the gate sealing spacers 80 and the gate spacers 86 along the side walls of the masks 74. After the planarization process, the cover surfaces of the dummy gates 72, the gate sealing spacers 80, the gate spacers 86, and the first ILD 88 are flush with each other within process variations of the planarization process. Therefore, the cover surfaces of the dummy gates 72 are exposed by the first ILD 88. In some embodiments, the masks 74 may remain, in which case the planarization process makes the cover surface of the first ILD 88 flush with the cover surfaces of the masks 74.

[0037] In Fig. 13A and Fig. 13B will be the dummy gates 72 and the masks 74 (see Fig. 11A and Fig. 11B), if present, are removed in one or more etching steps, forming openings 90. Sections of the dielectric dummy layer 60 in the openings 90 may also be removed. In some embodiments, only the dummy gates 72 are removed, and the dielectric dummy layer 60 remains and is exposed through the openings 90. In some embodiments, the dielectric dummy layer 60 is removed from the openings 90 in a first region of a die (e.g., a core logic region) and remains in openings 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gates 72 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reaction gas(es) that selectively etches (etches) the dummy gates 72 without etching the first ILD 88 or the gate spacers 86.Each opening 90 exposes a channel region 58 of a corresponding fin 52. Each channel region 58 is arranged between adjacent pairs of epitaxial source / drain regions 82. During removal, the dielectric dummy layer 60 can be used as an etch stop layer when the dummy gates 72 are etched. The dielectric dummy layer 60 can then optionally be removed after the dummy gates 72 have been removed.

[0038] Fig. Figure 14 is a flowchart illustrating a procedure 200 for forming gate stacks 102 (see Fig. 21A-21D) according to some embodiments. Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C and Fig. Figure 21D shows cross-sectional views of intermediate stages in the manufacture of the gate stacks 102 according to method 200. The gate stacks 102 can also be referred to as substitute gate stacks or metal gate stacks.

[0039] With reference to Fig. 14, Fig. 15A and Fig. In step 202, an interface layer 92 is formed along the sidewalls and bottoms of the openings 90 and over the first ILD 88. The interface layer 92 may contain silicon dioxide and may be formed using a chemical deposition process such as ALD, CVD, or the like, or using an oxidation process. In some embodiments, when the interface layer 92 is formed using a deposition process, the interface layer 92 extends along exposed surfaces of the fins 52, the insulating areas 56, and the gate sealing spacers 80. In some embodiments, when the interface layer 92 is formed using an oxidation process, the interface layer 92 extends along exposed surfaces of the fins 52 but does not extend along exposed surfaces of the insulating areas 56 and the gate sealing spacers 80.In some embodiments, the interface layer 92 has a thickness between about 8 Å and about 20 Å.

[0040] With reference to Fig. 14, Fig. 16A and Fig. In step 204, a dipole layer 94 is formed above the interface layer 92 in the openings 90. In some embodiments, the dipole layer 94 contains in the region 50N (see Fig. 2) a metal oxide material, such as lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), a combination thereof, or the like, and can be formed using ALD, CVD, a combination thereof, or the like. In such embodiments, the dipole layer 94 can also be referred to as an n-dipole layer. In some embodiments, the dipole layer 94 contains in region 50P (see Fig. 2) a metal oxide material, such as zinc oxide (ZnO), aluminum oxide (Al₂O₃), gallium oxide (Ga₂O or Ga₂O₃), a combination thereof, or the like, and may be formed using ALD, CVD, a combination thereof, or the like. In such embodiments, the dipole layer 94 may also be referred to as a p-dipole layer. In some embodiments, during the deposition process, some metal atoms from the dipole layer 94 diffuse into the interface layer 92 to form a metal-doped interface layer 92'. In some embodiments, diffused metal atoms form dipoles at an interface between the metal-doped interface layer 92' and the subsequently formed dielectric gate layer, modifying a threshold voltage of a resulting FinFET device. In some embodiments, the amount of metal atoms that diffuse into the interface layer 92 (see Fig. 15A and Fig. 15B), by increasing the thickness of the dipole layer 94. In some embodiments, the dipole layer 94 has a thickness between about 1 Å and about 15 Å.

[0041] Fig. Figure 17 is a flowchart illustrating a procedure 300 for forming the dipole layer 94 (see Fig. 16A and Fig. 16B) according to some embodiments. In some embodiments, method 300 can be described as step 204 of method 200 (see Fig. 14) be implemented. In the illustrated embodiment, the method 300 comprises an ALD process. The method 300 comprises performing an ALD cycle 302 once or several times. In some embodiments, the ALD cycle 302 is performed N2 times. In some embodiments, N2 can be between 1 and 100. In some embodiments, the method 300 is performed at a temperature between about 150°C and about 650°C. In some embodiments, the method 300 can be performed at a pressure between about 13.33 Pa (0.1 Torr) and about 9332.57 Pa (70 Torr).

[0042] In some embodiments, the ALD cycle 302 may include performing step 304, where a metal-containing precursor is introduced above the interface layer 92 (see Fig. 15A and Fig. 15B). In some embodiments, the metal-containing precursor is adsorbed onto an exposed surface of the interface layer 92. In some embodiments, the metal-containing precursor can be introduced for a time between about 0.1 sec and about 60 sec. In some embodiments, the flow rate of the metal-containing precursor can be between about 200 sccm and about 5000 sccm.

[0043] In step 306, unadsorbed sections of the metal-containing precursor are purged using a non-reactive gas such as N₂, Ar, the like, or a combination thereof. In some embodiments, the purging is carried out for a time between 0.1 sec and about 60 sec. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0044] In step 308, an oxygen-containing precursor is introduced over adsorbed sections of the metal-containing precursor. The oxygen-containing precursor reacts with adsorbed sections of the metal-containing precursor to form a metal oxide material of the dipole layer 94. In some embodiments, the oxygen-containing precursor may contain H₂O, O₂, O₃, the like, or a combination thereof. In some embodiments, the oxygen-containing precursor is introduced for a time between 0.1 s and about 60 s. In some embodiments, the flow rate of the oxygen-containing precursor may be between about 200 sccm and about 5000 sccm.

[0045] In step 310, reaction byproducts from step 308 are purged using a non-reactive gas such as N₂, Ar, the like, or a combination thereof. In some embodiments, the purging is carried out for a time between 0.1 sec and about 60 sec. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0046] In some embodiments, when the dipole layer contains aluminium oxide (Al2O3), the metal-containing precursor contains TMA (Al2(CH3)6), the oxygen-containing precursor contains H2O, and the process 300 is carried out at a temperature between about 250°C and about 550°C and a pressure between about 66.66 Pa (0.5 Torr) and about 5332.89 Pa (40 Torr).

[0047] In some embodiments, when the dipole layer contains lanthanum oxide (La2O3), the metal-containing precursor contains La(fAMD)3, the oxygen-containing precursor contains H2O, and the process 300 is carried out at a temperature between about 100 °C and about 450 °C and a pressure between about 1.33 Pa (0.01 Torr) and about 6666.12 Pa (50 Torr).

[0048] In some embodiments, when the dipole layer contains 94 yttrium oxide (Y2O3), the metal-containing precursor contains Y(DPfAMD)3, the oxygen-containing precursor contains H2O, and the process 300 is carried out at a temperature between about 100 °C and about 450 °C and a pressure between about 1.33 Pa (0.01 Torr) and about 6666.12 Pa (50 Torr).

[0049] In some embodiments, when the dipole layer contains zinc oxide (ZnO), the metal-containing precursor contains DEZn, the oxygen-containing precursor contains O3, and the process 300 is carried out at a temperature between about 100 °C and about 450 °C and a pressure between about 1.33 Pa (0.01 Torr) and about 6666.12 Pa (50 Torr).

[0050] In some embodiments, when the dipole layer contains 94 gallium oxide (Ga2O or Ga2O3), the metal-containing precursor contains TDMAGa, the oxygen-containing precursor contains O3, and the process 300 is carried out at a temperature between about 100 °C and about 450 °C and a pressure between about 13.33 Pa (0.1 Torr) and about 6666.12 Pa (50 Torr).

[0051] With reference to Fig. 14, Fig. 18A and Fig. In step 206, 18B, a fluorine impregnation process is carried out on the dipole layer 94 (see Fig. 16A and Fig. 16B), to form a fluorine-doped dipole layer 94'. In some embodiments, the fluorine impregnation process includes impregnating the structure of Fig. 16A and Fig. 16B with a fluorine-containing chemical. The fluorine-containing chemical may contain WF6, NF3, the like, or a combination thereof. In some embodiments, the fluorine impregnation process comprises a gas-phase process and the structure of Fig. 16A and Fig. 16B is impregnated with gas from fluorine-containing molecules 96 of the fluorine-containing chemical. In some embodiments, the fluorine-containing molecules 96 are adsorbed on an exposed surface of the dipole layer 94 (see Fig. 16A and Fig. 16B) and fluorine atoms from the fluorine-containing molecules 96 are diffused into the dipole layer 94 to form the fluorine-doped dipole layer 94'. In other embodiments, the fluorine impregnation process includes a liquid-phase process. In some embodiments, during the fluorine impregnation process, some of the metal atoms of the fluorine-doped dipole layer 94' diffuse further into the metal-doped interface layer 92'.

[0052] In some embodiments, the fluorine impregnation process is carried out at a temperature between approximately 250 °C and approximately 550 °C. In some embodiments, the fluorine impregnation process is carried out at a pressure between approximately 66.66 Pa (0.5 Torr) and approximately 5332.89 Pa (40 Torr). In some embodiments, the fluorine concentration in the fluorine-doped dipole layer 94' can be increased by increasing the duration of the fluorine impregnation process. In some embodiments, the fluorine impregnation process is carried out for a time between approximately 0.1 sec and approximately 1800 sec. In some embodiments, the fluorine-doped dipole layer 94' has a fluorine concentration between approximately 0.01 att% and approximately 25 att%.

[0053] With reference to Fig. 14, Fig. 19A and Fig. In step 208, 19B undergoes a tempering process on the structure of Fig. 18A and Fig. 18B. In some embodiments, the annealing process drives some of the fluorine and metal atoms from the fluorine-doped dipole layer 94' into the metal-doped interface layer 92' (see Fig. 18A and Fig. 18B), to form a metal / fluorine-doped interface layer 92". In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped lanthanum oxide layer (La₂O₃ layer), the metal atoms are lanthanum atoms (La atoms). In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped yttrium oxide layer (Y₂O₃ layer), the metal atoms are yttrium atoms (Y atoms). In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped zinc oxide layer (ZnO layer), the metal atoms are zinc atoms (Zn atoms). In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped aluminum oxide layer (Al₂O₃ layer), the metal atoms are aluminum atoms (Al atoms). In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped gallium oxide layer (Ga2O or Ga2O3 layer), the metal atoms are gallium atoms (Ga atoms).In some embodiments, the tempering process is carried out at a temperature between approximately 450 °C and approximately 1100 °C. In some embodiments, the tempering process is carried out for a time between approximately 0.1 seconds and approximately 30 seconds. In some embodiments, steps 206 and 208 are carried out N1 times. N1 can be between approximately 1 and approximately 5.

[0054] In some embodiments, the diffusion depth of fluorine and metal atoms within the metal / fluorine-doped interface layer 92'' can be increased by increasing the temperature and / or duration of the annealing process. In some embodiments, when the annealing process is carried out for a time between approximately 0.1 sec and approximately 1800 sec, fluorine and metal atoms diffuse to an upper surface of the metal / fluorine-doped interface layer 92''. In such embodiments, the upper surface of the metal / fluorine-doped interface layer 92'' has a fluorine concentration between approximately 0.001 att% and approximately 20 att%. Furthermore, in some embodiments, when the fluorine-doped dipole layer 94' contains fluorine-doped lanthanum oxide (La₂O₃), the upper surface of the metal / fluorine-doped interface layer 92'' has a lanthanum concentration between approximately 0.001 att% and approximately 15 att%.

[0055] In some embodiments, when the tempering process is carried out for a time between about 0.1 sec and about 1800 sec, fluorine and metal atoms diffuse to an interface between the metal / fluorine-doped interface layer 92'' and a corresponding fin 52. In such embodiments, the upper surface of the metal / fluorine-doped interface layer 92'' has a fluorine concentration between about 0.001 att% and about 20 att%, an interior of the metal / fluorine-doped interface layer 92'' has a fluorine concentration between about 0.001 att% and about 20 att%, and the interface between the metal / fluorine-doped interface layer 92'' and the corresponding fin 52 has a fluorine concentration between about 0.001 att% and about 20 att%.Moreover, in some embodiments, if the fluorinated dipole layer 94' contains fluorinated lanthanum oxide (La2O3), the upper surface of the metal / fluorinated interface layer 92'' has a lanthanum concentration between about 0.001 att% and about 15 att%, the interior of the metal / fluorinated interface layer 92'' has a lanthanum concentration between about 0.001 att% and about 15 att%, and the interface between the metal / fluorinated interface layer 92'' and the corresponding fin 52 has a lanthanum concentration between about 0.001 att% and about 15 att%.

[0056] In some embodiments, the metal atoms that have diffused into the 92'' interface layer can introduce energy states near a conduction band edge, which can lead to a leakage path and reliability weakness of the resulting gate stack. In some embodiments, the fluorine atoms that have diffused into the 92'' interface layer can remove the energy states near a conduction band edge, improve the reliability of the gate stack, and reduce or eliminate gate leakage current.

[0057] With reference to Fig. 14, Fig. 20A and Fig. In step 210, the fluorine-doped dipole layer 94' (see 20B) is formed. Fig. 19A and Fig. 19B) removed to expose the metal / fluorine-doped interface layer 92''. In some embodiments, the removal process may include a wet etching process, such as dilute hydrofluoric acid etching (dHF etching), an SC1 process, SC2 process, the like, or a combination thereof.

[0058] With reference to Fig. 14, Fig. 21A and Fig. In step 212, a dielectric gate layer 98 is formed above the metal / fluorine-doped interface layer 92'' in the openings 90 (see Fig. 20A and Fig. 20B). In some embodiments, the dielectric gate layer 98 contains silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the dielectric gate layer 98 contains a high-k dielectric material, and in these embodiments, the dielectric gate layer 98 may have a k-value greater than about 7.0 and may contain a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation methods of the dielectric gate layer 98 may include molecular beam deposition (MBD), ALD, PECVD, a combination thereof, or the like. In some embodiments, the dielectric gate layer 98 contains atoms of a first metallic element, and the metal / fluorine-doped interface layer 92'' contains atoms of a second metallic element that is different from the first metallic element.

[0059] With further reference to Fig. 14, Fig. 21A and Fig. In step 214, the gate electrode layer 100 is deposited over the dielectric gate layer 98 and fills the remaining sections of the openings 90 (see Fig. 20A and Fig. 20B). Although a single-layer gate electrode layer 100 in Fig. 21A and Fig. As illustrated in Figure 21B, the gate electrode layer 100 can have any number of lining layers 100A, any number of output working tuning layers 100B, and a conductive filler layer 100C, as shown by Fig. 21C illustrates a detailed view of area 104 of Fig. 21B shows the following. The lining layers 100A can contain TiN, TiO, TaN, TaC, combinations thereof, multiple layers thereof, or the like, and can be formed using PVD, CVD, ALD, a combination thereof, or the like. In area 50N, the output work tuning layers 100B can contain Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multiple layers thereof, or the like, and can be formed using PVD, CVD, ALD, a combination thereof, or the like. In area 50P, the output work tuning layers 100B can contain TiN, WN, TaN, Ru, Co, combinations thereof, multiple layers thereof, or the like, and can be formed using PVD, CVD, ALD, a combination thereof, or the like.In some embodiments, the conductive filler layer 100C may contain Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, multiple layers thereof or the like, and may be formed using PVD, CVD, ALD, plating, a combination thereof or the like.

[0060] After filling the openings 90 (see Fig. 20A and Fig. 20B) A planarization process, such as a CMP, can be performed to remove the excess sections of the dielectric gate layer 98, the gate electrode layer 100, and / or the metal / fluorine-doped interface layer 92'', which excess sections are located above the top surface of the first ILD 88. The remaining sections of the dielectric gate layer 98, the gate electrode layer 100, and the metal / fluorine-doped interface layer 92'' thus form gate stacks 102 of the resulting FinFETs. The gate stacks 102 can extend along sidewalls of channel regions 58 of the fins 52.

[0061] Fig. 21D illustrates a detailed view of area 106 of Fig. 21C. In some embodiments, fluorine atoms diffuse within the metal / fluorine-doped interface layer 92'' into a corresponding fin 52 and a corresponding dielectric gate layer 98 and form various bonds at an interface between the metal / fluorine-doped interface layer 92'' and the corresponding fin 52 and at an interface between the metal / fluorine-doped interface layer 92'' and the corresponding dielectric gate layer 98. In some embodiments, the fluorine atoms form F-Si bonds at the interface between the metal / fluorine-doped interface layer 92'' and the corresponding fin 52 and at the interface between the metal / fluorine-doped interface layer 92'' and the corresponding dielectric gate layer 98.In some embodiments, when the dielectric gate layer 98 is made of hafnium oxide (HfO2), the fluorine atoms form Hf-F bonds at the interface between the metal / fluorine-doped interface layer 92'' and the corresponding dielectric gate layer 98. The F-Si and Hf-F bonds form strong bonds at the interfaces and improve the reliability of the gate stack 102.

[0062] In some embodiments, some of the metal atoms within the metal / fluorine-doped interface layer 92'' diffuse into the corresponding dielectric gate layer 98 and the corresponding fin 52. In some embodiments, when the dielectric gate layer 98 is made of hafnium oxide (HfO2) and the metal atoms are lanthanum (La atoms), the ratio of lanthanum concentration (La concentration) to hafnium concentration (Hf concentration) in the dielectric gate layer 98 is between about 0.014 and about 0.4. In some embodiments, when the dielectric gate layer 98 is made of hafnium oxide (HfO2), the ratio of fluorine concentration (F concentration) to hafnium concentration (Hf concentration) in the dielectric gate layer 98 is between about 0.014 and about 0.4.

[0063] The formation of the dielectric gate layers 98 in region 50N and region 50P can occur simultaneously, so that the dielectric gate layers 98 in each region are formed from the same materials. In other embodiments, the dielectric gate layers 98 in each region can be formed by separate processes, so that the dielectric gate layers 98 in different regions can be formed from different materials. The formation of the conductive filler layers 100C in region 50N and region 50P can occur simultaneously, so that the conductive filler layers 100C in each region are formed from the same materials. In other embodiments, the conductive filler layers 100C in each region can be formed by separate processes, so that the conductive filler layers 100C in different regions can be formed from different materials.Different masking steps can be used to mask and reveal suitable areas when using custom processes.

[0064] In Fig. 22A and Fig. In 22B, after passing through the gate stacks 102, a second ILD 110 is deposited above the first ILD 88 and the gate stacks 102. In some embodiments, the second ILD 110 is formed using similar materials and methods as the first ILD 88, and the description is not repeated here. In some embodiments, the first ILD 88 and the second ILD 110 contain the same material. In other embodiments, the first ILD 88 and the second ILD 110 contain different materials.

[0065] In some embodiments, prior to the formation of the second ILD 110, the gate stacks 102 are recessed, creating depressions directly above the gate stacks 102 and between opposing sections of gate sealing spacers 80. Gate masks 108, comprising one or more layers of a dielectric material such as silicon nitride, silicon oxynitride, a combination thereof, or the like, are filled into the depressions, followed by a planarization process to remove excess sections of the dielectric material extending over the first ILD 88. The gate contacts 112 subsequently formed (see Fig. 23A and Fig. 23B) penetrate the corresponding gate mask 108 to come into contact with the top surface of the corresponding recessed gate electrode layer 100.

[0066] In Fig. 23A and Fig. In some embodiments, gate contacts 112 and source / drain contacts 114 are formed by the second ILD 110 and the first ILD 88. Openings for the source / drain contacts 114 are formed by the first ILD 88, the second ILD 110, and the CESL 87, and openings for the gate contacts 112 are formed by the second ILD 110 and the gate masks 108. The openings can be formed using acceptable photolithography and etching techniques. After the openings for the source / drain contacts 114 are formed, silicide layers 116 are formed through the openings for the source / drain contacts 114. In some embodiments, a metallic material is deposited in the openings for the source / drain contacts 114. The metallic material may contain Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, a combination thereof or the like, and may be formed using PVD, sputtering, a combination thereof or the like.Subsequently, an annealing process is carried out to form the silicide layers 116. In some embodiments, where the epitaxial source / drain regions 82 contain silicon, the annealing process causes the metallic material to react with silicon to form a silicide of the metallic material at interfaces between the metallic material and the epitaxial source / drain regions 82. After formation of the silicide layers 116, unreacted sections of the metallic material are removed using a suitable removal process, such as an etching process.

[0067] Subsequently, a lining, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings for the source / drain contacts 114 and in the openings for the gate contacts 112. The lining can contain titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like. The conductive material can contain copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, a combination thereof, or the like. A planarization process, such as a CMP process, can be performed to remove excess material from one surface of the second ILD 110. The remaining sections of the lining and the conductive material form the source / drain contacts 114 and the gate contacts 112 in the openings.The source / drain contacts 114 are electrically coupled to the corresponding epitaxial source / drain regions 82, and the gate contacts 112 are electrically coupled to the corresponding gate electrode layers 100. The source / drain contacts 114 and gate contacts 112 can be formed in different processes or in the same process. Although they are shown with the same cross-sections in the diagram, it should be clear that each of the source / drain contacts 114 and the gate contacts 112 can have different cross-sections, which can prevent short-circuiting of the contacts.

[0068] Fig. 24A and Fig. Figure 24B shows cross-sectional views of a FinFET device according to some embodiments. Fig. Figure 24A illustrates a cross-sectional view along the in Fig. 1 illustrated reference cross-section AA. Fig. 24B illustrates a cross-sectional view along the in Fig. 1 illustrated reference cross-section BB. In some embodiments, the in Fig. 24A and Fig. The FinFET device shown in Figure 24B is described in Figure 24B. Fig. 23A and Fig. The FinFET device shown in Figure 23B is similar, with identical structural elements designated by the same numerical reference symbols and descriptions of the identical structural elements not repeated here. In some embodiments, the Fig. 24A and Fig. The FinFET device shown in Figure 24B is formed using process steps that are described above with reference to Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 23A and Fig. The process steps described in 23B are similar and the description is not repeated here. In the Fig. 24A and Fig. In the embodiment illustrated in 24B, the interface layers 92'' are formed using an oxidation process such that the interface layers 92'' extend along surfaces of the fins 52 and do not extend along cover surfaces of the insulating areas 56 and side walls of the gate sealing spacers 80.

[0069] The disclosed FinFET embodiments could also be applied to a gate-all-around (GAA) device, such as nanostructured (e.g., nanosheet, nanowire, or the like) field-effect transistors (NSFETs). In one NSFET embodiment, the fins are replaced by nanostructures formed by structuring a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a similar manner to the embodiments described above. After removal of the dummy gate stacks, the sacrificial layers can be partially or completely removed in channel regions.The replacement gate structures are formed in a similar manner to the embodiments described above. These replacement gate structures can partially or completely fill openings left by the removal of the sacrificial layers and can partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source / drain regions can be formed in a similar manner to the embodiments described above. A nanostructured device can be formed as disclosed in U.S. Patent No. 9,647,071, which is cited herein for reference in its entirety. Such NSFET embodiments are shown below. Fig. 25A, Fig. 25B, Fig. 26A and Fig. 26B illustrates.

[0070] Fig. 25A and Fig. Figure 25B shows cross-sectional views of an NSFET device according to some embodiments. Fig. Figure 25A illustrates a cross-sectional view along the in Fig. 1 illustrated reference cross-section AA. Fig. 25B illustrates a cross-sectional view along the in Fig. 1 illustrated reference cross-section BB. The in Fig. 25A and Fig. The structure illustrated in 25B is the one shown in Fig. 23A and Fig. 23B illustrated a similar structure, where identical structural elements are designated with the same numerical reference symbols and descriptions of the same structural elements are not repeated here. Instead of the fins 52 (see Fig. 23A and Fig. 23B) indicates the in Fig. 25A and Fig. Figure 25B illustrates the structure of nanostructures 118 such that sections of the gate stack 102 are wound around the nanostructures 118. In some embodiments, the sections of the gate stack 102 wound around the nanostructures 118 are spaced from adjacent epitaxial source / drain regions 82 by spacers 120. In some embodiments, the nanostructures 118 can be formed using materials similar to the substrate 50, and the description is not repeated here. In some embodiments, the nanostructures 118 and the substrate 50 contain the same material. In other embodiments, the nanostructures 118 and the substrate 50 contain different materials. The spacers 120 can contain a material such as silicon nitride or silicon oxynitride, although any suitable material, such as materials with a low dielectric constant (low-k materials) with a k-value less than about 3.5, can be used.

[0071] Fig. 26A and Fig. Figure 26B shows cross-sectional views of an NSFET device according to some embodiments. Fig. 26A illustrates a cross-sectional view along the in Fig. 1 illustrated reference cross-section AA. Fig. 26B illustrates a cross-sectional view along the in Fig. 1 illustrated reference cross-section BB. The in Fig. 26A and Fig. The structure illustrated in 26B is the one shown in Fig. 24A and Fig. 24B illustrated a similar structure, where identical structural elements are designated with the same numerical reference symbols and descriptions of the same structural elements are not repeated here. Instead of the fins 52 (see Fig. 24A and Fig. 24B) indicates the in Fig. 26A and Fig.Figure 26B illustrates the structure of nanostructures 118 such that sections of the gate stack 102 are wound around the nanostructures 118. In some embodiments, the sections of the gate stack 102 wound around the nanostructures 118 are spaced from adjacent epitaxial source / drain regions 82 by spacers 120. In some embodiments, the nanostructures 118 can be formed using materials similar to the substrate 50, and the description is not repeated here. In some embodiments, the nanostructures 118 and the substrate 50 contain the same material. In other embodiments, the nanostructures 118 and the substrate 50 contain different materials. The spacers 120 can contain a material such as silicon nitride or silicon oxynitride, although any suitable material, such as materials with a low dielectric constant (low-k materials) with a k-value less than about 3.5, can be used.

[0072] Embodiments can offer advantages. Doping the interface layers with metal and fluorine atoms as described above improves (or reduces) the threshold voltage (Vt) of a semiconductor device, enhances the reliability of a gate stack, and reduces or eliminates the gate leakage current.

[0073] According to one embodiment, a method comprises forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along side walls and a top surface of the fin. The dummy gate is removed to form a depression. A replacement gate is formed in the depression. Forming the replacement gate comprises forming an interface layer along side walls and a bottom of the depression. A dipole layer is formed over the interface layer. The dipole layer contains metal atoms. Fluorine atoms are inserted into the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interface layer. The dipole layer is removed. In one embodiment, the dipole layer contains a metal oxide material. In another embodiment, inserting the fluorine atoms into the dipole layer comprises impregnating the dipole layer in a fluorine-containing chemical.In one embodiment, the fluorine-containing chemical contains WF6 or NF3. In one embodiment, driving the fluorine atoms and the metal atoms from the dipole layer into the interface layer includes performing a tempering process. In one embodiment, removing the dipole layer includes etching the dipole layer. In one embodiment, forming the dipole layer includes performing an atomic layer deposition (ALD) process.

[0074] According to another embodiment, a method comprises structuring a substrate to form a fin. A dummy gate is formed over the fin. The dummy gate extends along the sidewalls and a top surface of the fin. The dummy gate is etched to form a depression. A replacement gate is formed in the depression. Forming the replacement gate comprises depositing an interfacial layer along the sidewalls and a bottom surface of the depression. A dipole layer is deposited over the interfacial layer. The dipole layer contains metal atoms. A fluorine impregnation process is carried out on the dipole layer to form a doped dipole layer. The doped dipole layer contains fluorine atoms. An annealing process is carried out to drive the fluorine atoms and the metal atoms from the doped dipole layer into the interfacial layer, forming a doped interfacial layer.The doped dipole layer is etched to expose the doped interface layer. A dielectric gate layer is deposited over the doped interface layer. A gate electrode layer is deposited over the dielectric gate layer. In one embodiment, the dipole layer contains lanthanum oxide, yttrium oxide, zinc oxide, aluminum oxide, or gallium oxide. In one embodiment, the annealing process forces some of the fluorine atoms and some of the metal atoms to an interface between the doped interface layer and the fin. In one embodiment, the interface layer contains silicon oxide. In one embodiment, the fluorine impregnation process and the annealing process are performed two or more times. In one embodiment, performing the fluorine impregnation process on the dipole layer includes impregnating the dipole layer with WF6 or NF3.In one embodiment, the metal atoms are lanthanum atoms, yttrium atoms, zinc atoms, aluminum atoms or gallium atoms.

[0075] According to a further embodiment, a device comprises a fin extending from a substrate and an insulating structure above the substrate and adjacent to the fin. A top surface of the fin lies over a top surface of the insulating structure. The device further comprises a gate stack extending along the top surface and side walls of the fin and the top surface of the insulating structure. The gate stack includes an interface layer along the top surface and side walls of the fin and a dielectric gate layer above the interface layer. The interface layer contains a dielectric material doped with atoms of a first metallic element and fluorine atoms. An interface between the interface layer and the fin exhibits F-Si bonds. The dielectric gate layer contains atoms of a second metallic element.An interface between the interface layer and the dielectric gate layer exhibits bonds between some of the atoms of the second metallic element and some of the fluorine atoms. In one embodiment, the first metallic element is lanthanum, yttrium, zinc, aluminum, or gallium. In another embodiment, the dielectric material contains silicon oxide. In yet another embodiment, the first metallic element differs from the second metallic element. In yet another embodiment, the dielectric gate layer contains hafnium oxide (HfO₂), and the interface between the interface layer and the dielectric gate layer exhibits Hf-F bonds. In yet another embodiment, the dielectric gate layer is a metal / fluorine-doped layer.

Claims

[1] Procedure, encompassing: Forming a fin (52) extending from a substrate (50); Forming a dummy gate (72) over the fin (52), wherein the dummy gate (72) extends along side walls and a top surface of the fin (52); Removing the dummy gate (72) to form a recess (90); and Forming a replacement gate in the recess (90), wherein forming the replacement gate includes: Forming a boundary layer (92) along side walls and a bottom of the depression (90); Forming a dipole layer (94) above the interface layer (92), wherein the dipole layer (94) contains metal atoms; Insertion of fluorine atoms into the dipole layer (94); Driving the fluorine atoms and the metal atoms from the dipole layer (94) into the interface layer (92); and Removal of the dipole layer (94). [2] Method according to claim 1, wherein the dipole layer (94) contains a metal oxide material. [3] Method according to claim 1 or 2, wherein inserting the fluorine atoms into the dipole layer (94) comprises impregnating the dipole layer (94) with a fluorine-containing chemical. [4] Method according to claim 3, wherein the fluorine-containing chemical contains WF6 or NF3. [5] Method according to any of the preceding claims, wherein driving the fluorine atoms and the metal atoms from the dipole layer (94) into the interface layer (92) comprises carrying out a tempering process. [6] Method according to any of the preceding claims, wherein removing the dipole layer (94) comprises etching the dipole layer (94). [7] Method according to any of the preceding claims, wherein forming the dipole layer (94) comprises carrying out an atomic layer deposition (ALD) process. [8] Procedures, comprehensive: Structuring a substrate (50) to form a fin (52); Forming a dummy gate (72) over the fin (52), wherein the dummy gate (72) extends along side walls and a top surface of the fin (52); Etching the dummy gate (72) to form a depression (90); and Forming a replacement gate in the recess (90), wherein forming the replacement gate includes: Deposition of an interface layer (92) along side walls and bottom of the depression (90); Deposition of a dipole layer (94) over the interface layer (92), wherein the dipole layer (94) contains metal atoms; Performing a fluorine impregnation process on the dipole layer (94) to form a doped dipole layer (94') wherein the doped dipole layer (94') contains fluorine atoms; Performing a tempering process to drive the fluorine atoms and the metal atoms from the doped dipole layer (94') into the interface layer (92) and to form a doped interface layer (92''); Etching of the doped dipole layer (94') to expose the doped interface layer (92'); Deposition of a dielectric gate layer (98) over the doped interface layer (92''); and Deposition of a gate electrode layer (100) over the dielectric gate layer (98). [9] Method according to claim 8, wherein the dipole layer (94) contains lanthanum oxide, yttrium oxide, zinc oxide, aluminium oxide or gallium oxide. [10] Method according to claim 8 or 9, wherein the annealing process drives some of the fluorine atoms and some of the metal atoms to an interface between the doped interfacial layer (92'') and the fin (52). [11] Method according to any one of claims 8 to 10 above, wherein the interface layer (92'') contains silicon oxide. [12] Method according to any one of claims 8 to 11 above, wherein the fluorine impregnation process and the tempering process are carried out two or more times. [13] Method according to any one of the preceding claims 8 to 12, wherein carrying out the fluorine impregnation process on the dipole layer (94) comprises impregnating the dipole layer (94) with WF6 or NF3. [14] Method according to any one of the preceding claims 8 to 13, wherein the metal atoms are lanthanum atoms, yttrium atoms, zinc atoms, aluminium atoms or gallium atoms. [15] Device comprising: a fin (52) extending from a substrate (50); an insulating structure (56) above the substrate (50) and next to the fin (52), wherein a covering surface of the fin (52) lies above a covering surface of the insulating structure (56); and a gate stack (102) extending along the deck surface and side walls of the fin (52) and the deck surface of the insulation structure (56), wherein the gate stack (102) comprises: an interface layer (92'') along the top surface and the side walls of the fin (52), wherein the interface layer (92'') contains a dielectric material doped with atoms of a first metallic element and fluorine atoms, wherein an interface between the interface layer (92'') and the fin (52) contains F-Si bonds; and a dielectric gate layer (98) above the interface layer (92''), wherein the dielectric gate layer (98) contains atoms of a second metallic element, wherein an interface between the interface layer (92'') and the dielectric gate layer (98) has bonds between some of the atoms of the second metallic element and some of the fluorine atoms. [16] Device according to claim 15, wherein the first metallic element is lanthanum, yttrium, zinc, aluminium or gallium. [17] Device according to claim 15 or 16, wherein the dielectric material contains silicon oxide. [18] Device according to any one of the preceding claims 15 to 17, wherein the first metallic element differs from the second metallic element. [19] Device according to any one of the preceding claims 15 to 18, wherein the dielectric gate layer (98) contains hafnium oxide (HfO2) and wherein the interface between the interface layer (92'') and the dielectric gate layer (98) has Hf-F bonds. [20] Device according to any one of the preceding claims 15 to 19, wherein the dielectric gate layer (98) is a metal / fluorine-doped layer.

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