Multiplex series-stacked phase DC / DC converters

Abstract

Power converter circuit (100), comprising: a first buck converter (109) having a first switch (102) with a first gate terminal, a first drain terminal and a first source terminal, and a second switch (104) with a second gate terminal, a second drain terminal and a second source terminal, wherein the first source terminal is coupled to the second drain terminal at a first switching node (103); a second buck converter (111) having a third switch (106) having a third gate terminal, a third drain terminal and a third source terminal and a fourth switch (108) having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, wherein the third source terminal is coupled to the fourth source terminal at a second switching node (117), wherein the second buck converter (111) is coupled in series to the first buck converter (109) at a junction (107) such that the third drain terminal is coupled to the second source terminal; an input terminal (110) coupled to the first drain terminal; an output terminal (118) coupled to the first (103) and second (117) switching nodes; and a control circuit (158) coupled to both the first (109) and the second (111) down converter, the control circuit (158) being arranged to: detecting a voltage at the connection point (107); comparing the detected voltage with a first threshold voltage, and in response to the detected voltage having a lower voltage than the first threshold voltage, the control circuit (158) operates the first buck converter (109) and deactivates the second buck converter; and comparing the detected voltage with a second threshold voltage, and in response to the detected voltage having a higher voltage than the second threshold voltage, the control circuit (158) operates the second buck converter (111) and deactivates the first buck converter (109).

Description

AREA

[0001] The described embodiments relate generally to power converters, and more particularly, the present embodiments relate to multiplexed series stack phase DC / DC power converter circuits. GENERAL STATE OF THE ART

[0002] A wide variety of electronic devices are available to consumers today. Many of these devices have integrated circuits powered by regulated low-voltage DC power sources. These low-voltage power sources are often generated by dedicated power converter circuits that use a higher input voltage from a battery or other power source. In some applications, the dedicated power converter circuit can be one of the most power-dissipating components of the electronic device and can sometimes occupy more space than the integrated circuit that supplies it with power. As electronic devices become more sophisticated and compact, more efficient power converter circuits are needed.

[0003] CN 1 05 703 621 A discloses a three-stage ISOP (Input-Series-Output-Parallel) buck converter and a method for controlling neutral point potential equalization. The combined converter consists of non-isolated DC / DC converters. Furthermore, the input voltage unbalance problem of the existing ISOP combination converter can cause damage to modules with high voltages. Therefore, a specific neutral point potential equalization control strategy must be applied to balance the input voltages of the combined ISOP converter.

[0004] CN 1 05 406 709 A discloses a three-stage nested two-input boost converter and a control strategy. The boost converter topology comprises a first unit, a second unit, a third unit, a resistor, a first low-frequency switch, a second low-frequency switch, a third low-frequency switch, a first input source, and a second input source; the first unit comprises a first inductor, a first switching tube, a first diode, and a second capacitor; the second unit comprises a second inductor, a second switching tube, a third diode, and a third capacitor; the third unit comprises a first capacitor and a second diode.The working mode of the converter circuit includes a time-sharing power supply mode and a simultaneous power supply mode. The time-sharing power supply mode includes independent operation of the first input source and independent operation of the second input source. In the time-sharing power supply mode, its control strategy includes a dual voltage and current 2 control loop and a capacitor voltage balancing control loop; in the simultaneous power supply mode, its control strategy includes dual voltage and current 1 control loop and dual voltage and current 2 control loop.

[0005] DE 10 2019 002 880 A1 discloses reducing switching losses at a lower load current while maintaining the switching frequency for a hybrid switched capacitor converter circuit. A control and / or regulating circuit is coupled to the hybrid switched capacitor converter circuit and configured to measure a load current at an output of the hybrid switched capacitor converter circuit in a buck phase mode. The disclosed control and / or regulating circuit is configured to compare the measured load current to a set of predetermined thresholds. The disclosed control and / or regulating circuit is configured to drive and / or apply a first voltage to the second set of transistors, which periodically turns on the second set of transistors to regulate the output and / or the output during the buck phase mode.The disclosed control and / or regulation circuit is also configured to drive and / or apply a second voltage to the first set of transistors that turns off the first set of transistors for one or more switching cycles while turning on the second set of transistors based on the comparison. SUMMARY

[0006] In some embodiments, a power converter circuit is disclosed. The power converter circuit includes a first buck converter having a first switch with a first gate terminal, a first drain terminal, and a first source terminal, and a second switch with a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal coupled to the second drain terminal at a first switch node;a second buck converter having a third switch with a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch with a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switching node, the second buck converter being coupled in series to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal; an input terminal coupled to the first drain terminal; an output terminal coupled to the first and second switching nodes; and a control circuit coupled to each of the first and second buck converters, the control circuit being arranged to: detect a voltage at the junction;Comparing the detected voltage to a first threshold voltage, and in response to the detected voltage having a lower voltage than the first threshold voltage, the control circuit operates the first buck converter and disables the second buck converter; and Comparing the detected voltage to a second threshold voltage, and in response to the detected voltage having a higher voltage than the second threshold voltage, the control circuit operates the second buck converter and disables the first buck converter.;

[0007] In some embodiments, the first and second buck converters are arranged to generate an output voltage at the output terminal that is lower than an input voltage at the input terminal.

[0008] In some embodiments, the first and second buck converters are arranged to control power transfer from the input terminal to the output terminal.

[0009] In some embodiments, the control circuit includes a window comparator including a first comparator and a second comparator.

[0010] In some embodiments, the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

[0011] In some embodiments, the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

[0012] In some embodiments, the output terminal is coupled to the first switching node through a first inductor.

[0013] In some embodiments, the output terminal is coupled to the second switching node through a second inductor.

[0014] In some embodiments, the first inductor is coupled to the first switching node via a first capacitor.

[0015] In some embodiments, a second capacitor is coupled to the junction at its first terminal and to ground at its second terminal.

[0016] In some embodiments, a method of operating a power converter circuit is disclosed. The method includes providing a first buck converter having a first switch with a first gate terminal, a first drain terminal, and a first source terminal, and a second switch with a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal coupled to the second drain terminal at a first switch node;Providing a second buck converter having a third switch with a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch with a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal coupled to the fourth drain terminal at a second switching node, the second buck converter being coupled in series to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal; providing an input terminal coupled to the first drain terminal; providing an output terminal coupled to the first and second switching nodes; and providing a control circuit coupled to each of the first and second buck converters; sensing a voltage at the junction by the control circuit;Comparing the sensed voltage by the control circuit to a first threshold voltage; operating the first buck converter by the control circuit and disabling the second buck converter in response to the sensed voltage having a lower voltage than the first threshold voltage; comparing the sensed voltage by the control circuit to a second threshold voltage; and operating the second buck converter by the control circuit and disabling the first buck converter in response to the sensed voltage having a higher voltage than the second threshold voltage.

[0017] In some embodiments, the method further includes generating an output voltage at the output terminal by the first and second buck converters that is lower than an input voltage at the input terminal.

[0018] In some embodiments, the method further includes controlling power transfer through the first and second buck converters from the input terminal to the output terminal.

[0019] In some embodiments, a circuit is disclosed. The circuit includes a first buck converter having a first switching node; a second buck converter having a second switching node coupled in series with the first buck converter at a junction; an input terminal coupled to the first buck converter; an output terminal coupled to the first and second switching nodes; and a control circuit coupled to each of the first and second buck converters, the control circuit being arranged to: detect a voltage at the junction; compare the detected voltage to a first threshold voltage, and in response to the detected voltage having a lower voltage than the first threshold voltage, the control circuit operating the first buck converter and disabling the second buck converter;and comparing the detected voltage with a second threshold voltage, and in response to the detected voltage having a higher voltage than the second threshold voltage, the control circuit operates the second buck converter and deactivates the first buck converter; BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a multiplexed series-stack phase DC / DC power converter circuit according to an embodiment of the disclosure; and Fig. Figure 2 illustrates a switching sequence and timing diagram for the DC / DC power converter circuit of Fig. 1 according to an embodiment of the disclosure DETAILED DESCRIPTION

[0020] Circuits and related techniques disclosed herein generally relate to power converters. More specifically, circuits, devices, and related techniques disclosed herein relate to multiplexed series-stack phase DC / DC power converters. In some embodiments, the multiplexed series-stack phase DC / DC power converter may include an upper phase buck converter and a lower phase buck converter. Under light load conditions, or when the power converter operates with a relatively high voltage at its input and there is a relatively low rated output current and a fixed switching frequency, such as in battery-powered IoT applications, the upper phase and lower phase may be alternately turned on and off so that only one phase is running at a time. Further, a voltage at a node where the upper phase is connected to the lower phase may be sensed and regulated.This can lead to a significant reduction of voltage fluctuations at the output voltage of the power converter, since the voltage fluctuations at the output terminal can be shifted to an internal node of the power converter.

[0021] Embodiments of the disclosure may enable the multiplexed series-stack phase DC / DC power converter to operate in burst mode while significantly reducing output voltage ripple by shifting the output voltage ripple to an internal node of the power converter. Further, the disclosed multiplexed series-stack phase DC / DC power converter may exhibit an improved electromagnetic interference (EMI) spectrum while operating in burst mode. Furthermore, embodiments of the disclosure may enable a reduction of inductor losses at low rated loads. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.

[0022] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form a part hereof. The following description provides only one or more embodiments and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the following description of the one or more embodiments will provide those skilled in the art with a description enabling them to implement one or more embodiments. It should be understood that various changes in the function and arrangement of elements may be made without departing from the spirit and scope of this disclosure. In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. It will be apparent, however, that various embodiments may be practiced without these specific details.The figures and description are not intended to be limiting. The word "example" or "exemplary" is used herein to mean "serving as an example or illustration." Any embodiment or configuration described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments or configurations.

[0023] Current approaches to series-stack DC / DC power converters can have relatively low efficiency in systems operating with a relatively high input voltage (V IN), have a relatively low rated output current, and also have a fixed switching frequency, such as systems used in battery-powered IoT applications. With current approaches, the equivalent series resistance (ESR) of the inductor can increase significantly due to the relatively large AC ripple current that can flow in the high-impedance outer skin of the inductor compared to the DC current. Furthermore, current approaches can exhibit an undesirable electromagnetic interference (EMI) spectrum when the power converter operates in a burst mode.

[0024] Fig. 1 illustrates a multiplexed series-stack phase DC / DC power converter circuit 100 according to an embodiment of the disclosure. As shown in Fig. 1, the multiplexed series-stack phase DC / DC power converter circuit 100 may include an upper phase 109 (buck converter stage) and a lower phase 111 (step-down converter stage). In the illustrated embodiment, the upper phase 109 and lower phase 111 step-down converter stages may be arranged in a series-stack configuration. The upper phase 109 may be connected to a node 107 having a voltage V M connected to the lower phase 111. The upper phase buck converter stage 109 may include a first switch 102 and a second switch 104 connected in series. The lower phase buck converter stage 111 may include a third switch 106 and a fourth switch 108 connected in series.

[0025] The multiplexed series-stack phase DC / DC power converter circuit 100 may include a flying capacitor 112 coupled to a node 103. The node 107 may be connected to a capacitor 115. The multiplexed series-stack phase DC / DC power converter circuit 100 may have an input terminal 110 having a voltage V in and may be coupled to ground 120. The multiplexed series stack phase DC / DC power converter circuit 100 may have an output voltage V OUT at an output terminal 118. The output terminal 118 may be coupled to a load capacitor 131 and a load 135. The output voltage V OUT may be lower than an input voltage V at the input terminal 110 inThe multiplexed series-stack phase DC / DC power converter circuit 100 may include a first inductor 114 connected between the flying capacitor 112 and the output terminal 118. The circuit 100 may also include a second inductor 116 connected between a node 117 and the output terminal 118.

[0026] The multiplexed series-stack phase DC / DC power converter circuit 100 may also include a first clock generator 142 that generates a first clock φ1 146, and a second clock generator 144 that generates a second clock φ2 148. The logic and control circuit 158 ​​may be arranged to generate control signals for controlling the upper phase buck converter stages 109 and the lower phase buck converter stages 111. In some embodiments, the upper phase buck converter stages 109 and the lower phase buck converter stages 111 may be alternatively turned on and off by the logic and control circuit 158. In various embodiments, the control circuit 158 ​​is arranged to operate the upper phase buck converter 109 and deactivate the lower phase buck converter 111. In one embodiment, the logic and control circuit 158 ​​may include a window comparator 128 and a Set-Reset (S / R) latch 141.The window comparator 128 can measure the voltage at node 107 (V. M ) with a preset threshold and measure the voltage at node 107 (V M ) within a preset window, for example, within 100 mV of an ideal value for V M . As one of ordinary skill in the art having knowledge of this disclosure will appreciate, the value of the preset window may be set to any suitable value. In some embodiments, an ideal value for V M Vin / 2.

[0027] The window comparator 128 may include a first comparator 151 and a second comparator 153. The outputs of the first comparator 151 and the second comparator 153 may be coupled to a set / reset latch (S / R latch) 141 and may toggle the S / R latch 141 and alternatively enable operation of either the upper phase 109 or the lower phase 111. The first input of the first comparator 151 may be connected to the node 107. The second input 124 of the first comparator 151 may be connected to a first reference voltage set to a preset threshold, for example, a value equal to an ideal value of V Mplus 100 mV. The first input of the second comparator 153 may be connected to the node 107. The second input 126 of the first comparator 153 may be connected to a second reference voltage set to a preset threshold, for example, a value equal to an ideal value of V M minus 100 mV. In this way, node 107 can, for example, be within a preset window of ±100 mV of the ideal value of V M If the node 107 rises above the preset threshold, for example, above 100 mV, the lower phase 111 goes into operation until the voltage V M at node 107 falls below the preset threshold, for example below 100 mV, at which time the upper phase 109 comes into operation.

[0028] The S / R latch 141 may generate a signal HiZ at its output node 130. The signal HiZ may enable / disable the operation of the upper phase 109. The inverse of the signal HiZ may be generated by an inverter 159. The inverse of the signal HiZ at node 136 may enable / disable the operation of the lower phase 111. The first clock 146 may be applied to the gate of the first switch 102 via a first OR gate 132, and the inverse of the first clock 146 may be applied to the gate of the second switch 104 via a first AND gate 134. The second clock 148 may be applied to the gate of the third switch 106 via a second OR gate 138, and the inverse of the second clock 148 may be applied to the gate of the fourth switch 108 via a second AND gate 140.Although a specific control circuit and algorithm have been discussed above, one of ordinary skill in the art having knowledge of this disclosure will recognize that other control circuit architectures and control algorithms may be used for the multiplexed series stack phase DC / DC power converter circuit 100 and are within the scope of this disclosure.

[0029] Now, with simultaneous reference to Fig. 1 and Fig. 2 illustrates one embodiment of a switching sequence and timing diagrams for circuit 100. Fig. Figure 2 illustrates waveforms for the signal at the gate of the second switch 104 (inverse ϕ 1Gate ), the signal at the gate of the fourth switch 108 (inverse ϕ 2Gate ), the preset threshold window for the (V M) node 107 (Vin / 2 ±100 mV), the signal HiZ at node 130 and the output voltage at output terminal 118. During a first period, referred to in diagram 208 as the “upper phase switching period”, the signal HiZ is high, therefore the upper phase 109 can operate for several cycles, as shown in diagram 202, where inverse ϕ 1Gate switches while the lower phase 111 is switched off, as shown in diagram 204, where inverse ϕ 2Gate is switched off. During the “high-phase switching period” the voltage rises at (V M ) node 107 until it reaches, for example, 100 mV above Vin / 2, as shown in diagram 206. Then, window comparator 128 switches S / N latch 141. This causes the "high-phase switching period" to end and a "low-phase switching period" to begin.

[0030] During a second period, referred to in diagram 208 as the “low-phase switching period,” the signal HiZ is low, allowing the lower phase 111 to operate for several cycles, where inversely ϕ 2Gate switches while the upper phase 109 is switched off, where inverse ϕ 1Gate is switched off. During the “underphase switching period” the voltage at (V M ) node 107 until it reaches, for example, 100 mV below Vin / 2. Then, the window comparator 128 switches the S / R latch 141. This causes the "low-phase switching period" to end and a new "high-phase switching period" to begin. As one of ordinary skill in the art, aware of this disclosure, will recognize that an acceptable level of voltage swings at (V M ) node 107 based on the power converter specifications. The voltage fluctuations at the (V M) node 107 can set the number of switching cycles that can be performed consecutively for each of the phases. Diagram 210 shows the voltage at the output terminal 118 (V OUT ). As can be seen in diagram 210, V OUT a relatively small ripple compared to the ripple at node 107 (V M ). For example, a value of the ripple at V OUT less than a few mV. The ripple at the output terminal 118 has a frequency equal to the switching frequency of the DC / DC power converter, in contrast to current approaches where the output voltage ripple may have a frequency equal to the burst mode operating frequency.

[0031] The rate of change of voltage V Mat node 107 can be adjusted by capacitor 115, the size of flying capacitor 112, and a current through inductor 114. In various embodiments, a value of the capacitance of capacitor 115 at node 107 can be increased independently of other operating parameters of the power converter. As one of ordinary skill in the art having knowledge of this disclosure will appreciate, other feedback loops based on voltages and / or currents at other nodes within multiplexed series-stack phase DC / DC power converter circuit 100 can be used for phase multiplexing. Furthermore, open-loop operations can be used to achieve phase multiplexing in series-stack DC / DC converters.Those of ordinary skill in the art will understand that there may be alternative methods for controlling the switches in circuit 100 to phase-multiplex the switches to achieve total loop control, and such methods are within the scope of this disclosure. Those of ordinary skill in the art will further understand that alternative methods for controlling the switches in circuit 100 may be used to optimize light load efficiency or to minimize area and / or electromagnetic interference (EMI), and such methods are within the scope of this disclosure.

[0032] Although multiplexed series-stack phase DC / DC power converter circuits are described and illustrated herein with respect to a particular configuration of multiplexed series-stack phase DC / DC power converter circuits, embodiments of the disclosure may be suitable for use with other configurations of DC / DC power converters.

[0033] In some embodiments, the described switches may be formed from silicon or any other suitable semiconductor material. In various embodiments, the described switches may be transistors. In some embodiments, the described switches may be metal-oxide-semiconductor field-effect transistors (MOSFETs). In various embodiments, the disclosed MOSFETs may all be formed within a single die cavity. In some embodiments, the disclosed multiplexed series-stack phase DC / DC power converter circuits (including the transistors and control circuitry) may be monolithically integrated on a single die. In various embodiments, upper phase and lower phase stages may be formed on separate individual die.In some embodiments, the upper phase, the lower phase, and the logic and control circuits, as well as any combination thereof, may be formed in groups on separate chips. For example, the upper phase and the lower phase may be formed on a single chip and the logic and control circuits may be formed on a separate chip, or the upper phase and the lower phase may be formed on the same chip as the logic and control circuits. In various embodiments, the upper phase, the lower phase, and the logic and control circuits may all be integrated into an electronic package, for example, but not limited to, a quad flat no-lead (QFN) package, a dual flat no-lead (DFN) package, or a ball grid array (BGA) package. In some embodiments, the upper phase and the lower phase may be individually packaged into an electronic package.In various embodiments, control circuits and / or control logic circuits may be integrated into a single chip along with the disclosed multiplexed series stack phase DC / DC converter.

[0034] In the foregoing description, embodiments of the disclosure have been described with reference to numerous specific details that may vary from implementation to implementation. The specification and drawings are accordingly to be considered illustrative rather than restrictive. The sole and exclusive indicator of the scope of the disclosure, and what applicants intend as the scope of the disclosure, is the literal and equivalent scope of the set of claims arising from this application, in the specific form in which those claims arise, including any later correction. The specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of the disclosure.

[0035] In addition, spatially relative terms such as "bottom" or "top," and the like, may be used to describe the relationship of one element and / or feature to another element(s) and / or feature(s) illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass various orientations of the device in use and / or operation, in addition to the orientation illustrated in the figures. For example, if the device is turned over in the figures, elements described as being "bottom" may then be oriented "above" other elements or features. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0036] The terms "and," "or," and "and / or," as used herein, may encompass a variety of meanings, and are also expected to depend, at least in part, on the context in which these terms are used. Typically, "or," when used to describe a list such as A, B, or C, is intended to mean A, B, and C, used herein inclusively, as well as A, B, or C, used herein exclusive. In addition, the term "one or more," as used herein, may be used to describe any feature, structure, or property in the singular, or may be used to describe a combination of features, structures, or properties. It should be noted, however, that this is merely an illustrative example, and the claimed subject matter is not limited to this example.Furthermore, the term “at least one of,” when used to describe a list such as A, B, or C, can be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0037] References throughout this specification to "a single example," "an example," "certain examples," or "exemplary implementation" mean that a particular feature, structure, or characteristic described in connection with the feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the phrases "in a single example," "an example," "in certain examples," "in certain implementations," or other similar phrases in various places throughout this specification do not necessarily all refer to the same feature, example, and / or limitation. Furthermore, the particular features, structures, or characteristics may be combined in one or more examples and / or features.

[0038] In the foregoing detailed description, numerous specific details have been set forth in order to provide a thorough understanding of the claimed subject matter. However, one skilled in the art will understand that the claimed subject matter may be practiced without these specific details. In other instances, methods and apparatus that would be known to one of ordinary skill in the art have not been described in detail in order not to obscure the claimed subject matter. Therefore, it is not intended that the claimed subject matter be limited to the particular examples disclosed; rather, such claimed subject matter may include all aspects falling within the scope of the appended claims and their equivalents.

Claims

[1] Power converter circuit (100), comprising: a first buck converter (109) having a first switch (102) with a first gate terminal, a first drain terminal and a first source terminal, and a second switch (104) with a second gate terminal, a second drain terminal and a second source terminal, wherein the first source terminal is coupled to the second drain terminal at a first switching node (103); a second buck converter (111) having a third switch (106) having a third gate terminal, a third drain terminal and a third source terminal and a fourth switch (108) having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, wherein the third source terminal is coupled to the fourth source terminal at a second switching node (117), wherein the second buck converter (111) is coupled in series to the first buck converter (109) at a junction (107) such that the third drain terminal is coupled to the second source terminal; an input terminal (110) coupled to the first drain terminal; an output terminal (118) coupled to the first (103) and second (117) switching nodes; and a control circuit (158) coupled to both the first (109) and the second (111) down converter, the control circuit (158) being arranged to: detecting a voltage at the connection point (107); comparing the detected voltage with a first threshold voltage, and in response to the detected voltage having a lower voltage than the first threshold voltage, the control circuit (158) operates the first buck converter (109) and deactivates the second buck converter; and comparing the detected voltage with a second threshold voltage, and in response to the detected voltage having a higher voltage than the second threshold voltage, the control circuit (158) operates the second buck converter (111) and deactivates the first buck converter (109). [2] The power converter circuit of claim 1, wherein the first (109) and second (111) step-down converter circuits are arranged to generate an output voltage at the output terminal (118) that is lower than an input voltage at the input terminal (110). [3] The power converter circuit of claim 1, wherein the first (109) and second (111) buck converters are arranged to control power transfer from the input terminal (110) to the output terminal (118). [4] The power converter circuit of claim 1, wherein the control circuit (158) comprises a window comparator (128) including a first comparator (151) and a second comparator (153). [5] The power converter circuit of claim 4, wherein the first comparator (151) is arranged to receive the voltage at the junction (107) and to receive the first threshold voltage. [6] The power converter circuit of claim 5, wherein the second comparator (153) is arranged to receive the voltage at the junction (107) and to receive the second threshold voltage. [7] The power converter circuit of claim 5, wherein the output terminal (118) is coupled to the first switching node (103) via a first inductor (114). [8] The power converter circuit of claim 5, wherein the output terminal (118) is coupled to the second switching node (117) via a second inductor (116). [9] The power converter circuit of claim 7, wherein the first inductor (114) is coupled to the first switching node (103) via a first capacitor (112). [10] The power converter circuit of claim 9, wherein a second capacitor (115) is coupled at its first terminal to the junction (107) and at its second terminal to ground. [11] A method of operating a power converter circuit (100), the method comprising: Providing a first buck converter (109) having a first switch (102) having a first gate terminal, a first drain terminal and a first source terminal, and a second switch (104) having a second gate terminal, a second drain terminal and a second source terminal, wherein the first source terminal is coupled to the second drain terminal at a first switching node (103); Providing a second buck converter (111) having a third switch (106) having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch (108) having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switching node (117), the second buck converter (111) being coupled in series to the first buck converter (109) at a junction (107) such that the third drain terminal is coupled to the second source terminal; Providing an input terminal (110) coupled to the first drain terminal; Providing an output terminal (118) coupled to the first (103) and second (117) switching nodes; and Providing a control circuit (158) coupled to each of the first (109) and second (110) buck converters; Detecting a voltage at the connection point (107) by the control circuit (158); Comparing the detected voltage with a first threshold voltage by the control circuit (158); Operating the first buck converter (109) by the control circuit (158) and deactivating the second buck converter (111) in response to the detected voltage having a lower voltage than the first threshold voltage; Comparing the detected voltage with a second threshold voltage by the control circuit (158); and Operating the second buck converter (111) by the control circuit (158) and deactivating the first buck converter (109) in response to the detected voltage having a voltage higher than the second threshold voltage. [12] The method of claim 11, further comprising generating an output voltage at the output terminal (118) by the first (109) and second (111) buck converters that is lower than an input voltage at the input terminal (110). [13] The method of claim 11, further comprising controlling the power transfer through the first (109) and second (111) buck converters from the input terminal (110) to the output terminal (118). [14] The method of claim 11, wherein the control circuit (158) comprises a window comparator (128) including a first comparator (151) and a second comparator (153). [15] The method of claim 14, wherein the first comparator (151) is arranged to receive the voltage at the junction (107) and to receive the first threshold voltage. [16] The method of claim 15, wherein the second comparator (153) is arranged to receive the voltage at the junction (107) and to receive the second threshold voltage. [17] Circuit comprising: a first buck converter (109) having a first switching node (103); a second buck converter (111) having a second switching node (117) and coupled in series to the first buck converter (109) at a junction (107); an input terminal (110) coupled to the first buck converter (109); an output terminal (118) coupled to the first (103) and second (117) switching nodes; and a control circuit (158) coupled to both the first (109) and the second (111) down converter, the control circuit (158) being arranged to: detecting a voltage at the connection point (107); comparing the detected voltage with a first threshold voltage and, in response to the detected voltage having a lower voltage than the first threshold voltage, the control circuit (158) operates the first buck converter (109) and deactivates the second buck converter (111); and comparing the detected voltage with a second threshold voltage and in response to the detected voltage having a higher voltage than the second threshold voltage, the control circuit (158) operates the second buck converter (111) and deactivates the first buck converter (109). [18] The circuit of claim 17, wherein the first (109) and second (111) buck converter circuits are arranged to generate an output voltage at the output terminal (118) that is lower than an input voltage at the input terminal (110). [19] The circuit of claim 17, wherein the first (109) and second (111) buck converters are arranged to control the power transfer from the input terminal (110) to the output terminal (118). [20] The circuit of claim 17, wherein the control circuit (158) comprises a window comparator (128) including a first comparator (151) and a second comparator (153).

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