Device with a comparator and use of the device
A comparator device architecture addresses inefficiencies in analog/digital converters by using output signals from higher-order bits to influence lower-order bit comparisons, improving conversion accuracy and efficiency across multiple stages.
Patent Information
- Application Number
- DE102022202425
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-03-10
- Publication Date
- 2025-10-16
- Estimated Expiration
- 2042-03-10
AI Technical Summary
Existing analog/digital converter devices face challenges in efficiently handling multiple stages of bit significance, particularly in accurately determining the state changes of least significant bits (LSBs) based on the state of most significant bits (MSBs), leading to inefficiencies in current comparisons.
The implementation of a comparator device architecture that includes multiple stages, each with a reference and comparison current supply, where later stages utilize output signals from previous stages to influence and refine current comparisons, allowing for a cascaded approach that accounts for state changes across bit significance levels.
This architecture enables precise and efficient conversion of analog signals to digital outputs by considering the state of higher-order bits to adjust lower-order bit comparisons, enhancing the accuracy and efficiency of analog/digital conversion processes.
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
State of the art
[0001] The disclosure relates to a device with a comparator device.
[0002] The disclosure further relates to a use of the device.
[0003] Hardware computing structures are known from US 6 150 967 A and DE 10 2021 208 010 A1. Disclosure of the invention
[0004] Exemplary embodiments relate to a device comprising a first comparator device, wherein the first comparator device comprises a first reference current providing device for providing a first reference current and a first comparison current providing device for providing a first comparison current, and wherein the first comparator device is designed to compare the first reference current with the first comparison current in order to obtain a first comparison result and, based on the first comparison result, to output a first output signal characterizing the first comparison result, wherein it is provided that the device comprises at least one second comparator device,wherein the second comparator device comprises a second reference current providing device for providing a second reference current and a second comparison current providing device for providing a second comparison current, and wherein the second comparator device is designed to compare the second reference current with the second comparison current in order to obtain a second comparison result and, based on the second comparison result, to output a second output signal characterizing the second comparison result, and wherein it is provided that the second comparator device is designed to provide a current associated with the first comparator device based on the first output signal and to include the current associated with the first comparator device in the comparison,For example, the second comparator device comprises a current source controllable based on the first output signal to provide the current associated with the first comparator device. This allows, for example, when providing an analog-to-digital converter device, a state change, e.g., of the MSB, to be taken into account, e.g., by influencing a current comparison of the LSB stage based on the current associated with the first comparator device.
[0005] In further exemplary embodiments, this enables, for example, the provision of a, for example, two-stage, analog / digital converter device, wherein a first stage, for example corresponding to a most significant bit (MSB), can be realized, for example, by means of the first comparator device, and wherein a second stage, for example corresponding to a least significant bit (LSB), can be realized, for example, by means of the second comparator device.
[0006] In further exemplary embodiments, it is provided that the second comparator device is designed to receive the first output signal and to form the second comparison result based on the second reference current and the second comparison current and the first output signal.
[0007] In further exemplary embodiments, it is provided that the second comparator device is designed to form a sum of the second comparison current and the current associated with the first comparator device and to subtract the second reference current from the sum.
[0008] In further exemplary embodiments, it is provided that the second comparator device is designed to supply the second comparison current and the current associated with the first comparator device to a circuit node associated with the second comparator device and to discharge the second reference current from the circuit node associated with the second comparator device. In further exemplary embodiments, for example, an electrical potential of the circuit node associated with the second comparator device can be used as the second output signal. In further exemplary embodiments, this applies in a comparable manner, for example, also to the first comparator device or, in the case of several (e.g. more than two) comparator devices, to the several existing comparator devices.
[0009] In further exemplary embodiments, it is provided that the device has n many, n = 1, 2, 3, ..., comparator devices (e.g. also containing the first and / or second comparator device already mentioned above by way of example), wherein the n-th comparator device has an n-th reference current providing device for providing an n-th reference current and an n-th comparison current providing device for providing an n-th comparison current, and wherein the n-th comparator device is designed to compare the n-th reference current with the n-th comparison current in order to obtain an n-th comparison result and, based on the n-th comparison result, to output an n-th output signal characterizing the n-th comparison result. In other words, in further exemplary embodiments, several orall comparator devices of the device have an at least partially identical or comparable structure, for example with regard to the respective reference current supply device and / or the respective comparison current supply device.
[0010] In this case, in first alternative embodiments, it is further provided that a k-th comparator device, k=2, .., n, of the n plurality of comparators is designed to receive respective output signals of each i-th comparator device, i=k-1, k-2, ..., 1, and to form the k-th comparison result based on the k-th reference current and the k-th comparison current and the respective output signals of each i-th comparator device. As a result, in further exemplary embodiments, comparisons of some stages or comparator devices can be carried out based on the state or output signal of some other stages or comparator devices, for example, in applications in the field of analog / digital converter devices according to further exemplary embodiments, based on the state or output signal of those stages of the analog / digital converter device that correspond to the k-th stage, e.g.in a sequence of values from MSB to LSB (thus affecting the higher-order levels than the k-th level).
[0011] In second alternative embodiments, it is alternatively provided that at least one n-th comparator device has a series circuit comprising a first transistor and a second transistor, wherein the first transistor forms at least part of the n-th reference current providing device, and wherein the second transistor forms at least part of the n-th comparison current providing device, and that the series circuit is assigned a compensation device for compensating a voltage drop, for example, at the first transistor, wherein, for example, the compensation device is connected in series to the series circuit
[0012] In further exemplary embodiments, it is provided that a k-th comparator device, k=2, .., n, of the n plurality of comparators is configured to receive at least one output signal from a (k-1)-th comparator device and to form the k-th comparison result based on the k-th reference current and the k-th comparison current and the at least one output signal of the (k-1)-th comparator device. Thus, in further exemplary embodiments, comparisons of some stages or comparators can be performed based on the state or output signal of at least one other comparator device.
[0013] In further exemplary embodiments, it is provided that the k-th comparator device is designed to provide a current associated with the i-th comparator devices based on the respective output signals of each i-th comparator device and to include the current associated with the i-th comparator devices in the comparison, wherein, for example, the k-th comparator device is designed to form a sum of the k-th comparison current and the current associated with the i-th comparator devices and to subtract the k-th reference current from the sum.
[0014] In further exemplary embodiments, it is provided that the first transistor and / or the second transistor is designed as a field-effect transistor, for example a MOSFET, e.g., as an N-channel MOSFET or as a P-channel MOSFET. In further exemplary embodiments, the drain-source paths of the first transistor and the second transistor are then connected in series in the sense of the series circuit described above by way of example.
[0015] In further exemplary embodiments, it is provided that the first transistor and / or the second transistor is designed as a bipolar transistor, for example of the NPN or PNP type. In further exemplary embodiments, the collector-emitter paths of the first transistor and the second transistor are then connected in series in the sense of the series circuit described above by way of example.
[0016] In further exemplary embodiments, instead of the first transistor and / or the second transistor, a (e.g. different) controllable current source or a controllable electrical resistor may also be provided.
[0017] In further exemplary embodiments, it is provided that a circuit node of the series circuit located between the first transistor and the second transistor can be at least temporarily supplied with the current associated with the i-th comparator devices.
[0018] In further exemplary embodiments, it is provided that the n-th reference current providing device is part of a first current mirror device. In further exemplary embodiments, it is provided that the first current mirror device, for example, supplies a plurality of the comparator devices each with a corresponding reference current. In further exemplary embodiments, the first current mirror device can, for example, be designed as a current mirror device with one input and n many outputs, wherein, for example, a reference current, e.g., a base reference current, can be supplied to the first current mirror device via its input, and wherein the first current mirror device outputs, for example, an n-th reference current derived from the reference current, e.g., a base reference current, at its n many outputs.
[0019] In further exemplary embodiments, it is provided that the n-th comparison current providing device is part of a second current mirror device. In further exemplary embodiments, it is provided that the second current mirror device, for example, supplies a plurality of the comparator devices each with a corresponding comparison current. In further exemplary embodiments, the second current mirror device can, for example, be designed as a current mirror device with one input and n many outputs, wherein, for example, an input current, for example an input current to be transformed into a digital output signal (analog, i.e., for example, continuous in time and value), can be supplied to the second current mirror device via its input, and wherein the second current mirror device outputs, for example, an n-th comparison current derived from the input current at its n many outputs.
[0020] Purely by way of example, an analog / digital converter device is described, comprising at least one device according to at least one of the preceding claims, wherein the converter device is configured to receive an input current and to form a digital output signal based on the input current. For example, a respective comparator device of the device can be used to determine a bit of a corresponding value of the converter device. For this purpose, in further exemplary embodiments, the current intensities of the reference currents and / or comparison currents for the various comparator devices can be selected appropriately.
[0021] In further exemplary embodiments, it is provided that the converter device is designed to form at least the first or an n-th reference current based on a reference current, for example by means of a or the first current mirror device, wherein, for example, a current intensity of the n-th reference current corresponds to a value of the n-th stage of the converter device.
[0022] In further exemplary embodiments, it is provided that the converter device is designed to form at least the first or n-th comparison current based on the input current, for example by means of a or the second current mirror device, wherein, for example, a current intensity of the n-th comparison current corresponds to a value of the n-th stage of the converter device.
[0023] Further exemplary embodiments relate to a method for operating a device comprising a first comparator device, wherein the first comparator device comprises a first reference current providing device and a first comparison current providing device, wherein the method comprises: providing a first reference current by means of the first reference current providing device, providing a first comparison current by means of the first comparison current providing device, comparing the first reference current with the first comparison current to obtain a first comparison result, and, based on the first comparison result, outputting a first output signal characterizing the first comparison result.
[0024] In further exemplary embodiments, it is provided that the device has at least one second comparator device, wherein the second comparator device has a second reference current providing device for providing a second reference current and a second comparison current providing device for providing a second comparison current, and wherein the second comparator device compares the second reference current with the second comparison current in order to obtain a second comparison result and, based on the second comparison result, outputs a second output signal characterizing the second comparison result, wherein, for example, the second comparator device receives the first output signal and forms the second comparison result based on the second reference current and the second comparison current and the first output signal.
[0025] In further exemplary embodiments, the principle according to the embodiments is also applicable in a corresponding manner to devices or methods for operating such devices having n many, n=1, 2, 3, ..., comparator devices.
[0026] Purely by way of example, a computing device is described, for example for determining a scalar product, for example a vector matrix multiplier, for example a dot product engine, comprising a matrix of elements with a controllable electrical resistance, and at least one analog / digital converter device according to the embodiments.
[0027] Purely by way of example, a use of the device according to the embodiments and / or the analog / digital converter device according to the embodiments and / or the method according to the embodiments and / or the computing device according to the embodiments is described for at least one of the following elements: a) converting a current into a binary value, b) performing binary coding, c) providing an, for example, completely current-driven analog / digital converter.
[0028] The drawing shows: Fig. 1 schematically shows a simplified block diagram according to exemplary embodiments, Fig. 2 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 3 schematically shows a simplified block diagram according to exemplary embodiments, Fig. 4 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 5 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 6 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 7 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 8 schematically shows a simplified circuit diagram according to exemplary embodiments, Fig. 9 schematically shows a simplified block diagram according to exemplary embodiments, Fig. 10 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 11 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 12 schematically shows a simplified block diagram according to exemplary embodiments, Fig. 13 schematically shows a simplified flow diagram according to exemplary embodiments, Fig. 14A schematically shows a simplified circuit diagram according to exemplary embodiments, Fig. 14B schematically shows a simplified circuit diagram according to exemplary embodiments, Fig. 15 schematically shows a simplified circuit diagram according to exemplary embodiments, Fig. 16 schematically shows a simplified circuit diagram according to exemplary embodiments, Fig. 17 schematically illustrates aspects of uses according to exemplary embodiments.
[0029] For exemplary embodiments, see Fig. 1 and Fig. 2, refer to a device 100 comprising a first comparator device 110-1, wherein the first comparator device 110-1 comprises a first reference current providing device 120-1 for providing 200 ( Fig. 2) a first reference current I_Ref-1 and a first comparison current providing device 130-1 for providing 202 a first comparison current I_Vergl-1, and wherein the first comparator device 110-1 is designed to compare 204 the first reference current I_Ref-1 with the first comparison current I_Vergl-1 in order to obtain a first comparison result VE-1 and, based on the first comparison result VE-1, to output 206 a first output signal AS-1 characterizing the first comparison result VE-1, for example as a binary signal or logic signal. In further exemplary embodiments, a temporal sequence of the blocks according to Fig. 2 can also be depicted differently than in the present example, e.g. several blocks can be executed at least partially overlapping in time or simultaneously with each other.
[0030] In further exemplary embodiments, Fig. 3, Fig. 4, it is provided that the device 100a has at least one second comparator device 110-2, wherein the second comparator device 110-2 has a second reference current providing device 120-2 for providing 210 ( Fig. 4) a second reference current I_Ref-2 and a second comparison current providing device 130-2 for providing 212 a second comparison current I-Vergl-2, and wherein the second comparator device 110-2 is designed to compare 214 the second reference current I_Ref-2 with the second comparison current I_Vergl-2 in order to obtain a second comparison result VE-2 and, based on the second comparison result VE-2, to output 216 a second output signal AS-2 characterizing the second comparison result VE-2.
[0031] In further exemplary embodiments, this enables, for example, the provision of a, for example, two-stage, analog / digital converter device 1000, wherein a first stage, e.g., corresponding to a most significant bit (MSB), can be implemented, for example, by means of the first comparator device 110-1, and wherein a second stage, e.g., corresponding to a least significant bit (LSB), can be implemented, for example, by means of the second comparator device 110-2. The digital output signal AS-AD of the analog / digital converter device 1000 is characterized, for example, by the output signals AS-1, AS-2 of the two stages 110-1, 110-2.
[0032] For example, the first reference current I_Ref-1 usable for the first comparator device 110-1 associated with the MSB can be selected to correspond, for example, to half the maximum current. For example, the second reference current I_Ref-2 usable for the second comparator device 110-2 associated with the LSB can be selected to correspond, for example, to a quarter of the maximum current. The provision of the comparison currents I_Vergl-1, I_Vergl-2 for the two stages according to further exemplary embodiments is described in more detail below.
[0033] In further exemplary embodiments, Fig. 3, Fig. 5, it is provided that the second comparator device 110-2 is designed to receive the first output signal AS-1, see also block 220 according to Fig. 5, and to form the second comparison result VE-2 based on the second reference current I_Ref-2 and the second comparison current I_Vergl-2 and the first output signal AS-1, see block 222 according to Fig. 5, see also the dashed arrow A1 in Fig. 3, which symbolizes a supply of the first output signal AS-1 from the first comparator device 110-1 to the second comparator device 110-2.
[0034] In further exemplary embodiments, Fig. 6, it is provided that the second comparator device 110-2 ( Fig. 3) is designed to provide a current I-110-1 associated with the first comparator device 110-1 based on the first output signal AS-1 225 ( Fig. 6) and to include 227 the current I-110-1 associated with the first comparator device 110-1 in the comparison 214, 222, wherein, for example, the second comparator device 110-2 comprises a current source SQ2 ( Fig. 3) to provide the current I-110-1 associated with the first comparator device 110-1 225.
[0035] As a result, for example when providing an analog / digital converter device 1000, a change in state, for example of the MSB, can be taken into account, for example by influencing a current comparison of the LSB stage 120-2 based on the current I-110-1 associated with the first comparator device 110-1.
[0036] In further exemplary embodiments, Fig. 7, it is provided that the second comparator device 110-2 is designed to form 230 a sum SUM-2 from the second comparison current I_Vergl-2 and the current I-110-2 associated with the first comparator device 110-1 and to subtract the second reference current I_Ref-2 from the sum SUM-2.
[0037] In further exemplary embodiments, Fig. 8, it is provided that the second comparator device 110-2 is designed to supply the second comparison current I_Vergl-2 and the current I-110-1 associated with the first comparator device 110-1 to a circuit node N-110-2 associated with the second comparator device 110-2 and to discharge the second reference current I_Ref-2 from the circuit node N-110-2 associated with the second comparator device 110-2. In further exemplary embodiments, for example, an electrical potential of the circuit node N-110-2 associated with the second comparator device can be used as the second output signal AS-2. In further exemplary embodiments, this applies in a comparable manner, for example, also to the first comparator device 110-1 or, in the case of several (e.g.more than two) comparator devices, for the several existing comparator devices, whereby, for example, in the MSB alone a comparison of the two currents I_Ref-1, I_Vergl-1 takes place (and thus a formation of an electrical potential characterizing the output signal AS-1), so, for example, no consideration of a further current, as is the case for the LSB, for example with the current I-110-1 associated with the MSB, because the MSB already represents the most significant digit.
[0038] In further exemplary embodiments, Fig. 9, Fig. 10, it is provided that the device 100b has n many, n = 1, 2, 3, ..., comparator devices 110-1, 110-2, ..., 110-n (e.g. also containing the first and / or second comparator device 110-1, 110-2 already mentioned above by way of example), wherein the n-th comparator device 110-n has an n-th reference current providing device 120-n for providing an n-th reference current I_Ref-n (see block 240 according to Fig. 10) and an n-th comparison current providing device 130-n for providing an n-th comparison current I_Vergl-n (see block 242 according to Fig. 10), and wherein the n-th comparator device 110-n is designed to compare the n-th reference current I_Ref-n with the n-th comparison current I_Vergl-n (see block 244 according to Fig. 10) to obtain an n-th comparison result VE-n and, based on the n-th comparison result VE-n, to output an n-th output signal AS-n characterizing the n-th comparison result VE-n (see block 246 according to Fig. 10). In other words, in further exemplary embodiments, several or all comparator devices 110-1, 110-2, ..., 110-n of the device 100b may have an at least partially identical or comparable structure, for example with regard to the respective reference current providing device and / or the respective comparison current providing device.
[0039] In further exemplary embodiments, Fig. 11, it is provided that a k-th comparator device, k=2, .., n, of the n plurality of comparators is designed to receive 250 at least one output signal from a (k-1)-th comparator device and to form 252 the k-th comparison result VE-k based on the k-th reference current and the k-th comparison current and the at least one output signal of the (k-1)-th comparator device, see e.g. arrow A1, which illustrates this by way of example for k=2, see e.g. arrow A2, which illustrates this by way of example for k=3, see e.g. arrow An-1, which illustrates this by way of example for k=n-1. As a result, in further exemplary embodiments, comparisons of some stages or comparators can be carried out based on the state or output signal of at least one other comparator device.
[0040] In further exemplary embodiments, Fig. 12, Fig. 13, it is provided that a k-th comparator device 110-k, k=2, .., n, of the n plurality of comparators is designed to receive respective output signals AS-(k-1), AS-(k-2), ..., AS-1 of each i-th comparator device, i=k-1, k-2, ..., 1 255 ( Fig. 13) and to form 257 the k-th comparison result VE-k based on the k-th reference current I_Ref-k and the k-th comparison current I_Vergl-k and the respective output signals AS-(k-1), AS-(k-2), ..., AS-1 of each i-th comparator device. As a result, in further exemplary embodiments, comparisons of some stages or comparator devices can be carried out based on the state or output signal of some other stages or comparator devices, for example, in applications in the field of analog / digital converter devices according to further exemplary embodiments, based on the state or output signal of those stages of the analog / digital converter device which are arranged upstream of the k-th stage, e.g. in a sequence of values from MSB to LSB, and thus concern the more significant stages than the k-th stage.
[0041] In further exemplary embodiments, Fig. 12, it is provided that the k-th comparator device 110-k ( Fig. 12) is designed to provide a current associated with the i-th comparator devices based on the respective output signals of each i-th comparator device and to include the current associated with the i-th comparator devices in the comparison, wherein, for example, the k-th comparator device is designed to form a sum SUM-k from the k-th comparison current and the current associated with the i-th comparator devices and to subtract the k-th reference current I_Ref-k from the sum SUM-k.
[0042] In further exemplary embodiments, Fig. 14A, it is provided that at least one n-th comparator device comprises a series circuit SS comprising a first transistor T1 and a second transistor T2, wherein the first transistor T1 comprises at least a part of the n-th reference current providing device 120-n ( Fig. 9), and wherein the second transistor T2 forms at least part of the nth comparison current supply device 130-n. The series circuit SS is connected, for example, between a first reference potential BP1, e.g., a supply voltage potential, and a second reference potential BP2, e.g., a ground potential.
[0043] In further exemplary embodiments, it is provided that the first transistor T1 and / or the second transistor T2 is designed as a field-effect transistor, for example a MOSFET, e.g., as an N-channel MOSFET or as a P-channel MOSFET. In further exemplary embodiments, the drain-source paths of the first transistor T1 and the second transistor T2 are then connected in series in the sense of the series circuit SS described above as an example.
[0044] In further exemplary embodiments, it is provided that the first transistor T1 and / or the second transistor T2 is designed as a bipolar transistor, for example of the NPN or PNP type. In further exemplary embodiments, the collector-emitter paths of the first transistor T1 and the second transistor T2 are then connected in series in the sense of the series circuit SS described above by way of example.
[0045] In further exemplary embodiments, Fig. 14B, it is provided that the series circuit SS is assigned an optional compensation device KE for compensating a voltage drop, for example, at the first transistor, wherein, for example, the compensation device is connected in series to the series circuit SS ( Fig. 14A).
[0046] In further exemplary embodiments, Fig. 14A, Fig. 14B, it is provided that a circuit node N-110-n of the series circuit SS located between the first transistor T1 and the second transistor T2 can be at least temporarily supplied with the current associated with the i-th comparator devices.
[0047] In further exemplary embodiments, it is provided that the n-th reference current providing device 120-n is part of a first current mirror device SP1 ( Fig. 3). In further exemplary embodiments, it is provided that the first current mirror device SP1, for example, supplies several (for example all) of the comparator devices 110-1, 110-2, ..., 110-n each with a corresponding reference current I_Ref-1, I_Ref-2, ..., I_Ref-n. In further exemplary embodiments, the first current mirror device SP1 can, for example, be designed as a current mirror device with one input and n many outputs, wherein a reference current, for example a base reference current, can be supplied to the first current mirror device SP1 via its input, and wherein the first current mirror device SP1 outputs, for example, an n-th reference current derived from the reference current, for example a base reference current, at its n many outputs.
[0048] In further exemplary embodiments, it is provided that the n-th comparison current providing device 130-n is part of a second current mirror device SP2 ( Fig. 3). In further exemplary embodiments, it is provided that the second current mirror device SP2, for example, supplies several (for example all) of the comparator devices 110-1, 110-2, ..., 110-n each with a corresponding comparison current. In further exemplary embodiments, the second current mirror device SP2 can, for example, be designed as a current mirror device with one input and n many outputs, wherein the second current mirror device SP2 can, for example, be supplied with an input current, e.g., a digital output signal AS-AD ( Fig. 3) an input current (analog, e.g. continuous in time and value) to be transformed can be supplied, and wherein the second current mirror device SP2 outputs at its n many outputs, for example, an n-th comparison current derived from the input current.
[0049] Further exemplary embodiments, Fig. 15, relate to an analog / digital converter device 1000a having at least one device according to at least one of the preceding claims, wherein the converter device 1000a is designed to receive an input current I1 and to form a digital output signal AS-AD' based on the input current. For example, a respective comparator device of the device can be used to determine a bit of a corresponding value of the converter device 1000a. For this purpose, in further exemplary embodiments, the current strengths of the reference currents and / or comparison currents for the various comparator devices can be suitably selected, which is explained below by way of example with reference to Fig. 15, according to further exemplary embodiments and without limitation of generality also to other than those in Fig. 15 The configuration shown as an example is applicable.
[0050] The converter device 1000a here has four stages S1, S2, S3, S4, of which the first stage S1 characterizes, for example, an MSB, and of which the fourth stage S4 characterizes, for example, an LSB. An output signal of the first stage S1 is characterized by the potential at the circuit node D, an output signal of the second stage S2 is characterized by the potential at the circuit node C, an output signal of the third stage S3 is characterized by the potential at the circuit node B, and an output signal of the fourth stage S4 is characterized by the potential at the circuit node A. Together, the output signals A, B, C, D form the digital output signal AS-AD', which in the present case has four bits, by way of example.
[0051] A comparator device of the first stage S1 is realized in the present case, for example, by the two transistors T1-D, T2-D, which in further exemplary embodiments essentially correspond to the ones described above with reference to Fig. 14A, Fig. 14B, wherein the circuit node D is arranged according to Fig. 15 e.g. the circuit node N-110-n according to Fig. 14A.
[0052] In further exemplary embodiments, it is provided that the converter device 1000a is designed to form at least the first or an n-th reference current based on a reference current, e.g. base reference current, Iref, for example by means of a or the first current mirror device SP1 ( Fig. 3), where, for example, a current intensity of the n-th reference current corresponds to a value of the n-th stage of the converter device. In the present case, Fig. 15 a first current mirror device formed by the transistors T-SP1, T1-A, T1-B, T1-C, T1-D, wherein the transistor T-SP1 characterizes an input of the first current mirror device, and wherein the transistors T1-A, T1-B, T1-C, T1-D each characterize an output for a respective stage of the four stages S1, S2, S3, S4.
[0053] In further exemplary embodiments, it is provided that the converter device 1000a is designed to form at least the first or n-th comparison current based on the input current I1, for example by means of a or the second current mirror device (see eg SP2 according to Fig. 3), where, for example, a current intensity of the n-th reference current corresponds to a value of the n-th stage of the converter device. In the present case, Fig. 15 a second current mirror device formed by the transistors T-SP2, T2-A, T2-B, T2-C, T2-D, wherein the transistor T-SP2 characterizes an input of the second current mirror device, and wherein the transistors T2-A, T2-B, T2-C, T2-D each characterize an output for a respective stage of the four stages S1, S2, S3, S4.
[0054] In further exemplary embodiments, a compensation device KE according to Fig. 14B in the first stage S1 according to Fig. 15 is realized by the transistor KE-D. The same applies to the further stages S2, S3, S4 and a transistor T-SP-2 of the second current mirror device SP2 ( Fig. 3) for the transistors KE-C, KE-B, KE-A, KE-SP2 according to Fig. 15.
[0055] Below are further exemplary aspects of the embodiment 1000a according to Fig. 15 described.
[0056] First, consider the first stage S1 with its two transistors T1-D, T2-D, which provide the respective currents (reference current of stage S1 provided by transistor T1-D, comparison current of stage S1 provided by transistor T2-D). The series circuit T1-D, T2-D results in a comparator device, since the transistor T1-D, T2-D providing the larger current determines the electrical potential at circuit node D, which characterizes the respective comparison result.
[0057] Via the current source device SQ-2-D, a current I2-D associated with the stage S1, which depends, for example, on the potential of the circuit node D, is provided to the stage S2, namely its circuit node C. Thus, the comparison executable by the comparator device T1-C, T2-C of the stage S2, which determines the potential at the circuit node C, can be carried out based on the potential of the circuit node D, i.e., based on the output signal D of the next higher (first) stage S1.
[0058] In a similar manner, a current I3-D associated with stage S1, which depends, for example, on the potential of circuit node D, is provided to stage S3, namely its circuit node B, via current source device SQ-3D. Thus, the comparison executable by comparator device T1-B, T2-B of stage S3, which determines the potential at circuit node B, can be carried out based on the potential of circuit node D, i.e., based on the output signal D of the first stage S1.
[0059] In a similar manner, a current I4-D associated with stage S1, which depends, for example, on the potential of circuit node D, is provided to stage S4, namely its circuit node A, via current source device SQ-4D. Thus, the comparison executable by comparator device T1-A, T2-A of stage S4, which determines the potential at circuit node A, can be carried out based on the potential of circuit node D, i.e., based on the output signal D of the first stage S1.
[0060] In a similar manner, a current I3-C associated with stage S2, which depends, for example, on the potential of circuit node C, is provided to stage S2, namely its circuit node B, via current source device SQ-3C. Thus, the comparison executable by comparator device T1-B, T2-B of stage S3, which determines the potential at circuit node B, can also be carried out based on the potential of circuit node C, i.e., based on the output signal C of the second stage S2.
[0061] In a similar manner, a current I4-C associated with stage S2, which depends, for example, on the potential of circuit node C, is provided to stage S4, namely its circuit node A, via current source device SQ-4C. Thus, the comparison executable by comparator device T1-A, T2-A of stage S4, which determines the potential at circuit node A, can be carried out based on the potential of circuit node C, i.e. (also) based on the output signal C of the second stage S2.
[0062] In a similar manner, a current I4-B associated with stage S3, which depends, for example, on the potential of circuit node B, is provided to stage S4, namely its circuit node A, via current source device SQ-4B. Thus, the comparison executable by comparator device T1-A, T2-A of stage S4, which determines the potential at circuit node A, can be carried out based on the potential of circuit node B, i.e. (also) based on the output signal B of the third stage S3.
[0063] In further exemplary embodiments, the current source devices SQ-2D, SQ-3D, SQ-3C, SQ-4D, SQ-4C, SQ-4B thus enable output signals from stages of the converter device 1000a with higher significance to be taken into account, wherein the currents I2-D, I3-D, I3-C, I4-D, I4-C, I4-B that can be provided by means of the respective current source devices SQ-2D, SQ-3D, SQ-3C, SQ-4D, SQ-4C, SQ-4B can be used, for example, to form the respective output signal A, B, C.
[0064] In further exemplary embodiments, the current source devices SQ-2D, SQ-3D, SQ-3C, SQ-4D, SQ-4C, SQ-4B each comprise, for example, a first MOSFET whose gate electrode is controllable by a signal from another stage, and a second MOSFET, for example, in series with the first MOSFET, which can also form part of the second current mirror device, for example. This is described below by way of example for the current source device SQ-2D of stage S2.
[0065] The current source device SQ-2D of stage S2 has a first MOSFET T3, whose gate electrode is controllable by the signal D of the MSB stage S1, and a second MOSFET T4, e.g., in series with the first MOSFET T3, which, e.g., can also form part of the second current mirror device—analogous to the transistor T2-C of stage S2. The further current source devices SQ-3D, SQ-3C, SQ-4D, SQ-4C, SQ-4B can, in further exemplary embodiments, each have at least approximately a comparable structure or topology.
[0066] As already mentioned, the Fig. 15 first stage S1 shown on the right is the MSB, while the one in Fig. 15 The fourth stage S4 shown on the left forms the LSB.
[0067] For an exemplary description of the function of the converter device 1000a, it is assumed below that the input current I1 is zero. In this case, all output signals A, B, C, D or the electrical potentials or voltages characterizing them, e.g., with reference to the ground potential BP2, are also zero. In this state, e.g., the third transistors T3 of the current source devices SQ-2D, SQ-3D, SQ-3C, SQ-4D, SQ-4C, SQ-4B are switched on, i.e., conductive (e.g., low-impedance). The transistors T1-A, T1-B, T1-C, T1-D, which provide the reference currents for the stages S1 to S4, are, for example, always switched on, since they are supplied with a non-zero gate voltage by the input transistor T-SP1 of the first current mirror device.
[0068] For example, as mentioned above, the transistors KE-SP2, KE-A, KE-B, KE-C, KE-D are always switched on and are used to compensate the voltage drop of the transistors T-SP1, T1-A, T1-B, T1-C, T1-D of their respective stage.
[0069] For an exemplary description of the function of converter device 1000a, it is assumed below that an input current is present with a current intensity close to the switching threshold of the first stage S1 (MSB). In this state, all stages or bits are '1' except for the MSB of stage S1; the output signal AS-AD' is therefore binary "1110." As soon as the input current I1 reaches the switching threshold of the MSB, the MSB assumes the value '1', and the voltage at the circuit node has a value corresponding to the value '1'. This deactivates the transistors T3 of the current source devices SQ-2D, SQ-3D, SQ-4D, so that the low-order bits of the stages S2, S3, S4 now drive a lower current into their respective comparator device (namely, for example, currents lower by the currents I2-D, I3-D, I4-D), which causes, for example, the low-order bits of the stages S2, S3, S4 to change from '1' to '0'.
[0070] In further exemplary embodiments, the switching thresholds or the currents used can be designed as follows: Setting the threshold current for the MSB, i.e. the first stage S1. The first reference current through the comparator device of the first stage S1 is defined by the transistors T-SP1, T1-D of the first current mirror device. In exemplary embodiments, the first reference current should correspond, for example, to a weight of the MSB, for example 800 nA (nanoamperes), when a maximum input current range for the converter device 1000a is 1600 nA. In exemplary embodiments, the first comparison current for the first stage S1 should be set such that it corresponds to the first reference current of, for example, 800 nA when the input current I1 is 800 nA, which can be realized, for example, by selecting the ratio of the gate length to the gate width (“W / L ratio”) of the respective transistors (e.g. in the case of MOSFETs).
[0071] In further exemplary embodiments, the further, lower-order stages S2, S3, S4 can be designed, for example, as follows: a) Ensure that transistors of the current source devices SQ-2D, SQ-3D, SQ-3C, SQ-4D, SQ-4C, SQ-4B, e.g. transistor T3 for stage S2, are switched off (high-impedance). This state occurs at a specific input current, for example for “bit 3” of stage S2 when the output signal changes from “1011” to “1100”, which occurs, for example, at an input current of 1200 nA when the input current range is 1600 nA. In further exemplary embodiments, it is advantageous in this state if the current provided by transistor T2-C corresponds to the current of transistor T1-C (e.g. by appropriately designing the w / I ratio of transistor T2-C). It should be noted that transistor T3, for example, is switched off. b) In further exemplary embodiments, there is a second condition for bit "C" of stage S2, whereby, for example, the next transistor T4 provided in stage S2 is activated. When transistor T4 is active and bit "C" of stage S2 undergoes a state change, i.e., flips, the input current is, for example, 400 nA, corresponding to a transition of the output signal from "0011" to "0100." In this state, the current, which should correspond to the reference current of stage S2, flows through the two transistors T2-C and T4.
[0072] In further exemplary embodiments, a w / L ratio of transistor T2-C has already been determined in aspect a) described above. In further exemplary embodiments, it can be determined what current the transistor T2-C contributes at an input current of, for example, 400 nA. For example, this is, for example, exactly 1 / 3 of the total current flowing through the comparator device of stage S2 at an input current of 400 nA.
[0073] Therefore, the additional transistor T4 should provide the differential current to the mentioned 400nA, so that the w / I ratio of the transistor T4, for example, is twice as large as the w / I ratio of the transistor T2-C.
[0074] In further exemplary embodiments, the further transistors T2-A, T2-B and the respective fourth (i.e. in Fig. 15 lower) transistors of the current source devices SQ-4B, SQ-4C, SQ-4D, SQ-3C, SQ-3D can be scaled or designed based on the aspects described above.
[0075] For example, if the transistor T-2D has a w / L ratio of one, the w / L ratio for the other transistors can be: T2-C: 0.33; T4: 0.66; T4-B: 0.76; T4-B': 0.23; T4-A: 0.08; T3-A: 0.03; T3-A': 0.014; T2-A: 0.062, where it is assumed by way of example that the reference branch for the MSB is set to a predeterminable reference current Iref-1, that the reference branch of stage S2 is set to half the predeterminable reference current Iref-1, that the reference branch of stage S3 is set to a quarter of the predeterminable reference current Iref-1, and that the reference branch of stage S1 is set to one eighth of the predeterminable reference current Iref-1.
[0076] In further exemplary embodiments, the w / L ratios can be increased, for example, if they would become too small, for example by increasing the reference current for a given stage. In this case, the w / L ratios of the other transistors in the same stage can also be scaled. For example, if a reference current through transistor T1-A of stage S4 is to be doubled, the w / L ratio for the other transistors T2-A, T4-A, T4-A', T4-A'' of the same stage can also be doubled.
[0077] In further exemplary embodiments, it may be provided, e.g. if a width or other structure size of the transistors under consideration becomes too small, e.g. for a specific manufacturing technology of a target system, to increase a length of a gate channel of the transistors under consideration, e.g. in order to obtain a desired w / L ratio.
[0078] In further exemplary embodiments, the converter device 1000a may be configured according to Fig. 15 (as well as all other devices described above by way of example) can be realized by means of an inverse circuit, for example by a vertical mirroring of the circuit according to Fig. 15 and replacing NMOS transistors with PMOS transistors, and vice versa.
[0079] In further exemplary embodiments, the outputs A, B, C, D of the comparator devices of the stages S1, S2, S3, S4 can be extended by respective buffer circuits (not shown), the outputs of which can then, for example, each act on the current source devices SQ-2D, SQ-3D, ... of the downstream stages, which can, for example, result in increased stability and fewer disturbances (e.g., glitches).
[0080] In further exemplary embodiments, resistors (not shown) may be provided, for example in the region of the gate electrodes of at least some transistors, in order to counteract an undesirable tendency to oscillate.
[0081] Further exemplary embodiments, see e.g. Fig. 1, Fig. 2, relate to a method for operating a device 100 comprising a first comparator device 110-1, wherein the first comparator device has a first reference current providing device and a first comparison current providing device, the method comprising: providing 200 a first reference current I_Ref-1 by means of the first reference current providing device, providing 202 a first comparison current I_Vergl-1 by means of the first comparison current providing device, comparing 204 the first reference current with the first comparison current to obtain a first comparison result VE-1, and, based on the first comparison result VE-1, outputting 206 a first output signal AS-1 characterizing the first comparison result VE-1.
[0082] In further exemplary embodiments, Fig. 3, Fig. 4, it is provided that the device 100a has at least one second comparator device 110-2, wherein the second comparator device has a second reference current providing device for providing a second reference current and a second comparison current providing device for providing a second comparison current, and wherein the second comparator device compares the second reference current with the second comparison current in order to obtain a second comparison result and, based on the second comparison result, outputs a second output signal characterizing the second comparison result, wherein, for example, the second comparator device receives the first output signal and forms the second comparison result based on the second reference current and the second comparison current and the first output signal.
[0083] In further exemplary embodiments, the principle according to the embodiments is also applicable in a corresponding manner to devices or methods for operating such devices having n many, n=1, 2, 3, ..., comparator devices, see for example Fig. 9.
[0084] Further exemplary embodiments, Fig. 16, relate to a computing device 10, for example for determining a scalar product, for example a vector matrix multiplier, for example a dot product engine, comprising a matrix M of elements with a controllable electrical resistance, and at least one analog / digital converter device 1000a, 1000b, 1000c according to the embodiments.
[0085] For example, the at least one analog / digital converter device 1000a, 1000b, 1000c can be used according to exemplary embodiments for current measurement with respect to at least one column of the matrix M, compare the currents Ia, Ib, Ic, in particular on a “high side”, i.e. in the region of a comparatively large electrical potential, for example an operating voltage potential different from a ground potential BP2, see the voltage source V4.
[0086] In further exemplary embodiments, the computing device 10 can be used, for example, for machine learning (ML) methods or for applications in the field of artificial intelligence, for example for hardware accelerators for training deep neural networks (DNN).
[0087] Further exemplary embodiments, Fig. 17, relate to a use 300 of the device 100, 100a, 100b according to the embodiments and / or the analog / digital converter device 1000, 1000a, 1000b, 1000c according to the embodiments and / or the method according to the embodiments and / or the computing device 10 according to the embodiments for at least one of the following elements: a) Converting 301 a current I1 ( Fig. 15) into a binary value AS-AD', b) executing 302 a binary coding, c) providing 303 an, for example, fully current-driven analog-to-digital converter. Information on funding and support
[0088] The project leading to this notification has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No. 826655. The JU receives support from the European Union's Horizon 2020 research and innovation programme and from Belgium, France, Germany, the Netherlands, and Switzerland.
Claims
[1] Device (100; 100a; 100b) comprising a first comparator device (110-1), wherein the first comparator device (110-1) comprises a first reference current provision device (120-1) for providing (200) a first reference current (I_Ref-1) and a first comparator current provision device (130-1) for providing (202) a first comparator current (I_Vergl-1), and wherein the first comparator device (110-1) is configured to compare the first reference current (I_Ref-1) with the first comparator current (I_Vergl-1) (204) in order to obtain a first comparator result (VE-1) and, based on the first comparator result (VE-1), to output a first output signal (AS-1) characterizing the first comparator result (VE-1) (206), wherein the device (100a) has at least one second comparator device (110-2),wherein the second comparator device (110-2) comprises a second reference current provision device (120-2) for providing (210) a second reference current (I_Ref-2) and a second comparator current provision device (130-2) for providing (212) a second comparator current (I_Vergl-2), and wherein the second comparator device (110-2) is configured to compare the second reference current (I_Ref-2) with the second comparator current (I_Vergl-2) (214) in order to obtain a second comparator result (VE-2) and to output (216) a second output signal (AS-2) characterizing the second comparator result (VE-2) based on the second comparator result (VE-2), wherein the second comparator device (110-2) is configured tobased on the first output signal (AS-1) to provide a current (I-110-1) associated with the first comparator device (110-1) (225) and to include the current (I-110-1) associated with the first comparator device (110-1) in the comparison (214) (227), wherein a current source (SQ-2) controllable based on the first output signal (AS-1) is provided to provide the current (I-110-1) associated with the first comparator device (110-1). [2] Device (100a) according to claim 1, wherein the second comparator device (110-2) is configured to receive the first output signal (AS-1) (220) and to form the second comparison result (VE-2) based on the second reference current (I_Ref-2) and the second comparison current (I_Vergl-2) and the first output signal (AS-1) (222). [3] Device (100a) according to claim 1 or 2, wherein the second comparator device (110-2) is configured to form a sum (SUM-2) of the second comparator current (I_Vergl-2) and the current (I-110-1) associated with the first comparator device (110-1) (230) and to subtract the second reference current (I_Ref-2) from the sum (232). [4] Device (100a) according to claim 1 or 3, wherein the second comparator device (110-2) is configured to supply the second comparator current (I_Vergl-2) and the current (I-110-1) associated with the first comparator device (110-1) to a circuit node (N-110-2) associated with the second comparator device (110-2) and to discharge the second reference current (I_Ref-2) from the circuit node (N-110-2) associated with the second comparator device (110-2). [5] Device (100; 100a; 100b) comprising n many, n = 1, 2, 3, ..., comparator devices (110-1, 110-2, ..., 110-n), wherein the nth comparator device (110-n) comprises an nth reference current provision device (120-n) for providing (240) an nth reference current (I_Ref-n) and an nth comparator current provision device (130-n) for providing (242) an nth comparator current (I_Vergl-n), and wherein the nth comparator device (110-n) is configured to compare the nth reference current (I_Ref-n) with the nth comparator current (I_Vergl-n) (244) in order to obtain an nth comparator result to obtain (VE-n) and, based on the nth comparison result (VE-n), to output an nth output signal (AS-n) characterizing the nth comparison result (VE-n) (246), wherein a k-th comparator device, k=2, .., n, of the n many comparator devices (110-1, 110-2, ..., 110-n) is configured to output respective output signals (AS-(k-1), AS-(k-2), ..., AS-1) of each i-th comparator device, i=k-1, k-2, ..., 1 to receive (255) and to form the k-th comparison result (VE-k) based on the k-th reference current (I_Refk) and the k-th comparison current (I_Vergl-k) and the respective output signals (AS-(k-1), AS-(k-2), ..., AS-1) of each i-th comparator device (257). [6] Device (100; 100a; 100b) according to claim 5, wherein at least one nth comparator device (110-n) comprises a series circuit (SS) of a first transistor (T1) and a second transistor (T2), wherein the first transistor (T1) forms at least a part of the nth reference current provision device (120-n), and wherein the second transistor (T2) forms at least a part of the nth comparator current provision device (130-n). [7] Device (100; 100a; 100b) according to claim 6, wherein a compensation device (KE) for compensating a voltage drop is associated with the series circuit (SS).[8] Device (100; 100a; 100b) comprising n many, n = 1, 2, 3, ..., comparator devices (110-1, 110-2, ..., 110-n), wherein the nth comparator device (110-n) comprises an nth reference current provision device (120-n) for providing (240) an nth reference current (I_Ref-n) and an nth comparator current provision device (130-n) for providing (242) an nth comparator current (I_Vergl-n), and wherein the nth comparator device (110-n) is configured to compare the nth reference current (I_Ref-n) with the nth comparator current (I_Vergl-n) (244) in order to obtain an nth comparator result to obtain (VE-n) and to output an nth output signal (AS-n) characterizing the nth comparison result (VE-n) based on the nth comparison result (VE-n) (246), wherein at least one nth comparator device (110-n) has a series circuit (SS) of a first transistor (T1) and a second transistor (T2),wherein the first transistor (T1) forms at least a part of the nth reference current provision device (120-n), and wherein the second transistor (T2) forms at least a part of the nth comparator current provision device (130-n), wherein a compensation device (KE) for compensating a voltage drop is associated with the series circuit (SS). [9] Device (100a) according to claim 8, wherein a k-th comparator device, k=2, .., n, of the n many comparator devices (110-1, 110-2, ..., 110-n) is configured to receive at least one output signal of a (k-1)-th comparator device (250) and to form the k-th comparison result (VE-k) based on the k-th reference current (I_Ref-k) and the k-th comparison current (I_Verglk) and the at least one output signal of the (k-1)-th comparator device (252). [10] Device (100; 100a; 100b) according to claim 5 or 6 or 7, wherein the k-th comparator device (110-k) is configured to provide a current (I-110-i) associated with the i-th comparator devices based on the respective output signals (AS-(k-1), AS-(k-2), ..., AS-1) of each i-th comparator device and to include the current (I-110-i) associated with the i-th comparator devices in the comparating (244), wherein the k-th comparator device (110-k) is configured to form a sum (SUM-k) of the k-th comparator current (I_Vergl-k) and the current (I-110-i) associated with the i-th comparator devices and to subtract the k-th reference current (I_Ref-k) from the sum (SUM-k). [11] Device (100; 100a; 100b) according to claim 7 or 8 or 9, wherein the compensation device (KE) is connected in series with the series circuit (SS). [12] Device (100; 100a; 100b) according to claim 10 referred back to claim 6 or claim 10 referred back to claim 7 or claim 11 referred back to claim 7, wherein a circuit node (N-110-n) of the series circuit (SS) located between the first transistor (T1) and the second transistor (T2) is at least temporarily supplied with the current (I-110-i) associated with the i-th comparator devices. [13] Device (100; 100a; 100b) according to at least one of claims 5 to 12, wherein the nth reference current provision device (120-n) is part of a first current mirror device (SP1). [14] Device (100; 100a; 100b) according to at least one of claims 5 to 13, wherein the nth comparator current provision device (130-n) is part of a second current mirror device (SP2). [15] Use (300) of the device (100; 100a; 100b) according to at least one of claims 1 to 14 for at least one of the following elements: a) converting (301) a current (1a; 1b; 1c) into a binary value, b) performing (302) a binary encoding, c) providing (303) a current-driven analog-to-digital converter.
Citation Information
Patent Citations
HARDWARE COMPUTING STRUCTURE FOR DEEP EQUILIBRIUM MODELS
DE102021208010A1
Semiconductor integrated circuit
US6150967A