DC / DC converter

Abstract

The invention relates to a DC / DC converter (1) comprising: - a primary side (P) with at least two half-bridges (HB1, HB2), each with a high-side switch designed as a semiconductor switch (S1, S3) and a low-side switch designed as a semiconductor switch (S2, S4), - a secondary side (S) with at least two half-bridges (HB3, HB4), each with a high-side switch designed as a semiconductor switch (S5, S7, D) and a low-side switch designed as a semiconductor switch (S6, S8, D), - at least one LC resonant circuit (2.1, 2.2) designed as a series resonant circuit, which is arranged between a center tap of one of the half-bridges (HB1, HB2) on the primary side (P) and a center tap of one of the half-bridges (HB3, HB4) on the secondary side (S), - at least one further LC resonant circuit (2.1, 2.2) designed as a series resonant circuit or a capacitor (C1, C2) which is arranged between a center tap of another of the half-bridges (HB1, HB2) on the primary side (P) and a center tap of another of the half-bridges (HB3, HB4) on the secondary side (S).

Description

The invention relates to a DC / DC converter according to claim 1 and a method for operating the same according to the preamble of claim 4 or 10.If two high-voltage systems are coupled to one another via a voltage converter, the two voltage systems are dependent on one another. Depending on the functional principle of the voltage converter, this dependence can be more or less pronounced. In principle, it is possible to distinguish between galvanically coupled voltage converters and galvanically isolated voltage converters (insulating DC / DC converters). Depending on the application, it is advantageous or necessary to use an insulating or coupled DC / DC converter. Galvanically coupled DC / DC converters are distinguished by a high efficiency (provided that the transmission ratio does not become too large) and a high power density.Insulating DC / DC converters are constructed with a transformer for energy transmission. As a result, the transformer with the galvanic isolation represents two independent high-voltage systems on the primary and secondary sides. They are distinguished in that they have a freedom of selection of the reference potential on the secondary side. Connected with this, there are advantages in that the potential distribution of the primary side does not affect the secondary side. The insulation configuration on the secondary side is thus also independent of the primary side, since an insulation fault has no influence on the secondary side. Furthermore, insulating DC / DC converters with a transformer on the secondary side are all-pole free when no AC voltage is generated at the primary winding.Insulating voltage converters have an efficiency advantage compared to galvanically coupled DC / DC converters at high transformation ratios. The main fields of application of the insulating DC / DC converters are the transfer of energy from a high-voltage system to a low-voltage system in which touch protection cannot be implemented. Furthermore, in a small embodiment, they are used to generate a voltage in gate controls of high-side semiconductors which is above the high-voltage operating voltage (freedom of reference of the secondary side allows the addition of the two voltages). Disadvantages of the insulating DC / DC converters are the lower power density, the higher component outlay and the small variation of the transmission ratio, since this is determined mainly by the transformer and its actuation.EP 4 147 344 A1 describes a power converter circuit comprising: a full bridge inverter, a resonant circuit and a control circuit. The full bridge consists of a first branch and a second branch, each branch having two switches and a switching node between the switches, the switches of the first branch being different from those of the second branch. The resonant circuit is connected between the switching nodes and includes an inductor in series with a capacitance. The control circuit generates control signals for the switches according to a predefined scheme with two excitation phases and two passive conducting phases with a configurable duty cycle to achieve zero voltage switching.The invention is based on the object of specifying a novel DC / DC converter and a novel method for operating the same.The object is achieved according to the invention by a DC / DC converter having the features of claim 1 and by a method having the features of claim 4 or 10.Advantageous embodiments of the invention are the subject matter of the dependent claims.A DC / DC converter is proposed, comprising:a primary side having at least two half bridges, each having a high-side switch designed as a semiconductor switch and a low-side switch designed as a semiconductor switch,a secondary side having at least two half bridges, each having a high-side switch configured as a semiconductor switch and a low-side switch configured as a semiconductor switch,at least one LC resonant circuit, which is designed as a series resonant circuit and is arranged between a center tap of one of the half bridges on the primary side and a center tap of one of the half bridges on the secondary side,at least one further LC resonant circuit embodied as a series resonant circuit or a capacitor which is arranged between a center tap of a further one of the half bridges on the primary side and a center tap of a further one of the half bridges on the secondary side.In one embodiment, a source capacitance or an intermediate circuit capacitor is arranged on the primary side and / or a drain capacitance is arranged on the secondary side.In one embodiment, the semiconductor switches on the primary side are embodied as MOSFETs or IGBTs and / or the semiconductor switches on the secondary side are embodied as MOSFETS, IGBTs or diodes.According to one aspect of the present invention, a method for operating the above-described DC / DC converter is proposed, wherein the primary side is or is connected to a DC voltage source, wherein the secondary side is or is connected to a drain. According to the invention, the high-side switch of a first half bridge and the low-side switch of a second half bridge are switched on on the primary side at least substantially in push-pull with respect to the low-side switch of the first half bridge and the high-side switch of the second half bridge at a clock frequency, wherein the high-side switch of each half bridge is only switched on when the low-side switch of the same half bridge has been switched off and vice versa. This mode of operation can be used in a buck mode in which the voltage at the DC voltage source is higher than at the drain, and also as the basis of a boost mode in which the voltage at the DC voltage source is lower than at the drain.In an embodiment, the clock frequency for resonant switching is set at a natural frequency of the LC resonant circuit or lower.In one embodiment, in the boost mode, simultaneously with the switching on of the high-side switch of one of the half bridges of the primary side, the low-side switch of the half bridge connected thereto via one of the LC resonant circuits or the capacitor on the secondary side or the high-side switch of the other half bridge of the secondary side is initially switched on, wherein this low-side switch or high-side switch of the secondary side is driven with the same clock frequency, but with a smaller duty cycle than the simultaneously switching on semiconductor switches of the primary side.In one embodiment, the semiconductor switches of the primary side are only switched off when a reactor current through the at least one LC resonant circuit has decreased to zero.In one embodiment, the semiconductor switches of the primary side are driven with a duty cycle of less than 0.5.In one embodiment, the semiconductor switches of the secondary side are driven in boost mode with a duty cycle that has to be selected to be smaller than the duty cycle of the semiconductor switches of the primary side. The duty cycle of the semiconductor switches of the secondary side is dependent on the transmission ratio of the DC / DC converter to be represented, i.e. the ratio of secondary voltage to primary voltage. The duty cycle of the switches on the secondary side approaches the duty cycle of the switches on the primary side when the gear ratio needs to increase. An exemplary value in the simulation for boosting 400V to 600V is 0.2.According to one aspect of the present invention, a method for operating the above-described DC / DC converter, in particular in buck mode, is proposed, wherein the primary side is or is connected to a DC voltage source, wherein the secondary side is or is connected to a drain. The DC / DC converter is configured in three phases,wherein the primary side has three half bridges each having a high-side switch configured as a semiconductor switch and a low-side switch configured as a semiconductor switch,wherein the secondary side has three half bridges each having a high-side switch configured as a semiconductor switch and a low-side switch configured as a semiconductor switch. According to the invention, the high-side switch of each half bridge and the low-side switch of the same half bridge are connected at least substantially in a push-pull manner at a clock frequency on the primary side, wherein the three half bridges are driven with a phase offset of 120°.The DC / DC converter and the described methods can be used, for example, for charging a high-voltage battery of an electrically driven vehicle at a DC charging station.The solution according to the invention provides a voltage converter which fulfills some advantages of a galvanically insulating voltage converter based on a transformer and can nevertheless have a power density like a galvanically coupled voltage converter.The core feature of the voltage converter with LC resonant circuit is that the positive HV potential of the primary side is not directly connected to the positive HV potential of the secondary side and that the negative HV potential of the primary side does not have a direct connection to the negative HV potential of the secondary side. The connection between the HV potentials of the primary and secondary sides is effected via in each case one LC resonant circuit per potential. The capacitor ensures galvanic isolation. A rectangular voltage with a change in sign is generated from the DC operating voltage via semiconductor switches on the primary side by switching the semiconductor switches in alternation. Due to the AC component of this square-wave voltage, the capacitors do not represent an interruption, but an impedance, during operation. The inductances serve to limit the current in the switching operation of the semiconductor switches.The voltage converter has a DC insulation. Therefore, it is voltage-free at its secondary terminals and galvanically separated from the HV potentials of the primary side at both terminals, as long as the clocking of the primary side is deactivated. It is thus suitable as a connecting element of system boundaries at which galvanic isolation is necessary before startup, for example as in the case of contactors within the battery or in the case of insulating DC / DC converters with a transformer from one HV voltage to a second HV voltage. The voltage converter represents an interruption for DC currents in all poles. It can thus be used for power transmission to a less insulated HV system whose insulation layout is lower, e.g. from 800 V (1000 V insulation layout) to 400 V (500 V insulation layout). The potential distribution of the secondary side is independent of the primary side in the long term. The potential difference between the primary side and the secondary side can be adjusted by a superimposed DC voltage across the capacitors. With this converter concept, both a buck and a boost converter can be represented. A conversion of current-free switching processes is possible in order to increase the efficiency. The LC resonant circuit or the LC resonant circuits can be designed to be smaller and less complex than a transformer. The voltage converter is therefore smaller than an insulating voltage converter with transformer: it is lighter, more favorable and more efficient (no leakage flux in the transformer, no iron losses). The voltage converter is not limited to a transmission ratio of 2 as a charge pump. An interleaved operation is possible in order to increase the frequency of an interference suppression filter and thus to make the filter smaller.Exemplary embodiments of the invention are explained in more detail below with reference to drawings.The following are shown: FIG. 1 shows a schematic circuit diagram of a capacitively galvanically insulating DC / DC converter with two LC resonant circuits, FIG. 2 shows a schematic circuit diagram of the DC / DC converter in buck mode, FIG. 3 shows a schematic circuit diagram of the DC / DC converter in buck mode when two semiconductor switches are opened prematurely, FIG. 4 shows a schematic circuit diagram of the DC / DC converter in buck mode in a subsequent phase, FIG. 5 shows a schematic circuit diagram of the DC / DC converter in buck mode when two further semiconductor switches are opened prematurely, FIG. 6 shows a schematic circuit diagram of a simulation circuit of the DC / DC converter in buck mode, FIG. 7 is a schematic diagram of signals of the simulation circuit, FIG. 8 is a schematic view of a simulation circuit of a three-phase DC / DC converter with three LC resonant circuits, FIG. 9 shows a schematic diagram of signals of the simulation circuit from FIG. 8, FIG. 10 is a schematic view of the DC / DC converter of FIG. 1 in a boost mode, FIG. 11 is a schematic view of the DC / DC converter in boost mode in a subsequent state, FIG. 12 shows a schematic view of the DC / DC converter in boost mode in a state following FIG. 11 when two semiconductor switches are opened prematurely, FIG. 13 shows a schematic view of the DC / DC converter in boost mode in a further subsequent state, FIG. 14 shows a schematic view of the DC / DC converter in boost mode in a further subsequent state, FIG. 15 shows a schematic view of the DC / DC converter in boost mode in a subsequent freewheeling phase, FIG. 16 shows a schematic circuit diagram of a simulation circuit of the DC / DC converter in boost mode, and FIG. 17 is a schematic diagram of signals of the simulation circuit of FIG. 16.Corresponding parts are provided with the same reference numerals in all figures.FIG. 1 is a schematic circuit diagram of a capacitively galvanically insulating DC / DC converter 1 with two LC resonant circuits 2.1, 2.2. A direct voltage source 3 having a source capacitance CX_P is arranged on a primary side P of the DC / DC converter 1. On a secondary side S of the DC / DC converter 1, a load or a drain 4 with a drain capacitance CX_S is arranged. The primary side P has two half bridges HB 1, HB 2 each with two semiconductor switches S 1, S 2 and S 3, S 4. The secondary side S has two half bridges HB 3, HB 4 each having two semiconductor switches S 5, S 6 and S 7, S 8. The semiconductor switches S 1 to S 8 may be, for example, MOSFETs or IGBTs.In the DC / DC converter 1 shown, neither a positive high-voltage potential HV+1of the primary side P is directly connected to a positive high-voltage potential HV+2of the secondary side S nor a negative high-voltage potential HV- 1of the primary side P is directly connected to a negative high-voltage potential HV- 2of the secondary side S.The connection between the high-voltage potentials HV+1, HV+2, HV-1, HV-2 of the primary and secondary sides P, S is effected via in each case one LC resonant circuit 2.1, 2.2, in particular a series resonant circuit, for each high-voltage potential HV+1, HV+2, HV-1, HV-2, which is in each case arranged between a center tap of one of the half bridges HB 1, HB 2 on the primary side P and between a center tap of one of the half bridges HB 3, HB 4 on the secondary side S. In this case, the galvanic isolation is ensured by a capacitor C 1, C 2 in each of the LC resonant circuits 2.1, 2.2. A rectangular voltage with a change in sign is generated via the semiconductor switches S 1 to S 4 on the primary side P from a DC voltage of the DC voltage source 3 by alternating switching of the semiconductor switches S 1, S 3 and S 2, S 4. Due to the AC component of this square-wave voltage, the capacitors C 1, C 2 do not represent an interruption, but an impedance with the value X C=1 / ( ω·C), during operation. The LC resonant circuits 2.1, 2.2 each have an inductance L1, L2 which serves to limit the current in the switching operation of the semiconductor switches S1 to S4 (ω→∞, i.e. X C→0). In addition, the inductances L 1, L 2 can be used to build up an LC resonant circuit 2.1, 2.2 with the capacitances or capacitors C 1, C 2 and thus to enable current-free switching (ZCS) or voltage-free switching (ZVS) in the semiconductor switches S 1 to S 4. Both serve to avoid and / or reduce the switching losses in the semiconductor switches S 1 to S 4 and thus to increase the efficiency of the DC / DC converter 1.In order to construct a resonant circuit, at least one of the two inductances L 1 and L 2 is necessary (i.e. vice versa: instead of a total of two inductances L 1, L 2, one can be omitted in one path).In order to enable the advantages of galvanic isolation, however, both capacitances C 1 and C 2 are always necessary.The secondary side S likewise has four semiconductor switches S 5 to S 8. However, it is also possible to replace the semiconductor switches S 5 to S 8 of the secondary side S by diodes D (see FIG. 6 ). Thus, the DC / DC converter 1 would be unidirectional.The DC / DC converter 1 can function both as a buck converter (i.e. the input voltage is always greater than the output voltage) and as a boost converter (i.e. the output voltage is higher than the input voltage).FIG. 2 is a schematic circuit diagram of the DC / DC converter 1 in buck mode. In this case, the semiconductor switches S 1 and S 4 on the primary side P are or are initially switched through. The semiconductor switches S 2 and S 3 remain open. The semiconductor switches S 5 to S 8 on the secondary side are open and function as diodes D via their respective body diodes. a current I flows from the DC voltage source 3 via the semiconductor switch S 1, LC resonant circuit 2.1, the drain 4, LC resonant circuit 2.2 and the semiconductor switch S 4 back to the DC voltage source 3. If the semiconductor switches S 1 and S 4 remain closed during this half-sine oscillation, the opening of the semiconductor switches S 1, S 4 can subsequently take place without current. The following voltage is established across the capacitances C1 and C2 at the end:In this case: U_C1 is the voltage across the capacitor C1, U_C2 is the voltage across the capacitor C2, U P is the input voltage or voltage of the DC voltage source 3, U S is the output voltage or voltage at the drain 4.The peak value of the current is dependent on the input and output voltage of the DC / DC converter 1 and on the ohmic components in the circuit.FIG. 3 is a schematic circuit diagram of the DC / DC converter 1 in buck mode upon premature opening of the semiconductor switches S 1 and S 4 after the situation shown in FIG. 2. If the semiconductor switches S 1 and S 4 are opened while a current I is still flowing, a voltage of smaller magnitude is established across the capacitances C 1 and C 2. The switching operation would then lead to switching losses in the semiconductor switches S 1, S 4. By switching more quickly in comparison with the resonant frequency of the LC resonant circuit 2.1, 2.2, high current amounts can be avoided.If the semiconductor switches S 1 and S 4 are opened, although a positive current is impressed in the inductor L 1 and a negative current is impressed in the inductor L 2, a current flow (reverse current) from the LC resonant circuit 2.1 occurs via the body diode of the semiconductor switch S 5, the drain 4, the body diode of the semiconductor switch S 8, the LC resonant circuit 2.2, the body diode of the semiconductor switch S 3, the DC voltage source 3 and the body diode of the semiconductor switch S 2 back to the LC resonant circuit 2.1. This state is omitted in the case of resonant switching at the natural frequency of the LC resonant circuit 2.1, 2.2.The current flow via the DC voltage source 3 can be avoided if either the semiconductor switch S 4 or the semiconductor switch S 1 remains closed in this state. Alternatively, an intermediate circuit capacitor can also be placed at the input of the DC / DC converter 1, which reduces or eliminates the reverse current.FIG. 4 is a schematic circuit diagram of the buck mode DC / DC converter 1 in a subsequent stage in which the semiconductor switches S 2 and S 3 are turned on. This results in a state which is comparable to that of FIG. 2, in which the semiconductor switches S 1 and S 4 are switched on. However, the polarity of the current flow in chokes L1 and L2 is reversed. Thus, the capacitances C 1 and C 2 are discharged and charged in the opposite direction.FIG. 5 is a schematic circuit diagram of the DC / DC converter 1 in buck mode upon premature opening of the semiconductor switches S 2 and S 3 after the situation shown in FIG. 4. If the semiconductor switches S 2 and S 3 are opened, although a positive current is impressed in the inductor L 1 and a negative current is impressed in the inductor L 2, a current flow (reverse current) from the LC resonant circuit 2.1 occurs via the body diode of the semiconductor switch S 1, the DC voltage source 3, the body diode of the semiconductor switch S 4, the LC resonant circuit 2.2, the body diode of the semiconductor switch S 7, the sink 4 and the body diode of the semiconductor switch S 6 back to the LC resonant circuit 2.1. This state is omitted in the case of resonant switching at the natural frequency of the resonant circuit. The current flow via the DC voltage source 3 can be avoided if either the semiconductor switch S 2 or the semiconductor switch S 3 remains closed in this state.FIG. 6 is a schematic circuit diagram of a simulation circuit of the DC / DC converter 1 in buck mode.The DC / DC converter 1 can be operated in buck mode, for example, in the following configuration: the DC voltage source 3 can be, for example, a DC voltage charging station for an electrically driven vehicle. A voltage of the DC voltage source 3 is, for example, 800 V. The drain 4 can be, for example, a high-voltage battery of an electrically driven vehicle. A rated voltage of the drain 4 is, for example, 400 V. The DC / DC converter 1 can be configured to limit the current I across the chokes L 1, L 2 when 50 A is reached and to switch it on again at 30 A. Superimposed is a clock frequency f from two clock generators 5 of, for example, 200 kHz. The inductances L 1, L 2 are, for example, 10 μH. The capacitances C 1, C 2 are, for example, 100 μF. The duty cycle (duty cycle) d of the two clock generators 5 is, for example, 0.45.FIG. 7 is a schematic diagram of signals of the simulation circuit from FIG. 6 ; the time profile of a source current I_Q through the DC voltage source 3, a control signal Gate_S 1+S 4 at the gates of the semiconductor switches S 1 and S 4, a control signal Gate_S 2+S 3 at the gates of the semiconductor switches S 2 and S 3, a choke current I_L 1 through the choke L 1, a choke current I_L 2 through the choke L 2, a capacitor voltage U_C 1 through the capacitor C 1, a capacitor voltage U_C 2 through the capacitor C 2 and a sink current I_S through the sink 4 is illustrated, Since the DC / DC converter 1 between its H-bridge (semiconductor switches S 1 to S 4) and the DC voltage source 3 still has the source capacitance CX_P, which prevents current fluctuations with a reverse current across the DC voltage source 3. The control signals Gate_S1+S4, Gate_S2+S3 show that the clock frequency f has been selected to be quite high, so that the upper switch-off threshold of 50 A is not yet reached in the LC resonant circuits 2.1, 2.2. The capacitor voltages U_C1, U_C2 fluctuate around a DC value of about 0 V.The principle of the DC / DC converter 1 can in principle also be applied for polyphase, for example three-phase DC / DC converters 1.FIG. 8 is a schematic circuit diagram of a simulation example of a three-phase DC / DC converter 1 having three LC resonant circuits 2.1, 2.2, 2.3. A direct voltage source 3 having a source capacitance CX_P is arranged on a primary side P of the DC / DC converter 1. On a secondary side S of the DC / DC converter 1, a load or a drain 4 with a drain capacitance CX_S is arranged. The primary side P has three half bridges HB 1, HB 2, HB 3 each having two semiconductor switches S 1, S 2 and S 3, S 4 and S 5, S 6. The secondary side S has three half bridges HB 4, HB 5, HB 6 each having two semiconductor switches S 7, S 8 and S 9, S 10 and S 11, S 12. The semiconductor switches S 1 to S 12 may be, for example, MOSFETs or IGBTs.In the DC / DC converter 1 shown, neither a positive high-voltage potential HV+1of the primary side P is directly connected to a positive high-voltage potential HV+2of the secondary side S nor a negative high-voltage potential HV- 1of the primary side P is directly connected to a negative high-voltage potential HV- 2of the secondary side S.The connection between the high-voltage potentials HV+1, HV+2, HV-1, HV-2 of the primary and secondary sides P, S is effected via in each case one LC resonant circuit 2.1, 2.2, 2.3, in particular a series resonant circuit, for each high-voltage potential HV+1, HV+2, HV-1, HV-2, which is in each case arranged between a center tap of one of the half bridges HB 1, HB 2, HB 3 on the primary side P and between a center tap of one of the half bridges HB 4, HB 5, HB 6 on the secondary side S. In this case, the galvanic isolation is ensured by a capacitor C 1, C 2, C 3 in each of the LC resonant circuits 2.1, 2.2, 2.3. The half bridges HB 1 to HB 3 are driven with 120° phase offset with respect to one another (similar to fundamental frequency clocking in inverters).The DC / DC converter 1 can be operated in buck mode, for example, in the following configuration: the DC voltage source 3 can be, for example, a DC voltage charging station for an electrically driven vehicle. A voltage of the DC voltage source 3 is, for example, 800 V. The drain 4 can be, for example, a high-voltage battery of an electrically driven vehicle. A rated voltage of the drain 4 is, for example, 400 V. The semiconductor switches S 1 to S 6 are driven at a clock frequency f from a clock generator 5 of, for example, 200 kHz. The inductances L 1, L 2, L 3 are, for example, 10 μH. The capacitances C 1, C 2, C 3 are, for example, 10 μF. The duty cycle (duty cycle) d of the clock generator 5 is, for example, 0.5.FIG. 9 is a schematic diagram of signals of the simulation circuit from FIG. 8, which illustrates the temporal profile of a source current I_Q by the DC voltage source 3, of control signals Gate_S1, Gate_S3, Gate_S5 at the gates of the semiconductor switches S 1, S 3 and S 5, of the inductor currents I_L1, I_L2, I_L3 by the inductors L 1, L 2, L 3, of the capacitor voltages U_C 1, U_C 2, U_C 3 by the capacitors C 1, C 2, C 3 and of a drain current I_S by the drain 4.In comparison with the DC / DC converter 1 having two half bridges HB 1, HB 2, the three LC resonant circuits 2.1, 2.2, 2.3 are not operated simultaneously, but with a 120° phase offset. The input and output frequency of the current ripple is accordingly three times higher than the frequency of the currents in the resonant circuits 2.1, 2.2, 2.3.Reference will be made again to the DC / DC converter 1 shown in FIG. 1. If an insulation fault occurs on one of the two sides during operation of the DC / DC converter 1 from FIG. 1, this fault is transmitted to the respective other side at the first instant. However, in the further course, the side without potential faults automatically balances itself again and reaches a high-voltage potential distribution with respect to a potential compensation line PA as before the insulation fault occurs. The connection side with the insulation fault still remains completely unsymmetrical here, viewed from the high-voltage potentials HV+1, HV+2, HV-1, HV-2.If the insulation fault takes place, for example, on the primary side P from the positive high-voltage potential HV+1 to the potential compensation line PA, this first causes a shift of the high-voltage potentials HV+2, HV-2 on the secondary side S. If the insulation on the secondary side S should be designed to be weaker (for example to 500 V), this could lead to a brief overload of the insulation. However, over the course of a few seconds, the HV potential distribution returns to its original state. In this case, the two capacitances C 1, C 2 in the LC resonant circuit 2.1, 2.2 are charged with a DC value which corresponds to half the primary voltage.FIG. 10 is a schematic view of the DC / DC converter 1 of FIG. 1 in boost mode.The semiconductor switches S 1, S 4 and S 6 are turned on. If the output voltage across the drain 4 is higher than the input voltage at the DC voltage source 3 on the primary side P, then energy must first be stored in a reactor L 1, L 2, similar to a galvanically coupled (inductive) boost converter, in order to achieve a higher voltage level on the secondary side S in a second phase with the aid of this energy and the voltage induced by the reactor L 1, L 2.In the case of the capacitively insulating converter, the inductances L1 and L2 are used for this purpose. In a first phase, a short circuit is generated by the closing of the semiconductor switch S 6 on the secondary side S. The current I flows from the DC voltage source 3 via the semiconductor switch S 1, LC resonant circuit 2.1, semiconductor switch S 6, body diode of the semiconductor switch S 8, LC resonant circuit 2.2 and semiconductor switch S 4 back to the DC voltage source 3. Alternatively, instead of the semiconductor switch S 6, the semiconductor switch S 7 can also be closed, so that the current flows via the body diode of the semiconductor switch S 5. In this phase, no power is transmitted to the secondary side S.FIG. 11 is a schematic view of the DC / DC converter 1 in the boost mode in a state following FIG. 10. In this case, the previously opened semiconductor switch S 6 or S 7 is opened. The current impressed in the chokes L 1 and L 2 generates an induced voltage, whereby a current flow to the secondary side S to a higher voltage level is possible. Power is thus now transmitted to the secondary side S. In this case, the current flows from the DC voltage source 3 via the semiconductor switch S 1, the LC resonant circuit 2.1, the body diode of the semiconductor switch S 5, the drain 4, the body diode of the semiconductor switch S 8, the LC resonant circuit 2.2 and the semiconductor switch S 4 back to the DC voltage source 3.FIG. 12 is a schematic view of the DC / DC converter 1 in the boost mode in a state following FIG. 11 when the semiconductor switches S 1 and S 4 are opened prematurely. If these are opened, although a current is still impressed in the LC resonant circuits 2.1, 2.2, a return current results from the LC resonant circuit 2.1 via the body diode of the semiconductor switch S5, the drain 4, the body diode of the semiconductor switch S8, the LC resonant circuit 2.2, the body diode of the semiconductor switch S3, the DC voltage source 3 and the body diode of the semiconductor switch S2 back to the LC resonant circuit 2.1. This state can be avoided by waiting until the current in the LC resonant circuits 2.1, 2.2 has returned to zero. This is called intermittent operation. The advantage is that current-free switching on and off of the semiconductor switches S 1 and S 4 on the primary side P is made possible, as a result of which the switching losses can be avoided there. In addition, by avoiding the reverse current via the DC voltage source 3, ohmic losses in this circuit are avoided.FIG. 13 is a schematic view of the boost mode DC / DC converter 1 in a subsequent state in which the semiconductor switches S 2, S 3, and S 8 are turned on. This results in a state which is comparable to that of FIG. 10, where the semiconductor switches S 1, S 4 and S 6 are switched on. However, the polarity of the current flow in chokes L1 and L2 is reversed. In a first phase, a short circuit is generated by the closing of the semiconductor switch S 8 on the secondary side S. The current flows from the DC voltage source 3 via the semiconductor switch S 3, LC resonant circuit 2.2, semiconductor switch S 8, the body diode of the semiconductor switch S 6, LC resonant circuit 2.1 and semiconductor switch S 2 back to the DC voltage source 3. Thus, the capacitances C 1 and C 2 are discharged and charged in the opposite direction. In this case, no power is transmitted to the secondary side S. Alternatively to the semiconductor switch S 8, the semiconductor switch S 5 can also be closed.FIG. 14 is a schematic view of the DC / DC converter 1 in boost mode in a subsequent state, wherein the previously opened semiconductor switch S 8 or S 5 is opened. The current impressed in the chokes L 1 and L 2 generates an induced voltage, whereby a current flow to the secondary side S to a higher voltage level is possible. Thus, the capacitances C 1 and C 2 are discharged and charged in the opposite direction. Power is thus now transmitted to the secondary side S. In this case, the current I flows from the DC voltage source 3 via the semiconductor switch S 3, the LC resonant circuit 2.2, the body diode of the semiconductor switch S 7, the drain 4, the body diode of the semiconductor switch S 6, the LC resonant circuit 2.1 and the semiconductor switch S 2 back to the DC voltage source 3.FIG. 15 is a schematic view of the DC / DC converter 1 in boost mode in a subsequent free-wheeling phase in which all semiconductor switches S 1 to S 8 are opened and / or remain, wherein a negative current I_L 1 (in the direction of the primary side P) flows in the reactor L 1. This state is comparable to the state in which all semiconductor switches S 1 to S 8 are opened and a positive current I_L 1 (in the direction of secondary side S) is impressed in reactor L 1.FIG. 16 is a schematic circuit diagram of a simulation circuit of the DC / DC converter 1 in the boost mode.The DC / DC converter 1 can be operated in boost mode, for example, in the following configuration: the DC voltage source 3 can be, for example, a DC voltage charging station for an electrically driven vehicle. A voltage of the DC voltage source 3 is, for example, 400 V. The drain 4 can be, for example, a high-voltage battery of an electrically driven vehicle. A rated voltage of the drain 4 is 600 V, for example. A clock frequency f from four clock generators 5 of 20 kHz, for example, is used for the semiconductor switches S 1 to S 4, S 6 and S 8. The inductances L 1, L 2 amount to, for example, 100 μH. The capacitances C 1, C 2 are, for example, 10 μF. The duty cycle (duty cycle) d of the two clock generators 5 for the semiconductor switches S 1 to S 4 is, for example, 0.45. the duty cycle d 2 of the two clock generators 5 for the semiconductor switches S 6 and S 8 is, for example, 0.2.FIG. 17 is a schematic diagram of signals of the simulation circuit of FIG. 16 ; the time profile of a source current I_Q due to the DC voltage source 3, a control signal Gate_S 1+S 4 due to the gates of the semiconductor switches S 1 and S 4, a control signal Gate_S 6 due to the gate of the semiconductor switch S 6, a control signal Gate_S 2+S 3 due to the gates of the semiconductor switches S 2 and S 3, a control signal Gate_S 8 due to the gate of the semiconductor switch S 8, a choke current I_L 1 due to the choke L 1, a choke current I_L 2 due to the choke L 2, a capacitor voltage U_C 1 due to the capacitor C 1 is illustrated, a capacitor voltage U_C2 across the capacitor C2 and a drain current I_S through the drain 4. During this time, the throttle current I_L1, I_L2 in the throttles L1 and L2 increases in terms of amount. The sink current I_S in the sink 4 remains at 0 A during this time. As soon as the semiconductor switches S 6, S 8 on the secondary side S are opened, the throttle currents I_L 1, I_L 2 in the chokes L 1 and L 2 reduce and a sink current I_S is transmitted to the sink 4. The semiconductor switches S 1 to S 4 on the primary side P are now opened and a reverse current is produced via the DC voltage source 3.In a simulation for the method of one embodiment, the semiconductor switches of the primary side are driven with a duty cycle of less than 0.5.In addition, the semiconductor switches of the secondary side are controlled in the boost mode with a duty cycle that has to be selected to be smaller than the duty cycle of the semiconductor switches of the primary side. The duty cycle of the semiconductor switches of the secondary side is dependent on the transmission ratio of the DC / DC converter to be represented, i.e. the ratio of secondary voltage to primary voltage. The duty cycle of the switches on the secondary side approaches the duty cycle of the switches on the primary side when the gear ratio needs to increase. An example value in the simulation of FIG. 17 for boosting 400V to 600V is from 0.2.List of reference characters1 DC / DC converter 2.1, 2.2, 2.3 LC resonant circuit 3 DC voltage source 4 drain 5 clock generator D diode P primary side S secondary side C1, C2, C3 capacitor, capacitance CX_P source capacitance CX_S drain capacitance Gate_S1 control signal Gate_S3 control signal Gate_S5 control signal Gate_S6 control signal Gate_S8 control signal Gate_S1+S4 control signal Gate_S2+S3 control signal HB1 to HB6 half bridge HV+1, HV+2, HV-1, Hv-2 High-voltage potential I Current I_L1 Inductor current I_L2 Inductor current I_L3 Inductor current I_Q Source current I_S Sink current L1, L2, L3 Inductance, Inductor S1 to S12 Semiconductor switch U_C1 Capacitor voltage U_C2 Capacitor voltage U_C3 Capacitor voltageReferences included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedEP 4 147 344 A1

[0005]

Claims

DC / DC converter (1), having: - a primary side (P) having at least two half bridges (HB1, HB2) each having a high-side switch designed as a semiconductor switch (S1, S3) and a low-side switch designed as a semiconductor switch (S2, S4), - a secondary side (S) having at least two half bridges (HB3, HB4) each having a high-side switch designed as a semiconductor switch (S5, S7, D) and a low-side switch designed as a semiconductor switch (S6, S8, D), - at least one LC resonant circuit (2.1, 2.2) designed as a series resonant circuit which is connected between a center tap of one of the half bridges (HB1, Hb2) on the primary side (P) and a center tap of one of the half bridges (HB3, HB4) on the secondary side (S), - at least one further LC resonant circuit (2.1, 2.2) designed as a series resonant circuit or a capacitor (C1, C2) which is arranged between a center tap of a further one of the half bridges (HB1, HB2) on the primary side (P) and a center tap of a further one of the half bridges (HB3, HB4) on the secondary side (S).DC / DC converter (1) according to Claim 1, characterized in that a source capacitor (CX_P) or an intermediate circuit capacitor is arranged on the primary side (P), and / or in that a drain capacitor (CX_S) is arranged on the secondary side (S).DC / DC converter (1) according to Claim 1 or 2, characterized in that the semiconductor switches (S1 to S4) on the primary side (P) are designed as MOSFETs or IGBTs and / or in that the semiconductor switches (S5 to S8) on the secondary side (S) are designed as MOSFETS, IGBTs or diodes (D).Method for operating the DC / DC converter (1) according to one of the preceding claims, wherein the primary side (P) is or is connected to a DC voltage source (3), wherein the secondary side (S) is or is connected to a drain (4), characterized in that, on the primary side (P), the high-side switch of a first half bridge (HB1, HB2) and the low-side switch of a second half bridge (HB3, HB4) are switched at least substantially in push-pull with respect to the low-side switch of the first half bridge (HB1 HB2) and the high-side switch of the second half bridge (HB3, HB4) at a clock frequency, wherein the high-side switch of each half bridge (HB1, hb2) is only turned on when the low-side switch of the same half bridge (HB1, HB2) has been turned off and vice versa.Method according to claim 4, characterised in that the clock frequency for resonant switching is set at a natural frequency of the LC resonant circuit (2.1, 2.2) or higher.Method according to Claim 4 or 5, characterized in that, in a boost mode, simultaneously with the switching on of the high-side switch, one of the half bridges (HB1, HB2) of the primary side (P) is initially switched on the low-side switch of the half bridge (HB3, HB4) on the secondary side (S) connected thereto via one of the LC resonant circuits (2.1, 2.2) or the capacitor (C1, C2) or the high-side switch of the other half bridge (HB3, HB4) of the secondary side (S), this low-side switch or high-side switch of the secondary side (S) being switched on at the same clock frequency, However, the switching ratio is selected to be smaller than that of the simultaneously switching-on semiconductor switches (S1 to S4) of the primary side (P).Method according to one of Claims 4 to 6, characterized in that the semiconductor switches (S1 to S4) of the primary side (P) are only switched off when a choke current (I_L1, I_L2) has decreased to zero by the at least one LC resonant circuit (2.1, 2.2).Method according to one of Claims 4 to 7, characterized in that the semiconductor switches (S1 to S4) of the primary side (P) are actuated with a duty cycle of at most 0.5.Method according to one of Claims 4 to 8, characterized in that the semiconductor switches (S5 to S8) of the secondary side (S) are driven with a duty cycle which is selected to be smaller than the duty cycle of the semiconductor switches (S1 to S4) of the primary side.Method for operating the DC / DC converter (1) according to one of Claims 1 to 3, wherein the primary side (P) is or is connected to a DC voltage source (3), wherein the secondary side (S) is or is connected to a drain (4), - wherein the primary side (P) has three half bridges (HB1, HB2, HB3) each having a high-side switch formed as a semiconductor switch (S1, S3, S5) and a low-side switch formed as a semiconductor switch (S2, S4, S6), - wherein the secondary side (S) has three half bridges (HB4, HB5, HB6) each having a low-side switch formed as a semiconductor switch (S7, S9, S11, D) and one low-side switch each formed as a semiconductor switch (S8, S10, S12, D), characterized in that, on the primary side (P), the high-side switch of each half bridge (HB1, HB2, HB3) and the low-side switch of the same half bridge (HB1, HB2, HB3) are switched at least substantially in a push-pull manner with a clock frequency, wherein the three half bridges (HB1, HB2, HB3) are driven with a phase offset of 120°.

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