Semiconductor package with optically coupled IC chips and method for manufacturing

Abstract

Semiconductor package with: a substrate; a first IC chip (IC: integrated circuit) and a second IC chip over the substrate, the first and second IC chips being arranged in a recess in the substrate at the center thereof; a laser device (LD) chip over the substrate at a periphery of the substrate, the LD chip being adjacent to the second IC chip and configured to generate a laser beam; and a photonic chip above the first and second IC chips and level with the LD chip, the photonic chip configured to modulate the laser beam in response to an electrical signal from the second IC chip and to direct the modulated laser beam to the first IC chip.

Description

background

[0001] A system-on-a-chip (SoC) is traditionally constructed from a single integrated circuit (IC) chip containing all functionalities. Recently, however, a chiplet design has emerged. Instead of a single large IC chip, several smaller IC chips are encapsulated together to form an SoC. The smaller IC chips are aptly called chiplets and implement individual functional blocks of the SoC. Among other things, chiplet design makes it possible to reduce waste, increase yields, and produce smaller components and larger chips.

[0002] US 2018 / 0275359 A1 discloses an optical transceiver by hybrid multichip integration. The optical transceiver includes a printed circuit board having a plurality of prefabricated surface interconnect pads. A first chip includes a FOWLP package of a plurality of electronic devices embedded in a dielectric mold layer overlying a dielectric redistribution layer and is arranged on the printed circuit board by connecting a plurality of conductive balls between the dielectric redistribution layer and the plurality of prefabricated surface interconnect pads, respectively, while exposing solder material filled in a plurality of through-hole vias (TMVs) in the dielectric mold layer. The optical transceiver also includes a second chip configured as a siphon chip and including photonic devices embedded in an SOI wafer substantially free of any electronic device process.The second chip is stacked over the first chip, with multiple conductive balls each connected to the solder material in the multiple TMVs.

[0003] US 2021 / 0271020 A1 discloses a structure comprising an optical interposer mounted on a package substrate, the optical interposer comprising a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending across the silicon waveguide, across the first photonic component, and across the second photonic component, the interconnect structure being electrically connected to the first photonic component and to the second photonic component, a first semiconductor device mounted on the interconnect structure, the first semiconductor device being electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device mounted on the interconnect structure.wherein the second semiconductor device is electrically connected to the second photonic component by the connection structure.,

[0004] US 2021 / 0018360 A1 discloses an electronic packaging structure. A photonic chip is arranged on an electronic package, and an optical guide chip is not arranged on the electronic package.

[0005] The invention is defined in the claims. Short description of the drawings

[0006] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a cross-sectional view of some embodiments of a semiconductor package with IC chips that are optically coupled to each other. The Fig. 2A and Fig. 2B show various top views of some embodiments of the semiconductor package of Fig. 1, where the IC chips have one-way communication. The Fig. 3A and Fig. 3B show various top views of some embodiments of the semiconductor package of Fig. 1, where the IC chips have two-way communication. The Fig. 4A and Fig. 4B show various sectional views of some embodiments of the IC chips of Fig. 1. Fig. 5 shows a sectional view of some embodiments of the semiconductor package of Fig. 1, in which substrate vias (TSVs) extend through a carrier substrate. Fig. 6 shows a sectional view of some alternative embodiments of the semiconductor package of Fig. 1, in which a photonic chip is arranged between the IC chips. The Fig. 7A and Fig. 7B show various top views of some embodiments of the semiconductor package of Fig. 6, in which the IC chips each have one-way and two-way communication. Fig. Figure 8 shows a sectional view of some embodiments of the semiconductor package of Fig. 6, in which TSVs extend through a carrier substrate. Fig. 9 shows a top view of some embodiments of the semiconductor package of Fig. 6, where the semiconductor package contains additional IC chips. The Fig. 10A and Fig. 10B show various sectional views of some alternative embodiments of the semiconductor package of Fig. 1, where the semiconductor package has multiple IC chip levels and multiple photonic chip levels. The Fig. 11A and Fig. 11B show various top views of some embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, where the IC chips have one-way communication. The Fig. 12A and Fig. 12B show various top views of some embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, where the IC chips have two-way communication. The Fig. 13A and Fig. 13B show sectional views of some embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, in which TSVs extend through a carrier substrate. Fig. 14 shows a sectional view of some alternative embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, in which the semiconductor package has multiple laser device chip levels. The Fig. 15A and Fig. 15B show various top views of some embodiments of the semiconductor package of Fig. 14, where the IC chips each have one-way and two-way communication. Fig. 16 shows a sectional view of some embodiments of the semiconductor package of Fig. 14, in which TSVs extend through a carrier substrate. The Fig. 17A, 17B, 18A, 18B and 19 to 21 show a series of illustrations of some embodiments of a method for simultaneously aligning and bonding a chip to a substrate. The Fig. 22A and Fig. 22B show various top views of some alternative embodiments of the substrate and the chip of the Fig. 17A, 17B, 18A, 18B and 19 to 21. The Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29 show a series of illustrations of some alternative embodiments of the method of Fig. 17A, 17B, 18A, 18B and 19 to 21, in which substrate openings have stepped profiles and stepped top geometries. The Fig. 30A and Fig. 30B show various top views of some alternative embodiments of the substrate and the chip of the Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29. The Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B show a series of illustrations of some alternative embodiments of the method of Fig. 17A, 17B, 18A, 18B and 19 to 21, in which the substrate openings are replaced by substrate projections. The Fig. 36A and Fig. 36B show various top views of some alternative embodiments of the substrate and the chip of the Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B. The Fig. 37A to 37G show sectional views of various other embodiments of semiconductor packages in which, according to the methods described with reference to the Fig. 17A to 36B, components were simultaneously aligned and bonded to each other. The Fig. 38 to 42 show a series of cross-sectional views of some embodiments of a method for manufacturing a semiconductor package having IC chips that are optically coupled to one another. Fig. 43 shows a block diagram of some embodiments of the method of Fig. 38 to 42. Detailed description

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, the fabrication of a first element over or on top of a second element may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] A system-on-a-chip (SoC) with a chiplet design may include a plurality of integrated circuit chiplets encapsulated together. For example, the SoC may include a memory controller chiplet and a memory chiplet encapsulated together. The integrated circuit chiplets implement individual functional blocks of the SoC and communicate electrically.

[0010] Because the functional blocks are distributed among the IC chiplets, electrical paths between functional blocks can be longer than if the functional blocks were integrated into a single IC chip. Longer electrical paths result in higher resistance, greater latency, and higher power consumption. Furthermore, longer electrical paths lead to noise and signal loss along the electrical paths. Therefore, these chiplets can have individual circuits for filtering noise, amplifying signals, and so on. However, these circuits increase the size of the chiplets and make them more complex and expensive.

[0011] Various embodiments of the present disclosure are directed to a semiconductor package including optically coupled IC chips. In some embodiments, the semiconductor package corresponds to an SoC with a chiplet design, so the optically coupled IC chips may also be referred to as optically coupled IC chiplets.

[0012] First and second IC chips are disposed adjacent to each other over a center of a carrier substrate. A photonic chip is disposed above the first and second IC chips and is electrically connected to the second IC chip. A laser device chip is disposed above the carrier substrate, adjacent to the photonic chip and the second IC chip, at a periphery of the carrier substrate. The photonic chip is configured to modulate a laser beam from the laser device chip according to an electrical signal from the second IC chip and provide the modulated laser beam to the first IC chip. The first IC chip has a photodetector configured to convert the modulated laser beam into an electrical signal. This allows the second IC chip to optically communicate with the first IC chip.

[0013] Optical signals can be transmitted over longer distances and with lower power consumption and less delay than electrical signals. Therefore, with optical communication, the first and second IC chips can communicate with lower power consumption and less delay than would otherwise be possible with electrical communication. Furthermore, optical signals are less susceptible to noise and signal loss than electrical signals. Therefore, circuits for filtering noise, amplifying signals, and the like can be omitted from the first and second IC chips, or the IC chips can have simpler circuits for performing these functions than would be possible with electrical communication. This, in turn, allows the first and second IC chips to be smaller in size or have higher feature density, lower complexity, and lower cost.

[0014] In Fig. 1 shows a cross-sectional view 100 of some embodiments of a semiconductor package with a plurality of IC chips 102 that are optically coupled to one another. The IC chips 102 are arranged over a central portion 104c of a carrier substrate 104 and implement individual functional blocks of the semiconductor package. Furthermore, the IC chips 102 include a first IC chip 102a and a second IC chip 102b. In some embodiments, the semiconductor package corresponds to an SoC with a chiplet design, so the IC chips 102 may also be referred to as IC chiplets.

[0015] The first and second IC chips 102a, 102b are defined by a recess 106 of the carrier substrate 104, and the first IC chip 102a further includes a photodetector 108a. The photodetector 108a is configured to receive an optical signal and convert it into an electrical signal. As explained later, the optical signal is modulated according to an electrical signal from the second IC chip 102b, allowing the second IC chip 102b to communicate with the first IC chip 102a.

[0016] A photonic chip 110a is disposed above the first and second IC chips 102a, 102b and is electrically connected to the second IC chip 102b. The photonic chip 110a includes a light modulator 112a and a plurality of waveguides and couplers (not shown). The light modulator 112a is configured to modulate a laser beam 114 according to an electrical signal 116 received from the second IC chip 102b. An input coupler is configured to receive the laser beam 114 from a laser device chip 118a, and an input waveguide is configured to guide the laser beam 114 from the input coupler to an input of the light modulator 112a.In addition, an output waveguide is configured to guide a modulated laser beam 120 from an output of the light modulator 112a, and an output coupler is configured to couple the modulated laser beam 120 from the output waveguide into the photodetector 108a.

[0017] The laser device chip 118a is adjacent to the second IC chip 102b and the photonic chip 110a at a peripheral portion 104p of the carrier substrate 104. Furthermore, the laser device chip 118a is arranged outside the recess 106, at the same height as the photonic chip 110a. The laser device chip 118a is configured to generate the laser beam 114, which is then modulated in the photonic chip 110a according to the electrical signal 116 received from the second IC chip 102b. Through this modulation, the second IC chip 102b can optically communicate with the first IC chip 102a. Since the laser device chip 118a is configured to emit the laser beam 114, the laser device chip 118a may also be referred to as a laser emission chip or the like.

[0018] Optical signals can be transmitted over longer distances and with lower power consumption and less delay than electrical signals. Therefore, with optical communication, the first and second IC chips 102a, 102b can communicate with lower power consumption and less delay than would otherwise be possible with electrical communication. Furthermore, optical signals are less susceptible to noise and signal loss than electrical signals. Therefore, the first and second IC chips 102a, 102b can omit circuits for filtering out noise, amplifying signals, and the like, or they can have simpler circuits for performing these functions than would actually be required with electrical communication.This in turn allows the first and second IC chips 102a, 102b to have a smaller size or higher functional density, lower complexity and lower cost.

[0019] Let us stay with Fig. 1. A plurality of pads 122 are disposed in and / or on the photonic chip 110a, the IC chips 102, the laser device chip 118a, and the carrier substrate 104 to establish an electrical connection between them. For example, at a boundary between the photonic chip 110a and the second IC chip 102b, the pads 122 establish an electrical connection between the photonic chip 110a and the second IC chip 102b. As another example, at a boundary between the carrier substrate 104 and the laser device chip 118a, the pads 122 establish an electrical connection between the carrier substrate 104 and the laser device chip 118a. The pads 122 are conductive and may be or include, for example, a metal, a metal alloy, one or more other suitable conductive materials, or a combination thereof.

[0020] It should be noted that for simplicity, only some of the pads 122 are illustrated. Although not illustrated, further conductive features may be disposed in and / or on the photonic chip 110a, the IC chips 102, the laser device chip 118a, and the carrier substrate 104. The further conductive features define conductive paths leading to the pads 122 to electrically connect the pads 122 to devices and / or structures in and / or on the photonic chip 110a, the IC chips 102, the laser device chip 118a, and the carrier substrate 104. The further conductive features may be, for example, wires, vias, contacts, and the like. Furthermore, the further conductive features may also be referred to as interconnect elements, for example.

[0021] In some embodiments, the first and second IC chips 102a, 102b have individual top surfaces that are level with or approximately level with a top surface of the carrier substrate 104. Furthermore, in some embodiments, the first and second IC chips 102a, 102b are spaced apart from each other and / or from sidewalls of the carrier substrate 104 in the recess 106. In some embodiments, the first and second IC chips 102a, 102b implement functional blocks of an SoC. For example, the first IC chip 102a may implement a memory controller, while the second chip 102b may implement DDR2 (Double Data Rate 2) memory, or vice versa. As another example, the first IC chip 102a may implement a memory controller, while the second chip 102b may implement a central processing unit (CPU), or vice versa.

[0022] In some embodiments, the carrier substrate 104 is a bulk substrate made of microcrystalline silicon or another semiconductor material. In other embodiments, the carrier substrate 104 is a glass substrate or the like. In still further embodiments, the carrier substrate 104 comprises a semiconductor substrate and an interconnect structure on the semiconductor substrate. In some embodiments where the carrier substrate 104 is or comprises a semiconductor material, the semiconductor material is undoped. For example, the carrier substrate 104 may be undoped monocrystalline silicon.

[0023] In some embodiments, the laser device chip 118a is or includes a laser diode or the like configured to generate the laser beam 114. In some embodiments, a bottom surface of the laser device chip 118a is flush with or approximately flush with a bottom surface of the photonic chip 110a. Furthermore, in some embodiments, the bottom surface of the laser device chip 118a is flush with or approximately flush with individual top surfaces of the first and second IC chips 102a, 102b.

[0024] In the Fig. 2A and Fig. 2B are various top views 200A and 200B of some embodiments of the semiconductor package of Fig. 1, in which the first and second IC chips 102a, 102b have one-way communication. The sectional view 100 of Fig. 1 may, for example, be drawn along a line A - A' or along another suitable line. As will be explained below and can be seen, Fig. 2A directed to a plane of the first and second IC chips 102a, 102b, and Fig. 2B is directed to a plane of the photonic chip 110a.

[0025] In the top view 200A of Fig. 2A, the first IC chip 102a has a plurality of photodetectors 108, which detect the photodetector 108a of Fig. 1. In addition, each of the photodetectors 108 is such as the photodetector 108a of Fig. 1. Thus, the photodetectors 108 are configured to receive respective optical signals and convert them into electrical signals.

[0026] A plurality of laser device chips 118 comprising the laser device chip 118a of Fig. 1, adjoins the second IC chip 102b and the photonic chip 110a outside the recess 106. The laser device chips 118 correspond to the photodetectors 108 and are each as the laser device chip 118a of Fig. 1. Thus, the laser device chips 118 are configured to generate laser beams 114 directed toward the photonic chip 110a. In some embodiments, the laser device chips 118 and the photodetectors are in a one-to-one relationship.

[0027] Let us now turn to the top view 200B of Fig. 2B, in which the photonic chip 110a has a plurality of light modulators 112, which modulate the light modulator 112a of Fig. 1. In addition, the photonic chip 110a includes a plurality of input couplers 202, a plurality of input waveguides 204, a plurality of output waveguides 206, and a plurality of output couplers 208, which together form a plurality of input and output light paths.

[0028] The light modulators 112 correspond to the photodetectors 108, and they also include the laser device chips 118. In some embodiments, the light modulators 112 are in a one-to-one relationship with the photodetectors 108, and / or they are in a one-to-one relationship with the laser device chips 118. In addition, the light modulators 112 are each such as the light modulator 112a of Fig. 1. Thus, the light modulators 112 are configured to each receive the laser beams 114 from the laser device chips 118 and modulate them into modulated laser beams 120 in accordance with respective electrical signals received from the second IC chip 102b.

[0029] The input couplers 202 and the input waveguides 204 form a plurality of input light paths corresponding to the light modulators 112, and the output waveguides 206 and the output couplers 208 form a plurality of output light paths corresponding to the light modulators 112. Each of the input light paths includes a respective input coupler 202 and a respective input waveguide 204 connected in series. Each of the output light paths includes a respective output waveguide 206 and a respective output coupler 208 connected in series.

[0030] The input couplers 202 are configured to receive the laser beams 114 from the laser device chips 118, and the input waveguides 204 are configured to guide laser beams 114 from the input couplers 202 to inputs of the light modulators 112. In some embodiments, the input couplers 202 are in a one-to-one relationship with the light modulators 112, and the input waveguides 204 are also in a one-to-one relationship with the light modulators 112. Therefore, in some embodiments, the input light paths are also in a one-to-one relationship with the light modulators 112.

[0031] The output waveguides 206 are configured to guide the modulated laser beams 120 from outputs of the light modulators 112 to the output couplers 208, and the output couplers 208 are configured to couple the modulated laser beams 120 from the output waveguides 206 into the photodetectors 108 of the first IC chip 102a. The output couplers 208 may be, for example, grating couplers or another suitable type of coupler. In some embodiments, the output waveguides 206 are in a one-to-one relationship with the light modulators 112, and the output couplers 208 are also in a one-to-one relationship with the light modulators 112. Therefore, in some embodiments, the output light paths are also in a one-to-one relationship with the light modulators 112.

[0032] The Fig. 2A and Fig. 2B show two photodetectors 108, two light modulators 112, and two laser device chips 118, but additional photodetectors, additional light modulators, and additional laser device chips are also possible. Each of the ellipses is used to represent zero or more of the corresponding structures. In some embodiments, the semiconductor package includes twenty photodetectors 108, twenty light modulators 112, and twenty laser device chips 118. In alternative embodiments, other suitable numbers are also possible.

[0033] In the Fig. 3A and Fig. 3B are various top views 300A and 300B of some embodiments of the semiconductor package of Fig. 1, in which the first and second IC chips 102a, 102b have two-way communication. The sectional view 100 of Fig. 1 may, for example, be drawn along a line A - A' or along any other suitable line. Fig. 3A is directed to a plane of the first and second IC chips 102a, 102b, and Fig. 3B is directed to a plane of the photonic chip 110a. As can be seen below, the structure shown in the Fig. 2A and Fig. 2B and described with reference thereto, is repeated for each communication direction, thereby enabling two-way communication.

[0034] Let us now turn to the top view 300A of Fig. 3A, in which the first and second IC chips 102a, 102b each have a plurality of photodetectors 108. The plurality of photodetectors 108 of the first chip 110a includes the first photodetector 108a of Fig. 1, and the plurality of photodetectors 108 of the second IC chip 102b includes a second photodetector 108b. In addition, the photodetectors 108 of the first and second IC chips 102a, 102b are each as the first photodetector 108a of Fig. 1, and thus the photodetectors 108 are configured to receive respective optical signals and convert them into electrical signals, respectively.

[0035] A plurality of laser device chips 118 are divided into a first group 302a and a second group 302b, each arranged on opposite sides of the recess 106. The first group 302a includes the first laser device chip 118a of Fig. 1 and is adjacent to the second IC chip 102b and the first photonic chip 110a outside the recess 106. The second group 302b includes the second laser device chip 118b and is adjacent to the first IC chip 102a and the second photonic chip 110b outside the recess 106. When viewed in a sectional view, the second photonic chip 110b is arranged over the first and second IC chips 102a, 102b, as for the first photonic chip 110a of Fig. 1 is shown.

[0036] The laser device chips 118 are each as the first laser device chip 118a of Fig. 1, and are therefore configured to generate laser beams 114 directed toward a photonic chip (e.g., the first or second photonic chip 110a, 110b). The laser device chips 118 of the first group 302a correspond to the photodetectors 108 of the first IC chip 102a, while the laser device chips 118 of the second group 302b correspond to the photodetectors 108 of the second IC chip 102b. In some embodiments, the laser device chips 118 of the first group 302a and the photodetectors 108 of the first IC chip 102a are in a one-to-one relationship with each other, and / or the laser device chips 118 of the second group 302b and the photodetectors 108 of the second IC chip 102b are in a one-to-one relationship with each other.

[0037] Let us now turn to the top view 300B of Fig. 3B, in which the first and second photonic chips 110a, 110b each have a plurality of light modulators 112. The plurality of light modulators 112 of the first photonic chip 110a includes the first light modulator 112a of Fig. 1, while the plurality of light modulators 112 of the second photonic chip 110b includes a second light modulator 112b. Furthermore, the first and second photonic chips 110a, 110b each include a plurality of input couplers 202, a plurality of input waveguides 204, a plurality of output waveguides 206, and a plurality of output couplers 208.

[0038] The light modulators 112 of the first photonic chip 110a correspond to the photodetectors 108 of the first IC chip 102a and the laser device chips 118 of the first group 302a. In some embodiments, they are in a one-to-one relationship to each other. Similarly, the light modulators 112 of the second photonic chip 110b correspond to the photodetectors 108 of the second IC chip 102b and the laser device chips 118 of the second group 302a. In some embodiments, they are in a one-to-one relationship to each other. Furthermore, the light modulators 112 of the first and second photonic chips 110a, 110b are each as the light modulator 112a of Fig. 1, except that the light modulators 112 of the second photonic chip 110b receive electrical signals from the first IC chip 102a. Thus, the light modulators 112 are configured to each receive the laser beams 114 and modulate them into modulated laser beams 120 according to respective electrical signals received from the first and second IC chips 102a, 102b.

[0039] The input couplers 202 of the first and second photonic chips 110a, 110b and the input waveguides 204 of the first and second photonic chips 110a, 110b are as their counterparts described with reference to Fig. 2B, and thus define input light paths. The input couplers 202 receive the laser beams 114 from corresponding laser device chips 118, and the input waveguides 204 guide the laser beams 114 to corresponding light modulators 112. Similarly, the output couplers 208 of the first and second photonic chips 110a, 110b and the output waveguides 206 of the first and second photonic chips 110a, 110b are as their counterparts described with reference to Fig. 2B, and thus define output light paths. The output waveguides 206 guide the modulated laser beams 120 to corresponding output couplers 208, and the output couplers 208 couple the modulated laser beams 120 into corresponding photodetectors 108.

[0040] In the Fig. 4A and Fig. 4B are various sectional views 400A and 400B of some embodiments of the first and second IC chips 102a, 102b of Fig. 1 shown. Fig. 4A can, for example, be drawn along a line A - A' of the Fig. 2A and Fig. 2B or the Fig. 3A and Fig. 3B, while Fig. 4B for example along a line B - B' of the Fig. 3A and Fig. 3B can be created.

[0041] Let us now turn to the section view 400A of Fig. 4A, in which the first and second IC chips 102a, 102b include individual semiconductor substrates 402, individual semiconductor devices 404 (except for the photodetector 108a), and individual interconnect structures 406. In addition, the first IC chip 102a further includes the photodetector 108a.

[0042] The semiconductor devices 404 and the interconnect structures 406 are arranged on front sides of the respective semiconductor substrates 402, and the semiconductor devices 404 are arranged between the respective semiconductor substrates 402 and the respective interconnect structures 406. Furthermore, the photodetector 108a is arranged in the semiconductor substrate 402 of the first IC chip 102a and adjoins and partially forms a respective one of the semiconductor devices 404. The semiconductor substrates 402 may be, for example, bulk monocrystalline silicon substrates, silicon-on-insulator substrates, or another suitable type of substrate.

[0043] The photodetector 108a has a collector region 408 in the semiconductor substrate 402 of the first IC chip 102a. The collector region 408 is a doped semiconductor region with a doping type opposite to that of neighboring semiconductor regions, such that the collector region 408 is partially bounded by a pn junction. The photodetector 108a may, for example, be a photodiode or another arranged type of photodetector.

[0044] The semiconductor devices 404 are separated from each other by a corresponding trench isolation structure 410 extending into the front sides of corresponding semiconductor substrates 402. The trench isolation structures 410 are (or comprise) a dielectric material, and they may, for example, be or comprise shallow trench isolation (STI) structures or the like. Furthermore, the semiconductor devices 404 may, for example, be transistors, memory cells, other suitable types of semiconductor devices, or a combination thereof. The transistors may, for example, be planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), gate-all-around FETs (GAA-FETs), other suitable transistor types, or a combination thereof.

[0045] In some embodiments, semiconductor devices 404 include individual pairs of source / drain regions 412, individual gate dielectric layers 414, and individual gate electrodes 416. Gate dielectric layers 414 separate gate electrodes 416 from corresponding semiconductor substrates 402. The pairs of source / drain regions 412 are disposed in corresponding semiconductor substrates 402 and are doped semiconductor regions. Gate electrodes 416 are disposed between corresponding source / drain regions 412, and in the case that semiconductor device 404 is adjacent to photodetector 108a, a source / drain region of this semiconductor device is partially or completely formed by collector region 408.

[0046] The interconnect structures 406 include a plurality of conductive features 418 grouped in layers and stacked to form conductive paths leading away from the semiconductor devices 404. Furthermore, the conductive features 418 are embedded in corresponding dielectric interconnect layers 420 that are unique to the interconnect structures 406. The conductive features 418 may be, for example, vias 418v, wires 418w, front-side IC pads 122fi, other suitable conductive features, or a combination thereof.

[0047] Rear IC pads 122bi of the second IC chip 102b and a plurality of rear dielectric layers 422 are arranged on the rear sides of corresponding semiconductor substrates 402. Furthermore, the rear IC pads 122bi of the second IC chip 102b are separated from the semiconductor substrate 402 of the second IC chip 102b by a corresponding rear dielectric layer 422 and are electrically connected to the interconnect structure 406 of the second IC chip 102b. The electrical connection is established by a plurality of substrate vias (TSVs) 424 extending between the rear IC pads 122bi of the second IC chip 102b and the interconnect structure 406 of the second IC chip 102b. In addition, the TSVs 424 are separated from the semiconductor substrate 402 of the second IC chip 102b by TSV dielectric layers 426.

[0048] Let us now turn to the section view 400B of Fig. 4B. The first and second IC chips 102a, 102b are generally as described with reference to Fig. 4A. However, the second IC chip 102b includes the second photodetector 108b, and the first IC chip 102a lacks the first photodetector 108a. Furthermore, the first IC chip 102a, but not the second IC chip 102b, includes TSVs 424 and backside IC pads 122bi. The second photodetector 108b may, for example, be as described for the first photodetector 108a.

[0049] The Fig. 2A and Fig. 2B are described together, but it is understood that the Fig. 2A and Fig. 2B can be independent. In other words, the Fig. 2A and Fig. 2B may, but need not, correspond to the same embodiments. Similarly, the Fig. 3A and Fig. 3B are described together, but it is understood that they can be independent. In addition, the Fig. 4A and Fig. 4B are described together, but it is understood that they can be independent.

[0050] In Fig. 5 is a sectional view 500 of some embodiments of the semiconductor package of Fig. 1, in which TSVs 502 extend through the carrier substrate 104. The TSVs 502 each extend from front-side carrier pads 122fc on a front side of the carrier substrate 104 through to back-side carrier pads 122bc on a back side of the carrier substrate 104, thereby electrically connecting the first and second IC chips 102a, 102b and the laser device chip 118a to the back-side carrier pads 122bc. The TSVs 502 are separated from the carrier substrate 104 by respective TSV dielectric layers 504. Similarly, the front-side carrier pads 122fc and the back-side carrier pads 122bc are separated from the carrier substrate 104 by respective dielectric layers 506.

[0051] In Fig. 6 is a sectional view 600 of some alternative embodiments of the semiconductor package of Fig. 1, in which the photonic chip 110a is arranged between the first and second IC chips 102a, 102b instead of above the first and second IC chips 102a, 102b. This eliminates the recess 106, and the light modulator 112a is electrically connected to the second IC chip 102b through the carrier substrate 104. Furthermore, the laser device chip 118a is arranged above the photonic chip 110a. In alternative embodiments, the laser device chip 118a is arranged on one side of the photonic chip 110a.

[0052] In the Fig. 7A and Fig. 7B are various top views 700A and 700B of some embodiments of the semiconductor package of Fig. 6, in which the first and second IC chips 102a, 102b each have one-way and two-way communication. The sectional view 600 of Fig. 6 may, for example, be drawn along a line C - C' or along any other suitable line.

[0053] Let us now turn to the top view 700A of Fig. 7A, in which the semiconductor package of Fig. 7A, with some exceptions, is largely the same as the semiconductor package of Fig. 2A and / or Fig. 2B. The recess 106 is missing, and the photonic chip 110a is arranged between the first and second IC chips 102a, 102b. In addition, the laser device chips 118 overlap the second IC chip 102b, and the photodetectors 108 are arranged closer to the second IC chip 102b. In some embodiments, the sectional view 400A of Fig. 4A along a line C - C'.

[0054] Let us now turn to the top view 700B of Fig. 7B, in which the structure shown in Fig. 7A and described with reference thereto, is repeated for each communication direction. In addition, the semiconductor package of Fig. 7B, with some exceptions, largely resembles the semiconductor package of Fig. 3A and / or Fig. 3B. The recess 106 is missing, and the first and second photonic chips 110a, 110b are arranged between the first and second IC chips 102a, 102b. In addition, the laser device chips 118 of the first group 302a overlap with the first photonic chip 110a, the laser device chips 118 of the second group 302b overlap with the second photonic chip 110b, the photodetectors 108 of the first IC chip 102a are arranged closer to the second IC chip 102b, and the photodetectors 108 of the second IC chip 102b are arranged closer to the first IC chip 102a. In some embodiments, the cross-sectional view 400B of Fig. 4B along a line D - D'.

[0055] In Fig. 8 is a sectional view 800 of some embodiments of the semiconductor package of Fig. 6, in which the carrier substrate 104 comprises a semiconductor substrate 802 and an interconnect structure 804 over the semiconductor substrate 802. In some embodiments, the semiconductor substrate 802 is a bulk substrate made of monocrystalline silicon or another semiconductor material. In other embodiments, the semiconductor substrate 802 is a glass substrate or another type of substrate.

[0056] The interconnect structure 804 includes a plurality of conductive features 806 grouped in layers and stacked to form conductive paths. Such a conductive path may, for example, electrically connect the second IC chip 102b to the photonic chip 110a. Furthermore, the conductive features 806 are embedded in a dielectric interconnect layer 808. The conductive features 806 may, for example, be vias 806v, wires 806w, front-side support pads 122fc, other suitable conductive features, or a combination thereof.

[0057] TSVs 810 each extend from the interconnect structure 804, which is arranged on a front side of the semiconductor substrate 802, through the semiconductor substrate 802 to back-side support pads 122bc on a back side of the semiconductor substrate 802. This establishes an electrical connection from the first and second IC chips 102a, 102b and the photonic chip 110a to the back-side support pads 122bc. The TSVs 810 are separated from the support substrate 802 by corresponding TSV dielectric layers 812. Similarly, the back-side support pads 122bc are separated from the support substrate 104 by a dielectric layer 814.

[0058] In Fig. 9 is a top view 900 of some alternative embodiments of the semiconductor package of Fig. 6, in which the plurality of IC chips 102 comprises further IC chips. Furthermore, the IC chips 102 in each adjacent pair of IC chips 102 are optically coupled to one another by corresponding photonic chips 110. The photonic chips 110 are each as the first photonic chip 110a and / or the second photonic chip 110b with reference to the Fig. 6, Fig. 7A and Fig. 7B have been described.

[0059] A pair of photonic chips 110 is disposed between the IC chips 102 in each adjacent pair of IC chips 102 to enable two-way optical coupling between these IC chips 102, as described with reference to Fig. 7B. In alternative embodiments, only one photonic chip 110 is disposed between the IC chips 102 in each adjacent pair of IC chips 102 to enable one-way optical coupling between these IC chips 102, as described with reference to Fig. 7A. In alternative embodiments, some adjacent pairs of IC chips 102 have a two-way optical coupling, as described with reference to Fig. 7B, while other adjacent pairs of IC chips 102 have a one-way optical coupling as described with reference to Fig. 7A has been described.

[0060] In the Fig. 10A and Fig. 10B are various sectional views 1000A and 1000B of some alternative embodiments of the semiconductor package of Fig. 1, where the semiconductor package has multiple IC chip levels and multiple photonic chip levels. As seen below, the sectional views 1000A and 1000B may extend parallel, for example, and may be spaced apart in a direction into and out of the sheet, for example.

[0061] The plurality of IC chips 102 are grouped into a first IC chip level 1002a and a second IC chip level 1002b above the first IC chip level 1002a. Furthermore, the plurality of IC chips 102 are grouped such that each IC chip level includes a pair of IC chips. The first IC chip level 1002a includes a first level-one IC chip 102a and a second level-one IC chip 102b, and the second IC chip level 1002b includes a first level-two IC chip 102c and a second level-two IC chip 102d, which are arranged above the first level-one IC chip 102a and the second level-one IC chip 102b, respectively. For example, the first and second level-two IC chips 102c, 102d are as described for the first and second level-one IC chips 102a, 102b.

[0062] A plurality of photonic chips 110 are grouped into a first photonic chip level 1004a and a second photonic chip level 1004b above the first photonic chip level 1004a. The first photonic chip level 1004a includes a photonic level-one chip 110a, while the second photonic chip level 1004b includes a photonic level-two chip 110c. Furthermore, the first and second photonic chip levels 1004a, 1004b are alternately stacked with the first and second IC chip levels 1002a, 1002b. Additional photonic chip levels and IC chip levels are possible.

[0063] Let us now turn to the section view 1000A of Fig. 10A, in which the level-one photonic chip 110a is adjacent to a level-one laser device chip 118a configured to generate a laser beam 114 directed toward the level-one photonic chip 110a. The level-one photonic chip 110a also includes a level-one light modulator 112a and a plurality of waveguides and couplers (not shown). The level-one light modulator 112a is configured to modulate the laser beam 114 into a modulated laser beam 120 in accordance with an electrical signal 116 from the second level-one chip 110b. The waveguides and the couplers are configured to form an input light path that directs the laser beam 114 to an input of the level-one light modulator 112a, and they are also configured to form an output light path that directs the modulated laser beam 120 to a level-one photodetector 108a of the first level-one chip 110a.

[0064] Let us now turn to the section view 1000B of Fig. 10B, in which the level-one photonic chip 110a further includes a reflector 1006a. The reflector 1006a is adjacent to a level-two laser device chip 118c and is configured to reflect a laser beam 114 from the level-two laser device chip 118c to the level-two photonic chip 110c. Note that "level-two" in the term "level-two laser device chip 118c" refers to a photonic chip level to which light energy of the level-two laser device chip 118c is ultimately provided and / or on which the light energy is modulated.

[0065] The level-two photonic chip 110c includes a level-two light modulator 112c and a plurality of waveguides and couplers (not shown). The level-two light modulator 112c is configured to modulate the laser beam 114 from the reflector 1006a into a modulated laser beam 120 in accordance with an electrical signal 116 from the second level-two IC chip 102d. The waveguides and couplers are configured to form an input light path that directs the laser beam 114 to an input of the level-two light modulator 112c and are also configured to form an output light path that directs the modulated laser beam 120 to a level-two photodetector 108c of the first level-two IC chip 102c.

[0066] In the Fig. 11A and Fig. 11B are various top views 1100A and 1100B of some embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, in which the IC chips 102 have one-way communication. The sectional view 1000A of Fig. 10A may, for example, be drawn along a line D - D' or along another suitable line, and / or the sectional view 1000B of Fig. 10B may, for example, be drawn along a line E - E' or along another suitable line. As will be explained below and will be appreciated, Fig. 11A directed to a plane of the first and second level-one IC chips 102a, 102b, while Fig. 11B is directed to a plane of the first and second level two IC chips 102c, 102d.

[0067] Let us now turn to the top view 1100A of Fig. 11A, in which a plurality of laser device chips 118 are grouped into a level-one group 302a and a level-two group 302c, both adjacent to the level-one photonic chip 110a on a common side of the recess 106. Similar to the level-two laser device chip 118c, "level-two" in the term "level-two group 302c" refers to a photonic chip level to which light energy of the level-two group 302c is ultimately provided and / or on which the light energy is modulated. The laser device chips 118 of the level-one group 302a are each as described for the level-one laser device chip 118a, and the laser device chips 118 of the level-two group 302c are each as described for the level-two laser device chip 118c.Thus, the laser device chips 118 of the level-one and level-two groups 302a, 302c are configured to generate laser beams 114 directed toward the first photonic level-one chip 110a.

[0068] The level-one photonic chip 110a includes a plurality of light modulators 112 corresponding to the laser device chips 118 of the level-one group 302a, and further includes a plurality of reflectors 1006 corresponding to the laser device chips 118 of the level-two group 302c. In some embodiments, a one-to-one relationship exists between the laser device chips 118 of the level-one group 302a and the light modulators 112 of the level-one photonic chip 110a. In some embodiments, a one-to-one relationship exists between the laser device chips 118 of the level-two group 302c and the reflectors 1006. The level-one photonic chip 110a also includes a plurality of waveguides and / or couplers (not shown).

[0069] The light modulators 112 of the level-one photonic chip 110a are configured to modulate corresponding laser beams 114 from the level-one array 302a according to electrical signals from the second level-one IC chip 102b. Furthermore, the waveguides and / or couplers of the level-one photonic chip 110a are configured to guide the laser beams 114 from the level-one array 302a to the light modulators 112 of the level-one photonic chip 110a and / or to guide the modulated laser beams 120 from the light modulators 112 to corresponding photodetectors 108 of the first level-one IC chip 102a.

[0070] The reflectors 1006 are configured to reflect corresponding laser beams 114 from the level-two array 302c to the level-two photonic chip 110c. Furthermore, the waveguides and / or couplers of the level-one photonic chip 110a are configured to guide the laser beams 114 from the level-two array 302c to the reflectors 1006 and / or to guide the laser beams 114 after reflection from the reflectors 1006 to the level-two photonic chip 110c.

[0071] Let us now turn to the top view 1100B of Fig. 11B, in which the level-two photonic chip 110c includes a plurality of light modulators 112 that correspond to the reflectors 1006 of the level-one photonic chip 110a. In some embodiments, there is a one-to-one relationship between the light modulators 112 of the level-two photonic chip 110c and the reflectors 1006. In addition, the level-two photonic chip 110c includes a plurality of waveguides and / or couplers (not shown) similar to those of the level-one photonic chip 110a.

[0072] The light modulators 112 of the level-two photonic chip 110c are configured to modulate corresponding laser beams 114 from the level-two array 302c according to electrical signals from the second level-two IC chip 102d. Furthermore, the waveguides and / or couplers of the level-two photonic chip 110c are configured to guide the laser beams 114 from the level-two array 302c to the light modulators 112 of the level-two photonic chip 110c and / or to guide the modulated laser beams 120 from the light modulators 112 to corresponding photodetectors 108 of the first level-two IC chip 102c.

[0073] In the Fig. 12A and Fig. 12B are various top views 1200A and 1200B of some embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, in which the IC chips 102 have two-way communication. The sectional view 1000A of Fig. 10A may, for example, be drawn along a line D - D' or along another suitable line, and / or the sectional view 1000B of Fig. 10B may, for example, be drawn along a line E - E' or along another suitable line. As will be explained below and will be appreciated, Fig. 12A directed to a plane of the first and second level-one IC chips 102a, 102b, while Fig. 12B is directed to a plane of the first and second level-two IC chips 102c, 102d. In addition, as will be explained below and will be appreciated, the structure of the Fig. 11A and Fig. 11B is repeated for each communication direction, enabling two-way communication.

[0074] Now let’s look at the top view 1200A of Fig. 12A, in which the plurality of laser device chips 118 are further grouped into a second level-one group 302b and a second level-two group 302d. The first level-one group 302a and the first level-two group 302c are adjacent to the second level-one IC chip 102b and the level-one photonic chip 110a on a first side of the recess 106. Furthermore, on a second side of the recess 106 opposite the first side, the second level-one group 302b and the second level-two group 302d are adjacent to the first level-one IC chip 102a and a second level-one photonic chip 110b.

[0075] The first photonic chip level 1004a (see e.g. Fig. 10A and Fig. 10B) includes the second level-one photonic chip 110b, which is similar to the first level-one photonic chip 110a described above. Thus, the second level-one photonic chip 110b includes a plurality of light modulators 112 corresponding to the laser device chips 118 of the second level-one group 302b, and further includes a plurality of reflectors 1106 corresponding to the laser device chips 118 of the second level-two group 302d. The light modulators 112 of the second level-one photonic chip 110b are configured to modulate respective laser beams 114 from the second level-one group 302b according to electrical signals from the first level-one IC chip 110a. The reflectors 1006 of the second photonic level-one chip 110b are configured to direct corresponding laser beams 114 from the second level-two group 302d to the second photonic level-two chip 110d (see, e.g., Fig. 12B) reflect.

[0076] Let us now turn to the top view 1200B of Fig. 12B, in which the second photonic chip level 1004b (see e.g. Fig. 10A and Fig. 10B) further includes the second level-two photonic chip 110d. The second level-two photonic chip 110d is as described for the first level-two photonic chip 110c. Thus, the second level-two photonic chip 110d includes a plurality of light modulators 112 corresponding to the reflectors 1106 of the second level-one photonic chip 110b. The light modulators 112 of the second level-two photonic chip 110d are configured to modulate respective laser beams 114 from the second level-two array 302d in accordance with electrical signals from the first level-two IC chip 110c.

[0077] In the Fig. 13A and Fig. 13B are sectional views 1300A and 1300B of some embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, in which TSVs 502 extend through the carrier substrate 104, as described with reference to Fig. 5 has been explained.

[0078] In Fig. 14 is a sectional view 1400 of some alternative embodiments of the semiconductor package of the Fig. 10A and Fig. 10B, in which the semiconductor package has multiple laser device chip levels. In particular, the level-two laser device chip 118c is located in the second photonic chip level 1004b. Therefore, the reflector 1006a (see, e.g., Fig. 10B), and the level-two laser device chip 118c is located above the level-one laser device chip 118a. In addition, a dielectric layer 1402 fills gaps in the recess 106 (see, e.g., Fig. 10A and Fig. 10B) and around the IC chips 102, and further includes conductive features (not shown) leading from the pads 122 in the level-two laser device chip 118c to electrically connect these pads 122 to other devices and / or structures. The further conductive features may be, for example, wires, vias, and the like.

[0079] In the Fig. 15A and Fig. 15B are various top views 1500A and 1500B of some embodiments of the semiconductor package of Fig. 14, in which the IC chips 102 each have one-way and two-way communication. Fig. 15A is directed towards one-way communication, while Fig. 15B is directed to the two-way communication. The sectional view 1400 of Fig. 14 may, for example, be drawn along a line D - D' or along any other suitable line.

[0080] What the top view 1500A of Fig. 15A, Fig. 2A is representative of each IC chip level, including the first IC chip level 1002a and the second IC chip level 1002b, and Fig. 2B is representative of each photonic chip level, including the first photonic chip level 1004a and the second photonic chip level 1004b. Regarding the top view 1500B of Fig. 15B, Fig. 3A is representative of each IC chip level, including the first IC chip level 1002a and the second IC chip level 1002b, and Fig. 3B is representative of each photonic chip level, including the first photonic chip level 1004a and the second photonic chip level 1004b.

[0081] In Fig. 16 is a sectional view 1600 of some embodiments of the semiconductor package of Fig. 14, in which TSVs 502 extend through the carrier substrate 104, as described with reference to Fig. 5. Furthermore, the dielectric layer 1402 includes a plurality of conductive features 1602. The conductive features 1602 are stacked together to form an interconnect structure that electrically connects the pads 122 on the level-two laser device die 118c to other devices and / or structures. The conductive features 1602 may be, for example, wires 1602w, vias 1602v, contacts, and the like.

[0082] The embodiments of the semiconductor package of the Fig. Although Figures 10A to 16 show two IC chip levels and two photonic chip levels, more IC chip levels and more photonic chip levels are possible. For example, N IC chip levels and N photonic chip levels can be alternately stacked, where N is an integer greater than two. In these alternative embodiments, the semiconductor package includes further groups of laser device chips corresponding to the further photonic chip levels. Insofar as these alternative embodiments Fig. 10A to 13B, photonic chips in a lowest level have further reflectors for reflecting laser beams to higher-lying photonic chips. Insofar as these alternative embodiments Fig. 14 to 16, the semiconductor package has further laser device chip levels for a total of N laser device chip levels.

[0083] The present disclosure has thus far been directed to general layouts for semiconductor packages. However, it is understood that challenges may arise when aligning and bonding components of the semiconductor packages. For example, tolerances in the x, y, and z directions of a Cartesian coordinate system may be small when an output of a laser device chip (e.g., laser device chip 118a of Fig. 1) to an input of a corresponding photonic chip (e.g., the photonic chip 110a of Fig. 1). These small tolerances can be, for example, approximately ±1 µm or so. Difficulties in aligning and bonding components of semiconductor packages can reduce yields, increase costs, and so on.

[0084] The present disclosure also provides alignment elements and methods for simultaneously aligning and bonding components of a semiconductor package. As set forth below, the alignment elements and methods may, for example, improve alignment accuracy, increase alignment speed, increase yields, reduce costs, and the like. The semiconductor package may, for example, be a semiconductor package according to one of the embodiments described with reference to the Fig. 1 to 16. As explained below, the adjustment elements may be, for example, openings and / or projections.

[0085] The alignment elements and methods may be used, for example, to adjust a laser device chip (e.g., the laser device chip 118a of Fig. 1) to a corresponding carrier substrate (e.g., the carrier substrate 104 of Fig. 1) and simultaneously bond it thereto. As another example, the alignment elements and methods can be used, for example, to align a photonic chip (e.g., the photonic chip 110a of Fig. 1) to corresponding IC chips (e.g., the first and second IC chips 102a, 102b of Fig. 1) and simultaneously bond it thereto. As yet another example, the alignment elements and methods can be used, for example, to align IC chips (e.g., the first and second level-two IC chips 102c, 102d of the Fig. 10A and Fig. 10B) to a corresponding photonic chip (e.g., the photonic level-one chip 110a of the Fig. 10A and Fig. 10B) and bond them to them at the same time.

[0086] In the Fig. 17A, 17B, 18A, 18B, and 19-21 show a series of cross-sectional and top views of some embodiments of a method for simultaneously aligning and bonding a chip 1802 to a substrate 1702. Figures labeled with a suffix "A" or without a suffix letter correspond to cross-sectional views, while figures labeled with a suffix "B" correspond to top views for similarly numbered figures labeled with a suffix "A." In addition, figures labeled with a suffix "A" may be drawn along a line F-F' or a line G-G' (whichever is present) in similarly numbered figures labeled with a suffix "B."

[0087] Let us now turn to a sectional view 1700A of Fig. 17A and to a plan view 1700B of Fig. 17B, ​​in which the substrate 1702 is provided or otherwise fabricated. In some embodiments, the substrate 1702 is a carrier substrate 104, an integrated circuit chip (e.g., 102, 102a, 102b, 102c, or 102d), or a photonic chip (e.g., 110, 110a, 110b, 110c, 110d) in one of the semiconductor packages described above. In alternative embodiments, the substrate 1702 is another structure to which the chip 1802 described below may be bonded.

[0088] A top surface of the substrate 1702 includes a plurality of substrate openings 1702so receiving a plurality of substrate pads 122s, respectively, at bottom surfaces of the substrate openings 1702so. The substrate openings 1702so have individual widths Wso that decrease from a top surface of the substrate 1702 to bottom surfaces of the substrate openings 1702so. In other words, the substrate openings 1702so have profiles with an inverse taper or the like. Furthermore, the substrate openings 1702so have square top surface geometries. In alternative embodiments, the substrate openings 1702so have other suitable top surface geometries and / or profiles. The substrate openings 1702so may be created, for example, by wet or dry etching the substrate 1702. In some embodiments, the widths Wso at top surfaces of the substrate openings 1702so are about 50 µm, about 40 µm to 70 µm, about 40 µm to 55 µm, or about 55 µm to 70 µm.However, other suitable values ​​are also possible for alternative embodiments.

[0089] Since the widths Wso of the substrate openings 1702so decrease from top to bottom, sidewalls 1702sw of the substrate 1702 in the substrate openings 1702so are angled and form an angle α with respect to a top surface of the substrate 1702. In some embodiments, the angle α is about 54.74°, about 40° to 70°, about 40° to 55°, or about 55° to 70°. However, other suitable values ​​are also possible in alternative embodiments. In addition, the sidewalls 1702sw extend outwardly away from corresponding substrate pads 122s to the top surface of the substrate 1702.

[0090] Let us now turn to a sectional view 1800A of Fig. 18A and to a plan view 1800B of Fig. 18B, in which chip 1802 is provided or otherwise fabricated. In some embodiments, chip 1802 is a laser device chip (e.g., 118, 118a, 118b, or 118c), a photonic chip (e.g., 110, 110a, 110b, 110c, 110d), or an integrated circuit chip (e.g., 102, 102a, 102b, 102c, or 102d) in one of the semiconductor packages described above. In alternative embodiments, chip 1802 is another structure that can be bonded to substrate 1702.

[0091] A bottom surface of the chip 1802 has a plurality of chip protrusions 1802cp corresponding to the substrate openings 1702so of the Fig. 17A and Fig. 17B. In some embodiments, the chip protrusions 1802cp are in a one-to-one relationship with the substrate openings 1702so. The chip protrusions 1802cp are adapted to a plurality of chip pads 122c, respectively, at bottoms or ends of the chip protrusions 1802cp, and they have smaller widths Wcp than the widths Wso of the substrate openings 1702so. Furthermore, the chip protrusions 1802cp have rectangular profiles and square top geometries, the latter being the same as or substantially the same as the top geometries of the chip pads 122c. In alternative embodiments, the chip protrusions 1802cp have wedge-shaped profiles or other suitable profiles, and / or they have other suitable top geometries. In some embodiments, the chip protrusions 1802cp and the chip pads 122c have the same size and / or the same top surface geometry as the substrate pads 122S.

[0092] Let us now turn to a sectional view from 1900 of Fig. 19, in which the chip 1802 of the Fig. 18A and Fig. 18B above the substrate 1702 of the Fig. 17A and Fig. 17B, ​​such that a bottom surface of the chip 1802 faces a top surface of the substrate 1702. Furthermore, the chip 1802 and the substrate 1702 are roughly aligned with each other so that the chip protrusions 1802cp and the chip pads 122c are each located above the substrate openings 1702so. Since the substrate openings 1702so are wider at the top surfaces than at the bottom surfaces, this rough alignment may be easier than in the case where the top surface widths of the substrate openings 1702so are equal to their bottom surface widths.

[0093] Let us now turn to a sectional view 2000 of Fig. 20, in which the chip 1802 is lowered so that the chip protrusions 1802cp and the chip pads 122c enter the corresponding substrate openings 1702so of the substrate 1702. In addition, the chip pads 122c come into contact with the sidewalls 1702sw of the substrate 1702.

[0094] Let us now turn to a sectional view 2100 of Fig. 21, in which the inclination of the sidewalls 1702sw of the substrate 1702 serves to finely align the chip pads 122c with the substrate pads 122s and bring them into direct contact with them. For example, the chip 1802 can be moved laterally in the direction in which it can be further lowered until the substrate 1702 and the chip pads 122s, 122c are in direct contact. Thus, the inclination of the sidewalls 1702sw can facilitate the alignment of the chip 1802 with the substrate 1702 while the chip 1802 is bonded to the substrate 1702 and simultaneously electrically connected thereto. When the substrate 1702 and the chip pads 122s, 122c are in direct contact, in some embodiments, an annealing process and / or another suitable process may be performed to strengthen the bond between the substrate and the chip pads 122s, 122c.

[0095] In the Fig. 22A and Fig. 22B are various top views 2200A and 2200B of some alternative embodiments of the substrate 1702 and the chip 1802 of the Fig. 17A, 17B, 18A, 18B and 19 to 21, in which the substrate 1702 has further substrate openings 1702so and the chip 1802 has further chip projections 1802cp corresponding to the further substrate openings 1702so. Fig. 22A corresponds to the substrate 1702, while Fig. 22B corresponds to the chip 1802. In addition, the sectional view 2100 of Fig. 21 for example along a line H - H' in the Fig. 22A and Fig. 22B must be created.

[0096] In the Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29 is a series of sectional and plan views of some alternative embodiments of the method of Fig. 17A, 17B, 18A, 18B, and 19-21, in which the substrate openings 1702 have stepped profiles (see, for example, section views described below) and stepped top geometries (see, for example, plan views described below). Figures labeled with a suffix "A" or without a suffix letter correspond to section views, while figures labeled with a suffix "B" correspond to plan views for similarly numbered figures labeled with a suffix "A." In addition, figures labeled with a suffix "A" may be drawn along a line I-I', a line J-J', or a line K-K' (whichever is present) in similarly numbered figures labeled with a suffix "B."

[0097] Let us now turn to a sectional view 2300A of Fig. 23A and to a plan view 2300B of Fig. 23B, in which the substrate 1702 is provided or otherwise manufactured. The substrate 1702 is as described with reference to the Fig. 17A and Fig. 17B, ​​except that the substrate openings 1702 have stepped profiles (see, e.g., Fig. 23A) and stepped top geometries (see e.g. Fig. 23B).

[0098] How best in Fig. As can be seen in Figure 23A, due to the stepped profiles, the substrate openings 1702so extend into the substrate 1702 with individual depths Dso, wherein the depth Dso of each substrate opening 1702so discretely increases from a first side of this substrate opening 1702so to a second side of this substrate opening 1702so opposite the first side. Furthermore, the substrate openings 1702so have individual shallow portions SH and individual deep portions DP. The shallow portions SH extend into the substrate 1702 with a smaller depth than the deep portions DP, and the substrate pads 122s are each located on undersides of the deep portions DP.

[0099] How best in Fig. 23B, the flat parts SH have larger top surface geometries than the deep parts DP. For example, surface areas of the flat parts SH may be larger than surface areas of the deep parts DP. As another example, widths and lengths of the flat parts SH may be larger than corresponding widths and lengths of the deep parts DP (e.g., they may be 1.5, 2, or 3 times, or even larger). Additionally, the flat parts SH and the deep parts DP have square or rectangular top surface geometries. In alternative embodiments, the flat parts SH and / or the deep parts DP have other suitable top surface geometries.

[0100] Let us now turn to a sectional view 2400A of Fig. 24A and to a plan view 2400B of Fig. 24B in which the chip 1802 is provided or otherwise manufactured. The chip 1802 is as described with reference to the Fig. 18A and Fig. 18B, except that the chip protrusions 1802cp and the chip pads 122c are dimensioned to fit into the deep parts DP of the substrate openings 1702so of the Fig. 23A and Fig. 23B. In other words, top surface geometries of the chip protrusions 1802cp and top surface geometries of the chip pads 122c are equal to or approximately equal to the top surface geometries of the deep parts DP, so that the deep parts DP can accommodate the chip protrusions 1802cp and the chip pads 122c. And since the flat parts SH of the substrate openings 1702so of the Fig. 23A and Fig. 23B have larger top surface geometries than the deep parts DP, the flat parts SH can also accommodate the chip protrusions 1802cp and the chip pads 122c.

[0101] Let us now turn to a sectional view 2500 of Fig. 25, in which the chip 1802 of the Fig. 24A and Fig. 24B above the substrate 1702 of the Fig. 23A and Fig. 23B. In addition, the chip 1802 and the substrate 1702 are roughly aligned with each other so that the chip protrusions 1802cp and the chip pads 122c are respectively located above the shallow parts SH of the substrate openings 1702so. Since the top surface geometries of the shallow parts SH are larger than the top surface geometries of the deep parts DP, this rough alignment may be easier than in the case where the shallow parts SH are missing and the alignment is performed to the deep parts DP.

[0102] Let us now turn to a sectional view 2600 of Fig. 26, in which the chip 1802 is lowered so that the chip protrusions 1802cp and the corresponding chip pads 122c enter the flat parts SH of the corresponding substrate openings 1702so. Furthermore, the chip pads 122c come into contact with the substrate 1702.

[0103] Let us now turn to a sectional view 2700A of Fig. 27A and to a plan view 2700B of Fig. 27B, in which the chip protrusions 1802cp and the chip pads 122c are moved laterally in a first direction toward the deep parts DP until the chip protrusions 1802cp and the chip pads 122c enter the deep parts DP, or, as shown, are stopped by the sidewalls 1702sw of the substrate 1702 in the substrate openings 1702so. These sidewalls 1702sw are best seen in Fig. 27B can be seen.

[0104] Let us now turn to a sectional view 2800 of Fig. 28, in which the stepped top geometry (see e.g. Fig. 27B) of the substrate openings 1702so serves to finely adjust the chip pads 122c to the substrate pads 122s. For example, with a small lateral force, the chip pads 122c and the chip protrusions 1802cp can be pushed to the deep parts DP, while the chip pads 122c and the chip protrusions 1802cp move along the side walls 1702sw (see Fig. 27B) which, with reference to the Fig. 27A and Fig. 27B have stopped. This can continue until the chip pads 122c and the chip protrusions 1802cp reach the deep portions DP. Since the deep portions DP have top surface geometries that are approximately equal to the top surface geometries of the chip protrusions 1802cp and the top surface geometries of the chip pads 122c, the chip pads 122c move into alignment with the substrate pads 122s when the chip pads 122c have reached the deep portions DP. Furthermore, the chip 1802 generally moves into alignment with the substrate 1702.

[0105] Let us now turn to a sectional view 2900 of Fig. 29, in which the chip 1802 is lowered until the substrate 1702 and the chip pads 122s, 122c are in direct contact. As discussed above, the substrate openings 1702 thus facilitate the alignment of the chip 1802 to the substrate 1702 while the chip 1802 is bonded to the substrate 1702 and simultaneously electrically connected thereto. In some embodiments, when the substrate 1702 and the chip pads 122s, 122c are in direct contact, an annealing process and / or other suitable process may be performed to strengthen the bond between the substrate 1702 and the chip pads 122s, 122c.

[0106] In the Fig. 30A and Fig. 30B are various top views 3000A and 3000B of some alternative embodiments of the substrate 1702 and the chip 1802 of the Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29, in which the substrate 1702 has further substrate openings 1702so and the chip 1802 has further chip protrusions 1802cp corresponding to the further substrate openings 1702so. Fig. 30A corresponds to the substrate 1702, while Fig. 30B corresponds to the chip 1802. In addition, the sectional view 2900 of Fig. 29 for example along a line K - K' in the Fig. 30A and Fig. 30B must be created.

[0107] In the Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B is a series of sectional and plan views of some alternative embodiments of the method of Fig. 17A, 17B, 18A, 18B, and 19 to 21, in which the substrate openings 1702so are replaced by substrate protrusions 1702sp. Figures designated with a suffix "A" or without a suffix letter correspond to sectional views, while figures designated with a suffix "B" correspond to plan views for similarly numbered figures designated with a suffix "A." In addition, figures designated with a suffix "A" may be drawn along a line M-M', a line N-N', a line O-O', or a line Q-Q' (whichever is present) in similarly numbered figures designated with a suffix "B."

[0108] Let us now turn to a sectional view 3100A of Fig. 31A and to a plan view 3100B of Fig. 31B, in which the substrate 1702 is as described with reference to the Fig. 17A and Fig. 17B, ​​except that the substrate openings 1702so are replaced by the substrate protrusions 1702sp. The substrate protrusions 1702sp are each adapted to substrate protrusion pads 122sp on top surfaces or ends of the substrate protrusions 1702sp. Furthermore, the substrate protrusions 1702sp have the same top surface geometries as corresponding substrate protrusion pads 122sp. Top surface geometries of the substrate protrusions 1702sp have the shape of an isosceles trapezoid and thus widths Wsp that decrease (see, e.g., Fig. 31B). In alternative embodiments, the top surface geometries of the substrate protrusions 1702sp may be square, rectangular, triangular, diamond-shaped, or have a trapezoidal shape other than an isosceles trapezoid, or another suitable shape. And, as the widths Wsp decrease, the sidewalls 1702sw of the substrate protrusions 1702sp are angled.

[0109] In addition to the substrate protrusion pads 122sp, substrate body pads 122sb corresponding to the substrate protrusions 1702sp are disposed in and / or on a body of the substrate 1702, at a base of the corresponding substrate protrusions 1702sp. The substrate body pads 122sb have individual first body segments 122sb1 and individual second body segments 122sb2. For each substrate body pad 122sb, the first body segment 122sb1 and the second body segment 122sb2 of that substrate body pad 122sb are elongated parallel to a corresponding substrate protrusion 1702sp and respectively on opposite sides of a corresponding substrate protrusion 1702sp. Furthermore, the first body segment 122sb1 and the second body segment 122sb2 of this substrate body pad 122sb have individual ends connected on one side of the corresponding substrate protrusion 1702sp. Thus, the substrate body pads 122sb enclose the corresponding substrate protrusions 1702sp.In alternative embodiments, the first and second body segments 122sb1, 122sb2 are separate.

[0110] Top surface geometries of the first and second body segments 122sb1, 122sb2 have the shape of an isosceles trapezoid and thus widths Wsbs that decrease in a common direction. In alternative embodiments, the top surface geometries of the first and second body segments 122sb1, 122sb2 may be square, rectangular, triangular, or diamond-shaped, or have a trapezoidal shape other than an isosceles trapezoid, or another suitable shape. Furthermore, the top surface geometries of the first and second body segments 122sb1, 122sb2 are the same as those of the substrate protrusions 1702sp, but rotated 180° (when viewed from top to bottom). In addition, the widths Wsbs of the first and second body segments 122sb1, 122sb2 decrease in a direction opposite to that of the widths Wsp of the substrate protrusions 1702sp.In alternative embodiments, top surface geometries of the first and second body segments 122sb1, 122sb2 are different from those of the substrate protrusions 1702sp.

[0111] Let us now turn to a sectional view 3200A of Fig. 32A and to a plan view 3200B of Fig. 32B in which the chip 1802 is provided or otherwise manufactured. The chip 1802 is as described with reference to the Fig. 18A and Fig. 18B, except that the die protrusions 1802cp and the die pads have a different layout. The die protrusions 1802cp are aligned with die protrusion pads 122cp at bottoms or ends of the die protrusions 1802cp, respectively. Furthermore, the die protrusions 1802cp have the same top surface geometries as corresponding die protrusion pads 122cp.

[0112] The chip protrusions 1802cp include individual first protrusion segments 1802cp1 and individual second protrusion segments 1802cp2. For each chip protrusion 1802cp, the first protrusion segment 1802cp1 and the second protrusion segment 1802cp2 of this chip protrusion 1802cp are elongated in parallel and have individual ends connected on only one side of this chip protrusion 1802cp. As a result, the chip protrusions 1802cp form lateral recesses 1802r having open ends (e.g., to connect the substrate protrusions 1702sp of the Fig. 31A and Fig. 31B).

[0113] Top surface geometries of the first and second protrusion segments 1802cp1, 1802cp2 have the shape of an isosceles trapezoid and have widths Wcps that decrease in a common direction. In alternative embodiments, the top surface geometries of the first and second protrusion segments 1802cp1, 1802cp2 may be square, rectangular, triangular, or diamond-shaped, or have a trapezoidal shape other than an isosceles trapezoid, or another suitable shape. As the widths Wcps decrease, sidewalls 1802sw of the chip protrusions 1802cp on the first and second protrusion segments 1802cp1, 1802cp2 are angled. In addition, widths Wr of the lateral recesses 1802r decrease, so that the widths of the lateral recesses 1802r increase away from connected ends of the first and second projection segments 1802cp1, 1802cp2.In other words, the widths Wr of the lateral recesses 1802r decrease in a direction laterally into the lateral recesses 1802r.

[0114] In some embodiments, the top surface geometries of the first and projection segments 1802cp1, 1802cp2 are equal to the top surface geometries of the first and second body segments 122sb1, 122sb2 of the Fig. 31A and Fig. 31B. In some embodiments, the top surface geometries of the chip protrusions 1802cp are equal to the top surface geometries of the substrate body pads 122sb of the Fig. 31A and Fig. 31B. In some embodiments, the top surface geometries of the lateral recesses 1802r are equal to the top surface geometries of the substrate protrusions 1702sp of the Fig. 31A and Fig. 31B.

[0115] In addition to the chip protrusion pads 122cp, chip body pads 122cb, corresponding to the lateral recesses 1802r, are arranged in and / or on a body of the chip 1802, in the corresponding lateral recesses 1802r. Top surface geometries of the chip body pads 122cb have the shape of an isosceles trapezoid and thus widths Wcbp that decrease (see, e.g., Fig. 32B). In alternative embodiments, the top surface geometries of the chip body pads 122cb may be square, rectangular, triangular, or diamond-shaped, or have a trapezoidal shape other than an isosceles trapezoid, or another suitable shape. Furthermore, the widths Wcbp of the chip body pads 122cb decrease in a direction opposite to that of the widths Wcps of the first and second protrusion segments 1802cp1, 1802cp2. In some embodiments, the top surface geometries of the chip body pads 122cb are equal to the top surface geometries of the lateral recesses 1802r. Furthermore, in some embodiments, the top surface geometries of the chip body pads 122cb are equal to the top surface geometries of the substrate protrusions 1702sp of the Fig. 31A and Fig. 31B.

[0116] Let us now turn to a sectional view 3300A of Fig. 33A and to a plan view 3300B of Fig. 33B, in which the chip 1802 of the Fig. 32A and Fig. 32B above the substrate 1702 of the Fig. 31A and Fig. 31B. It should be noted that the chip body pads 122cb of the Fig. 32A and Fig. 32B and the substrate body pads 122sb of the Fig. 31A and Fig. 31B for the sake of clarity in Fig. 33B are not shown. In addition, the chip 1802 and the substrate 1702 are roughly aligned with each other so that open ends of the lateral recesses 1802r are located above the nearest ends of the substrate protrusions 1702sp. Since the open ends correspond to the widest parts of the lateral recesses 1802r, the rough alignment occurs between the widest parts of the lateral recesses 1802r and the narrowest parts of the substrate protrusions 1702sp. This simplifies the rough alignment compared to the case where the lateral recesses 1802r have only one width and / or the substrate protrusions 1702sp have only one width.

[0117] Let us now turn to a sectional view 3400 of Fig. 34, in which the chip 1802 is lowered so that the substrate protrusions 1702sp and the substrate pads 122s enter corresponding lateral recesses 1802r. Furthermore, the chip pads 122c come into contact with the substrate pads 122s.

[0118] Let us now turn to a sectional view 3500A of Fig. 35 and to a plan view 3500B of Fig. 35B, in which the inclination of the sidewalls 1702sw of the substrate protrusions 1702sp and the inclination of the sidewalls 1802sw of the chip protrusions 1802cp serve to finely adjust the chip pads 122c to the substrate pads 122s. For example, the chip protrusions 1802cp may be moved laterally in a direction along which the widths Wsp of the substrate protrusions 1702sp decrease. This lateral movement may continue until the substrate protrusions 1702sp come into contact with the chip protrusions 1802cp at the connected ends of the first and second protrusion segments 1802cp1, 1802cp2. Furthermore, it is understood that due to the inclination of the side walls 1702sw of the substrate protrusions 1702sp and the inclination of the side walls 1802sw of the chip protrusions 1802cp, the alignment between the chip pads 122c and the substrate pads 122s improves with progressive lateral movement.

[0119] In view of the foregoing, the top-side geometries of the substrate 1702 and the chip protrusions 1702sp, 1802cp facilitate the alignment of the chip 1802 to the substrate 1702 while bonding the chip 1802 to the substrate 1702 and simultaneously electrically connecting it. In some embodiments, when the substrate 1702 and the chip pads 122s, 122c are aligned and in direct contact, an annealing process and / or other suitable process may be performed to strengthen the bond.

[0120] In the Fig. 36A and Fig. 36B are various top views 3600A and 3600B of some alternative embodiments of the substrate 1702 and the chip 1802 in the Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B, in which the substrate 1702 has further substrate protrusions 1702sp and the chip 1802 has further chip protrusions 1802cp corresponding to the further substrate protrusions 1702sp. Fig. 36A corresponds to the substrate 1702, while Fig. 36B corresponds to the chip 1802. In addition, the sectional view 3500A of Fig. 35A for example along a line Q - Q' in the Fig. 36A and Fig. 36B must be created.

[0121] The Fig. 17 to 36B are described for a method, but it is understood that the structures shown in these figures are not limited to the method, but can be used as stand-alone structures independent of the method. Fig. 17 to 36B are described as a series of steps, but it should be understood that the order of these steps may be changed in other embodiments. Fig. Although Figures 17 through 36B are illustrated and described as a particular group of steps, some of the illustrated and / or described steps may be omitted in other embodiments. Furthermore, steps not illustrated and / or described may be used in other embodiments.

[0122] The Fig. 37A to 37G show sectional views 3700A to 3700G of various other embodiments of semiconductor packages in which, according to the methods described with reference to the Fig. 17A to 36B, components have been simultaneously aligned and bonded to one another. As will be seen below, these semiconductor packages correspond to alternative embodiments of the semiconductor packages described with reference to the Fig. 1 to 16 have been described.

[0123] Let us now turn to the sectional views 3700A to 3700C of the Fig. 37A to 37C, in which alternative embodiments of the semiconductor package of Fig. 1, in which the photonic chip 110a and the laser device chip 118a are configured according to the embodiments described with reference to Fig. 17A to 36B, respectively, are aligned with and bonded to the second IC chip 102b and the carrier substrate 104. In Fig. 37A, the procedures of Fig. 17A, 17B, 18A, 18B and 19 to 21. In Fig. 37B, the procedures of Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29 used. In Fig. 37C, the procedures of Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B is used.

[0124] In the section view 3700D of Fig. 37D are alternative embodiments of the semiconductor package of Fig. 37A, in which the first and second IC chips 102a, 102b are arranged in accordance with the arrangements described with reference to Fig. 17A, 17B, 18A, 18B and 19 to 21, further aligned with and bonded to the carrier substrate 104.

[0125] In the section view 3700E of Fig. 37E are alternative embodiments of the semiconductor package of Fig. 6, in which the laser device chip 118a is configured according to the steps described with reference to Fig. 17A, 17B, 18A, 18B and 19 to 21 is aligned with and bonded to the photonic chip 110a.

[0126] In the section view 3700F of Fig. 37F are alternative embodiments of the semiconductor package of Fig. 10A, in which the level-one laser device chip 118a is configured according to the steps described with reference to Fig. 17A, 17B, 18A, 18B and 19 to 21. In addition, according to the methods described with reference to Fig. 17A, 17B, 18A, 18B and 19 to 21, the first and second level-two IC chips 102c, 102d are aligned with and bonded to the level-one photonic chip 110a.

[0127] In the section view 3700G of Fig. 37G are alternative embodiments of the semiconductor package of Fig. 14, in which the level-one laser device chip 118a and the level-two laser device chip 118c are configured according to the configurations described with reference to FIGS. Fig. 17A, 17B, 18A, 18B and 19 to 21 to the carrier substrate 104 and the dielectric layer 1402 and bonded thereto.

[0128] The Fig. 37D to 37G show the alignment and bonding of components according to the methods described with reference to FIGS. 17A, 17B, 18A, 18B and 19 to 21, but alternatively, the methods of Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29 and / or the procedures of Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B can be used. In addition, the Fig. 37A to 37G are exemplary applications of the procedures of Fig. 17A to 36B for some of the semiconductor packages of the Fig. 1 to 16, but the methods can also be used for one of the semiconductor packages of the Fig. 1 to 16. In particular, one of the methods can be used for components of the semiconductor packages of the Fig. 1 to 16, which are bonded together at the pads 122, wherein the components include IC chips (e.g., 102, 102a, 102b, 102c, 102d), photonic chips (e.g., 110, 110a, 110b, 110c, 110d), laser device chips (e.g., 118, 118a, 118b, 118c), the dielectric layer 1402, and the carrier substrate 104.

[0129] The Fig. 38 to 42 show a series of cross-sectional views 3800 to 4200 of some embodiments of a method for manufacturing a semiconductor package having IC chips that are optically coupled to one another. The semiconductor package may, for example, be similar to alternative embodiments of the semiconductor package of Fig. 1, in which the laser device chip 118a is configured in accordance with the methods described with reference to Fig. 17A, 17B, 18A, 18B and 19 to 21 method is aligned with the carrier substrate 104 and bonded thereto.

[0130] As shown in section view 3800 of Fig. 38, the support substrate 104 is provided. The support substrate 104 may, for example, be a bulk substrate made of monocrystalline silicon or another semiconductor material. In other embodiments, the support substrate 104 is a glass substrate or another type of substrate.

[0131] As also shown in section view 3800 of Fig. 38, the carrier substrate 104 is patterned to create a recess 106 in a central portion 104c of the carrier substrate 104, which is enclosed by a peripheral portion 104p of the carrier substrate 104. The patterning may be performed, for example, using a photolithography / etching process or another suitable patterning process.

[0132] As shown in section view 3900 of Fig. 39, pads 122 are formed in the recess 106. The pads 122 may be or include, for example, a metal, a metal alloy, one or more other suitable conductive materials, or a combination thereof. A process for forming the pads 122 may include, for example, depositing a metal layer in the recess 106 and then patterning the metal layer into the pads 122.

[0133] It should be noted that, for simplicity, the pads 122 may be separated from the carrier substrate 104 by a dielectric layer. It should also be noted that conductive features (e.g., TSVs, wires, vias, etc.) may be formed in and / or on the carrier substrate 104 to electrically connect the pads 122 to other pads and / or structures. This manufacturing process may be performed before and / or after forming the pads 122 in the recess 106.

[0134] As also shown in section view 3900 of Fig. 39, a first IC chip 102a and a second IC chip 102b are provided or otherwise manufactured, and are disposed over and bonded to the pads 122 in the recess 106. The first and second IC chips 102a, 102b are laterally spaced apart and include further pads 122. In addition, the first IC chip 102a includes a photodetector 108 for converting an optical signal into an electrical signal. The first and second IC chips 102a, 102b may, for example, be as shown in Fig. 4A and described with reference thereto. In addition, outside the sectional view 3900 of Fig. 39 the first and second IC chips 102a, 102b may, for example, be as shown in Fig. 4B and are described with reference thereto.

[0135] As shown in section view 4000 of Fig. 40, a photonic chip 110a is provided or otherwise fabricated, and is disposed over and bonded to the first and second IC chips 102a, 102b. The bonding creates an electrical connection between the photonic chip 110a and the second IC chip 102b, and in some embodiments, an electrical connection between the photonic chip 110a and the first IC chip 102a. The photonic chip 110a includes a light modulator 112 and a plurality of waveguides and couplers (not shown). Non-limiting examples of the waveguides and couplers are shown, for example, in FIGS. Fig. 2A and Fig. 2B. In addition, in some embodiments, a top view of the photonic chip 110a is as shown in Fig. 2B or Fig. 3B. For example, the sectional view 4000 may be taken along a line A - A' in Fig. 2B or Fig. 3B must be created.

[0136] The light modulator 112 is configured to modulate a laser beam according to an electrical signal 116 from the second IC chip 102b. In other words, the light modulator 112 is configured to convert the electrical signal 116 into an optical signal. The waveguides and the couplers are configured to form input and output light paths. An input light path guides an unmodulated laser beam to an input of the light modulator 112a, and an output light path guides a modulated laser beam from an output of the light modulator 112a to the photodetector 108a of the first IC chip 102a. Examples of these input and output light paths are shown in the Fig. 2B and Fig. 3B shown.

[0137] As shown in section views 4100 and 4200 of the Fig. 41 and Fig. 42, a laser device chip 118a is provided or otherwise fabricated, and is disposed over and bonded to the carrier substrate 104. This bonding is performed using the methods described with reference to Fig. 17A, 17B, 18A, 18B and 19 to 21, whereby the bonding occurs simultaneously with the alignment of the laser device chip 118a to the carrier substrate 104. In alternative embodiments, the bonding is performed using the methods described with reference to Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29, the method described with reference to the Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B or by any other suitable method.

[0138] In particular, as shown in section view 4100 of Fig. 41, the peripheral portion 104p of the carrier substrate 104 is patterned to create a plurality of openings 104so with an inverse taper. The patterning may be performed, for example, using a photolithography / etching process or another suitable patterning process. Furthermore, the etching of the photolithography / etching process may be performed, for example, by dry etching, wet etching, or another suitable type of etching.

[0139] As also shown in section view 4100 of Fig. 41, further pads 122 are formed on undersides of the openings 104so. A process for forming the further pads 122 may include, for example, depositing a metal layer in the openings 104so and subsequently patterning the metal layer to form the further pads 122.

[0140] As shown in section view 4200 of Fig. 42, a laser device chip 118a is provided or otherwise fabricated, and is disposed over the carrier substrate 104 and bonded thereto through the openings 104so. The laser device chip 118a has a plurality of protrusions to which further pads 122 are mounted. According to the methods described with reference to Fig. 17A, 17B, 18A, 18B, and 19 to 21, the protrusions are inserted into the openings 104so to bond the pads 122 of the laser device chip 118a to the pads 122 in the openings 104so. Furthermore, with the inclined side walls of the support substrate 104 in the openings 104so, the laser device chip 118a is horizontally aligned with the support substrate 104 while the protrusions are inserted into the openings 104so. Thus, bonding and alignment are performed simultaneously.

[0141] The Fig. Although Figures 38 to 42 are described for a method, it is understood that the structures shown in these figures are not limited to the method, but can be used as stand-alone structures independent of the method. Fig. Although Figures 38 to 42 are described as a series of steps, it should be understood that the order of the steps may be changed in other embodiments. Fig. Although Figures 38 to 42 are illustrated and described as a particular group of steps, some of the illustrated and / or described steps may be omitted in other embodiments. Furthermore, steps not illustrated and / or described may be used in other embodiments. For example, the steps may be modified to accommodate the semiconductor packages of the Fig. 1 to 16 or the Fig. 37A to 37G.

[0142] If, in alternative embodiments, the Fig. 41 and Fig. 42 described steps with the reference to the Fig. 31A, Fig. 31B, Fig. 32A, Fig. 32B, Fig. 33A, Fig. 33B, Fig. 34, Fig. 35A and Fig. 35B described procedures are carried out, are created by structuring in Fig. 41 projections instead of openings in the carrier substrate 104. The Fig. 31A and Fig. 31B show examples of these protrusions. Furthermore, the protrusions of the laser device chip 118a are manufactured as shown in Fig. 32A and Fig. 32B. In alternative embodiments, if the configuration described with reference to Fig. 41 and Fig. 42 described steps with the reference to the Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 28 and Fig. 29 described procedures are carried out, are created by structuring in Fig. 41 the openings 104so, which in the Fig. 23A and Fig. 23B. In addition, the protrusions of the laser device chip 118a are manufactured as shown in the Fig. 24A and Fig. 24B is shown.

[0143] In Fig. 43 is a block diagram 4300 of some embodiments of the method of Fig. 38 to 42 shown.

[0144] In a step 4302, a carrier substrate is patterned to create a recess in a central portion of the carrier substrate that is enclosed by a peripheral portion of the carrier substrate. See, for example, Fig. 38.

[0145] In a step 4304, carrier substrate pads are produced in the recess. See, for example, Fig. 39.

[0146] In a step 4306, a first IC chip and a second IC chip are provided or otherwise manufactured. See, for example, Fig. 39.

[0147] In a step 4308, the first and second IC chips are positioned over the carrier substrate pads in the recess and bonded thereto. See, for example, Fig. 39.

[0148] In a step 4310, a photonic chip is provided or otherwise manufactured. See, for example, Fig. 40.

[0149] In a step 4312, the photonic chip is placed over the first and second chips and bonded to them. See, for example, Fig. 40.

[0150] In a step 4314, the peripheral portion of the carrier substrate is patterned to create a plurality of openings with an inverse taper. See, for example, Fig. 41.

[0151] In a step 4316, additional carrier substrate pads are formed on the undersides of the openings. See, for example, Fig. 41.

[0152] In a step 4318, a laser device chip is provided or otherwise manufactured, the laser device chip having a plurality of protrusions corresponding to the openings and mounted with laser device pads. See, for example, Fig. 42.

[0153] In a step 4320, the protrusions are inserted into the corresponding openings to bond the laser device pads to the carrier substrate pads, with sidewalls of the carrier substrate being inclined in the openings to align the laser device pads horizontally with the carrier substrate pads. See, for example, Fig. 42.

[0154] The block diagram 4300 of Fig.43 is illustrated and described herein as a series of steps or events, but it should be understood that the illustrated order of those steps or events should not be construed in a limiting sense. For example, some steps may occur in different orders and / or concurrently with other steps or events than those illustrated and / or described herein. Furthermore, not all of the illustrated steps may be required to implement one or more aspects or embodiments of the description herein, and one or more of the steps described herein may be performed in one or more separate steps and / or phases.

[0155] In some embodiments, the present disclosure provides a semiconductor package comprising: a substrate; a first IC chip and a second IC chip over the substrate, the first and second IC chips disposed in a recess in the substrate at the center thereof; a laser device (LD) chip over the substrate at a periphery of the substrate, the LD chip adjacent to the second IC chip and configured to generate a laser beam; and a photonic chip over the first and second IC chips and flush with the LD chip, the photonic chip configured to modulate the laser beam in response to an electrical signal from the second IC chip and to direct the modulated laser beam to the first IC chip.In some embodiments, the substrate includes an opening receiving a first pad at the periphery of the substrate, and the LD chip includes a protrusion connected to a second pad and mounted within the opening. In some embodiments, a top surface of the second IC chip is approximately flush with a top surface of the substrate at the periphery of the substrate. In some embodiments, the first IC chip includes a photodetector configured to receive the modulated laser beam and convert it into a second electrical signal.In some embodiments, the semiconductor package further comprises: a second LD chip above the substrate at the periphery of the substrate, the second LD chip adjacent to the first IC chip and configured to generate a second laser beam; and a second photonic chip above the first and second IC chips and level with the second LD chip, the second photonic chip configured to modulate the second laser beam in response to a second electrical signal from the first IC chip and to direct the second modulated laser beam to the second IC chip.In some embodiments, the semiconductor package further comprises: a third IC chip and a fourth IC chip above the photonic chip and above the first and second IC chips, respectively; and a second photonic chip above the third and fourth IC chips, the second photonic chip configured to modulate a second laser beam in response to a second electrical signal from the fourth IC chip and to direct the second modulated laser beam to the third IC chip. In some embodiments, the semiconductor package further comprises: a second LD chip above the LD chip and flush with the second photonic chip, the second LD chip adjacent to the fourth IC chip and configured to generate the second laser beam.In some embodiments, the semiconductor package further comprises: a second LD chip above the substrate at the periphery of the substrate and level with the photonic chip, the second LD chip adjacent to the second IC chip and configured to generate the second laser beam, the photonic chip having a reflector configured to reflect the second laser beam toward the second photonic chip.

[0156] In some embodiments, the present disclosure provides another semiconductor package comprising: a substrate; a first IC chip and a second IC chip over the substrate; a photonic chip over the first and second IC chips, the photonic chip configured to modulate a laser beam in response to an electrical signal from the second IC chip and direct the modulated laser beam to the first IC chip; and a laser device (LD) chip over the substrate, adjacent to the photonic chip, the LD chip configured to generate the laser beam, wherein a top surface of the substrate includes a first alignment element receiving a first pad, and a bottom surface of the LD chip includes a second alignment element receiving a second pad, wherein the first or second alignment element is an opening or includes a recess,in which the other of the first and second alignment elements is arranged. In some embodiments, the first alignment element is the opening, the opening extending into a top surface of the substrate and receiving the first pad on its underside, and the second alignment element is a protrusion to which the second pad is mounted and which is arranged in the opening. In some embodiments, the opening has a width that decreases from the top surface of the substrate to the bottom surface of the opening. In some embodiments, the opening has a flat portion and a deep portion that are adjacent to one another to define a stepped profile of the opening and a stepped top surface geometry of the opening.wherein the deep portion receives the first pad, and a top surface geometry of the shallow portion is larger than a top surface geometry of the deep portion. In some embodiments, transverse dimensions of the opening on the second pad are approximately equal to corresponding transverse dimensions of the protrusion. In some embodiments, the second adjustment element is a downward protrusion with a recess, and the first adjustment element is an upward protrusion that is laterally recessed into one side of the downward protrusion in the recess. In some embodiments, the downward protrusion has a pair of protrusion segments, respectively on opposite sides of the upward protrusion, the protrusion segments being elongated in parallel and having individual ends connected on only one side of the upward protrusion.

[0157] In some embodiments, the present disclosure provides a method of manufacturing a semiconductor package, the method comprising: disposing first and second IC chips adjacent to each other on a central portion of a substrate; disposing a photonic chip over the first and second IC chips; patterning a peripheral portion of the substrate adjacent to the photonic chip and the second IC chip to create a first alignment element; forming a first pad on the first alignment element; forming a second alignment element on an LD chip, the second alignment element having a downward protrusion on which a second pad is disposed; and moving the first and second alignment elements toward each other, the first and second alignment elements cooperating to align the first and second pads.In some embodiments, the first alignment element is an opening that receives the first pad at a bottom side of the opening, wherein sidewalls of the substrate within the opening slope outwardly away from the first pad and are inserted into the opening by moving the downward projection and the second pad, the movement following an inclination of the sidewalls towards the first pad. In some embodiments, the first alignment element is an opening with a stepped profile and a stepped top geometry, wherein a depth of the opening increases and a width of the opening decreases from a first side of the opening to a second side of the opening opposite the first side, and are inserted into the opening by moving the downward projection and the second pad, the movement following the stepped profile and the stepped top geometry towards the first pad.In some embodiments, the first adjustment element is an upward protrusion, and the downward protrusion has a lateral recess with a top surface geometry complementary to a top surface geometry of the upward protrusion, wherein the lateral recess is configured to receive the upward protrusion and is moved laterally around the upward protrusion by moving the downward protrusion such that the lateral recess receives the upward protrusion. In some embodiments, a width of the upward protrusion and a width of the lateral recess increase in a direction along which the downward protrusion is moved around the upward protrusion.

Claims

[1] Semiconductor package with: a substrate; a first IC chip (IC: integrated circuit) and a second IC chip above the substrate, the first and second IC chips being arranged in a recess in the substrate at the center thereof; a laser device chip (LD chip) over the substrate at a periphery of the substrate, the LD chip being adjacent to the second IC chip and configured to generate a laser beam; and a photonic chip above the first and second IC chips and level with the LD chip, the photonic chip configured to modulate the laser beam in response to an electrical signal from the second IC chip and to direct the modulated laser beam to the first IC chip. [2] Semiconductor package according to claim 1, wherein the substrate has an opening that receives a first pad at the periphery of the substrate, and the LD chip has a protrusion that is mounted to a second pad and in the opening. [3] The semiconductor package according to claim 1 or 2, wherein a top surface of the second IC chip is approximately level with a top surface of the substrate at the periphery of the substrate. [4] A semiconductor package according to any one of the preceding claims, wherein the first IC chip comprises a photodetector configured to receive the modulated laser beam and convert it into a second electrical signal. [5] A semiconductor package according to any one of the preceding claims, further comprising: a second LD chip over the substrate at the periphery of the substrate, the second LD chip being adjacent to the first IC chip and configured to generate a second laser beam; and a second photonic chip above the first and second IC chips and level with the second LD chip, the second photonic chip configured to modulate the second laser beam in response to a second electrical signal from the first IC chip and to direct the second modulated laser beam to the second IC chip. [6] A semiconductor package according to any one of the preceding claims, further comprising: a third IC chip and a fourth IC chip above the photonic chip and above the first and second IC chips, respectively; and a second photonic chip over the third and fourth IC chips, the second photonic chip configured to modulate a second laser beam in response to a second electrical signal from the fourth IC chip and to direct the second modulated laser beam to the third IC chip. [7] A semiconductor package according to claim 6, further comprising: a second LD chip above the LD chip and level with the second photonic chip, the second LD chip being adjacent to the fourth IC chip and configured to generate the second laser beam. [8] A semiconductor package according to claim 6 or 7, further comprising: a second LD chip above the substrate at the periphery of the substrate and level with the photonic chip, the second LD chip adjacent to the second IC chip and configured to generate the second laser beam, the photonic chip having a reflector configured to reflect the second laser beam toward the second photonic chip. [9] Semiconductor package with: a substrate; a first IC chip (IC: integrated circuit) and a second IC chip over the substrate; a photonic chip over the first and second IC chips, the photonic chip configured to modulate a laser beam in response to an electrical signal from the second IC chip and to direct the modulated laser beam to the first IC chip; and a laser device chip (LD chip) over the substrate, adjacent to the photonic chip, the LD chip configured to generate the laser beam, wherein a top surface of the substrate has a first alignment element receiving a first pad, and a bottom surface of the LD chip has a second alignment element receiving a second pad, wherein the first or second alignment element is an opening or has a recess in which the other of the first and second alignment elements is disposed. [10] Semiconductor package according to claim 9, wherein the first alignment element is the opening, the opening extending into a top side of the substrate and receiving the first pad on its underside, and the second adjusting element is a projection on which the second pad is mounted and which is arranged in the opening. [11] The semiconductor package of claim 10, wherein the opening has a width that decreases from the top of the substrate to the bottom of the opening. [12] The semiconductor package of claim 10 or 11, wherein the opening has a shallow portion and a deep portion adjacent to each other to define a stepped profile of the opening and a stepped top surface geometry of the opening, wherein the deep portion receives the first pad and a top surface geometry of the shallow portion is larger than a top surface geometry of the deep portion. [13] A semiconductor package according to any one of claims 10 to 12, wherein transverse dimensions of the opening on the second pad are approximately equal to corresponding transverse dimensions of the projection. [14] Semiconductor package according to claim 9, wherein the second adjusting element is a downward projection with a recess, and the first adjusting element is an upward projection which is recessed laterally into one side of the downward projection in the recess. [15] The semiconductor package of claim 14, wherein the downward projection comprises a pair of projection segments respectively on opposite sides of the upward projection, the projection segments being elongated in parallel and having individual ends connected on only one side of the upward projection. [16] A method of manufacturing a semiconductor package, comprising: Arranging a first and a second IC chip (IC: integrated circuit) adjacent to each other on a central part of a substrate; disposing a photonic chip over the first and second IC chips; Structuring a peripheral portion of the substrate adjacent to the photonic chip and the second IC chip to produce a first alignment element; Producing a first pad on the first adjustment element; Producing a second alignment element on a laser device (LD) chip, the second alignment element having a downward projection on which a second pad is arranged; and Moving the first and second adjustment elements towards each other, wherein the first and second adjustment elements cooperate to adjust the first and second pads to each other. [17] The method of claim 16, wherein the first adjustment element is an opening that receives the first pad on its underside, side walls of the substrate in the opening slope outwardly away from the first pad, and by moving the downward projection and the second pad into the opening, wherein the movement follows an inclination of the side walls towards the first pad. [18] A method according to claim 16 or 17, wherein the first adjusting element is an opening with a stepped profile and a stepped top geometry, a depth of the opening increases and a width of the opening decreases from a first side of the opening to a second side of the opening opposite the first side, and by moving the downward projection and the second pad into the opening, the movement following the stepped profile and the stepped top geometry to the first pad. [19] Method according to one of claims 16 to 18, wherein the first adjusting element is an upward projection, the downward projection has a lateral recess with a top surface geometry complementary to a top surface geometry of the upward projection, the lateral recess being configured to receive the upward projection, and by moving the downward projection laterally around the upward projection so that the lateral recess accommodates the upward projection. [20] The method of claim 19, wherein a width of the upward projection and a width of the lateral recess increase in a direction along which the downward projection is moved around the upward projection.

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