Liner-free silicon vias formed by selective metal deposition

Abstract

Comprehensive structure: a substrate (10) comprising a trench (18) and a plurality of surfaces (20, 22) that define the trench (18); and a silicon via (26) comprising a layer (24) within the trench (18), wherein the layer (24) is in direct contact with the plurality of surfaces (20, 22) of the substrate (10), wherein the layer (24) comprises a first section adjoining the plurality of surfaces (20, 22) and a second section positioned within the first section, wherein the first section of the layer (24) has a first average grain size, and the second section of the layer (24) has a second average grain size that differs from the first average grain size, and wherein the layer (24) comprises tungsten, and the first section is formed by a silicon reduction reaction in which a tungsten-containing precursor reacts with silicon of the substrate, and the second section is formed by a hydrogen reduction reaction in which the tungsten-containing precursor reacts with hydrogen.

Description

BACKGROUND

[0001] The invention relates to semiconductor device manufacturing and integrated circuits and in particular structures for silicon through-hole plating and methods for forming a structure for silicon through-hole plating.

[0002] In the semiconductor manufacturing industry, three-dimensional integrated circuits with silicon through-holes have emerged as a technique for providing vertical interconnects. Silicon through-hole technology is of particular interest, for example, in the creation of three-dimensional chip stacks. Stacking chips in a three-dimensional stack reduces signal transmission distances for chip-to-chip communication and facilitates a significant increase in the number of inter-chip connections.

[0003] A silicon via can be formed by a process that creates a trench in a substrate, deposits a nucleation liner on the trench's sidewalls, and then deposits tungsten to fill the trench. The nucleation liner, positioned between the deposited tungsten and the trench's sidewalls, can, for example, consist of a titanium-titanium nitride bilayer. After its formation, the nucleation liner is subjected to annealing at 600°C. The silicon via formation process imparts significant stress to the substrate, which can result in bending and breakage during subsequent processing, such as chemical-mechanical polishing, which removes the deposited tungsten and nucleation liner from the substrate surrounding the trench and planars the silicon via. US 2019 / 0326168 A1 teaches a trench filling method in which fill material, such as tungsten, is grown from the trench bottom and the nucleation of the fill material on the trench side walls is suppressed.

[0004] Furthermore, DE 10 2021 121 297 A1 discloses the provision of contact structures for transistors, consisting of a seed layer made of a first crystalline material and a contact plug made of a second crystalline material arranged above it. Furthermore, US 2022 / 0 068 709 A1 discloses a trench-filling method in which a tungsten layer covering the trench walls is deposited using a physical vapor deposition (PVD) process and a tungsten layer filling the trench is deposited using a chemical vapor deposition (CVD) process.

[0005] Improved structures for silicon through-hole plating and methods for forming a structure for silicon through-hole plating are needed. BRIEF SUMMARY

[0006] In one embodiment of the invention, a structure comprises a substrate having a trench and a plurality of surfaces that define the trench. The structure further comprises a silicon via having a layer within the trench. The layer is in direct contact with the plurality of surfaces of the substrate.The layer comprises a first section adhering to the multitude of surfaces and a second section positioned within the first section, wherein the first section of the layer has a first average grain size, and the second section of the layer has a second average grain size that differs from the first average grain size, and wherein the layer comprises tungsten, and the first section is formed by a silicon reduction reaction in which a tungsten-containing precursor reacts with silicon of the substrate, and the second section is formed by a hydrogen reduction reaction in which the tungsten-containing precursor reacts with hydrogen.

[0007] In one embodiment of the invention, a method for forming a silicon via is provided. The method comprises forming a trench in a substrate comprising a plurality of surfaces that bound the trench, and forming a layer within the trench to define the silicon via. The layer directly contacts the plurality of surfaces of the substrate and comprises tungsten formed by a deposition process using a tungsten-containing precursor and hydrogen as reactant gases. The deposition process comprises: depositing a first section of the layer by a silicon reduction reaction; and depositing a second section of the layer by a hydrogen reduction reaction.The first section fits into the multitude of surfaces, and the second section is positioned within the first section, with the first section having a first average grain size, and the second section having a second average grain size that differs from the first average grain size. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated into and form part of this description, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain these embodiments. In the drawings, the same reference numerals refer to the same features in the different views. Fig. Figures 1-4 are cross-sectional views of a structure in successive manufacturing stages of a processing method according to embodiments of the invention. DETAILED DESCRIPTION

[0009] With reference to Fig. 1 and according to embodiments of the invention, a hard mask 16 is formed on a front surface 12 of a substrate 10. The substrate 10 can contain a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 10 can be a bulk substrate comprising a semiconductor material, such as single-crystal silicon.

[0010] The hard mask 16 can comprise a pad layer containing a dielectric material, such as boron phosphosilicate glass or silicon dioxide, and can be patterned by lithography and etching processes to define an opening that exposes a surface region of the substrate 10. In this respect, the hard mask 16 can be patterned using an etching mask formed by lithography. The etching mask can comprise a photoresist layer applied by a spin-coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define the opening to be formed in the hard mask 16. An etching process, such as a reactive ion etching process, can then be used to remove sections of the pad layer exposed through the opening in the etching mask, which are subsequently stripped to define the opening in the hard mask 16.

[0011] A trench 18 can be formed, extending from the front surface 12 of the substrate 10 to a given depth within the substrate 10. In one embodiment, the depth of the trench 18 can range from approximately 10 micrometers to approximately 150 micrometers, and the width of the trench 18 can range from approximately 2 micrometers to approximately 6 micrometers. The trench 18 can be formed at the location of the opening in the hard mask 16 by an etching process, using the hard mask 16 as an etching mask. The opening in the hard mask 16 can be slightly wider than the trench 18 to facilitate subsequent layer deposition within the trench 18 for the formation of a silicon via. The substrate 10 comprises surfaces 20 and 22, which define and extend along the side wall and bottom of the trench 18, respectively.

[0012] With reference to Fig. 2, in which the same reference sign refers to the same features in Fig. In a subsequent manufacturing stage, a layer 24 containing a metal is formed within the groove 18. Unlike conventional deposition processes used to form a silicon via, no liner (e.g., an adhesion liner, a barrier liner, a nucleation liner, or a combination thereof (e.g., a titanium-titanium nitride bilayer)) is pre-deposited onto the surfaces 20, 22 that define the groove 18 after the groove 18 is formed and before the layer 24 is formed. Thus, the subsequently formed silicon via is free of a liner between the layer 24 and the surfaces 20, 22 of the substrate 10. Instead, the layer 24 directly contacts the surfaces 20, 22 of the substrate 10.

[0013] Layer 24 can be formed with the hard mask 16 on the front surface 12 of the substrate 10. In one embodiment, layer 24 can be formed by a selective deposition process in which the metal of which it is composed nucleates and forms on the surfaces 20, 22 of the substrate 10, but not on the dielectric material of the hard mask 16. According to the invention, the deposited metal is tungsten, which is selectively deposited on the surfaces 20, 22 of the substrate 10 by a deposition process that uses a tungsten-containing precursor and a reducing agent as reaction gases in a chemical vapor deposition process. In another embodiment, the deposited metal can be tungsten, which is selectively deposited on the surfaces 20, 22 of the substrate 10 by a deposition process that uses tungsten hexafluoride and hydrogen as reaction gases in a chemical vapor deposition process.The gas mixture of reactant gases used in the selective deposition process contains no silane, which is present in conventional deposition processes. Process conditions can include a substrate temperature in the range of approximately 395°C to approximately 420°C, a flow rate for tungsten hexafluoride ranging from approximately 300 standard cubic centimeters per minute (sccm) to approximately 400 sccm, a chamber pressure of approximately 40 Torr, and a flow rate for hydrogen ranging from approximately 5500 sccm to approximately 9000 sccm.

[0014] Layer 24 is deposited in several stages, and each stage of the multi-stage deposition process is characterized by a different reduction reaction. In one embodiment, the multi-stage deposition process can be completely selective, so that tungsten is not deposited on the hard mask 16. In another embodiment, the multi-stage deposition process can be substantially selective, so that tungsten is deposited on the hard mask 16, but as a significantly thinner layer compared to the thickness of tungsten that would be deposited by a non-selective deposition process.

[0015] Layer 24 is initially formed by a reduction reaction in which the tungsten hexafluoride reacts with the semiconductor material (e.g., silicon) of the substrate 10 to preferably deposit massive tungsten on the surfaces 20, 22 of the trench 18. Silicon tetrafluoride (tetrafluorosilane) is formed as a byproduct of the silicon reduction reaction. Layer 24 thickens as the silicon reduction reaction progresses. However, the silicon reduction reaction is self-limiting due to the ability of tungsten hexafluoride species to diffuse through the increasing thickness of layer 24 to the substrate 10. An initial section of layer 24 forms on surfaces 20, 22, and as the thickness increases, this initial section eventually blocks significant diffusion of tungsten hexafluoride to surfaces 20, 22.

[0016] With reference to Fig. 3, in which the same reference sign refers to the same features in Fig. Referring to step 2, and in a subsequent manufacturing stage, the formation of layer 24 within trench 18 continues without interrupting the deposition process and under the same deposition conditions as those used to form the initial section of layer 24. However, the reduction reaction that forms layer 24 changes. In particular, the reduction reaction changes such that the tungsten hexafluoride reacts with the hydrogen in the reaction gases to preferably proceed with the deposition of solid tungsten within trench 18. Hydrogen fluoride is formed as a byproduct of the hydrogen reduction reaction.

[0017] The hydrogen reduction reaction creates an inner section of layer 24, which is located within the outer section of layer 24 ( Fig. 2) is positioned, which was formed by the silicon reduction reaction. In one embodiment, the layer 24 can fill the trench 18 after completion of the hydrogen reduction reaction section of the deposition process. In one embodiment, the layer 24 can substantially fill the trench 18. In one embodiment, the layer 24 can be seamless. The layer 24 can be completely surrounded by the surfaces 20, 22 of the substrate 10 below the front surface 12 of the substrate 10. The layer 24 can include a top section that protrudes from the trench 18 as an excess, which is removed during a subsequent polishing process.

[0018] The metal (e.g., tungsten) of layer 24 can be polycrystalline, and layer 24 can comprise the outer section formed by the silicon reduction reaction and the inner section formed by the hydrogen reduction reaction. According to the invention, the inner and outer sections of layer 24 have different average grain sizes. In one embodiment, the initial outer section of layer 24 can be characterized by smaller grains, and the inner section of layer 24 can be characterized by larger grains. As a result, layer 24 comprises an outer section characterized by an average grain size and an inner section (surrounded by the outer section) characterized by an average grain size that is larger (i.e., more extensive) than the average grain size of the inner section.The surfaces 20, 22 can define respective interfaces between the semiconductor material (e.g. silicon) of the substrate 10 and the metal (e.g. tungsten) of the layer 24.

[0019] With reference to Fig. 4, in which the same reference sign refers to the same features in Fig.3, and in a subsequent manufacturing stage, layer 24 can be planarized, for example, by a chemical-mechanical polishing process to be coplanar with the hard mask 16. The planarized layer 24 within the trench 18 defines a silicon via 26 having a peak at the bottom of the trench 18 and an upper surface 28 that is planar or substantially planar. In one embodiment, the silicon via 26 can be a single unit. In another embodiment, the silicon via 26 can have no layers other than layer 24. In another embodiment, the silicon via 26 can be a single piece of continuous material. In yet another embodiment, the silicon via 26 can comprise only the metal of layer 24.In one embodiment, the substrate 10 can subsequently be thinned from the rear surface to expose the tip of layer 24.

[0020] The silicon via formation process is simplified because the conventional nucleation liner and its anneals are removed at 600°C after deposition. Due to the deposition process used to form layer 24, the silicon via 26 is less likely to include a seam, which can reduce the incidence of trapped contaminants, for example, in a seam, that could later escape and cause defects. The deposition process can accelerate planarization by chemical-mechanical polishing because layer 24 is either not deposited on the exposed surface of the hard mask 16 or is deposited only as a thin layer on the exposed surface of the hard mask 16. The absence of a liner can also reduce the time required for chemical-mechanical polishing.

[0021] The processes described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either an intermediate or a final product. The final product can be any product that incorporates integrated circuit chips, such as computer products with a central processing unit or smartphones.

[0022] References herein to expressions modified by an approximation language, such as "about," "approximately," and "essentially," are not to be limited to the specified precise value. The approximation language may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of + / - 10% of the stated value(s).

[0023] References herein to terms such as "vertical," "horizontal," etc., are made for illustrative purposes only and not to limit or establish a frame of reference. The term "horizontal," as used herein, is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0024] A feature "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature "at" or "contacting" another feature can be directly at or in direct contact with the other feature, or one or more intervening features can be present. A feature can be "directly at" or in "direct contact" with another feature if no intervening features are present.A feature can be "indirectly related" or in "indirect contact" with another feature if at least one intervening feature is present. Different features can "overlap" if one feature extends over another and covers part of it, either through direct or indirect contact.

[0025] The descriptions of the various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are obvious to those skilled in the art without deviating from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over commercially available technologies, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Images