Semiconductor device, package and method for fabricating a wafer-on-wafer cascode HEMT device

Abstract

Semiconductor device with: a first semiconductor structure with a first HEMT device, wherein the first HEMT device comprises a first gate, a first source and a first drain; and a second semiconductor structure stacked over and bonded to the first semiconductor structure, wherein the second semiconductor structure comprises a second HEMT device and a third HEMT device, wherein the second HEMT device comprises a second gate, a second source and a second drain electrically connected to the first source, and wherein the third HEMT device comprises a third gate, a third source and a third drain electrically connected to the first gate.

Description

BACKGROUND

[0001] Modern integrated chips comprise millions or billions of semiconductor devices fabricated on a semiconductor substrate (e.g., silicon). Depending on the application of an integrated chip (IC), many different types of transistor devices can be used. In recent years, the growing market for cell and RF devices has led to a sharp increase in the use of high-voltage transistor devices. High-voltage transistor devices are often used, for example, in power amplifiers in RF transmit / receive chains because they can handle high breakdown voltages (e.g., greater than about 50 V) and high frequencies.

[0002] US 2020 / 0105741A1 describes a semiconductor device comprising: a first HEMT (High Electron Mobility Transistor) arranged in a semiconductor structure, comprising a first source, a first drain, and a first gate; a second HEMT arranged in the semiconductor structure, comprising a second source coupled to the first drain, a second drain, and a second gate; and a diode-switched transistor arranged in the semiconductor structure, comprising a third source, a third gate, and a third drain coupled to the second gate.

[0003] US 2022 / 0037515A1 discloses a bidirectional blocking monolithic heterogeneously integrated field-effect transistor with a cascode structure. The field-effect transistor consists of a substrate, a GaN buffer layer, an AlGaN junction, and a SiN insulating layer. An insulating groove is etched into the center of the SiN insulating layer. On one side of the insulating groove, an active silicon layer is printed onto the SiN insulating layer to form a silicon metal oxide semiconductor field-effect transistor. On the other side of the insulating groove, a high-electron-mobility GaN transistor is formed. The drain electrode of the high-electron-mobility GaN transistor is in Schottky contact with the AlGaN junction to form a bidirectional blocking monolithic heterogeneously integrated field-effect transistor with a cascode structure.

[0004] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a schematic representation of a cascode HEMT device (HEMT: high electron mobility transistor) according to some embodiments. Fig. Figure 2 shows a schematic sectional view of a cascode HEMT device according to some embodiments. The Fig. 3A, Fig. 3B, Fig. 4A, Fig. 4B, Fig. 5A, Fig. 5B, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A and Fig. Figure 9B shows sectional views of intermediate steps in the fabrication of a first semiconductor structure and a second semiconductor structure of a cascode HEMT device according to some embodiments. The Fig. 10 and Fig. Figure 11 shows intermediate steps in the manufacture of a cascode HEMT device according to some embodiments. The Fig. 12A and Fig. Figure 12B shows a sectional view and a top view of a package cascode HEMT device according to some embodiments. Fig. Figure 13 shows a schematic representation of a cascode HEMT device (HEMT: high electron mobility transistor) according to some embodiments. Fig. Figure 14 shows a schematic sectional view of a cascode HEMT device according to some embodiments. The Fig. 15A, Fig. 15B, Fig. 16A and Fig. Figure 16B shows sectional views of intermediate steps in the fabrication of a first semiconductor structure and a second semiconductor structure of a cascode HEMT device according to some embodiments. The Fig. Figure 17 shows an intermediate step in the manufacture of a cascode HEMT device according to some embodiments. DETAILED DESCRIPTION

[0006] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0008] This disclosure describes various aspects of a package containing HEMT devices (HEMT: high electron mobility transistor) and its fabrication. In some embodiments, the HEMT devices are connected in a cascode configuration (e.g., a "cascode HEMT device"). A cascode HEMT device as described in this disclosure can, in some cases, provide similar functionality to a single high-voltage transistor device with a relatively high breakdown voltage. For example, a circuit containing HEMT devices in a cascode configuration can have an effective breakdown voltage that is greater than the breakdown voltage of any single HEMT device in the circuit.In this way, the use of HEMT devices in a cascode configuration, as described in this disclosure, can enable a higher breakdown voltage without increasing the layer thickness of the individual HEMT devices. For example, the embodiments described in this disclosure can enable a cascode HEMT device with a breakdown voltage of about 1200 V or more.

[0009] In some embodiments, a die or package containing a cascode HEMT device is fabricated by producing HEMT devices on two wafers and then bonding the wafers together to electrically connect the HEMT devices. In some cases, bonding wafers to fabricate a cascode HEMT device can reduce the area of ​​a die or package containing a cascode HEMT device because the HEMT devices are arranged vertically instead of horizontally. Furthermore, bonding wafers to fabricate a cascode HEMT device, as described in this disclosure, can reduce the lengths or amounts of the required conductive traces, thereby reducing resistance or parasitic inductance.Furthermore, the cascode HEMT device as described in this disclosure allows heat dissipation from both the top and bottom surfaces, thereby improving its thermal performance. In this way, the efficiency, speed, heat dissipation, and power consumption of a cascode HEMT device can be improved.

[0010] Fig. Figure 1 shows a schematic representation of a cascode HEMT device 100 (HEMT: high electron mobility transistor) according to some embodiments. The cascode HEMT device 100 comprises a first HEMT device 112 with a first source S1, a first drain D1, and a first gate G1; a second HEMT device 114 with a second source S2, a second drain D2, and a second gate G2; and a third HEMT device 116 with a third source S3, a third drain D3, and a third gate G3. The first HEMT device 112 and the second HEMT device 114 are connected in a cascode configuration. The first HEMT device 112 can, for example, be considered a common gate stage, and the second HEMT device 114 can be considered a common source stage, with the first source S1 connected to the second drain D2.The third HEMT device 116 has a diode-connected configuration and is connected to the first HEMT device 112 and the second HEMT device 114. For example, the third gate G3 is connected to the third source S3, the third drain D3 is connected to the first gate G1, and the third source S3 is connected to the second source S2. The third HEMT device 116 can, for example, be configured to protect the second HEMT device 114 against high voltages (e.g., high voltages between the first drain D1 and the first gate G1) that could cause damage.

[0011] In some embodiments, the first HEMT device 112 can be a depletion device (i.e., a depletion-type device), the second HEMT device 114 can be an enrichment device (i.e., an enrichment-type device), and the third HEMT device 116 can be an enrichment-type HEMT device. The HEMT devices 112, 114, or 116 can have similar or different breakdown voltages. For example, in some embodiments, the first HEMT device 112 can have a higher breakdown voltage than the second HEMT device 114. Other configurations are also possible.

[0012] By connecting the first HEMT device 112 and the second HEMT device 114 in a cascode configuration, the cascode HEMT device 100 can be operated in a manner similar to the operation of a single high-voltage transistor device. For example, the first HEMT device 112 and the second HEMT device 114 are configured to collectively form a common source (SC) terminal 110S of the cascode HEMT device 100, a common drain (DC) terminal 110D of the cascode HEMT device 100, and a common gate (GC) terminal 110G of the cascode HEMT device 100. The cascode HEMT device 100 has a breakdown voltage that is greater than the respective breakdown voltages of either the first HEMT device 112 or the second HEMT device 114.In some embodiments, for example, the first HEMT device 112 and the second HEMT device 114 may each have breakdown voltages of about 650 V, while the cascode HEMT device 100 may have a breakdown voltage of about 1200 V. Other breakdown voltages are also possible. By using the first HEMT device 112 and the second HEMT device 114 to operate as a single high-voltage device, as described in this disclosure, a cascode HEMT device 100 can achieve a high breakdown voltage without using HEMT devices that individually exhibit high breakdown voltages, thereby reducing the size or cost of a high-voltage device.

[0013] In some embodiments, the various HEMT devices can be fabricated on separate substrates and then connected to form a single cascode HEMT device 100. As shown in Fig. As shown in Figure 1, for example, the first HEMT 112 can be fabricated in a first semiconductor structure 200, and the second HEMT 114 and the third HEMT 116 can both be fabricated in a separate second semiconductor structure 300. The first semiconductor structure 200 and the second semiconductor structure 300 can be fabricated on separate wafers or separate substrates, as described in more detail below. Other configurations of HEMT devices or semiconductor structures are also possible.

[0014] Fig. Figure 2 shows a schematic sectional view of a cascode HEMT device according to some embodiments. The in Fig. The cascode HEMT device 100 shown in 2 can be used in Fig. The cascode HEMT device shown in Figure 1 resembles 100. It is understood that the sectional view of Fig. 2. This is a schematic representation shown for illustrative purposes and may not be representative with regard to the size and / or shape of some components in the device. Furthermore, some features may only be shown schematically or not at all.

[0015] As in Fig. As shown in Figure 2, the cascode HEMT device 100 can comprise a first HEMT device 112, fabricated in a first semiconductor structure 200, which is connected to a second HEMT device 114 and a third HEMT device 116, fabricated in a second semiconductor structure 300. In some embodiments, the first semiconductor structure 200 can be fabricated on a first wafer 201, which has a substrate 202, a channel layer 204 over the substrate 202, and an active layer 206 over the channel layer 204; and the second semiconductor structure 300 can be fabricated on a second wafer 301, which has a substrate 302, a channel layer 304 over the substrate 302, and an active layer 306 over the channel layer 304. Substrate 202 and substrate 302 can be separate substrates, and consequently, the first wafer 201 and the second wafer 301 can be separate wafers.In some embodiments, the first semiconductor structure 200 and the second semiconductor structure 300 have different device areas that are subsequently separated. The first semiconductor structures 200 and / or the second semiconductor structures 300 can, for example, be separated before or after bonding a first semiconductor structure 200 to a second semiconductor structure 300 (see ). Fig. 10).

[0016] Substrate 202 and / or substrate 302 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. Substrate 202 and / or substrate 302 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 202 and / or substrate 302 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0017] Channel layer 204 and active layer 206 can have different semiconductor materials with different band gaps, forming a heterojunction between channel layer 204 and active layer 206. For example, the semiconductor material of channel layer 204 can have a smaller band gap than the semiconductor material of active layer 206. The heterojunction forms a two-dimensional electron gas (2DEG) by confining electrons to a quantum well along the interface between channel layer 204 and active layer 206. For example, channel layer 204 can have gallium nitride (GaN) or the like, and active layer 206 can have aluminum gallium nitride (AlGaN) or the like. Similarly, channel layer 304 and active layer 306 can have semiconductor materials that form a heterojunction.The semiconductor materials of the first wafer 201 may be similar to or different from the semiconductor materials of the second wafer 301.

[0018] In some cases, the breakdown voltage of a HEMT device depends on the thickness of its channel layer. For example, a HEMT device with a relatively thicker channel layer may have a correspondingly higher breakdown voltage. However, in some cases, fabricating a thick channel layer (e.g., with a thickness of about 5 µm or more) may increase the fabrication costs or may result in a channel layer having a higher concentration of defects. By connecting the first HEMT device 112 and the second HEMT device 114 to fabricate a cascode HEMT device 100, as described in this disclosure, the HEMT devices 112 / 114 can be fabricated with relatively thin channel layers 204 / 304 (e.g., with thicknesses of about 5 µm or less), while still achieving a high breakdown voltage for the cascode HEMT device 100.

[0019] Other semiconductor materials are also possible. For example, in other embodiments, the channel layers 204 / 304 and the active layers 206 / 306 can comprise III-V semiconductor materials, such as gallium arsenide (GaAs), gallium antimonide (GaSb), or the like. In some embodiments (not shown), a buffer layer can be arranged between the channel layer 204 / channel layer 304 and the corresponding active layer 206 / 306 to reduce the effects of a lattice mismatch. In some embodiments, the buffer layer can comprise aluminum nitride (AlN) or the like, but other materials are also possible.

[0020] Furthermore in Fig. 2. According to some embodiments, one or more isolation regions 208 can be produced in the first wafer 201, and one or more isolation regions 308 can be produced in the second wafer 301. The isolation regions 208 / 308 can provide electrical insulation for the HEMT devices 112 / 114 / 116. For example, in some embodiments, the isolation regions 308 in the second wafer 301 can provide electrical insulation between the second HEMT device 114 and the third HEMT device 116. In some embodiments, the isolation regions 208 are arranged in the channel layer 204 and the active layer 206, and the isolation regions 308 are arranged in the channel layer 304 and the active layer 306. In some embodiments, the isolation regions 208 / 308 can have doped regions (e.g., with fluorine dopant, oxygen dopant, or the like).In other embodiments, the insulation regions 208 / 308 may comprise an insulating material (e.g., a dielectric material or the like). In some cases, the insulation regions 208 / 308 may be shallow trench isolation structures (STI structures) or the like.

[0021] Each of the first HEMT device 112, the second HEMT device 114, and the third HEMT device 116 has a source contact, a drain contact, and a gate contact. Each gate contact is manufactured on a respective gate structure located between the source and drain contacts.For example, the first HEMT device 112 has a source contact 212S corresponding to the first source S1, a drain contact 212D corresponding to the first drain D1, and a gate contact 212G over a gate structure 213, which collectively correspond to the first gate G1; the second HEMT device 114 has a source contact 314S corresponding to the second source S2, a drain contact 314D corresponding to the second drain D2, and a gate contact 314G over a gate structure 315, which collectively correspond to the second gate G2; and the third HEMT device 116 has a source contact 316S corresponding to the third source S3, a drain contact 316D corresponding to the third drain D3, and a gate contact 316G over a gate structure 317, which collectively correspond to the third gate G3.In some embodiments, the distance from the gate to the drain of a HEMT device 112 / 114 / 116 can be in the range of about 15 µm to about 20 µm, but other distances are also possible.

[0022] In some embodiments, the gate structure (e.g., 213, 315, or 317) of each HEMT device 112 / 114 / 116 comprises one or more layers of one or more dielectric and / or semiconductor materials. For example, a gate structure may comprise one or more layers of one or more dielectric materials, such as an oxide, a nitride, or the like, or it may comprise one or more layers of one or more semiconductor materials, such as gallium nitride (e.g., p-doped GaN) or the like. In some embodiments, a gate electrode is fabricated over the gate structure. The gate electrode may comprise a metal (e.g., aluminum, titanium, copper, tungsten, tantalum, or the like), doped polysilicon, the like, or a combination thereof. In some embodiments, the gate contact (e.g., 212G, 314G, or 316G) may function as a gate electrode.The gate structures 213 / 315 / 317 of the HEMT devices 112 / 114 / 116 can be similar or different. For example, in embodiments where the second HEMT device 114 and the third HEMT device 116 are enrichment devices, the gate structure 315 of the second HEMT device 114 and the gate structure 317 of the third HEMT device 116 can each have a doped layer of a semiconductor material. In embodiments where the first HEMT device 112 is a depletion device, the gate structure 213 of the first HEMT device 112 can have a dielectric layer. In other embodiments, each of the three gate structures 213 / 315 / 317 can have a doped layer of semiconductor material. Other combinations are also possible.

[0023] In some embodiments, the first semiconductor structure 200 has a first interconnect structure 220 over the first wafer 201, and the second semiconductor structure 300 has a second interconnect structure 320 over the second wafer 301. The interconnect structures 220 / 320 can each have multiple layers of dielectric material and multiple layers of conductive structural elements. The conductive structural elements can, for example, be metallization structures, redistribution layers, conductive traces, conductive vias, interconnect layers, metal traces, or the like. The first interconnect structure 220 covers the active layer 206 of the first wafer 201 and provides electrical connections to the source contact 212S of the first source S1, to the drain contact 212D of the first drain D1, and to the gate contact 212G of the first gate G1.The second interconnect structure 320 covers the active layer 306 of the second wafer 301 and provides electrical connections to the source contact 314S of the second source S2, to the drain contact 314D of the second drain S2, to the gate contact 314G of the second gate G2, to the source contact 316S of the third source S3, to the drain contact 316D of the third drain D3 and to the gate contact 316G of the third gate G3.

[0024] The Fig. Figures 3A to 11 show sectional views of intermediate steps in the manufacture of a cascode HEMT device 100 (see Fig. 11) according to some embodiments. The cascode HEMT device 100 can be used in the Fig. 1 cascode HEMT device 100 shown or the one in Fig. The cascode HEMT device 100 shown in Figure 2 may resemble this device. For example, the cascode HEMT device 100 may comprise a first HEMT device 112, which is fabricated in a first semiconductor structure 200 and is electrically connected to a second HEMT device 114 and a third HEMT device 116, which are fabricated in a second semiconductor structure 300. Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A and Fig. Figure 9A shows cross-sectional views of intermediate steps in the fabrication of the first semiconductor structure 200, and the Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B and Fig. Figure 9B shows sectional views of intermediate steps in the fabrication of the second semiconductor structure 300 according to some embodiments. Fig. 10 and Fig. Figure 11 shows sectional views of intermediate steps in the manufacture of a cascode HEMT device 100 according to some embodiments, after the first semiconductor structure 200 has been bonded to the second semiconductor structure 300.

[0025] The first semiconductor structure 200 and the second semiconductor structure 300 can be fabricated separately using separate process steps, although in some cases, some of the same process steps can be shared in the fabrication of the first semiconductor structure 200 and the second semiconductor structure 300. The [unclear text] Fig. The process described in 3A-11 for manufacturing a cascode HEMT device 100 is a non-limiting example, and other process steps for manufacturing a cascode HEMT device 100 are also possible. Furthermore, the following should be considered: Fig. The sectional views shown in Figure 3A-11 serve as illustrative examples, and the arrangement, configuration, or dimensions of the structural elements may differ in other embodiments. For example, in other embodiments, some of the structural elements shown in the sectional views of the Fig. Figure 3A-11 is shown, not as a single sectional view. In other words, in other embodiments, some structural elements may be manufactured in different cross-sections than those shown in the figure. Fig. 3A-11. By fabricating the HEMT devices 112 / 114 / 116 in bonded semiconductor structures 200 / 300, as described in this disclosure, the area of ​​a cascode HEMT device 100 can be reduced and the electrical connections between the HEMT devices 112 / 114 / 116 can be improved.

[0026] The Fig. 3A and Fig. Figure 3B shows sectional views of a first wafer 201 and a second wafer 301 according to some embodiments. The first wafer 201 and the second wafer 301 can be added to the first wafer 201 and the second wafer 301 described above for Fig. 2, are similar. For example, the first wafer 201 may have a channel layer 204 and an active layer 206, which are fabricated on a substrate 202; and the second wafer 301 may have a channel layer 304 and an active layer 306, which are fabricated on a substrate 302. The first HEMT device 112 is then fabricated on the first wafer 201, and the Fig. Figure 3A shows approximately the area of ​​the first wafer 201 where the first HEMT device 112 is fabricated. The second HEMT device 114 and the third HEMT device 116 are subsequently fabricated on the second wafer 301, and the Fig. Figure 3B shows approximately the areas of the second wafer 301 where the second HEMT device 114 and the third HEMT device 116 are fabricated. The materials or thicknesses of the various layers of the first wafer 201 and the second wafer 301 can be similar or different. The properties of the various layers can depend on the properties of the subsequently fabricated HEMT devices 112 / 114 / 116. The various layers of the first wafer 201 and the second wafer 301 can be fabricated using suitable processes, which may include, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like.

[0027] With reference to the Fig. 4A and Fig. 4B According to some embodiments, isolation regions 208 can be produced in the first wafer 201, and isolation regions 308 can be produced in the second wafer 301. The isolation regions can, for example, be doped regions extending from a top surface of the active layer to the channel layer. For example, the isolation regions 208 can penetrate the active layer 206 and can extend partially or completely through the channel layer 204, and the isolation regions 308 can penetrate the active layer 306 and can extend partially or completely through the channel layer 304. The isolation regions can partially or completely enclose the subsequently produced HEMT devices 112 / 114 / 116 to provide electrical isolation.For example, one or more isolation areas 308 can be arranged laterally between the second HEMT device 114 and the third HEMT device 116.

[0028] In some embodiments, the isolation regions 208 / 308 can be produced by fabricating a structured mask 209 / 309 over the active layer 206 / 306 and performing an implantation process 211 / 311. For example, suitable photolithographic processes and materials can be used to fabricate the structured mask 209 over the active layer 206 and the structured mask 309 over the active layer 306. In some embodiments, each structured mask 209 / 309 can be produced by depositing a mask material (e.g., a hard mask material, a photoresist material, or the like) using suitable methods and subsequently structuring openings in the mask material using a suitable photolithographic process.The openings in each structured mask 209 / 309 expose portions of the active layer 206 / 306 corresponding to the positions of the isolation regions 208 / 308. An implantation process 211 / 311 can then be performed to implant dopants into the exposed portions of the active layer 206 / 306. In some embodiments, the dopants may be oxygen, fluorine, the like, or a combination thereof. In some embodiments, the implantation process 211 / 311 may have sufficient energy to drive the dopants into the channel layer 204 / 304. In some embodiments, a diffusion-tempering process may be performed to diffuse the dopants after the implantation process 211 / 311 has been carried out. After the implantation process 211 / 311 has been carried out, the structured mask 209 / 309 may be removed using a suitable removal process, etching process, or the like.Other dopants, process steps or methods for producing the isolation areas 208 / 308 are also possible.

[0029] In the Fig. 5A and Fig. 5B Source contacts, drain contacts, gate structures, and gate contacts of the HEMT devices are fabricated according to some embodiments. The source contact 212S, the drain contact 212D, the gate structure 213, and the gate contact 212G of the first HEMT device 112 can be fabricated on the first wafer 201. For example, in some embodiments, the gate structure 213 of the first HEMT device 112 is fabricated by depositing a gate structure material over the active layer 206 of the first wafer 201 and then structuring the gate structure material to fabricate the gate structure 213. In some embodiments, the gate structure material for the gate structure 213 can, for example, be a dielectric layer deposited using a suitable method.The gate structure material can then be structured using suitable photolithographic and etching processes, with the remaining parts of the gate structure material forming the gate structure 213. In other embodiments, the gate structure 213 can be produced by first producing a structured mask over the active layer 206 and then depositing the gate structure material over the structured mask and exposed parts of the active layer 206.

[0030] After fabrication of the gate structure 213, a conductive material can be deposited and patterned to create the source contact 212S, the drain contact 212D, and the gate contact 212G according to some embodiments. The conductive material can be a metal (e.g., aluminum, titanium, copper, tungsten, tantalum, or the like), doped polysilicon, the like, or a combination thereof. The conductive material can be deposited over the active layer 206 and the gate structure 213 using a suitable process, such as CVD, PECVD, ALD, PVD, plating, or the like. After deposition of the conductive material, it can be patterned using suitable photolithographic and etching techniques. For example, a photoresist can be deposited over the conductive material and patterned, the structure corresponding to the source contact 212S, the drain contact 212D, and the gate contact 212G.A suitable etching process (e.g., wet etching and / or dry etching) can then be performed. After the etching process, the remaining portions of the conductive material on the active layer 206 form the source contact 212S and the drain contact 212D, and the remaining portions of the conductive material on the gate structure 213 form the gate contact 212G. This is one example, and other materials or processes are also possible. For instance, in other embodiments, a dielectric layer of the first interconnect structure 220 can be deposited and patterned over the active layer 206 and the gate structure 213 to form openings, and then the conductive material can be deposited into the openings. The gate contact 212G and its underlying gate structure 213 can have the same width (e.g., have congruent sidewalls) or they can have different widths.In some embodiments, the process steps used to manufacture the source contact 212S, the drain contact 212D and the gate contact 212G also produce parts of one or more sealing ring structures 210, which are described below. Fig. 6A will be described in more detail.

[0031] The source contact 314S, the drain contact 314D, the gate structure 315, and the gate contact 314G of the second HEMT device 114, and the source contact 316S, the drain contact 316D, the gate structure 317, and the gate contact 316G of the third HEMT device 116, can be fabricated on the second wafer 301. In some embodiments, the contacts and gate structures of the second HEMT device 114 and the third HEMT device 116 are fabricated using materials and / or methods similar to those used to fabricate the contacts and gate structure of the first HEMT device 112.For example, in some embodiments, the gate structure 315 of the second HEMT device 114 and the gate structure 317 of the third HEMT device 116 can be fabricated by depositing a gate structure material over the active layer 306 of the second wafer 301 and subsequently structuring the gate structure material using suitable photolithographic and etching processes. In some embodiments, the gate structure material for the gate structure 315 and the gate structure 317 can, for example, be a semiconductor material deposited by a suitable process.

[0032] After fabricating the gate structures 315 / 317, the source contacts 314S / 316S, the drain contacts 314D / 316D, and the gate contacts 314G / 316G can be produced, for example, by depositing a conductive material over the active layer 306 and the gate structures 315 / 317 and subsequently structuring the conductive material using suitable photolithographic and etching processes. The remaining portions of the conductive material on the active layer 306 form the source contacts 314S / 316S and the drain contacts 314D / 316D, the remaining portions of the conductive material on the gate structure 315 form the gate contact 314G, and the remaining portions of the conductive material on the gate structure 317 form the gate contact 316G. This is one example, and other materials or processes are also possible. The 314G / 316G gate contacts and the respective underlying 315 / 317 gate structures can have the same width (e.g.,(have congruent sidewalls) or can have different widths. In some embodiments, the process steps used to manufacture the source contacts 314S / 316S, the drain contacts 314D / 316D, and the gate contacts 314G / 316G also produce parts of one or more sealing ring structures 310, which are described below. Fig. 6B will be described in more detail.

[0033] In the Fig. 6A and Fig. In some embodiments of 6B, a first interconnect structure 220 is fabricated over the first wafer 201, and a second interconnect structure 320 is fabricated over the second wafer 301. The interconnect structures 220 / 320 each have one or more dielectric layers and one or more layers of conductive structural elements (e.g., metallization structures or the like). For example, the first interconnect structure 220 may have conductive structural elements, such as conductive traces 222, conductive vias 223, conductive pads 224, or the like, fabricated in the dielectric layers 221, and the second interconnect structure 320 may have conductive structural elements, such as conductive traces 322, conductive vias 323, conductive pads 324, or the like, fabricated in the dielectric layers 321.The conductive structural elements of the interconnect structures 220 / 320 can also include sealing ring structures 210 / 310, which are described in more detail below. The interconnect structures 220 / 320, which are described in the... Fig. Figures 6A-6B are examples, and the interconnect structures 220 / 320 may have different numbers, configurations or arrangements of conductive structural elements or dielectric layers 221 / 321 in other embodiments.

[0034] The dielectric layers 221 / 321 of the interconnect structures 220 / 320 can be, for example, interlayer dielectric layers (ILD layers) and / or intermetallization dielectric layers (IMD layers). In some embodiments, the dielectric layers 221 / 321 are made from a dielectric material (which may be a low-k dielectric material) such as phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon oxide, silicon nitride, silicon oxide carbide, silicon-carbon, spin-on glass (SOG), one or more polymers, molding compounds, combinations thereof, or the like. The dielectric layers 221 / 321 can be produced using suitable processes such as spin deposition, CVD, PECVD, ALD, or the like.

[0035] In some embodiments, etch stop layers (not shown) can be produced between adjacent dielectric layers of dielectric layers 221 / 321 (e.g., "arranged between"). The etch stop layers can be made of a dielectric material that has a different etch selectivity than adjacent layers (e.g., the dielectric layers above and below). In some embodiments, the etch stop layers are made of a material such as silicon nitride, silicon carbonitride, silicon oxide carbide, titanium oxide, tantalum oxide, the like, or a combination thereof. The etch stop layers can be produced using a suitable process such as CVD, PECVD, ALD, or the like.

[0036] The conductive lines 222 / 322 and conductive vias 223 / 323 in the interconnect structures 220 / 320 provide electrical connections to the HEMT devices 112 / 114 / 116. As shown in Fig. As shown in Figure 6A, the conductive lines 222 and the conductive vias 223 of the first interconnect structure 220 establish electrical connections to the source contact 212S, the drain contact 212D, and the gate contact 212G of the first HEMT 112. As shown in Fig. As shown in Figure 6B, the conductive lines 322 and the conductive vias 323 of the second interconnect structure 320 establish electrical connections to the source contact 314S, the drain contact 314D, and the gate contact 314G of the second HEMT 114 and to the source contact 316S, the drain contact 316D, and the gate contact 316G of the third HEMT 116. As shown in Fig. As shown in Figure 6B, the conductive lines 322 and the conductive vias 323 in the second interconnect structure 320 also connect the second HEMT device 114 and the third HEMT device 116 to each other. For example, the source contact 314S of the second HEMT device 114 is electrically connected to the source contact 316S and the gate contact 316G of the third HEMT device 116.

[0037] The conductive pads 224 / 324 are conductive structural elements on the top surfaces of each interconnect structure 220 / 320, which are electrically connected to the conductive lines 222 / 322 and / or the conductive vias 223 / 323 of the interconnect structure 220 / 320. Electrical connections to the interconnect structures 220 / 320 can be established via the conductive pads 224 / 324, such as electrical connections between the first interconnect structure 220 and the second interconnect structure 320 (see Fig. 10) or electrical connections to conductive pads 224 / 324 (see the Fig. 9A-9B). The first interconnect structure 220, for example, comprises a conductive pad 224S1 electrically connected to the source contact 212S; a conductive pad 224D1 electrically connected to the drain contact 212D; and a conductive pad 224G1 electrically connected to the gate contact 212G. The second interconnect structure 320, for example, comprises a conductive pad 324D2 electrically connected to the drain contact 314D; a conductive pad 324G2 electrically connected to the gate contact 314G; and a conductive pad 324D3 electrically connected to the drain contact 316D. and a conductive pad 324S2, which is electrically connected to the source contact 314S, the source contact 316S and the gate contact 316G. Other configurations of conductive pads 224 / 324 are also possible.

[0038] The conductive structural elements (e.g., conductive traces, conductive vias, conductive pads, or the like) can be fabricated using any suitable process, such as a Damascene process, a dual-Damascene process, or the like. In some embodiments, the conductive structural elements comprise a conductive material fabricated over a coating. The coating can be, for example, a barrier layer, an adhesive layer, or the like. The coating can be, for example, tantalum, tantalum nitride, titanium, titanium nitride, cobalt, tungsten, the like, or a combination thereof. The conductive material can be a conductive material such as copper, tungsten, aluminum, silver, combinations thereof, or the like. Other materials or fabrication methods are also possible.

[0039] In some embodiments, sealing ring structures 210 / 310 are manufactured within the interconnect structures 220 / 320. The sealing ring structures 210 / 310 can be manufactured, for example, to protect structural elements in the semiconductor structures 200 / 300 against water, chemicals, residues, and / or other contaminants that may be present during processing. In some cases, the sealing ring structures 210 / 310 can be manufactured along a periphery or near the edges of the interconnect structure 210 / 310. In some embodiments, the sealing ring structures 210 / 310 can be continuous structures.For example, the sealing ring structure 210 can enclose the first HEMT 112, the conductive traces 222, the conductive vias 223, and / or the conductive pads 224 of the first semiconductor structure 200; and the sealing ring structure 310 can enclose the second HEMT 114, the third HEMT 116, the conductive traces 322, the conductive vias 323, and / or the conductive pads 324 of the second semiconductor structure 300. In some embodiments, the sealing ring structures 210 / 310 are manufactured using the same process steps used to manufacture the contacts 212 / 314 / 316, the conductive traces 222 / 322, the conductive vias 223 / 323, and / or the conductive pads 224 / 324. In some embodiments, the sealing ring structures 210 / 310 are electrically isolated from some or all of the other conductive structural elements of the interconnect structures 220 / 320. The... Fig. The sealing ring structures 210 / 310 shown in Figures 6A-6B are examples, and the sealing ring structures 210 / 310 may have different numbers, configurations or arrangements in other embodiments.

[0040] The Fig. Figures 7A-7B, 8A-8B, and 9A-9B show intermediate steps in the fabrication of sealing ring structures 227 / 327 and contact structures 228 / 328 according to some embodiments. The sealing ring structures 227 and the contact structures 228 are fabricated in the first semiconductor structure 200 (see Figure 7A-7B). Fig. 9A), and the sealing ring structures 327 and the contact structures 328 are manufactured in the second semiconductor structure 300 according to some embodiments (see Fig. 9B). The sealing ring structures 227 / 327 are manufactured to enclose and protect structural elements in the semiconductor structures 200 / 300, similar to the sealing ring structures 210 / 310 described above. The sealing ring structures 227 / 327 can be manufactured along a periphery or near the edges of the semiconductor structures 200 / 300 and, in some embodiments, can be continuous structures. The sealing ring structures 227 / 327 can be manufactured in addition to or instead of the sealing ring structures 210 / 310, and they can be manufactured on the inside or outside of the sealing ring structures 210 / 310. The sealing ring structures 210 and 227 together, or the sealing ring structures 310 and 327 together, can, in some cases, be referred to as a “sealing ring”.In some embodiments, the contact structures 228 / 328 can be produced so that electrical connections can be established through the substrates 202 / 302 to the HEMT devices 112 / 114 / 116. In the case of... Fig. In the embodiment shown in 9B, for example, the contact structures 328S / 328G are produced to make electrical connections to the contacts 324S / 324G of connecting elements 332 (see Fig. 11) to provide. In some embodiments, a contact structure can be created to provide an electrical connection to a substrate. In the embodiment described in Fig. In the embodiment shown in Figure 9A, for example, the contact structure 228S is produced to provide an electrical connection between the source contact 212S and the substrate 202. In other embodiments, other dimensions, arrangements, or configurations of the sealing ring structures 227 / 327 or contact structures 228 / 328 are also possible.

[0041] In the Fig. 7A and Fig. In some embodiments, openings 225 and 226S are fabricated in the first semiconductor structure 200, and openings 325, 326S, and 326G are fabricated in the second semiconductor structure 300. Openings 225 and 226S extend through the first interconnect structure 220, the active layer 206, and the channel layer 204 to expose surfaces of the substrate 202. Subsequently, the sealing ring structure 227 is fabricated in opening 225. The contact structure 228S is then fabricated in opening 226S, and in some embodiments, opening 226S is fabricated such that a portion of the conductive pad 224S is exposed in opening 226S. The openings 325, 326S and 326G extend through the second interconnect structure 320, the active layer 306 and the channel layer 304 to expose surfaces of the substrate 302.The contact structure 328S is subsequently fabricated in the opening 326S, and in some embodiments, the opening 326S is fabricated such that part of the conductive pad 324S is exposed in the opening 326S. The contact structure 328G is subsequently fabricated in the opening 326G, and in some embodiments, the opening 326G is fabricated such that part of the conductive pad 324G is exposed in the opening 326G. The openings 225 / 226 / 325 / 326 can be fabricated using suitable photolithographic and etching processes.

[0042] In the Fig. 8A and Fig. In 8B, a conductive material is deposited in the openings 225 / 226 / 325 / 326 to produce sealing ring structures 227 / 327 and contact structures 228 / 328, according to some embodiments. The conductive material can be deposited on the sidewall surfaces and bottom surfaces of the openings 225 / 226 / 325 / 326. In some embodiments, the bottom surfaces of the openings 225 / 226 / 325 / 326 can be exposed surfaces of the substrates 202 / 302. In some embodiments, the sidewall surfaces of the openings 226 / 326 can have an exposed portion of a conductive pad 224 / 324. In some embodiments, the conductive material can be similar to the conductive material previously described for producing the conductive structural elements of the interconnect structures 220 / 320. For example, the conductive material deposited in the openings 225 / 226 / 325 / 326 may consist of aluminium, tungsten, copper or the like.The conductive material can be deposited using a suitable process such as CVD, PVD, plating, or the like. In some embodiments, for example, an unstructured seed layer (not shown) can be deposited on surfaces in openings 225 / 226 / 325 / 326, and the conductive material can then be deposited using a plating process. Other materials or processes are also possible.

[0043] As in Fig. As shown in Figure 8A, the conductive material in the openings 225 forms the sealing ring structures 227, and the conductive material in the opening 226S forms the contact structure 228S. The conductive material in the opening 226S makes physical and electrical contact with an exposed portion of the conductive pad 224S, and consequently, the contact structure 228S is electrically connected to the conductive pad 224S. The conductive material of the contact structure 228S also makes physical and electrical contact with an exposed surface of the substrate 202. In this way, the contact structure 228S can form an electrical connection between the source (e.g., S1) and the body of the first HEMT device 112 in some embodiments.

[0044] As in Fig. As shown in Figure 8B, the conductive material in openings 325 forms the sealing ring structures 327, the conductive material in opening 326S forms the contact structure 328S, and the conductive material in opening 326G forms the contact structure 328G. The conductive material in opening 326S physically and electrically contacts an exposed part of the conductive pad 324S, and consequently, the contact structure 328S is electrically connected to the conductive pad 324S. The conductive material in opening 326G physically and electrically contacts an exposed part of the conductive pad 324G, and consequently, the contact structure 328G is electrically connected to the conductive pad 324G.

[0045] In the Fig. 9A and Fig. In some embodiments, dielectric material 229 / 329 is deposited in 9B to fill the openings 225 / 226 / 325 / 326. The dielectric material 229 can be deposited over the first semiconductor structure 200 to fill the openings 225 and 226S, and the dielectric material 329 can be deposited over the second semiconductor structure 300 to fill the openings 325, 326S, and 326G. In some embodiments, the dielectric material 229 / 329 can be a material similar to that described above for the dielectric layers 221 / 321. For example, the dielectric material 229 / 329 can be silicon oxide, silicon nitride, glass, a molding compound, a polymer, or the like, and can be deposited using a suitable process such as CVD, flowable CVD (FCVD), PVD, ALD, or the like. Other materials or deposition methods are also possible.The dielectric material 229 / 329 can provide electrical insulation, protection during machining, and / or structural support. In some embodiments, a planarization process (e.g., a chemical mechanical polishing (CMP) process, a grinding process, or the like) is performed to remove excess dielectric material 229 / 329 from the top surfaces of the interconnect structures 220 / 320. In some embodiments, the planarization process can also remove excess conductive material that has been deposited to produce the sealing ring structures 227 / 327 and the contact structures 228 / 328.

[0046] In Fig. In some embodiments, the first semiconductor structure 200 is bonded to the second semiconductor structure 300. Bonding the first semiconductor structure 200 to the second semiconductor structure 300 electrically connects the first HEMT device 112, the second HEMT device 114, and the third HEMT device 116. In some embodiments, for example, the conductive pad 224S is bonded to the conductive pad 324D2 by a conductive connecting element 120A, which electrically connects the source (e.g., the first source S1) of the first HEMT device 112 to the drain (e.g., the second drain D2) of the second HEMT device 114. In some embodiments, a conductive pad 224G is bonded to the conductive pad 324D3 by a conductive connecting element 120B, which electrically connects the gate (e.g. the first gate G1) of the first HEMT device 112 to the drain (e.g. the third drain D3) of the third HEMT device 116.In this way, a single structure can be manufactured that includes the first HEMT device 112, the second HEMT device 114 and the third HEMT device 116 in a cascode configuration.

[0047] The conductive interconnects 120A-B can be, for example, ball grid array interconnects (BGA interconnects), solder balls, metal pillars, C4 contact bumps (C4: Controlled Collapse Chip Interconnect), microbumps, contact bumps produced using the ENEPIG process (ENEPIG: Electroless Nickel Electroless Palladium Immersion Gold), or the like. The conductive interconnects 120A-B can comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the interconnects 120A-B are manufactured by first producing a layer of solder by vapor deposition, electroplating, printing, solder transfer, bead placement, or the like. After the solder layer has been produced on the structure, a melting process can be performed to bring the material into the desired contact bump shapes.In another embodiment, the conductive connecting elements 120A-B are metal columns (such as copper columns) produced by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns may be solderless and have substantially vertical sidewalls. In some embodiments, a metallic capping layer is produced on the metal columns. The metallic capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be produced by a plating process.

[0048] In some embodiments, the conductive interconnects 120A-B are fabricated on the first semiconductor structure 200 (e.g., on the conductive pads 224S and 224G) and then brought into physical contact with the second semiconductor structure 300 (e.g., on the conductive pads 324D2 and 324D3) using, for example, a pick-and-place process or the like. After they have been brought into physical contact, a melting process can be used to bond the conductive interconnects 120A-B to the semiconductor structure 300. In other embodiments, the conductive interconnects 120A-B are fabricated on the second semiconductor structure 300 instead of on the first semiconductor structure 200. In still other embodiments, conductive interconnects or their materials are fabricated on both the first semiconductor structure 200 and the second semiconductor structure 300.

[0049] In other embodiments, no conductive connecting elements 120 are fabricated on the semiconductor structures 200 / 300, and the semiconductor structures 200 / 300 are bonded using a direct bonding process, such as fusion bonding, metal-to-metal bonding, dielectric-to-dielectric bonding, hybrid bonding, thermocompression bonding, or the like. For example, the conductive pad 224S can be bonded to the conductive pad 324D2 by metal-to-metal bonding, and the conductive pad 224G can be bonded to the conductive pad 324D3 by metal-to-metal bonding.

[0050] In some embodiments, an underfill 105 is deposited in the gap between the first semiconductor structure 200 and the second semiconductor structure 300. The underfill 105 can encapsulate the conductive interconnects 120A-B. The underfill 105 can be a material such as a molding compound, an encapsulation material, an epoxy, an underfill, a molding underfill (MUF), a resin, or the like. The underfill 105 can protect the conductive interconnects 120 and can provide structural support for the cascode HEMT device 100 (see Fig. 11) In some embodiments, the underfill 105 can be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the underfill 105, the first semiconductor structure 200, and / or the second semiconductor structure 300 have sidewalls that are coplanar or congruent. In other embodiments, the width of the first semiconductor structure 200 can differ from the width of the second semiconductor structure 300, and consequently, a sidewall of the first semiconductor structure 200 can be laterally offset from a sidewall of the second semiconductor structure 300. In other embodiments, a sidewall of the semiconductor structure 200 / 300 is an exposed surface of a gate sealing structure 227 / 327.

[0051] In Fig. Eleven vias 232D, 332S, and 332G are fabricated on the first semiconductor structure 200 and the second semiconductor structure 300 to fabricate the cascode HEMT device 100 according to some embodiments. The vias 232D / 332S / 332G enable external electrical connections to the contact structures 228 / 328. For example, in some embodiments, a via 232D is fabricated through the first semiconductor structure 200, providing an electrical connection to the drain (e.g., the first drain D1) of the first HEMT device 112. In this way, the via 232D can serve as the common drain terminal (DC terminal) 110D of the cascode HEMT device 100.In some embodiments, a via connection element 332S is made through the second semiconductor structure 300, which establishes an electrical connection to the contact structure 328S. In this way, the via connection element 332S can serve as the common source terminal (SC terminal) 110S of the cascode HEMT device 100. In some embodiments, a via connection element 332G is made through the second semiconductor structure 300, which establishes an electrical connection to the contact structure 328G. In this way, the via connection element 332G can serve as the common gate terminal (GC terminal) 110G of the cascode HEMT device 100.By manufacturing through-hole interconnects 232D / 332S / 332G as described in this disclosure, external connections to the cascode HEMT device 100 can be made on both sides of the cascode HEMT device 100 instead of only on a single side. This enables a more vertically structured cascode HEMT device 100, which has a reduced footprint and shorter internal connections.

[0052] In some embodiments, the substrate 202 and / or the substrate 302 are thinned using a planarization process, such as a CMP process or a grinding process, before the via interconnects 232D / 332S / 332G are fabricated. In some embodiments, the via interconnect 232D is fabricated by creating an opening (not shown) in the first semiconductor structure 200 that extends through the first wafer 201 and the dielectric layers 221 of the first interconnect structure 220 to expose a portion of the conductive pad 224D. The opening can be fabricated using a suitable photolithographic and etching process. In some embodiments, an insulating layer 230 is then deposited on the top surfaces of the substrate 202 and on the sidewalls of the opening.The insulating layer 230 can comprise one or more layers of dielectric material, such as an oxide material, a nitride material, a polymer material, a glass material, or the like, which can be produced using suitable methods. A conductive material is then deposited in the opening (e.g., on the exposed portion of the conductive pad 224D) and on top surfaces of the insulating layer 230 to form the via-hole interconnect 232D. The conductive material can be, for example, aluminum, tungsten, copper, or the like. The conductive material can be deposited using a suitable method, such as CVD, PVD, plating, or the like. For example, in some embodiments, a seed layer (not shown) can be deposited without a structure, and then the conductive material can be deposited onto the seed layer using a plating process.In some embodiments, areas of the seed layer can be covered (e.g., with a structured photoresist) to block the deposition of the conductive material in these areas. Other materials or methods are also possible. In some embodiments, the portion of the via-connection element 232D that extends onto a top surface of the insulating layer 230 can have an area in the range of approximately 10,000 µm. 2 up to about 100 mm 2 is located, but other surfaces are also possible. In some cases, the fabrication of a via-connection element 110D, as described in this disclosure, enables a large contact area (e.g., to the die pad 155, which is described in the Fig. 12A-12B is shown), which can reduce resistance and improve heat dissipation.

[0053] In some embodiments, the through-hole interconnects 332S and 332G are fabricated by creating openings (not shown) in the second semiconductor structure 300 that extend through the substrate 302 to expose portions of the contact structures 328S and 328G, respectively. The openings can be fabricated using a suitable photolithographic and etching process. In some embodiments, an insulating layer 330 is then fabricated on the top surfaces of the substrate 302 and on the sidewalls of the openings. A conductive material can then be deposited in the openings (e.g., on exposed portions of the contact structures 328S and 328G) and on the top surfaces of the insulating layer 330 to fabricate the through-hole interconnects 332S and 332G. The conductive material can be, for example, aluminum, tungsten, copper, or the like.The conductive material can be produced using a suitable process, such as CVD, PVD, plating, or the like. For example, in some embodiments, an unstructured seed layer (not shown) can be deposited, and then the conductive material can be deposited onto the seed layer using a plating process. In some embodiments, areas of the seed layer can be covered (e.g., with a structured photoresist) to block the deposition of the conductive material in those areas. Other materials or processes are also possible. In some embodiments, the portion of the via connection element 332S that extends onto a top surface of the insulating layer 230 can have an area in the range of approximately 10,000 µm. 2 up to about 100 mm 2lies, and the part of the via connection element 332G that extends through a top surface of the insulating layer 230 can have an area in the range of approximately 10000 µm 2 up to about 100 mm 2 It is located there, but other areas are also possible.

[0054] In some embodiments, a cascode HEMT device as described in this disclosure can be integrated into a package. For example, the Fig. 12A and Fig. Figure 12B shows a sectional view and a top view of a package 150 comprising a cascode HEMT device 100 according to some embodiments. The top view shown in Fig. Figure 12B is shown for illustrative purposes, and some structural elements are omitted for clarity. Furthermore, the embodiments described in the Fig. Figures 12A-12B are illustrative examples, and the dimensions, arrangement, or configuration of the various structural elements may differ in other embodiments. The cascode HEMT device 100 can be compared to the cascode HEMT device 100 shown in Fig. The device described in section 11 may resemble, or may resemble, some other embodiments of cascode HEMT devices described elsewhere in this disclosure. The structural elements in the package 150 may be enclosed or encapsulated by a molding material 152, which may, for example, be a molding compound, an encapsulation material, an epoxy, a composite material, or the like.

[0055] In some embodiments, the package 150 has a terminal frame 153 comprising a die pad 155 and a plurality of terminals 154. The terminals 154 are conductive structural elements through which external connections to the package 150 can be established. For example, the package 150 includes one or more terminals 154D that are electrically connected to the via connection element 232D of the cascode HEMT device 100, one or more terminals 154S that are electrically connected to the via connection element 332S of the cascode HEMT device 100, and one or more terminals 154G that are electrically connected to the via connection element 332G of the cascode HEMT device 100. The connection frame 153 also includes a die pad 155, which is a conductive plate to which the cascode HEMT device 100 is attached.In some embodiments, the connection frame 153 and the terminals 154D are part of a continuous conductive structure.

[0056] As in the Fig. As shown in Figures 12A-12B, the via connection element 232D of the cascode HEMT device 100 is attached to the die pad 155, which electrically connects the terminals 154D to the common drain (DC) terminal 110D of the cascode HEMT device 110. In some embodiments, the via connection element 232D is attached to the die pad 155 by a conductive adhesive, solder, or the like. In some embodiments, the area of ​​the via connection element 232D can be almost as large as the area of ​​the cascode HEMT device 100. For example, in some embodiments, the area of ​​the via connection element 232D can be between about 30% and about 100% of the area of ​​the cascode HEMT device 100.Accordingly, the contact area between the die pad 155 and the via connector 232D can be approximately the same size as the area of ​​the via connector 232D, which in some cases can be approximately the same size as the entire cascode HEMT device 100. In some cases, larger conductive structural elements and / or a larger contact area can provide a larger current path, lower resistance, better interconnection, greater current capacity, and / or less heat generation. For example, in some cases, a conductive structural element with a large area, such as the via connector 232D or the die pad 155, can exhibit less resistance than smaller conductive structural elements, such as wire bonds.In this way, connecting the terminals 154 to the cascode HEMT device 100 using the via connection element 232 and the die pad 155, as described in this disclosure, can lead to improved efficiency, lower heating, lower power consumption and / or better performance of a package, such as the package 150.

[0057] As in the Fig. As shown in Figures 12A-12B, in some embodiments the via connection element 332G of the cascode HEMT device 100 can be electrically connected to the terminal 154G by a terminal connection element 152G, which connects the terminal 154G to the common gate terminal (GC terminal) 110G of the cascode HEMT device 110. The terminal connection element 152G can, for example, be a metal plate, a metal pad, a metal terminal, a metal layer or foil, or the like, of a suitable shape, which is attached to both the via connection element 332G and the terminal 154G. In some embodiments, the terminal connection element 152G is attached with a conductive adhesive, solder, or the like. In other embodiments, the terminal connection element 152G can be formed from a layer of deposited metal.The terminal connector 152G can partially or completely cover the via connector 332G, and consequently, in some cases, the contact area between the terminal connector 152G and the via connector 332G can be approximately the same size as the area of ​​the via connector 332G. Providing a larger contact area in this way can reduce resistance and improve device performance, as described above. Furthermore, connecting terminal 154G using a terminal connector 152G, as described in this disclosure, instead of a wire bond connection, allows for lower resistance and improved device performance.

[0058] As in the Fig. As shown in Figures 12A-12B, in some embodiments the via connector 332S of the cascode HEMT device 100 can be electrically connected to the terminals 154S by a terminal connector 152S. The terminal connector 152S may resemble the terminal connector 152G, although the terminal connector 152S may have a different shape or dimensions. In some embodiments, all terminals 154S are connected to the via connector 332S by a single terminal connector 152S.The terminal connector 152S can partially or completely cover the via connector 332S, and consequently, in some cases, the contact area between the terminal connector 152S and the via connector 332S can be approximately the same size as the area of ​​the via connector 332S. Providing a larger contact area in this way reduces resistance and improves device performance, as described above. Furthermore, connecting the terminals 154G using a single terminal connector 152S, as described in this disclosure, instead of wire bonds, enables lower resistance and improved device performance.

[0059] In some embodiments, the package 150 may include one or more heat sinks 156 to improve the heat dissipation and thermal performance of the cascode HEMT device 100. For example, a heat sink 156A may be arranged over one side of the cascode HEMT device 100, and a heat sink 156B may be arranged over the opposite side of the cascode HEMT device 100. In this way, the cascode HEMT device 100 may be positioned between two heat sinks 156A-B. As shown in Fig. As shown in Figure 12A, a heat sink 156A can be positioned relatively close to the second HEMT device 114 and the third HEMT device 116, and a heat sink 156B can be positioned relatively close to the first HEMT device 112. By positioning the heat sinks 156A-B close to the HEMT devices 112 / 114 / 116 on opposite sides of the cascode HEMT device 100, improved heat dissipation and thermal performance can be achieved. In some embodiments, a heat sink 156A can be attached or positioned close to the terminal connectors 152S and / or 152G, and a heat sink 156B can be attached or positioned close to the die pad 155. In some cases, heat dissipation can be improved by attaching the heat sinks 156A-B to the conductive structural elements 152S / 152G / 155.In some cases, the large surfaces of the connection connectors 152S / 152G and the die pad 155 allow the attachment of heat sinks 156A-B with correspondingly large surfaces, thereby improving heat dissipation and thermal performance.

[0060] Fig. Figure 13 shows a schematic representation of a cascode HEMT device (HEMT: high electron mobility transistor) 400 according to some embodiments. The cascode HEMT device 400 comprises a first HEMT device 412, a second HEMT device 414, and a third HEMT device 416. The cascode HEMT device 400 is similar to the cascode HEMT device 100 described above for Fig. as described above, except that all three of the HEMT devices 412 / 414 / 416 of the cascode HEMT device 400 are enrichment devices. (In the cascode HEMT device 100, the first HEMT device 112 is a depletion device, and the second HEMT device 114 and the third HEMT device 116 are enrichment devices.) The cascode HEMT device 400 can be fabricated using similar materials and / or methods to those described above for the cascode HEMT device 100. For example, the first HEMT 412 can be formed in a first semiconductor structure 500, and the second HEMT 414 and the third HEMT 416 can both be formed in a separate second semiconductor structure 600.Accordingly, some details, structural elements, materials, or procedures of the Cascode HEMT Device 400, which are similar to those described above for the Cascode HEMT Device 100, may not be repeated in the following discussion.

[0061] Furthermore in Fig. The cascode HEMT device 400 comprises a first HEMT device 412 with a first source S1, a first drain D1, and a first gate G1; a second HEMT device 414 with a second source S2, a second drain D2, and a second gate G2; and a third HEMT device 416 with a third source S3, a third drain D3, and a third gate G3. The first HEMT device 412 and the second HEMT device 414 are connected in a cascode configuration. For example, the first HEMT device 412 can be considered a common drain stage, and the second HEMT device 414 can be considered a common source stage, with the first source S1 connected to the second drain D2. The third HEMT device 416 has a diode-connected circuit configuration and is connected to the first HEMT device 412 and the second HEMT device 414.For example, the third gate G3 is connected to the third source S3, the third drain D3 is connected to the first gate G1, and the third source S3 is connected to the second gate G2. The third HEMT device 416 can be configured to protect, for example, the second HEMT device 414 against high voltages (e.g., high voltages between the first drain D1 and the first gate G1) that could cause damage.

[0062] As described above, the first HEMT device 412, the second HEMT device 414, and the third HEMT device 416 are enhancement devices (i.e., enhancement-type devices). The HEMT devices 412, 414, or 416 may each have similar breakdown voltages or different breakdown voltages. For example, in some embodiments, the first HEMT device 412 may have a higher breakdown voltage than the second HEMT device 414. However, other configurations are also possible. By connecting the first HEMT device 412 and the second HEMT device 414 in a cascode configuration, the cascode HEMT device 400 can be operated in a manner similar to the operation of a single high-voltage transistor device.For example, the first HEMT device 412 and the second HEMT device 414 are configured to collectively form a common source terminal (SC terminal) 410S of the cascode HEMT device 400, a common drain terminal (DC terminal) 410D of the cascode HEMT device 400, and a common gate terminal (GC terminal) 410G of the cascode HEMT device 400. The cascode HEMT device 400 has a breakdown voltage that is greater than the respective breakdown voltages of either the first HEMT device 412 or the second HEMT device 414. For example, in some embodiments, the first HEMT device 412 and the second HEMT device 414 may each have breakdown voltages of approximately 650 V, while the cascode HEMT device 400 may have a breakdown voltage of approximately 1200 V. Other breakdown voltages are also possible.By using the first HEMT device 412 and the second HEMT device 414 to operate them as a single high-voltage device, as described in this disclosure, a cascode HEMT device 400 can achieve a high breakdown voltage without using HEMT devices that individually exhibit high breakdown voltages, thereby reducing the size or cost of a high-voltage device.

[0063] Fig. Figure 14 shows a schematic sectional view of a cascode HEMT device 400 according to some embodiments. The cascode HEMT device 400, which is described in Fig. Figure 14 shows that it may resemble the cascode HEMT device 400, which is shown in Fig. Figure 13 is shown. It is understood that the sectional view of Fig. Figure 14 is a schematic representation shown for illustrative purposes and may not be representative with regard to the size and / or shape of some components in the device. Furthermore, some structural elements may only be shown schematically or not at all.

[0064] As in Fig. As shown in Figure 14, the first HEMT device 412 has a source contact 512S corresponding to the first source S1, a drain contact 512D corresponding to the first drain D1, and a gate contact 512G over a gate structure 513, which collectively correspond to the first gate G1; the second HEMT device 414 has a source contact 614S corresponding to the second source S2, a drain contact 614D corresponding to the second drain D2, and a gate contact 614G over a gate structure 615, which collectively correspond to the second gate G2; and the third HEMT device 416 has a source contact 616S corresponding to the third source S3, a drain contact 616D corresponding to the third drain D3, and a gate contact 616G over a gate structure 617, which collectively correspond to the third gate G3. The gate structures 513 / 615 / 617 each have one or more layers of semiconductor materials with a gate electrode located above them.The semiconductor materials can, for example, be p-doped gallium nitride or the like. In some embodiments, the gate contact (e.g., 512G, 614G, or 616G) can function as the gate electrode.

[0065] In some embodiments, the first semiconductor structure 500 has a first interconnect structure 520 over a first wafer 501, and the second semiconductor structure 600 has a second interconnect structure 620 over a second wafer 601. The wafers 501 / 601 can be similar to the wafers 201 / 301 described above. For example, the wafers 501 / 601 can have a substrate 502 / 602, a channel layer 504 / 604, and an active layer 506 / 606. The interconnect structures 520 / 620 can each have multiple layers of dielectric material and multiple layers of conductive structural elements, similar to the interconnect structure 220 / 320 described above.

[0066] The Fig. Figures 15A to 17 show sectional views of intermediate steps in the manufacture of a cascode HEMT device 400 (see Fig. 17) according to some embodiments. The cascode HEMT device 400 can be the cascode HEMT device 400, which is in Fig. 13 is shown, or the cascode HEMT device 400, which is in Fig. The ones shown in 14 resemble each other. Fig. 15A and Fig. Figure 16A shows sectional views of intermediate steps in the fabrication of the first semiconductor structure 500 and the Fig. 15B and Fig. Figure 16B shows sectional views of intermediate steps in the fabrication of the second semiconductor structure 600 according to some embodiments. Fig. Figure 17 shows a sectional view of a cascode HEMT device 400 according to some embodiments.

[0067] The Fig. 15A and Fig. Figure 15B shows sectional views of a first semiconductor structure 500 and a second semiconductor structure 600 according to some embodiments. The first semiconductor structure 500 and the second semiconductor structure 600 can be fabricated using materials and processes similar to those described above for the first semiconductor structure 200 and the second semiconductor structure 300. In some embodiments, the first HEMT device 412 is fabricated in the first semiconductor structure 500, and the second HEMT device 414 and the third HEMT device 416 are fabricated in the second semiconductor structure 600. Isolation regions 508 can be fabricated in the first wafer 501, and isolation regions 608 can be fabricated in the second wafer 601.

[0068] The first interconnect structure 520 is fabricated over the first wafer 501 and can include dielectric layers 521 and conductive structural elements, such as conductive traces 522, conductive vias 523, conductive pads 524, and sealing ring structures 510. For example, a conductive pad 524S can be electrically connected to the source contact 512S, a conductive pad 524D can be electrically connected to the drain contact 512D, and a conductive pad 524G can be electrically connected to the gate contact 512G. The second interconnect structure 620 is fabricated over the second wafer 601 and can include dielectric layers 621 and conductive structural elements, such as conductive traces 622, conductive vias 623, conductive pads 624, and sealing ring structures 610.For example, a conductive pad 624S can be electrically connected to the source contact 614S, a conductive pad 624D2 can be electrically connected to the drain contact 614D, a conductive pad 624D3 can be electrically connected to the drain contact 616D, and a conductive pad 624G can be electrically connected to the gate contact 614G, the source contact 616S, and the gate contact 616G.

[0069] The Fig. 16A and Fig. Figure 16B shows the first semiconductor structure 500 and the second semiconductor structure 600 after fabrication of sealing ring structures 527 / 627 and contact structures 528 / 628 according to some embodiments. The sealing ring structures 527 / 627 and contact structures 528 / 628 may resemble the sealing ring structures 227 / 327 or contact structures 228 / 328 described above and may be fabricated using similar materials or processes. In some embodiments, for example, openings may be etched into the semiconductor structures 500 / 600, exposing the substrates 502 / 602. A conductive material may be deposited in the openings, and then a dielectric material may be deposited over the conductive material. This is one example, and other methods are possible.

[0070] In Fig. In 16A, the conductive material of the contact structure 528S physically and electrically contacts an exposed portion of the conductive pad 524S, and consequently, the contact structure 528S is electrically connected to the conductive pad 524S. The conductive material of the contact structure 528S also physically and electrically contacts an exposed surface of the substrate 502. In this way, in some embodiments, the contact structure 528S can form an electrical connection between the source (e.g., S1) and the body of the first HEMT device 412. Fig. 16B physically and electrically contacts an exposed part of the conductive pad 624S with the conductive material of contact structure 628S, and consequently, contact structure 628S is electrically connected to the conductive pad 624S. The conductive material of contact structure 628G physically and electrically contacts an exposed part of the conductive pad 624G, and consequently, contact structure 628G is electrically connected to the conductive pad 624G.

[0071] In Fig. 17. The first semiconductor structure 500 is bonded to the second semiconductor structure 600, and via interconnects 532D, 632S, and 632G are fabricated to form the cascode HEMT device 400 according to some embodiments. Bonding the first semiconductor structure 500 to the second semiconductor structure 600 electrically connects the first HEMT device 412, the second HEMT device 414, and the third HEMT device 416. For example, in some embodiments, the conductive pad 524S is bonded to the conductive pad 624D2 by a conductive interconnect 420A, which electrically connects the source (e.g., the first source S1) of the first HEMT device 412 to the drain (e.g., the second drain D2) of the second HEMT device 414. In some embodiments, the conductive pad 524G is connected by a conductive connecting element 420B, which connects the gate (e.g.The first gate G1) of the first HEMT device 412 is electrically connected to the drain (e.g., the third drain D3) of the third HEMT device 416 and bonded to the conductive pad 624D3. In this way, a single structure is formed comprising the first HEMT device 412, the second HEMT device 414, and the third HEMT device 416 in a cascode configuration. The conductive interconnects 420A-B may resemble the conductive interconnects 120A-B described above and may be fabricated or bonded using similar methods. In some embodiments, an underfill 405 is deposited in the gap between the first semiconductor structure 500 and the second semiconductor structure 600. The underfill 405 may surround the conductive interconnects 420A-B and may resemble the underfill 105 described above.

[0072] Furthermore in Fig. 17 According to some embodiments, through-hole interconnects 532D, 632S, and 632G are fabricated on the first semiconductor structure 500 and the second semiconductor structure 600. The through-hole interconnects 532D / 632S / 632G enable the fabrication of external electrical connections to the contact structures 527 / 627. For example, in some embodiments, a through-hole interconnect 532D is formed by the first semiconductor structure 500, which establishes an electrical connection to the drain (e.g., the first drain D1) of the first HEMT device 412. In this way, the through-hole interconnect 532D can function as the common drain terminal (DC terminal) 410D of the cascode HEMT device 400. In some embodiments, a through-hole connecting element 632S is formed by the second semiconductor structure 600, which establishes an electrical connection to the contact structure 628S.In this way, the via connection element 632S can function as the common source terminal (SC terminal) 410S of the cascode HEMT device 400. In some embodiments, a via connection element 632G is formed by the second semiconductor structure 600, which establishes an electrical connection to the contact structure 628G. In this way, the via connection element 632G can function as the common gate terminal (GC terminal) 410G of the cascode HEMT device 400.

[0073] The through-hole interconnects 532D / 632S / 632G can be similar to the through-hole interconnects 232D / 332S / 332G described above and can be fabricated using similar materials or processes. For example, an opening can be formed in the first semiconductor structure 500 extending through the substrate 502 and the first interconnect structure 520 to expose part of the conductive pad 524D. An insulating layer 530 can be deposited, and then a conductive material can be deposited in the opening to fabricate the through-hole interconnect 532D. Openings can be formed in the substrate 602 to expose the contact structure 628S and the contact structure 628G. An insulating layer 630 can be deposited and then a conductive material can be deposited in the openings to produce the via connecting elements 632S and 632G.However, other methods are also possible. In some embodiments, the substrate 502 and / or the substrate 602 can be thinned before the through-hole interconnects 532D / 632S / 632G are fabricated. In some embodiments, the cascode HEMT device 400 described in this disclosure can be integrated into a package that may resemble the package 150 described for the . Fig. has been described in sections 12A-12B.

[0074] Embodiments described in this disclosure may have several advantages. For example, a single device comprising three high electron mobility transistors (HEMTs) in a cascode configuration may enable higher breakdown voltages, such as greater than approximately 1200 V. In some embodiments, the HEMTs are fabricated on two substrates that are bonded together in a single HEMT structure (e.g., a die, a package component, or the like). By fabricating the HEMTs on two substrates, the electrical connections between the HEMTs can be shortened, thereby reducing parasitic resistance, parasitic inductance, and electrical mismatches. By improving the electrical connections in this way, the efficiency and performance of the device may also be improved.Fabricating a HEMT structure by bonding two substrates can also result in a smaller HEMT structure. Furthermore, bonding two substrates to create a single HEMT structure can improve heat dissipation, for example, by placing the HEMT structure between two heat sinks.

[0075] According to some embodiments of the present disclosure, a semiconductor device comprises a first semiconductor structure with a first HEMT device (HEMT: high electron mobility transistor), wherein the first HEMT device has a first gate, a first source and a first drain; and a second semiconductor structure stacked over and bonded to the first semiconductor structure, wherein the second semiconductor structure has a second HEMT device and a third HEMT device, the second HEMT device having a second gate, a second source and a second drain electrically connected to the first source, and the third HEMT device having a third gate, a third source and a third drain electrically connected to the first gate.In one embodiment, the second semiconductor structure is bonded to the first semiconductor structure by solder contact bumps. In another embodiment, the first HEMT device is a depletion transistor, the second HEMT device is an enhancement transistor, and the third HEMT device is an enhancement transistor. In another embodiment, the semiconductor device comprises a first contact structure electrically connected to the first source, a second contact structure electrically connected to the second gate, and a third contact structure electrically connected to the second source, wherein the first contact structure is between the first source and the first gate, the second contact structure is between the second drain and the second gate, and the third contact structure is between the second source and the second gate.In one embodiment, the second source, the third source, and the third gate in the second semiconductor structure are electrically interconnected. In another embodiment, the first gate has a gate electrode over a layer of p-doped gallium nitride. In another embodiment, the first semiconductor structure comprises a silicon substrate, a channel layer over the silicon substrate containing gallium nitride, and an active layer over the channel layer containing aluminum gallium nitride. In another embodiment, the channel layer has a thickness of less than 5 µm.

[0076] According to some embodiments of the present disclosure, a package comprises a first semiconductor structure with a first HEMT device (HEMT: high electron mobility transistor) fabricated on a first substrate; a second semiconductor structure with a second HEMT device and a third HEMT device fabricated on a second substrate, wherein the second semiconductor structure is attached to the first semiconductor structure, the first HEMT device, the second HEMT device, and the third HEMT device being connected in a cascode configuration; a first conductive structural element on the first substrate, wherein the first conductive structural element penetrates the first substrate to establish an electrical connection to the first HEMT device; a second conductive structural element on the second substrate,wherein the second conductive structural element penetrates the second substrate to establish an electrical connection to the second HEMT device; and a third conductive structural element on the second substrate, wherein the third conductive structural element penetrates the second substrate to establish an electrical connection to the second HEMT device. In one embodiment, the package comprises a terminal frame, wherein the terminal frame has a conductive die pad and conductive terminals, the first conductive structural element being attached to the die pad. In one embodiment, a first conductive terminal is electrically connected to the first conductive structural element through the die pad, and a second conductive terminal is electrically connected to the second conductive structural element through a first metal plate.wherein a third conductive connection is electrically connected to the third conductive structural element via a second metal plate. In one embodiment, a fourth conductive connection is electrically connected to the third conductive structural element via the second metal plate. In one embodiment, the package comprises a first heat sink above the first substrate and a second heat sink above the second substrate relative to the first substrate. In one embodiment, the third HEMT device is a diode-connected transistor. In one embodiment, the second conductive structural element is electrically connected to a gate contact of the second HEMT device, wherein the third conductive structural element is electrically connected to a source contact of the second HEMT device.

[0077] According to some embodiments of the present disclosure, a method comprises the following steps: fabricating a first HEMT device (HEMT: high electron mobility transistor) on a first semiconductor substrate; fabricating a first interconnect structure over the first semiconductor substrate, wherein the first interconnect structure is electrically connected to the first HEMT device; fabricating a second HEMT device and a third HEMT device on a second semiconductor substrate; fabricating a second interconnect structure over the second semiconductor substrate, wherein the second interconnect structure electrically connects the second HEMT device to the third HEMT device;and bonding the first interconnect structure to the second interconnect structure, wherein the bonding electrically connects the first HEMT device to the second HEMT device and the first HEMT device to the third HEMT device. In one embodiment, bonding the first interconnect structure to the second interconnect structure comprises creating solder pads on the first interconnect structure and placing the second interconnect structure on the solder pads. In one embodiment, bonding electrically connects a source of the first HEMT device to a drain of the second HEMT device, and a gate of the first HEMT device is electrically connected to a drain of the third HEMT device. In one embodiment, the method comprises creating sealing ring structures in the first interconnect structure.

Claims

[1] Semiconductor device with: a first semiconductor structure with a first HEMT device, wherein the first HEMT device comprises a first gate, a first source and a first drain; and a second semiconductor structure stacked over and bonded to the first semiconductor structure, wherein the second semiconductor structure comprises a second HEMT device and a third HEMT device, wherein the second HEMT device comprises a second gate, a second source and a second drain electrically connected to the first source, and wherein the third HEMT device comprises a third gate, a third source and a third drain electrically connected to the first gate. [2] Semiconductor device according to claim 1, wherein the second semiconductor structure is bonded to the first semiconductor structure by a plurality of solder contact mounds. [3] Semiconductor device according to claim 1 or 2, wherein the first HEMT device is a depletion transistor, the second HEMT device is an enhancement transistor and the third HEMT device is an enhancement transistor. [4] Semiconductor device according to one of the preceding claims, further comprising: a first contact structure electrically connected to the first source, a second contact structure electrically connected to the second gate, and a third contact structure electrically connected to the second source, wherein the first contact structure is between the first source and the first gate, the second contact structure is between the second drain and the second gate, and the third contact structure is between the second source and the second gate. [5] Semiconductor device according to one of the preceding claims, wherein the second source, the third source and the third gate in the second semiconductor structure are electrically connected to each other. [6] Semiconductor device according to any one of claims 1 to 4, wherein the second gate, the third source and the third gate in the second semiconductor structure are electrically connected to each other. [7] Semiconductor device according to one of the preceding claims, wherein the first gate has a gate electrode over a layer of p-doped gallium nitride. [8] Semiconductor device according to one of the preceding claims, wherein the first semiconductor structure comprises a silicon substrate, a channel layer above the silicon substrate comprising gallium nitride, and an active layer above the channel layer comprising aluminium gallium nitride. [9] Semiconductor device according to claim 8, wherein the channel layer has a thickness of less than 5 µm. [10] Package containing: a first semiconductor structure with a first HEMT device fabricated on a first substrate; a second semiconductor structure comprising a second HEMT device and a third HEMT device fabricated on a second substrate, wherein the second semiconductor structure is attached to the first semiconductor structure, wherein the first HEMT device, the second HEMT device and the third HEMT device are connected in a cascode configuration; a first conductive structural element on the first substrate, wherein the first conductive structural element penetrates the first substrate to establish an electrical connection to the first HEMT device; a second conductive structural element on the second substrate, wherein the second conductive structural element penetrates the second substrate to establish an electrical connection to the second HEMT device; and a third conductive structural element on the second substrate, wherein the third conductive structural element penetrates the second substrate to establish an electrical connection to the second HEMT device. [11] Package according to claim 10, further comprising: a connection frame, wherein the connection frame comprises a conductive die pad and a plurality of conductive terminals, wherein the first conductive structural element is attached to the die pad. [12] Package according to claim 11, wherein a first conductive connection is electrically connected to the first conductive structural element through the die pad, wherein a second conductive connection is electrically connected to the second conductive structural element through a first metal plate, and wherein a third conductive connection is electrically connected to the third conductive structural element through a second metal plate. [13] Package according to claim 12, wherein a fourth conductive connection is electrically connected to the third conductive structural element through the second metal plate. [14] Package according to any one of claims 10 to 13, further comprising a first heat sink above the first substrate and a second heat sink above the second substrate relative to the first substrate. [15] Package according to one of claims 10 to 14, wherein the third HEMT device is a transistor configured as a diode. [16] Package according to one of claims 10 to 15, wherein the second conductive structural element is electrically connected to a gate contact of the second HEMT device, wherein the third conductive structural element is electrically connected to a source contact of the second HEMT device. [17] Procedure with the following steps: Fabrication of a first HEMT device on a first semiconductor substrate; Fabricating a first interconnect structure over the first semiconductor substrate, wherein the first interconnect structure is electrically connected to the first HEMT device; Fabricating a second HEMT device and a third HEMT device on a second semiconductor substrate; Fabricating a second interconnect structure over the second semiconductor substrate, wherein the second interconnect structure electrically connects the second HEMT device to the third HEMT device; and Bonding the first interconnect structure to the second interconnect structure, wherein the bonding electrically connects the first HEMT device to the second HEMT device and electrically connects the first HEMT device to the third HEMT device. [18] Method according to claim 17, wherein bonding the first interconnect structure to the second interconnect structure comprises producing solder contact mounds on the first interconnect structure and placing the second interconnect structure on the solder contact mounds. [19] Method according to claim 17 or 18, wherein by bonding a source of the first HEMT device is electrically connected to a drain of the second HEMT device and a gate of the first HEMT device is electrically connected to a drain of the third HEMT device. [20] Method according to any one of claims 17 to 19, further comprising manufacturing sealing ring structures in the first interconnect structure.

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