Trench insulation connectors for stacked structures and methods for forming a wafer-on-wafer stack

Abstract

Stacked device arrangement comprising: a first device substrate (12) comprising a first device (10); a second device substrate (212) having a first surface (212A) opposite a second surface (212B), wherein the second device substrate (212) has a second device (200) on the first surface (212A) of the second device substrate (212), an insulation structure (220) arranged in the second device substrate (212) and surrounding the second device (200), the insulation structure (220) extending from the first surface (212A) of the second device substrate (212) through the second device substrate (212) to the second surface (212B) of the second device substrate (212); and a conductive connector (286) arranged in the insulation structure (220), wherein the conductive connector (286) is connected to the second device (200), the conductive connector (286) is connected to the first device (10), and the conductive connector (286) extends from the first surface (212A) of the second device substrate (212) to the second surface (212B) of the second device substrate (212).

Description

BACKGROUND

[0001] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to generations of ICs, each featuring smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be produced using a manufacturing process) has decreased. This process of downscaling generally delivers benefits by increasing production efficiency and reducing manufacturing costs.

[0002] Such downward scaling has also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are needed to realize these advances. For example, the denser packing of ICs in more advanced IC technology nodes requires denser interconnect connections between ICs. Although current interconnect connection techniques are generally adequate for their intended purposes, they are not satisfactory in every respect, and improvements are all the more urgent as IC components become smaller.

[0003] DE 10 2021 110 304 A1 describes an IC chip featuring a stilt pad structure. A wire is located beneath a semiconductor substrate at one front face of the substrate. A trench insulation structure extends into the front face of the semiconductor substrate. The stilt pad structure is embedded in the back face of the semiconductor substrate, opposite the front face. The stilt pad structure comprises a pad body and a pad projection. The pad projection is located beneath the pad body and extends from the pad body through a section of the semiconductor substrate and the trench insulation structure toward the wire. The pad body is located above the section of the semiconductor substrate and is separated from the trench insulation structure by this section of the semiconductor substrate.

[0004] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale and are for illustrative purposes only. The dimensions of the various structural elements may, in fact, be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. 1A, Fig. 1B, Fig. 2A, Fig. 2B, Fig. 3A-3C and Fig. Figures 4A-4C are different views of a device, in part or in whole, according to different aspects of the present disclosure. Fig. Figures 5-9 are fragmentary cross-sectional views of various stacked device structures, partial or complete, according to different aspects of the present disclosure. Fig. 10A and Fig. Figure 10B are schematic views of another stacked device structure, partial or complete, according to various aspects of the present disclosure. Fig. 11A and Fig. Figure 11B shows schematic views of another stacked device structure, in part or in full, according to various aspects of the present disclosure. Fig. Figures 12A-12E are fragmentary schematic cross-sectional views of the stacked device structure of Fig. 5, partially or completely, at various stages of their manufacture according to various aspects of the present disclosure. Fig. Figures 13A-13E are fragmentary schematic cross-sectional views of the stacked device structure of Fig. 6, partially or completely, at various stages of their manufacture according to various aspects of the present disclosure. Fig. Figures 14A-14E are fragmentary schematic cross-sectional views of the stacked device structure of Fig. 7, partially or completely, at various stages of their manufacture according to various aspects of the present disclosure. Fig. Figures 15A-15E are fragmentary schematic cross-sectional views of the stacked device structure of Fig. 8, partially or completely, at various stages of their manufacture according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0006] The present disclosure relates generally to IC devices and / or semiconductor devices, and in particular to interconnect structures for stacked semiconductor structures and methods for their fabrication.

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the invention. For example, the formation of a first structural element above a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact.Furthermore, spatially relative terms, for example, "lower," "upper," "horizontal," "vertical," "above," "over," "below," "under," "upward," "downward," "above," "below," etc., and their derivatives (for example, "in a horizontal direction," "downward," "upward," etc.), are used to simplify the present disclosure with respect to the relationship of one structural element to another. The spatially relative terms are intended to cover different orientations of the device containing the structural elements. Moreover, when a number or range of numbers is described by "about," "approximately," and the like, the term is also intended to include numbers that lie within a meaningful range that takes into account variations inherent in any manufacturing process, as the average person skilled in the art would understand them.For example, the number or range of numbers encompasses a meaningful range that includes the specified number plus a span of, for example, ±10% of the specified number, based on known manufacturing tolerances associated with the production of a structural element that has a property linked to the number. For example, a material layer having a thickness of "about 5 nm" may encompass a dimensional range of 4.5 nm to 5.5 nm if the person skilled in the art knows that the manufacturing tolerances associated with the deposition of the material layer are ±15%. Furthermore, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0008] This text discloses trench insulation connectors that electrically connect stacked structures, such as wafers, IC chips, IC dies, substrates, their devices, or combinations thereof. An exemplary trench insulation connector is a conductive structure arranged within the trench insulation of a device substrate on a wafer. The trench insulation structure encloses, delimits, and / or surrounds the device on the substrate. The trench insulation structure and the conductive structure arranged within it extend completely through the device substrate, for example, from a top surface of the device substrate (over which one or more devices are formed) to a bottom surface of the device substrate.The trench insulation structure can be a shallow trench insulation (STI), a deep trench insulation (DTI), another suitable insulation structure, or a combination thereof. The conductive structure contains an electrically conductive material. In some embodiments, multiple conductive structures are arranged within the trench insulation structure and isolated from one another (i.e., independent trench insulation connectors), such that the trench insulation connectors can provide various flexible back-to-back connections between devices on the device substrate and / or devices on other wafers.

[0009] The trench isolation connectors described in this text enable more compact interconnect connections between devices and / or wafers. High-voltage devices, in particular, can benefit from the trench isolation connectors described in this text. For example, it has been found that interconnect structures, which often connect high-voltage devices on a single wafer, require more space and / or area than would be desirable as IC technology nodes continue to scale up. By stacking high-voltage devices, as described in this text, and / or connecting high-voltage devices to one another using the disclosed trench isolation connectors, the area and / or space occupied by the interconnected high-voltage devices is considerably reduced.For example, stacked fixture structures, in which two high-voltage devices, as described in this text, are stacked and interconnected, can reduce the fixture area by up to 50%. In another example, stacked fixture structures, in which three high-voltage devices, as described in this text, are stacked and interconnected, can reduce the fixture area by up to 66%. Furthermore, rear interconnect structures (routing structures) incorporating the disclosed trench insulation connectors can significantly increase routing flexibility when connecting devices, reduce the area occupied by the interconnected devices, improve the area utilization of interconnected devices, and so on.The trench insulation connectors disclosed in this text can also provide silicon-on-insulator-like insulation between devices and / or wafers, thereby reducing electrical leakage current paths. Different embodiments may have different advantages, and no specific advantage is required for every embodiment.

[0010] Fig. 1A, Fig. 2A, Fig. 3A and Fig. 4A are fragmentary top views of a device 10, partial or complete, according to various aspects of the present disclosure. Fig. 1B, Fig. 2B, Fig. 3B and Fig. 4B are fragmentary cross-sectional views of the device 10 along line BB of Fig. 1A, Fig. 2A, Fig. 3A or Fig. 4A, in part or in full, according to various aspects of the present revelation. Fig. 3C and Fig. 4C are fragmentary cross-sectional views of the device 10 along line CC of Fig. 3A or Fig. 4A, partially or completely, according to various aspects of the present disclosure. The device 10 forms a section or an entirety of a wafer A having a front FA and a back BA. In the illustrated embodiments, the device 10 is manufactured on the front FA of wafer A, and the device 10 comprises a substrate 12, a device region 14, and an active region (OD region) 16. A deep trench insulation (DTI) structure 20, a shallow trench insulation (STI) structure 22, and an STI structure 24 are arranged in a substrate 12. The DTI structure 20 separates and / or electrically insulates, for example, the device region 14 from other device regions. The STI structure 22 separates and / or electrically insulates, for example, the active region 16 from other regions and / or device structure elements of the device region 14.The STI structure 24 separates and / or isolates, for example, device structure elements from other device structure elements. In the illustrated embodiments, the active region 16 is configured for a transistor and can be referred to as a transistor region. In some embodiments, the active region 16 includes a high-voltage device, for example, a high-voltage transistor. High-voltage devices operate at high voltages, the voltage ranges considered "high voltage" depending on the technology node.For example, 7 nm node devices operating at voltages above approximately 1.8 V can be considered high-voltage devices, while 0.18 µm node devices operating at voltages above approximately 6 V can be considered high-voltage devices (and 0.18 µm technology node devices operating at voltages of approximately 1.8 V can be considered low-voltage devices). Fig. 1A-4A, Fig. 1B-4B, Fig. 3C and Fig. Section 4C has been simplified for the sake of clarity in order to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the device 10, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the device 10.

[0011] We turn to Fig. 1A and Fig. 1B. The substrate 12 contains an elemental semiconductor, such as silicon and / or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In some embodiments, the substrate 12 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The substrate 12 has a thickness T1. The thickness T1 can extend along the z-direction between a surface 12A of the substrate 12 and a surface 12B of the substrate 12. Areas 12A and 12B form the front side FA and back side BA of wafer A, respectively. In some embodiments, areas 12A and 12B are a top side and a bottom side, respectively.a bottom side of the substrate 12. In some embodiments, the surface 12A and the surface 12B are a front and a back side of the substrate 12, respectively.

[0012] The substrate 12 can be doped with p-type and / or n-type dopants. In the illustrated embodiment, the substrate 12 is a silicon substrate doped with p-type dopants and may hereinafter be referred to as a p-type substrate. p-type dopants include boron, indium, gallium, other p-type dopants, or combinations thereof. n-type dopants include phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof. Because the illustrated embodiment contains a p-type doped substrate, the doping arrangements of the device 10 described below correspond to a p-type doped substrate. Alternatively, the device 10 may also have an n-type doped substrate. In this case, the doping arrangements described below are to be understood as corresponding to an n-type doped substrate (for example, doping arrangements having an opposite conductivity).The present disclosure considers any doping arrangement of the substrate 12, doped regions therein and / or doped depressions therein, which are arranged to provide a transistor, such as a high-voltage transistor, and / or other device which can take advantage of backside trench insulation connections.

[0013] As seen from a top view ( Fig. As shown in Figure 1A), the DTI structure 20 surrounds the device region 14, the STI structure 22 surrounds the active region 16, and the STI structure 24 surrounds at least one device structural element in the device region 14. The STI structure 24 is located between the DTI structure 20 and the STI structure 22. In the illustrated embodiment, the DTI structure 20, the STI structure 22, and the STI structure 24 are rectangular rings that extend continuously around their respective regions and / or structural elements of the device 10. The DTI structure 20, the STI structure 22, and the STI structure 24 can therefore be described as rectangular isolation rings. The STI structure 22 and the STI structure 24 are bounded by the DTI structure 20, and the STI structure 22 is bounded by the STI structure 24. The DTI structure 20, the STI structure 22, the STI structure 24 or combinations thereof may also have other top surface profiles.For example, the DTI structure 20, the STI structure 22, the STI structure 24, or combinations thereof can be a square ring, an oval ring, a circular ring, a hexagonal ring, an octagonal ring, or any other suitably shaped ring. In some embodiments, the DTI structure 20, the STI structure 22, the STI structure 24, or combinations thereof are discontinuous (for example, discrete insulation segments are arranged and combined to form an insulation ring around a region and / or a structural element).

[0014] The DTI structure 20 has a width W1 (for example, along the x-direction) corresponding to its inner width (that is, the width of an inner ring formed by the DTI structure 20), a width W2 (for example, along the x-direction) corresponding to its outer width (that is, the width of an outer ring formed by the DTI structure 20), and a width W3 (for example, along the x-direction) corresponding to a width and / or thickness of the DTI structure 20. Width W2 is greater than width W1. Width W3 is given by the difference between width W2 and width W1, divided by two (that is, width W3 = (width W2 - width W1) / 2). Width W1 corresponds to a width along the x-direction of the device region 14.

[0015] The depths of the STI structures are less than the depths of the DTI structures. For example, the DTI structure 20 has a depth D1 extending into the substrate 12, while the STI structures 22 and 24 have a depth D2 extending into the substrate 12, and the depth D1 is greater than the depth D2. The depth D1 is less than the thickness T1 of the substrate 12. In some embodiments, the depth D1 is approximately 1 µm to approximately 3 µm, and the depth D2 is less than 1 µm. The depth D1 can extend along the z-direction between a surface 12A of the substrate 12 and a bottom surface of the DTI structure 20. The depth D2 can extend along the z-direction between the surface 12A of the substrate 12 and a bottom surface of the STI structure 22 and / or a bottom surface of the STI structure 24. Fig. In 1B, STI structure 22 and STI structure 24 have the same depth. In some embodiments, the depth of STI structure 22 differs from the depth of STI structure 24, and both the depth of STI structure 22 and STI structure 24 are less than a depth D1. In some embodiments, DTI structure 20 is a high-aspect-ratio isolation structure, which generally refers to an isolation structure where one dimension (for example, depth D1) is significantly larger than another dimension (for example, width W3). For example, the ratio of depth D1 to width W3 is greater than approximately 5, while the ratio of depth D2 to the widths of STI structures 22 and 24 is less than 5.Since the dimensions of the DTI structure 20 and the STI structures 22, 24 can vary depending on the technology node, the present disclosure also considers other ratios of depth D1 to width W3 and / or ratios of depth D2 to widths of the STI structures 22, 24 that the facilities described in the present text can utilize, together with DTI structures having ratios of depth D1 to width W3 that are less than 5.

[0016] The DTI structure 20, the STI structure 22, and the STI structure 24 contain silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (including, for example, silicon, oxygen, nitrogen, carbon, another suitable insulating component, or combinations thereof), or combinations thereof. In some embodiments, the DTI structure 20, the STI structure 22, the STI structure 24, or combinations thereof are oxide layers. In some embodiments, the DTI structure 20, the STI structure 22, the STI structure 24, or combinations thereof have a multilayer structure, such as a dielectric bulk layer over a dielectric lining. For example, the DTI structure 20, the STI structure 22, the STI structure 24, or combinations thereof have an oxide layer over a silicon nitride lining.In another example, the DTI structure 20, the STI structure 22, the STI structure 24, or combinations thereof, feature a dielectric layer (for example, an oxide layer) over a doped lining, such as a borosilicate glass lining (BSG lining) and / or a phosphosilicate glass lining (PSG lining). In yet another example, the DTI structure 20, the STI structure 22, the STI structure 24, or combinations thereof, feature a polysilicon layer and an oxide layer, the oxide layer being located between the polysilicon layer and the substrate 12.

[0017] A buried layer 30 is located at a depth D3 in the substrate 12. A depth D3 can extend along the z-direction between surface 12A of the substrate 12 and the top of the buried layer 30. The buried layer 30 extends from depth D3 to a depth D4 in the substrate 12. A depth D4 can extend along the z-direction between surface 12A of the substrate 12 and the bottom of the buried layer 30. A thickness T2 of the buried layer 30 can extend along the z-direction between the top and bottom of the buried layer 30 (for example, thickness T2 = depth D4 - depth D3).The buried layer 30 is an n-type buried layer (NBL) (for example, an n-type semiconductor layer and / or an n-doped region of the substrate 12), a p-type buried layer (PBL) (for example, a p-type semiconductor layer and / or a p-doped region of the substrate 12), a buried dielectric layer (for example, a buried oxide layer (BOX layer)), or combinations thereof. In some embodiments, the buried layer 30 has a multilayer structure. For the purposes of the embodiment shown, the buried layer 30 is an NBL.

[0018] The buried layer 30 has a width (for example, along an x-direction) equal to the width W1, such that the buried layer 30 extends over a width of the device region 14. In some embodiments, the STI structure 22 and the STI structure 24 have depths less than a depth D3 (that is, depth D2 < depth D3), while the DTI structure 20 has a depth at least as great as depth D3 (that is, depth D1 ≥ depth D3). Fig. 1B is a depth D1 equal to a depth D4. In other words, the underside of the DTI structure 20 and the underside of the buried layer 30 are located at the same depth in the substrate 12. In some embodiments, the underside of the DTI structure 20 and the underside of the buried layer 30 form a substantially planar surface. In some embodiments, the underside of the DTI structure 20 is substantially coplanar with the underside of the buried layer 30.

[0019] Substrate 12 contains various doped regions, such as a deep p-well (DPW) 40, an n-well 42A, an n-well 42B, a p-well 44A, a p-well 44B, an n-well 46A, an n-well 46B, a p-well 48, an n-doped region 50, a p-doped region 52, an n-doped region 54A, an n-doped region 54B, and an n-doped region 56. DPW 40, p-well 44A, p-well 44B, p-well 48, and p-doped region 52 are doped with p-doped atoms. The n-well 42A, the n-well 42B, the n-well 46A, the n-well 46B, the n-doped region 50, the n-doped region 54A, the n-doped region 54B and the n-doped region 56 are doped with n dopants. P-doped regions / wells and n-doped regions / wells of the device 10 can be doped with the same or different p-dopants or n-dopants, respectively.The DPW 40, the n-well 42A, the n-well 42B, the p-well 44A, the p-well 44B, the n-well 46A, the n-well 46B, the p-well 48, the n-doped region 50, the p-doped region 52, the n-doped region 54A, the n-doped region 54B and the n-doped region 56 have dopant concentrations that correspond to a high-voltage transistor and / or enable the operation of a high-voltage transistor. In some embodiments, one or more of the different doped regions are doped sections of the substrate 12. In some embodiments, one or more of the different doped regions are doped semiconductor layers arranged in the substrate 12, such as an n-doped silicon germanium layer and / or a p-doped silicon germanium layer arranged in the p-silicon substrate 12.

[0020] The DPW 40 (also referred to as a PBL) is located on the buried layer 30 and has a width (for example along an x-direction) that is at least as large as the width (for example along the x-direction) of the active region 16. The n-shaped depressions 42A and 42B are located on the buried layer 30 and adjacent to the DTI structure 20. N-shaped depression 42A is located between the p-shaped depression 44A and the DTI structure 20, and n-shaped depression 42B is located between the p-shaped depression 44B and the DTI structure 20. A section of n-shaped depression 42A is located between the DTI structure 20 and the STI structure 24, and n-shaped depression 42A extends along the y-direction from the n-doped region 50 to the buried layer 30. A section of n-shaped depression 42B is located between the DTI structure 20 and the STI structure 24, and n-shaped depression 42B extends along the y-direction from from the n-doped region 50 to the buried layer 30.In some embodiments, the n-well 42A and the n-well 42B are sections of an n-well ring next to the DTI structure 20.

[0021] The p-trough 44A and the p-trough 44B are located between the DPW 40 and the n-trough 42A and the n-trough 42B, respectively. The p-trough 44A is located between the n-trough 42A and the n-trough 46A, and the p-trough 44B is located between the n-trough 42B and the n-trough 46B. A section of p-well 44A and a section of p-well 44B are located between STI structure 22 and STI structure 24. p-well 44A and p-well 44B extend along the y-direction from p-doped region 52 to buried layer 30. In some embodiments, p-well 44A and n-well 44B are sections of a p-well ring adjacent to an n-well ring (formed, for example, by n-well 42A and n-well 42B).An interface between the p-well 44A and the n-well 42A is located below the STI structure 24, an interface between the p-well 44B and the n-well 42B is located below the STI structure 24, an interface between the p-well 44A and the DPW 40 is located below the STI structure 22, an interface between the p-well 44A and the n-well 46A is located below the STI structure 22, an interface between the p-well 44B and the DPW 40 is located below the STI structure 22, and an interface between the p-well 44B and the n-well 46B is located below the STI structure 22.

[0022] The n-trough 46A, the n-trough 46B and the p-trough 48 are located on the DPW 40. The n-trough 46A and the n-trough 46B are located between the p-trough 48 and the p-trough 44A and the p-trough 44B, respectively. The n-wells 46A and n-wells 46B are located between the p-well 48 and the STI structure 22. The n-wells 46A, n-wells 46B, and p-well 48 extend along the y-direction from surface 12A of the substrate 12 to the DPW 40. The n-wells 46A and n-wells 46B can be drift-diffusion regions (for example, NDD regions). In some embodiments, the DPW 40 is implanted together with drift-diffusion regions, such as NDD regions (for example, the n-wells 46A and n-wells 46B).In some embodiments, the DPW 40, the n-well 46A, the n-well 46B, other doped regions of the substrate 12 or combinations thereof are implanted together with interfering atoms, such as nitrogen, carbon, fluorine, other interfering atoms or combinations thereof, which can inhibit dopant diffusion.

[0023] The n-doped region 50 is located in the n-trough 42A and the n-trough 42B. The n-doped region 50 is located between the DTI structure 20 and the STI structure 24, and in the plan view ( Fig. In 1A), the n-doped region 50 is a rectangular ring. The dopant concentration of the n-doped region 50 is greater than the dopant concentration of the n-well 42A and the n-well 42B, and therefore the n-doped region 50 is referred to as an “N+” region. In some embodiments, the n-doped region 50 is an n-protective ring that can allow the application of an electrical bias to the substrate 12 (for example, via the n-doped region 50, the n-doped wells (for example, the n-doped well 42A and the n-doped well 42B), and the buried layer 30) and / or improve the electrical insulation of a high-voltage transistor of the active region 16 of the device 10.

[0024] The p-doped region 52 is located in p-trough 44A and p-trough 44B. The p-doped region 52 is located between STI structure 24 and STI structure 22, and in the plan view ( Fig. In 1A), the p-doped region 52 is a rectangular ring. The dopant concentration in the p-doped region 52 is higher than the dopant concentration in the p-well 44A and the p-well 44B, and therefore the p-doped region 52 is referred to as a “P+” region. In some embodiments, the p-doped region 52 is a p-guard ring that can allow the application of an electrical bias to the substrate 12 (for example, via the p-doped region 52, the p-doped wells (for example, the p-doped well 44A and the p-doped well 44B), and the buried layer 30) and / or improve the electrical insulation of a high-voltage transistor in the active region 16 of the device 10.

[0025] The n-doped region 54A is located in the n-well 46A, the n-doped region 54B is located in the n-well 46B, and the n-doped region 56 is located in the p-well 48. The n-doped regions 54A and 54B are adjacent to the STI structure 22. In some embodiments, the n-doped regions 54A and 54B are source regions of the device 10, and the n-doped region 56 is a drain region of the device 10. In such embodiments, the n-doped region 54A and the n-doped region 54B can be referred to as a source 54A and a source 54B, and the n-doped region 56 can be referred to as a drain 56.

[0026] A gate structure 60 and a gate structure 70 are arranged above the substrate 12 in the active region 14. Gate structure 60 is located between source 54A and drain 56, and gate structure 70 is located between source 54B and drain 56. Gate structure 60 comprises a gate stack (for example, a gate dielectric 62 and a gate electrode 64) and gate spacers 66 arranged along the side walls of the gate stack. Gate structure 70 comprises a gate stack (for example, a gate dielectric 72 and a gate electrode 74) and gate spacers 76 arranged along the side walls of the gate stack. Gate structure 60 and / or gate structure 70 can form a section of a transistor.In some embodiments, a high-voltage transistor has a gate structure 60 arranged between the source 54A and the drain 56, wherein a channel region is located in the substrate 12 between the source 54A and the drain 56, and the gate structure 60 engages the channel region such that current can flow between the source 54A and the drain 56. In some embodiments, a high-voltage transistor has a gate structure 70 arranged between the source 54B and the drain 56, wherein a channel region is located in the substrate 12 between the source 54B and the drain 56, and the gate structure 70 engages the channel region such that current can flow between the source 54B and the drain 56.

[0027] The gate dielectric 62 and the gate dielectric 72 can contain a dielectric material, such as silicon oxide, a dielectric with a high k-value, another suitable dielectric material, or combinations thereof. Examples of high k-value dielectric materials include HfO₂, HfSiO₂, HfSiO₄, HfSiON, HfLaO, HfTaO, HfTiO₂, HfZrO, HfAlO, ZrO, ZrO₂, ZrSiO₂, AlO, AlSiO₂, Al₂O₃, TiO, TiO₂, LaO, LaSiO₂, Ta₂O₃, Ta₂O₅, Y₂O₃, SrTiO₃, BaZrO, BaTiO₃ (BTO), (Ba,Sr)TiO₃ (BST), Si₃N₄, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃), another suitable high k-value dielectric material, or combinations thereof. In some embodiments, the gate dielectric 62 and the gate dielectric 72 contain the same materials and / or the same arrangements (for example, the same number and / or arrangement of layers).In some embodiments, the gate dielectric 62 and the gate dielectric 72 contain different materials and / or different arrangements.

[0028] The gate electrode 64 and the gate electrode 74 can contain a conductive material, such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, another conductive material, or combinations thereof. In some embodiments, the gate electrode 74 can contain a dielectric material. In some embodiments, the gate electrode 64 and the gate electrode 74 contain the same materials and / or the same features (for example, the same number and / or the same arrangement of layers). In some embodiments, the gate electrode 64 and the gate electrode 74 contain different materials and / or different features. For example, the gate electrode 64 has one or more metal layers over the gate dielectric 72, while the gate electrode 74 has a polysilicon layer and / or a dielectric layer.

[0029] A resist protective oxide (RPO) 80A is arranged over the gate structure 60 and the n-well 46A, and an RPO 80B is arranged over the gate structure 70. The RPO 80A covers a section of the n-well 46A that is not covered by a corresponding gate spacer 66, and the RPO 80B covers a section of the n-well 46B that is not covered by a corresponding gate spacer 76. RPO 80A extends from source 54A and covers the section of n-well 46A, a side wall of gate dielectric 62, the respective gate spacer 66, and a section of gate electrode 64. RPO 80A extends from source 54B and covers the section of n-well 46B, a side wall of gate dielectric 72, the respective gate spacer 76, and a section of gate electrode 76. RPO 80A and RPO 80B can function as silicide barriers during subsequent silicification processes.For example, if contacts are formed with Source 54A and Source 54B, RPO 80A and RPO 80B can prevent the silicide layers formed on Source 54A and Source 54B from forming on n-well 46A and n-well 46B, respectively.

[0030] We turn to Fig. 2A and Fig. 2B. The device 10 has trench insulation connectors 85 (also referred to as trench insulation conductors) in the DTI structure 20. Each trench insulation connector 85 has a respective conductive via 86 and a respective conductive pad 88. The conductive vias 86 and the conductive pads 88 contain electrically conductive material, such as tungsten, ruthenium, molybdenum, cobalt, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, graphite, other suitable electrically conductive materials, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, the conductive vias 86 and the conductive pads 88 contain the same electrically conductive materials and / or the same structures (for example, the same number of layers and / or the same arrangement of layers).In some embodiments, the conductive vias 86 and the conductive pads 88 contain different electrically conductive materials and / or different structures (for example, different numbers of layers and / or different arrangements of the same number of layers). In some embodiments, the conductive vias 86 and / or the conductive pads 88 have multilayer structures, for example, a lining and a bulk layer.

[0031] Conductive vias 86 are arranged in the DTI structure 20. In a cross-sectional view ( Fig. 2B) The DTI structure 20 is arranged between the sidewalls of conductive vias 86 and the substrate 12 (and / or structural elements arranged therein, such as doped wells), and in a top view, the DTI structure 20 surrounds conductive vias 86. The DTI structure 20 can thus electrically insulate conductive vias 86 from the substrate 12 and / or structural elements located therein. The conductive vias 86 have a depth D5 in the substrate 12 and a width W4. A depth D5 can extend along the z-direction between the surface 12A of the substrate 12 and the undersides of the conductive vias 86, and a width W4 can extend along the x-direction between opposite sidewalls of conductive vias 86. A depth D5 is at least as large as a depth D1.In the illustrated embodiment, conductive vias 86 extend through the entire DTI structure 20, and a depth D5 is equal to the depth D1. In some embodiments, the depth D5 is approximately 1 µm to approximately 3 µm. The width W4 is less than the width W3 of the DTI structure 20. In the top view, the conductive vias 86 can have a circular and / or oval shape. In such embodiments, the conductive vias 86 can be conductive cylinders within the DTI structure 20, and the width W4 corresponds to a diameter of the conductive vias 86. In some embodiments, the conductive vias 86 can have square top profiles, rectangular top profiles, hexagonal top profiles, octagonal top profiles, or other suitably shaped top profiles.In embodiments in which the conductive pads 86 have rectangular profiles, the width W4 can also run along the y-direction, such as when the conductive pads 86 are aligned longitudinally along the x-direction and the y-direction.

[0032] The conductive pads 88 are arranged above the surface 12A of the substrate 12. For example, the conductive pads 88 are arranged on the top surfaces of conductive vias 86 and the top surface of the DTI structure 20. In a top view ( Fig. 2A) Conductive pads 88 are arranged in the DTI structure 20 and spaced apart from the substrate 12 and / or the structural elements in and / or on the substrate 12. The conductive pads 88 have a thickness T2 and a width W5. The thickness T2 can extend along the z-direction between top surfaces of conductive pads 88 and bottom surfaces of conductive pads 88 (and / or the surface 12A of the substrate 12), and the width W5 can extend along the x-direction (and / or the y-direction if the conductive pads 88 are oriented longitudinally along the x- and y-directions) between opposite side walls of conductive pads 88. The thickness T2 is less than the depth D5, the width W5 is greater than the width W4 and less than the width W3, and the total thickness of the trench insulation connectors 85 is the sum of the thickness T2 and the depth D5. In plan view, the conductive pads 88 can have a square and / or a rectangular shape.In some embodiments, the conductive pads 88 can have circular top profiles, oval top profiles, hexagonal top profiles, octagonal top profiles, or other suitably shaped top profiles. In some embodiments, the conductive pads 88 are omitted from the trench insulation connectors 85.

[0033] Trench insulation connectors 85 are discrete and independent segments arranged to form a trench insulation connector ring in the DTI structure 20. For example, the DTI structure 20 has an upper section, a lower section, a first lateral section, and a second lateral section, which together form the rectangular insulation ring. Trench insulation connectors 85 can be divided into a first group 85A, which is arranged in the upper section of the DTI structure 20, a second group 85B, which is arranged in the lower section of the DTI structure 20, a third group 85C, which is arranged in the first lateral section of the DTI structure 20, and a fourth group 85D, which is arranged in the second lateral section of the DTI structure 20. The first group 85A, the second group 85B, the third group 85C and the fourth group 85D together form a rectangular trench insulation connector ring.The trench insulation connectors 85 of the first group 85A and the second group 85B are horizontally aligned and arranged in respective lines along the x-direction, and the trench insulation connectors 85 of the third group 85C and the fourth group 85D are vertically aligned and arranged in respective lines along the y-direction. In some embodiments, trench insulation connectors 85 of the first group 85A, the second group 85B, the third group 85C, the fourth group 85D, or combinations thereof need not be aligned and / or may be arranged in a different configuration (for example, non-linear, zigzag, alternating, etc.). In some embodiments, trench insulation connectors 85 may be arranged differently within the DTI structure 20.In some embodiments, the trench insulation connector ring can be a square ring, a circular ring, an oval ring, a hexagonal ring, an octagonal ring, or another suitably shaped ring.

[0034] In some embodiments, the trench insulation connectors 85 of the device 10 have the same materials and / or the same features. In some embodiments, the trench insulation connectors 85 of the device 10 have different materials and / or different features. In some embodiments, the conductive vias 86 have the same materials and / or the same features. In some embodiments, the conductive vias 86 have different materials and / or different features. In some embodiments, the conductive pads 88 have the same materials and / or the same features. In some embodiments, the conductive pads 88 have different materials and / or different features.

[0035] We turn to the Fig. 3A-3C. The device 10 features a multilayer interconnect (MLI) arranged above a device layer (DL). In such embodiments, a top surface of the MLI provides the front surface FA of wafer A, and surface 12A of substrate 12 (for example, a bottom surface of the device layer DL) provides the back surface BA of wafer A. The device layer DL may include a circuit fabricated on and / or above it by front-end-of-line (FEOL) processing, such as a high-voltage transistor as shown in Fig. 1A, Fig. 1B, Fig. 2A and Fig. 2B is set up as described.

[0036] The multilayer interconnect (MLI) can include a circuit fabricated on and / or above the device layer (DL) by middle-of-line (MOL) processing and / or back-end-of-line (BEOL) processing. The MLI electrically connects devices of the device layer (DL) (e.g., high-voltage transistors), components of the device layer (DL), devices (e.g., a storage device) within the MLI, components of the MLI, or combinations thereof, such that the various devices and / or components can operate according to the design requirements of Device 10.The multilayer interconnect (MLI) comprises a combination of dielectric layers (generally represented as an insulating layer 90) and electrically conductive layers (for example, structured metal layers formed by conductors, conductive vias, conductive contacts, or combinations thereof) configured to form interconnect structures (routing structures). The conductive layers form vertical interconnect structures, such as contacts and / or vias at the device level, which connect horizontal interconnect structures, such as conductors, at different layers / heights (or different levels) of the multilayer interconnect (MLI). In some embodiments, the interconnect structures route electrical signals between devices and / or components of the device layer (DL) and / or the multilayer interconnect (MLI).In some embodiments, the interconnect structures distribute electrical signals (for example, clock signals, voltage signals and / or ground signals) to the devices and / or device components of the device layer DL and / or the multilayer interconnect connection MLI.

[0037] In the Fig. In 3A-3C, the multilayer interconnect MLI comprises a device-level interconnect layer (which may include a device-level contact layer (CO layer) and / or a device-level via layer (VG / VD layer)) and a metal zero layer (Mo layer). In some embodiments, the multilayer interconnect MLI includes a via zero layer (Vo layer), a metal one layer (M1 layer), a via one layer (V1 layer), a metal two layer (M2 layer), a via two layer (V2 layer), a metal three layer (M3 layer), and so on up to a via (X-1) layer (V(X-1) layer) and metal X layer (MX layer). The Vo level has a section of the insulation layer 90 in which V0 vias are arranged, with V0 vias connecting Mo lines to M1 lines.The M1 layer has a section of the insulation layer 90 in which M1 traces are arranged. The V1 layer has a section of the insulation layer 90 in which V1 vias are arranged, with V1 vias connecting M1 traces to M2 traces. The M2 layer has a section of the insulation layer 90 in which M2 traces are arranged. The V2 layer has a section of the insulation layer 90 in which V2 vias are arranged, with V2 vias connecting M2 traces to M3 traces. The M3 layer has a section of the insulation layer 90 in which M3 traces are arranged. The V(X-1) layer has a section of insulation layer 90 in which V(X-1) vias are arranged, with V(X-1) vias connecting M(X-1) lines to MX lines. The M2 layer has a section of insulation layer 90 in which M2 lines are arranged.The MX layer can be the top metal layer of the multilayer interconnect (MLI) connection.

[0038] Each layer of the multilayer interconnect (MLI) has a respective electrically conductive layer (for example, conductors, conductive vias, conductive contacts, or combinations thereof) that is arranged in a respective insulating layer (for example, an ILD layer and / or a CESL).For example, the device-level interconnect layer has a section of the insulation layer 90 in which source / drain contacts MD and / or source / drain vias VD (collectively referred to as source / drain contacts, such as a source / drain contact 92A to source 54A and a source / drain contact 92B to drain 56), gate vias VG (for example, a gate via 94 to the gate structure 60), device-level contacts (for example, contact 96 to the n-doped region 50) and trench isolation connector contacts (TIC contacts) and / or TIC vias (for example, a TIC contact 98A, a TIC contact 98B and a TIC contact 98C) are arranged. The Mo layer has a section of insulation layer 90 in which Mo conductors are arranged, such as a 100A conductor, a 100B conductor, a 100C conductor, a 100D conductor and a 100E conductor.The source / drain contact 92A connects the source 54A to the line 100A, the source / drain contact 92B connects the drain 56 to the line 100D, the gate via 94 connects the active gate stack of the gate structure 60 to the line 100E, the contact 96 connects the n-doped region 50 to the line 100B, the TIC 98A connects a respective trench insulation connector 85 to the line 100A, the TIC 98B connects a respective trench insulation connector 85 to the line 100B, and the TIC 98C connects a respective trench insulation connector 85 to the line 100C.In the illustrated embodiment, the source 54A is electrically connected to a respective trench insulation connector 85 via the source / drain contact 92A, the line 100A and the TIC 98A; the drain 56 is electrically connected to a respective trench insulation connector 85 via the source / drain contact 92B, the line 100D and a respective TIC; an active gate stack of the gate structure 60 is electrically connected to a respective trench insulation connector 85 via a gate via 94, a line 100E and a respective TIC; an n-doped region 50 is electrically connected to a respective trench insulation connector 85 via a contact 96, a line 100B and a TIC 98B; and the n-doped region 50 can furthermore be electrically connected via a respective contact, a line 100C and a respective TIC to a respective trench insulation connector 85 in the group 85C.

[0039] We turn to the Fig. 4A-4C. The multilayer interconnect MLI further comprises a via (X-1) layer (V(X-1) layer) and a metal X layer (MX layer), where X is an integer greater than or equal to 1. The V(X-1) layer has a section of the insulation layer 90 in which conductive vias are arranged, such as a conductive via 102A, a conductive via 102B, and a conductive via 102C. The MX layer has a section of the insulation layer 90 in which MX lines are arranged, such as a line 104A, a line 104B, and a line 104C. Conductive vias 102A-102C each connect lines 100A-100C to lines 104A-104C. In some embodiments, X equals 1, the V(X-1) level is a Vo level of the multilayer interconnect MLI, and the MX level is an M1 level of the multilayer interconnect.In such embodiments, the conductive vias 102A-102C are Vo vias, and the leads 104A-104C are M1 leads. In some embodiments, the conductive vias 102A-102C extend through one or more layers of the multilayer interconnect (MLI). For example, the conductive vias 102A-102C extend through a Vo layer, an M1 layer, a V1 layer, and so on, up to an MX layer that includes the leads 104A-104C. In some embodiments, the leads 104A and / or 104B are bonding pads. The MX layer may be the top metal layer of the multilayer interconnect (MLI).

[0040] The source / drain contact 92A, the source / drain contact 92B, the gate via 94, the contact 96, the TICs 98A-98C, the leads 100A-100E, the conductive vias 102A-102C and the leads 104A-104C contain electrically conductive material, such as tungsten, ruthenium, molybdenum, cobalt, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, graphite, other suitable electrically conductive materials, alloys thereof, silicides thereof or combinations thereof. In some embodiments, the source / drain contact 92A, the source / drain contact 92B, the gate via 94, the contact 96, the TICs 98A-98C, the leads 100A-100E, the conductive vias 102A-102C, the leads 104A-104C or combinations thereof contain the same electrically conductive materials and / or the same structures.In some embodiments, the source / drain contact 92A, the source / drain contact 92B, the gate via 94, the contact 96, the TICs 98A-98C, the leads 100A-100E, the conductive vias 102A-102C, the leads 104A-104C, or combinations thereof, contain different electrically conductive materials and / or different structures. In some embodiments, the source / drain contact 92A, the source / drain contact 92B, the gate via 94, the contact 96, the TICs 98A-98C, the leads 100A-100E, the conductive vias 102A-102C, the leads 104A-104C, or combinations thereof, have multilayer structures, such as a liner and a bulk layer.

[0041] Fig. Figure 5 is a schematic cross-sectional view of a stacked device structure 150, in part or in full, according to various aspects of the present disclosure. The stacked device structure 150 is a wafer-on-wafer (WoW) structure comprising a wafer A attached to and / or bonded to a wafer B. Wafer A has a device 10, and wafer B has a device 200 similar to the device 10. For example, the device 200 has a substrate 212 (which has an area 212A and an area 212B), a DTI structure 220, an STI structure 222, an STI structure 224, a buried layer 230, a DPW 240, an n-well 242A, an n-well 242B, a p-well 244A, a p-well 244B, an n-well 246A, an n-well 246B, a p-well 248, an n-doped region 250, a p-doped region 252, an n-doped region 254A, an n-doped region 254B, an n-doped region 256,a gate structure (for example, a gate dielectric 262, a gate electrode 264, and a gate spacer 266), another gate structure (for example, a gate dielectric 272, a gate electrode 274, and a gate spacer 276), RPOs 280, trench insulation connectors 285 (including, for example, conductive vias 286 and conductive pads 288), an insulating layer 290, a source / drain contact 292A, a source / drain contact 292B, a gate via 294, a contact 296, a TIC 298A, a TIC 298B, a line 300A, and a line 300B. Wafer B has a front face FB (which is connected, for example, by its multilayer interconnect connection MLI, such as a top side of the insulation layer 290,provided) and a rear side BB (which is provided, for example, by its surface 212B of the substrate 212). In some embodiments, the stacked device structure 150 has a stack of high-voltage devices (for example, high-voltage transistors), such as a first high-voltage device (for example, device 10) arranged vertically above or below a second high-voltage device (for example, device 100). The first high-voltage device is physically and / or electrically connected to the second high-voltage device using trench insulation connectors, as described in this text. Fig. Section 5 has been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 150, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 150.

[0042] In Fig. 5. The front face FA of wafer A is directly attached to and / or bonded to the back face BB of wafer B, and the device 10 of wafer A is electrically connected to the device 200 of wafer B. For example, the MLI interconnect connection of wafer A is attached to and / or bonded to the substrate face 212B of wafer B. To enable such a connection, the thickness of the substrate 212 is reduced from thickness T1 to thickness T3 to expose the trench insulation connectors 285 of wafer B. In the illustrated embodiment, the conductor 104A of wafer A is physically and / or electrically connected to a respective trench insulation connector 285 of wafer B, the conductor 104B of wafer A is physically and / or electrically connected to a respective trench insulation connector 285 of wafer B, and the insulation layer 90 physically contacts the buried layer 230 and the DTI structure 220 of wafer B.Accordingly, the Source 254A of the device 200 is electrically connected to the Source 54A of the device 10 via the Source / Drain contact 292A, the line 300A, the TIC 298A, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a line 104A, a conductive via 102A, a line 100A and a Source / Drain contact 92A. Furthermore, the n-doped region 250 of the device 200 (for example, its guard ring) is electrically connected to the n-doped region 50 of the device 10 via the contact 296, the line 300B, the TIC 298B, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), the line 104B, the conductive via 102B, the line 100B and the contact 96.

[0043] Fig. Figure 6 is a schematic cross-sectional view of a stacked device structure 350, in part or in full, according to various aspects of the present disclosure. The stacked device structure 350 is a WoW structure comprising a wafer A attached to and / or bonded to wafer B. Fig. 6. The back side BA of wafer A is directly attached to and / or bonded to the back side BB of wafer B, and the device 10 of wafer A is electrically connected to the device 200 of wafer B. For example, the substrate surface 12B of wafer A is attached to and / or bonded to the substrate surface 212B of wafer B. To enable such a connection, the thicknesses of substrate 12 and substrate 212 are reduced from a thickness T1 to a thickness T3 to expose trench insulation connectors 85 and 285, respectively, on their back sides.In the illustrated embodiment, trench insulation connectors 85 of wafer A are physically and / or electrically connected to respective trench insulation connectors 285 of wafer B (for example, conductive vias 86 physically contact conductive vias 286, and the DTI structure 20 contacts the DTI structure 220), and the buried layer 30 of wafer A is physically and / or electrically connected to the buried layer 230 of wafer B.Accordingly, the source 254A of the device 200 is electrically connected to the n-doped region 50 of the device 10 via the source / drain contact 292A, the line 300A, the TIC 298A, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a respective trench insulation connector 85 (i.e., a respective conductive pad 88 and a respective conductive via 86), the TIC 98B, the line 100B and the contact 96.Furthermore, the n-doped region 250 of the device 200 is electrically connected to the source 54A of the device 10 via the contact 296, the line 300B, the TIC 298B, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a respective trench insulation connector 85 (i.e., a respective conductive pad 88 and a respective conductive via 86), the TIC 98A, the line 100A, and the source / drain contact 92A. Fig. 6 The device 10 has a conductive via 102A, a conductive via 102B, a line 104A and a line 104B which can be physically and / or electrically connected to other devices and / or voltages, and the device 200 has a conductive via 302A, a conductive via 302B, a line 304A and a line 304B which can be physically and / or electrically connected to other devices and / or voltages. In some embodiments, the conductive via 102A, the conductive via 102B, the line 104A, the line 104B or combinations thereof and / or the conductive via 302A, the conductive via 302B, the line 304A, the line 304B or combinations thereof are omitted from the device 10 and / or the device 200. Fig. Section 6 has been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 350, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 350.

[0044] Fig. Figure 7 is a schematic cross-sectional view of a stacked device structure 400, in part or in full, according to various aspects of the present disclosure. The stacked device structure 400 is a WoW structure comprising a wafer A attached to and / or bonded to wafer B. Fig. 7. The back side BA of wafer A is attached to and / or bonded to the back side BB of wafer B via a bonding layer (wafer) 410, and the device 10 of wafer A is electrically connected to the device 200 of wafer B via the bonding layer 410. The bonding layer 410 is attached to and / or bonded to the back side BA of wafer A and the back side BB of wafer B. For example, the substrate area 12B of wafer A is attached to and / or bonded to a first side of the bonding layer 410, and the substrate area 212B of wafer B is attached to and / or bonded to a second side of the bonding layer 410. The bonding layer 410 has an insulating layer 420 in which conductive vias 425 and conductors 430 are arranged, and an interconnect structure of the bonding layer 410 (for example, a combination of conductive vias 425 and conductors 430) electrically connects wafer A and wafer B.In the illustrated embodiment, trench insulation connectors 85 of wafer A are physically and / or electrically connected to respective conductive vias 425 of the bonding layer 410 (for example, conductive vias 86 physically contact conductive vias 425), trench insulation connectors 285 of wafer B are physically and / or electrically connected to respective conductive vias 425 of the bonding layer 410 (for example, conductive vias 286 physically contact conductive vias 425), the DTI structure 20 and the DTI structure 220 are physically connected to the insulation layer 420, and the buried layer 30 and the buried layer 230 are also physically connected to the insulation layer 420.Accordingly, the source 254A of the device 200 is electrically connected to the n-doped region 50 of the device 10 via the source / drain contact 292A, the conductor 300A, the TIC 298A, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a respective interconnect structure of the bonding layer 410 (for example, a combination of conductive vias 425 and conductors 430), a respective trench insulation connector 85 (i.e., a respective conductive pad 88 and a respective conductive via 86), the TIC 98B, the conductor 100B and the contact 96.Furthermore, the n-doped region 250 of the device 200 is electrically connected to the source 54A of the device 10 via the contact 296, the line 300B, the TIC 298B, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a respective interconnect structure of the bonding layer 410 (for example, a combination of conductive vias 425 and lines 430), a respective trench insulation connector 85 (i.e., a respective conductive pad 88 and a respective conductive via 86), the TIC 98A, the line 100A, and the source / drain contact 92A. Fig. Section 7 has been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 400, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 400.

[0045] Fig. Figure 8 is a schematic cross-sectional view of a stacked device structure 450, in part or in full, according to various aspects of the present disclosure. The stacked device structure 450 is a WoW structure comprising a wafer A attached to and / or bonded to wafer B. Fig. 8. The front face FA of wafer A is attached to and / or bonded to the back face BB of wafer B via a bonding layer (wafer) 410, and the device 10 of wafer A is electrically connected to the device 200 of wafer B via the bonding layer 410. The bonding layer 410 is attached to and / or bonded to the front face FA of wafer A and the back face BB of wafer B. For example, the multilayer interconnect MLI of wafer A (for example, the top of the insulating layer 90) is attached to and / or bonded to a first side of the bonding layer 410, and the substrate face 212B of wafer B is attached to and / or bonded to a second side of the bonding layer 410.In the illustrated embodiment, the conductor 104A of wafer A is physically and / or electrically connected to a respective conductive via 425 of the bonding layer 410, the conductor 104B of wafer A is physically and / or electrically connected to a respective conductive via 425 of the bonding layer 410, the trench insulation connectors 285 of wafer B are physically and / or electrically connected to respective conductive vias 425 of the bonding layer 410 (for example, conductive vias 286 physically contact conductive vias 425), the insulation layer 90 of wafer A physically contacts the insulation layer 420 of the bonding layer 410, the DTI structure 220 of wafer B physically contacts the insulation layer 420, and the buried layer 230 of wafer B physically contacts the insulation layer 420.Accordingly, the Source 254A of the device 200 is electrically connected to the Source 54A of the device 10 via the Source / Drain contact 292A, the line 300A, the TIC 298A, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a respective interconnect structure of the bonding layer 410 (for example, a combination of conductive vias 425 and lines 430), the line 104A, the conductive via 102A, the line 100A and the Source / Drain contact 92A.Furthermore, the n-doped region 250 of the device 200 is electrically connected to the n-doped region 50 of the device 10 via the contact 296, the line 300B, the TIC 298B, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a respective interconnect structure of the bonding layer 410 (for example, a combination of conductive vias 425 and lines 430), the line 104B, the conductive via 102B, the line 100B and the contact 96. Fig. Section 8 has been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 450, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 450.

[0046] Fig. Figure 9 is a schematic cross-sectional view of a stacked device structure 500, in part or in full, according to various aspects of the present disclosure. The stacked device structure 500 is a WoW structure comprising a wafer B attached to and / or bonded to wafer A and wafer C. Wafer A has device 10, wafer B has device 200, and wafer C has a device 600 similar to device 10. For example, the device 600 has a substrate 612 (which has an area 612A and an area 612B), a DTI structure 620, an STI structure 622, an STI structure 624, a buried layer 630, a DPW 640, an n-well 642A, an n-well 642B, a p-well 644A, a p-well 644B, an n-well 646A, an n-well 646B, a p-well 648, an n-doped region 650, a p-doped region 652, an n-doped region 654A, an n-doped region 654B, an n-doped region 656,a gate structure (for example, a gate dielectric 662, a gate electrode 664, and a gate spacer 666), another gate structure (for example, a gate dielectric 672, a gate electrode 674, and a gate spacer 676), RPOs 680, trench insulation connectors 685 (including, for example, conductive vias 686 and conductive pads 688), an insulating layer 690, a source / drain contact 692A, a source / drain contact 692B, a gate via 694, a contact 696, a TIC 698A, a TIC 698B, a line 700A, and a line 700B. Wafer C has a front side FC (for example 750), which is connected by its multilayer interconnect MLI, such as a top side of the insulation layer 690,provided) and a rear side BC (which is provided, for example, by its surface 612B of the substrate 612). In some embodiments, the stacked device structure 500 has a stack of high-voltage devices (for example, high-voltage transistors), such as a first high-voltage device (for example, device 10) and a second high-voltage device (for example, device 600) arranged vertically above or below a third high-voltage device (for example, device 200). The first high-voltage device is located laterally next to the second high-voltage device. The first high-voltage device and the second high-voltage device are physically and / or electrically connected to the second high-voltage device using trench insulation connectors. Fig. Section 9 has been simplified for clarity and to facilitate understanding of the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 500, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 500.

[0047] In Fig. 9. The back side BA of wafer A and the back side BC of wafer C are attached to and / or bonded to the back side BB of wafer B via a bonding layer (wafer) 710, and the device 10 of wafer A and the device 600 of wafer C are electrically connected to the device 200 of wafer B via the bonding layer 710. The bonding layer 710 is attached to and / or bonded to the back side BA of wafer A, the back side BB of wafer B, and the back side BC of wafer C. For example, the substrate area 12B of wafer A is attached to and / or bonded to a first side of the bonding layer 710, the substrate area 212B of wafer B is attached to and / or bonded to a second side of the bonding layer 710, and the substrate area 612B of wafer C is attached to and / or bonded to the first side of the bonding layer 710. The bonding layer 710 has an insulating layer 720,in which conductive vias 725 and conductors 730 are arranged. Interconnect structures of the bonding layer 710 (for example, combinations of conductive vias 725 and conductors 730) electrically connect wafer B to wafer A and wafer C. In the illustrated embodiment, the trench insulation connectors 85 of wafer A are physically and / or electrically connected to respective conductive vias 725 of the bonding layer 710 (for example, conductive vias 86 physically contact conductive vias 725), and the trench insulation connectors 285 of wafer B are physically and / or electrically connected to respective conductive vias 725 of the bonding layer 710 (for example, conductive vias 286 physically contact conductive vias 725).The trench insulation connectors 685 of wafer C physically and / or electrically contact respective conductive vias 725 of the bonding layer 710 (for example, conductive vias 686 physically contact conductive vias 725), DTI structures (for example, DTI structure 20, DTI structure 220, and DTI structure 620) physically contact the insulation layer 720, and buried layers (for example, buried layer 30, buried layer 230, and buried layer 630) physically contact the insulation layer 720. Accordingly, the source 254A of the device 200 is connected via the source / drain contact 292A, the line 300A, the TIC 298A, a respective trench insulation connector 285 (that is, a respective conductive pad 288, and a respective conductive Through-hole plating 286),a respective interconnect structure of the bonding layer 710 (for example, a combination of conductive vias 725 and conductors 730), a respective trench insulation connector 685 (that is, a respective conductive pad 688 and a respective conductive via 686), the TIC 698B, the conductor 700B and the contact 696 electrically connected to the n-doped region 650 of the device 600. Furthermore, the n-doped region 250 of the device 200 is connected via the contact 296, the line 300B, the TIC 298B, a respective trench insulation connector 285 (i.e., a respective conductive pad 288 and a respective conductive via 286), a respective interconnect structure of the bonding layer 710 (for example, a combination of conductive vias 725 and lines 730), a respective trench insulation connector 85 (i.e., a respective conductive pad 88 and a respective conductive via 86).electrically connected the TIC 98B, the line 100B and the contact 96 to the n-doped region 50 of the device 10.

[0048] Because the trench insulation connectors disclosed in this text are independent and / or electrically insulated from each other, they provide flexible backend connections to adjacent devices, such as those described in Fig. 10A and Fig. 10B are shown, ready. Fig. Figure 10A is a schematic top view of a stacked device structure 800, partially or completely, according to various aspects of the present disclosure. Fig. Figure 10B is a schematic cross-sectional view of the stacked device structure 800, partially or completely, of Fig. 10A according to various aspects of the present disclosure. The stacked device structure 800 is a WoW structure comprising a wafer 810 attached to and / or bonded to a wafer 820. Wafer 810 and wafer 820 each have a respective BEOL structure (for example, a respective multilayer interconnect MLI) arranged over a respective device layer DL. In the illustrated embodiment, a rear side of wafer 810 (for example, a bottom side of a device substrate of its device layer DL) is attached to and / or bonded to a front side of wafer 820 (for example, a top side of its BEOL structure). The BEOL structure of wafer 820 provides electrical backend connections between devices of wafer 810, as described further below. Fig. 10A and Fig. References 10B have been simplified for the sake of clarity in order to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 800, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 800.

[0049] In Fig. 10A and Fig. In 10B, wafer 810 has a device 900A and a device 900B, which are formed from sections of the device layer DL and the BEOL structure of wafer 810. Device 900A and device 900B may resemble devices described in this text. For example, device 900A includes a substrate 912, an active region 916A, a DTI structure 920, an STI structure 922A, an STI structure 924A, an n-doped region 950A, a p-doped region 952A, active gate structures (for example, a gate structure 960A (G1) and a gate structure 960B (G2)), trench insulation connectors 985 (including, for example, conductive vias 986 and conductive pads 988), an insulation layer 990, a gate via 994A, a gate via 994B, a TIC 998A, and a conductor 1000A.Device 900B comprises a substrate 912, an active region 916B, a DTI structure 920, an STI structure 922B, an STI structure 924B, an n-doped region 950B, a p-doped region 952B, active gate structures (for example, a gate structure 960C (G3) and a gate structure 960D (G4)), trench insulation connectors 985 (including, for example, conductive vias 986 and conductive pads 988), an insulating layer 990, a gate via 994C, a gate via 994D, a TIC 998B, and a conductor 1000B. A section of the DTI structure 920 physically and / or electrically separates and / or isolates Device 900A and Device 900B. Active Region 916A and Active Region 916B may also contain a respective buried layer, a respective DPW, respective n-depressions, respective p-depressions, additional respective n-doped regions and / or p-doped regions, respective RPOs, respective dummy gate structures, etc.In some embodiments, the device 900A and the device 900B are high-voltage devices and / or transistors.

[0050] Gate structure 960A and gate structure 960B (for example, active gate stacks) of device 900A. For example, gate structure 960A is electrically connected to gate structure 960B via gate via 994A, line 1000A, and gate via 994B of the BEOL structure of wafer 810. Gate structure 960C and gate structure 960D (for example, their active gate stacks) are connected by front-side interconnect connections. For example, gate structure 960C is electrically connected to gate structure 960D via gate via 994C, line 1000B, and gate via 994D of the BEOL structure of wafer 810. Lines 1000A and 1000B are further connected via TIC 998A and 998B, respectively, to trench insulation connectors 985. Fig. Line 10A and line 1000B are generally L-shaped routing structures, although the present disclosure also considers other forms of routing structures.

[0051] The gate terminals of device 900A and the gate terminals of device 900B are connected by trench isolation connectors 985 and rear interconnect connections and / or rear routing layers provided by wafer 820. For example, wafer 820 comprises a substrate 1012, trench insulation connectors 1085 (including, for example, conductive vias 1086 and conductive pads), an insulating layer 1090, a bonding pad 1097A, a bonding pad 1097B, a TIC 1098A, a TIC 1098B, and a conductor 2000. In some embodiments, bonding pad 1097A and bonding pad 1097B are sections of TIC 1098A and TIC 1098, respectively. Bonding pad 1097A is physically and / or electrically connected to a respective trench insulation connector 985 of wafer 810, which is connected to gate terminals of device 900A (for example, G1 and G2).Bonding pad 1097B is physically and / or electrically connected to a respective trench insulation connector 985 of wafer 810, which is connected to gate terminals of device 900B (for example, G3 and G4). TIC 1098A and TIC 1098B are physically and / or electrically connected to bonding pad 1097A and bonding pad 1097B, respectively, and line 2000 physically and / or electrically connects TIC 1098A and TIC 1098B. Gate terminal G1 and gate terminal G2 of device 900A are thus electrically connected to gate terminal G3 and gate terminal G4 via an interconnect structure (routing structure) on the back side of wafer 810.Such a backside connection can be advantageous if the shortest connection between device 900A and device 900B on the front side of wafer 810 passes through an occupied region OC of the BEOL structure of wafer 810, such as when the BEOL structure has interconnect structures (routing structures) for other device structure elements and / or devices of wafer 810.

[0052] Because the trench insulation connectors disclosed in the present text are independent and / or electrically isolated from each other, the trench insulation connectors also provide flexible backend connections to devices of stacked device structures, such as those described in Fig. 11A and Fig. 11B are shown. Fig. Figure 11A is a schematic top view of a stacked device structure 3000, partially or completely, according to various aspects of the present disclosure. Fig. Figure 11B is a schematic cross-sectional view of the stacked device structure 3000, partially or completely, of Fig. 11A according to various aspects of the present disclosure. The stacked device structure 3000 is a WoW structure comprising a wafer 3010 attached to and / or bonded to a wafer 3020, which in turn is attached to and / or bonded to a wafer 3030. Wafer 3010, wafer 3020, and wafer 3030 can be referred to as a 3rd layer, 2nd layer, and 1st layer, respectively, of the stacked device structure 3000. Wafer 3010, wafer 3020, and wafer 3030 each have a respective BEOL structure (for example, a respective multilayer interconnect MLI) arranged above a respective device layer DL.In the illustrated embodiment, a back side of wafer 3010 (for example, a bottom side of a device substrate of its device layer DL) is attached to and / or bonded to a front side of wafer 3020 (for example, a top side of its BEOL structure), and a back side of wafer 3020 (for example, a bottom side of a device substrate of its device layer DL) is attached to and / or bonded to a front side of wafer 3030 (for example, a top side of its BEOL structure). The BEOL structure of wafer 3020 provides electrical back-end connections from devices of wafer 3010 to devices of wafer 3020 and / or devices of wafer 3030, and the BEOL structure of wafer 3030 provides electrical back-end connections from devices of wafer 3010 and devices of wafer 3020 to devices of wafer 3030.Such backend connections are made possible by trench insulation connectors of wafer 3010, wafer 3020 and wafer 3030, as described below. Fig. 11A and Fig. References 11B have been simplified for the sake of clarity in order to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 3000, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 3000.

[0053] In Fig. 11A and Fig. Wafer 11B features the stacked fixture structure 3000 with different fixtures, such as fixture A, fixture B, fixture C, fixture D, fixture E, and other fixtures. Wafer 3010 features fixture A and fixture C, wafer 3020 features fixture D, and wafer 3030 features fixture B and fixture E. Fixture A and fixture C are formed from sections of the fixture layer DL and the BEOL structure of wafer 3010. Fixture D is formed from sections of the fixture layer DL and the BEOL structure of wafer 3020. Fixture B and fixture E are formed from sections of the fixture layer DL and the BEOL structure of wafer 3030. Fixture A, fixture B, fixture C, fixture D, fixture E, or combinations thereof can be the same types or different types of fixtures.In some embodiments, Device B is a high-voltage device, such as the high-voltage devices described in this text, and Device A, Device C, Device D, and Device E are medium-voltage devices, low-voltage devices, other types of devices, or combinations thereof. Medium-voltage devices can operate at higher voltages (for example, threshold voltages) than low-voltage devices, and high-voltage devices can operate at higher voltages than medium-voltage devices.

[0054] Wafer 3010 comprises a substrate 4012, a DTI structure 4020 that defines and insulates various device regions of the substrate 4012, trench insulation connectors 4085 (including, for example, conductive vias 4086 and conductive pads 4088), an insulation layer 4090, a device contact 4092A, a device contact 4092B, a TIC 4098A, a TIC 4098B, a conductor 5000A, and a conductor 5000B. Device A and device C are electrically insulated from each other and / or from other devices of wafer 3010 by the DTI structure 4020 and / or other insulation structures, such as STI structures. Device A is connected to a respective trench insulation connector 4085 via the device contact 4092A, the line 5000A and the TIC 4098A (together referred to as an interconnect structure (routing structure)).Device C is connected to a respective trench insulation connector 4085 via the device contact 4092B, the line 5000B and the TIC 4098B.

[0055] Wafer 3020 comprises a substrate 6012, a DTI structure 6020 that defines and insulates various device regions of the substrate 6012, trench insulation connectors 6085 (including, for example, conductive vias 6086 and conductive pads 6088), an insulation layer 6090, a device contact 6092, a bonding pad 6097A, a bonding pad 6097B, a TIC 6098A, a TIC 6098B, a TIC 6098C, a TIC 6098D, a conductor 7000A, and a conductor 7000B. Device D is electrically insulated from other devices of wafer 3020 by the DTI structure 6020 and / or other insulation structures, such as STI structures. Device-D is connected via the device contact 6092, the line 7000B and the TIC 6098D to a respective trench insulation connector 4085.Device-D is further connected to device-C of wafer 3010 via the device contact 6092, the line 7000B, the TIC 6098B, the bonding pad 6097B, a respective trench insulation connector 4085 of wafer 3010, the TIC 4098B, the line 5000B and the device contact 4092B. The BEOL structure of wafer 3020 also connects the fixture layer DL of wafer 3010 to the fixture layer DL of wafer 3020. For example, each trench insulation connector 4085 of wafer 3010 is connected to a respective trench insulation connector 6085 of wafer 3020 via the bonding pad 6097A, the TIC 6098A, the conductor 7000A, and the TIC 6098C. Since the respective trench insulation connector 4085 is connected to fixture A, the BEOL structure of wafer 3020 and the respective trench insulation connector 6085 of wafer 3020 connect fixture A of wafer 3010 to wafer 3030.

[0056] Wafer 3030 comprises a substrate 8012, a DTI structure 8020 defining and isolating various device regions of the substrate 8012, trench insulation connectors 8085 (including, for example, conductive vias 8086 and conductive pads 8088), an insulation layer 8090, a device contact 8092A, a device contact 8092B, a bonding pad 8097A, a bonding pad 8097B, a bonding pad 8097C, a TIC 8098A, a TIC 8098B, a TIC 8098C, a TIC 8098D, a TIC 8098E, a TIC 8098F, a conductor 9000A and a conductor 9000B. Device B and Device E are electrically isolated from each other and / or from other devices of wafer 3030 by the DTI structure 8020 and / or other insulation structures, such as STI structures.

[0057] Device B is connected to a trench insulation connector 8085 via device contact 8092A, cable 9000A, and TIC 8098D. Alternatively and / or additionally, device B is connected to a trench insulation connector 8085 via device contact 8092A, cable 9000A, and TIC 8098F. Device E is connected to a trench insulation connector 8085 via device contact 8092B, cable 9000B, and TIC 8098E. Device E is furthermore connected to a trench insulation connector 6085 of wafer 3020 via device contact 8092B, cable 9000B, TIC 8098C, and bonding pad 8097C.

[0058] Device B is connected to device D of wafer 3020 via device contact 8092A, line 9000A, TIC 8098B, bonding pad 8097B, a respective trench insulation connector 6085 of wafer 3020, TIC 6098D, line 7000B, and device contact 6092B. Alternatively and / or additionally, device B is connected to device D via device contact 8092A, line 9000A, TIC 8098A, bonding pad 8097A, a respective trench insulation connector 6085 of wafer 3020, TIC 6098C, line 7000A, and another device contact of wafer 3020, which is connected to line 7000A and device D. The trench insulation connectors 6085 of wafer 3020 thus provide considerable interconnect connection or routing flexibility when connecting fixtures of wafers of the stacked fixture structure 3000.

[0059] Since Device-D is connected to Device-C via the BEOL structure of Wafer 3020, a respective trench insulation connector 4085 of Wafer 3010 and the BEOL structure of Wafer 3010, Device-B can also be connected to Device-C of Wafer 3010. Furthermore, device B can be connected to device A via the BEOL structure of wafer 3030A (for example, device contact 8092A, line 9000A, TIC 8098A, bonding pad 8097A), a respective trench insulation connector 6085 of wafer 3020, the BEOL structure of wafer 3020 (for example, TIC 6098C, line 700A, TIC 6089A and bonding pad 6097A), a respective trench insulation connector 4085 of wafer 3010 and the BEOL structure of wafer 3010 (for example, TIC 4098A, line 5000A and device contact 4092A).Various devices of the stacked device structure 3000 are thus electrically connected to rear interconnect structures (routing structures) that have trench insulation connectors, which can considerably increase routing flexibility when connecting devices together, reduce the area occupied by the interconnected devices, improve the area utilization of the connected devices, etc.

[0060] Fig. Figures 12A-12E are fragmentary schematic cross-sectional views of the stacked device structure of Fig. 5, partially or completely, at various stages of their manufacture according to various aspects of the present disclosure. As described above, the stacked device structure comprises 150 wafers A and B, wherein the front face of wafer A is attached to and / or bonded to the back face of wafer B, and wafers A and B are electrically connected to each other using trench insulation connectors. Fig. Figures 12A-12E have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 150, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 150. Additional steps can be provided before, during, and after the fabrication of the stacked device structure 150, and some of the described steps can be shifted, replaced, or omitted to obtain additional embodiments of the stacked device structure 150.

[0061] We turn to Fig. 12A. Wafer A and wafer B undergo FEOL processing, which includes forming device 10 on wafer A and forming device 200 on wafer B. The FEOL processing further includes trench isolation structures of wafer A and wafer B, such as DTI structure 20 and DTI structure 220, which are used to enable the interconnect connection between wafer A and wafer B. Forming a trench isolation structure may include: forming a structured mask layer over a substrate, etching the substrate to form a trench therein using the structured mask layer as an etch mask, depositing an insulating material (for example, an insulating material (for example, a dielectric material, such as an oxide material)) in the trench, and removing the structured mask layer. In some embodiments, the trench defines a device region of the substrate.In some embodiments, a structure in the structured mask layer defines the device region of the substrate. In some embodiments, the trench depth is at least as great as the depth of a buried layer, such as NBL 30 and / or NBL 230. In some embodiments, the trench depth is equal to the depth of the bottom of the buried layer. In some embodiments, the trench depth is less than the thickness of the substrate. In the embodiment shown, the trench insulation structure is a DTI. However, the present disclosure considers that the trench insulation structure could be a DTI, an STI, a Local Oxidation of Silicon (LOCOS) structure, another suitable insulation structure, or combinations thereof.

[0062] We turn to Fig. 12B. Trench insulation connectors are formed in the trench insulation structures, such as trench insulation connector 85 (including conductive vias 86 and conductive pads 88) in the DTI structure 20 of the device 10 and trench insulation connector 285 (including conductive vias 286 and conductive pads 288) in the DTI structure 220 of the device 200. Forming a trench insulation connector can include: forming a structured mask layer over a substrate that exposes a trench insulation structure, etching the trench insulation structure to form a trench therein using the structured mask layer as an etching mask, depositing an electrically conductive material (for example, metal) in the trench, and removing the structured mask layer.A conductive via and a conductive pad of the trench insulation connector can be formed by the same or different deposition processes, the same or different etching processes, the same or different structuring processes, or combinations thereof. In some embodiments, forming the conductive pad includes depositing the electrically conductive material in an opening in the structured mask layer that exposes the trench insulation connector, and / or an opening in a material layer deposited prior to the formation of the structured mask layer.

[0063] We turn to Fig. 12C to. Wafer A and Wafer B are subjected to BEOL processing, which includes forming a multilayer interconnect (MLI) connection of device 10 and / or Wafer A and forming a multilayer interconnect (MLI) connection of device 200 and / or Wafer B.

[0064] We turn to Fig. 12D, where a thinning process is performed on wafer B. For example, the thinning process reduces the thickness of the substrate 212 (for example, from a thickness T1 to a thickness T3) and exposes the trench insulation connectors 285 such that the DTI structure 220 and / or the trench insulation connectors 285 extend completely through the substrate 212. For example, after the thinning process, the DTI structure 220 and / or the trench insulation connectors 285 extend from face 212A (for example, the front) to face 212B (for example, the back) of the substrate 212. The thinning process reduces the thickness of the substrate 212 along the Z-direction. The thinning process is a grinding process, a planarization process (for example, CMP), an etching process, another suitable process, or a combination thereof.In some embodiments, the thinning process is a CMP applied to the backside BB of wafer B (i.e., a backside CMP). In some embodiments, wafer B is bonded to the support wafer (substrate) prior to performing the thinning process. For example, the insulating layer 290 and / or a structured metal layer within the insulating layer 290 can be bonded to a support wafer.

[0065] In some embodiments, bonding pads, such as bonding pad 306A and bonding pad 306B, can be formed from wafer B via trench insulation connectors 285. Bonding pad 306A and bonding pad 306B are physically and / or electrically connected to their respective trench insulation connectors 285. Bonding pad 306A and bonding pad 306B can be arranged in an insulation layer, similar to insulation layer 290 and / or insulation layer 90. In some embodiments, conductive vias 286 are formed from wafer B after the thinning process.

[0066] We turn to Fig. 12E. The front face FA of wafer A is attached to and / or bonded to the back face BB of wafer B. In such embodiments, a BEOL structure (for example, a multilayer interconnect MLI) of wafer A can provide silicon-on-insulator (SOI-like) insulation for the device 10 of wafer A, such as SOI-like electrical insulation from the device 200 of wafer B. Wafer A and wafer B can be attached by dielectric-to-dielectric bonding (for example, oxide-to-oxide bonding), metal-to-metal bonding (for example, copper-to-copper bonding), metal-to-dielectric bonding (for example, copper-to-oxide bonding), other types of bonding, or combinations thereof. For example, conductor 104A and conductor 104B from wafer A are attached to and / or bonded to the trench insulation connectors 286 of wafer B directly or via the bonding pad 306A and bonding pad 306B of wafer B, respectively.

[0067] Fig. Figures 13A-13E are fragmentary schematic cross-sectional views of the stacked device structure 350 of Fig. 6, partially or completely, at various stages of their fabrication according to various aspects of the present disclosure. As described above, the stacked device structure 350 comprises wafers A and B, wherein the back side of wafer A is attached to and / or bonded to the back side of wafer B, and wafers A and B are electrically connected to each other using trench insulation connectors. The fabrication of the stacked device structure 350 is similar to the fabrication of the stacked device structure 150 in Fig. 12A-12E. For example, the manufacturing process includes performing FEOL processing on wafer A and wafer B, including forming trench isolation structures of wafer A and wafer B ( Fig. 13A), forming trench isolation connectors in the trench isolation structures ( Fig. 13B), of performing BEOL processing on wafer A and wafer B ( Fig. 13C), of performing a thinning process on wafer B ( Fig. 13D), and the attachment and / or bonding of wafer A and wafer B ( Fig. 13E). In Fig. In step 13D, a thinning process is also carried out on wafer A to, for example, reduce the thickness of the substrate 12 (for example, from a thickness T1 to a thickness T3), thereby exposing trench insulation connectors 85, such that the DTI structure 20 and / or the trench insulation connectors 85 arranged therein extend completely through the substrate 12. Fig. 13E is the back side BA of wafer A directly attached to and / or bonded to the back side BB of wafer B. For example, the trench insulation connectors 85 of wafer A are physically and / or electrically connected to trench insulation connectors 285 of wafer B. Wafer A and wafer B can be attached by dielectric-to-dielectric bonding, metal-to-metal bonding, metal-to-dielectric bonding, other bonding methods, or combinations thereof. Fig. Figures 13A-13E have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 350, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 350. Additional steps can be provided before, during, and after the fabrication of the stacked device structure 350, and some of the described steps can be shifted, replaced, or omitted to obtain additional embodiments of the stacked device structure 350.

[0068] Fig. Figures 14A-14E are fragmentary schematic cross-sectional views of the stacked device structure 400 of Fig. 7, partially or completely, at various stages of their fabrication according to various aspects of the present disclosure. As described above, the stacked device structure 400 comprises wafers A and B, wherein the back side of wafer A is attached to and / or bonded to the back side of wafer B, and wafers A and B are electrically connected to each other using trench insulation connectors. The fabrication of the stacked device structure 400 is similar to the fabrication of the stacked device structure 150 in Fig. 12A-12E. For example, the manufacturing process includes performing FEOL processing on wafer A and wafer B, including forming trench isolation structures of wafer A and wafer B ( Fig. 14A), forming trench isolation connectors in the trench isolation structures ( Fig. 14B), of performing BEOL processing on wafer A and wafer B ( Fig. 14C), of performing a thinning process on wafer B ( Fig. 14D), and the attachment and / or bonding of wafer A and wafer B ( Fig. 14E). In Fig. In step 14D, a thinning process is also carried out on wafer A to, for example, reduce the thickness of the substrate 12 (for example, from a thickness T1 to a thickness T3), thereby exposing the DTI structure 20, such that the DTI structure 20 and / or the trench insulation connectors 85 extend completely through the substrate 12. Fig. In step 14E, the bonding layer 410 is formed on the back side BA of wafer A, the back side BB of wafer B, or a combination thereof, and then the back side BA of wafer A is applied to and / or bonded to the back side BB of wafer B. For example, the bonding layer 410 is formed on face 12B of wafer A, and the bonding layer 410 is applied to and / or bonded to face 212B of wafer B, or vice versa. Fig. References 14A-14E have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 400, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 400. Additional steps can be provided before, during, and after the fabrication of the stacked device structure 400, and some of the described steps can be shifted, replaced, or omitted to obtain additional embodiments of the stacked device structure 400.

[0069] Fig. Figures 15A-15E are fragmentary schematic cross-sectional views of the stacked device structure 450 of Fig. 8, partially or completely, at various stages of their fabrication according to various aspects of the present disclosure. As described above, the stacked device structure 450 comprises wafers A and B, wherein the front face of wafer A is attached to and / or bonded to the back face of wafer B, and wafers A and B are electrically connected to each other using trench insulation connectors. The fabrication of the stacked device structure 450 is similar to the fabrication of the stacked device structure 150 in Fig. 12A-12E. For example, the manufacturing process includes performing FEOL processing on wafer A and wafer B, including forming trench isolation structures of wafer A and wafer B ( Fig. 15A), forming trench isolation connectors in the trench isolation structures ( Fig. 15B), of performing BEOL processing on wafer A and wafer B ( Fig. 15C), of performing a thinning process on wafer B ( Fig. 15D), and the attachment and / or bonding of wafer A and wafer B ( Fig. 15E). In Fig. In step 15E, the bonding layer 410 is formed on the front face FA of wafer A, the back face BB of wafer B, or a combination thereof, and then the front face FA of wafer A is applied to and / or bonded to the back face BB of wafer B. For example, the bonding layer 410 is formed on the multilayer interconnect MLI of wafer A, and the bonding layer 410 is applied to and / or bonded to face 212B of wafer B, or vice versa. Fig.References 15A-15E have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional structural elements can be added to the stacked device structure 450, and some of the structural elements described below can be replaced, modified, or omitted in other embodiments of the stacked device structure 450. Additional steps can be provided before, during, and after the fabrication of the stacked device structure 450, and some of the described steps can be shifted, replaced, or omitted to obtain additional embodiments of the stacked device structure 450.

[0070] Wafers, as described in this text, can be processed wafers that have fixture structures and / or semiconductor structures before or after singulation (that is, when a processed wafer is divided into individual chips and / or dies). In some embodiments, Wafer A and Wafer B are wafers that have not been subjected to singulation, wherein Wafer A (and / or fixtures thereof) and Wafer B (and / or fixtures thereof) are physically and / or electrically connected prior to singulation. In such embodiments, the stacked fixtures described in this text are non-singled wafer stacks that can subsequently be subjected to a singulation process, such as a dicing process.The dicing process can be performed by sawing and / or scoring operations, such as mechanical sawing, laser sawing, structured etching, scoring followed by mechanical breaking, other dicing methods, or combinations thereof. In some embodiments, the singulation process includes separating stacked dies and / or stacked fixtures of the stacked wafers, such as the stacked fixture structures disclosed herein, from one another by cutting the stacked wafers along scoring lines, thereby providing individual, separate stacked dies and / or stacked fixtures. Following the singulation process, the resulting separate stacked dies and / or stacked fixtures can be sold and / or shipped and / or packaged and / or individually integrated into other packages.In some embodiments, the stacked device structures described in this text can be separated into separate stacked dies and / or stacked devices that are electrically connected by trench insulation connectors.

[0071] In some embodiments, wafer A and wafer B are wafers after a singulation process, wherein wafer A and wafer B are devices, chips, dies, packages, etc., that are physically and / or electrically connected after singulation. In such embodiments, the stacked device structures described in this text are device stacks, chip stacks, die stacks, package stacks, etc. For example, wafer A can be a first device, wafer B can be a second device, and the first device is electrically connected to the second device via a trench isolation connector, as described, for example, in this text. In another example, wafer A can be a first chip, wafer B can be a second chip, and the first chip (and / or a first device thereof) is electrically connected to the second chip (and / or a second device thereof) via a trench isolation connector, as described in this text.In another example, wafer A can be a first IC package, wafer B can be a second IC package, and the first IC package (and / or a first device thereof) is electrically connected to the second IC package (and / or a second device thereof) via a trench insulation connector, as described, for example, in this text. In yet another example, wafer A can be a first chip stack, wafer B can be a second chip stack, and the first chip stack (and / or a first device thereof) is electrically connected to the second chip stack (and / or a second device thereof) via a trench insulation connector, as described, for example, in this text.

[0072] This text discloses trench insulation connectors that electrically connect stacked structures, such as wafers, IC chips, IC dies, substrates, their fixtures, or combinations thereof. The present disclosure allows for many different embodiments. An exemplary stacked fixture arrangement comprises a first fixture substrate having a first fixture, and a second fixture substrate having a first face facing a second face. The second fixture substrate has a second fixture on the first face of the second fixture substrate. The stacked fixture arrangement further comprises an insulation structure located within the second fixture substrate and surrounding the second fixture. The insulation structure extends from the first face of the second fixture substrate through the second fixture substrate to the second face of the second fixture substrate.The stacked device arrangement further comprises a conductive connector located within the insulating structure. The conductive connector is connected to the second device, the conductive connector is connected to the first device, and the conductive connector extends from the first surface of the second device substrate to the second surface of the second device substrate. In some embodiments, the first device and the second device are high-voltage devices.

[0073] In some embodiments, a first chip comprises the first device substrate and a first multilayer interconnect (MLI) arranged above the first device substrate, and a second chip comprises the second device substrate and a second MLI arranged above the second device substrate. The first MLI is connected to the first device, and the second MLI is connected to the second device. The first MLI provides a front face of the first chip, and the first device substrate provides a back face of the first chip. The second MLI provides a front face of the second chip, and the second surface of the second device substrate provides a back face of the second chip. In some embodiments, the back face of the second chip is attached to the front face of the first chip, and the conductive connector is connected to both the first and second MLIs.In some embodiments, the back of the second chip is attached to the front of the first chip via a bonding layer, an interconnect structure of the bonding layer is connected to the conductive connector and the first MLI, and the conductive connector is connected to the second MLI.

[0074] In some embodiments, the insulating structure is a first insulating structure, and the conductive connector is a first conductive connector. In such embodiments, the stacked device assembly may also include a second insulating structure located within the first device substrate. The second insulating structure surrounds the first device and extends from a first surface of the first device substrate through the first device substrate to a second surface of the first device substrate. The stacked device assembly may further include a second conductive connector located within the second insulating structure.The second conductive connector is connected to the first device, the second conductive connector is connected to the second device, and the second conductive connector extends from the first surface of the first device substrate to the second surface of the first device substrate.

[0075] In some embodiments, the back side of the second chip is attached to the back side of the first chip, and the first conductive connector is connected to the second conductive connector. In some embodiments, the back side of the second chip is attached to the back side of the first chip via a bonding layer, and an interconnect structure of the bonding layer is connected to the first conductive connector and the second conductive connector.

[0076] An exemplary device stack comprises a first device above a second device. The first device is formed above a first device layer by a first back-end-of-line (BEOL) structure. The second device is formed above a second device layer by a second BEOL structure. A trench isolation connector connects the first device to the second device. The trench isolation connector is a section of the first device layer, has a conductive through-hole arranged within an isolation structure, and is a back-end interconnect of the first device. In some embodiments, the isolation structure is a deep trench isolation structure located within a substrate of the first device layer.In some embodiments, the trench isolation connector joins a front face of the first device to a front face of the second device. In some embodiments, the first device and the second device are high-voltage transistors. In some embodiments, the device stack has a bonding layer that attaches the first device layer and the second BEOL structure, and the trench isolation connector is bonded to the bonding layer.

[0077] In some embodiments, the trench insulation connector is a first trench insulation connector, the backside interconnect is a first backside interconnect, and the conductive via is a first conductive via. In such embodiments, the device stack may further comprise a third device formed by the first device layer and the first BEOL structure, and a second trench insulation connector linking the third device to the second device. The second trench insulation connector is a section of the first device layer, the second trench insulation connector has a second conductive via located within the insulation structure, and the second trench insulation connector is a second backside interconnect of the third device.

[0078] The first BEOL structure can connect a gate of the first device to the first trench insulation connector and a gate of the third device to the second trench insulation connector. The second BEOL structure can connect the first trench insulation connector and the second trench insulation connector. In some embodiments, the gate of the first device is a first gate of the first device, and the gate of the third device is a first gate of the third device. The first BEOL structure can connect the first gate of the first device to a second gate of the first device. The first BEOL structure can connect the first gate of the third device to a second gate of the third device.

[0079] An exemplary method for forming a wafer-on-wafer stack comprises performing front-end-of-line processing on a first wafer and a second wafer. The first wafer has a first trench insulation structure embedded in a first substrate, and the second wafer has a second trench insulation structure embedded in a second substrate. The first trench insulation structure surrounds a first fixture of the first wafer, and the second trench insulation structure surrounds a second fixture of the second wafer. The method further comprises forming a first trench insulation connector in the first trench insulation structure and a second trench insulation connector in the second trench insulation structure. The first trench insulation connector is connected to the first fixture, and the second trench insulation connector is connected to the second fixture.The method further comprises attaching the first wafer to the second wafer. The second trench insulation connector is connected to the first and second devices. In some embodiments, the first device is a first high-voltage transistor, and the second device is a second high-voltage transistor. In some embodiments, the method comprises performing a thinning process on the second wafer. In some embodiments, the method comprises directly attaching the first wafer to the second wafer.

[0080] In some embodiments, the method includes singulating the first wafer and the second wafer. In some embodiments, the first wafer and the second wafer are singulated before forming the first trench insulation connector and the second trench insulation connector, respectively. In some embodiments, the first wafer and the second wafer are singulated after forming the first trench insulation connector and the second trench insulation connector, respectively. In some embodiments, the first wafer and the second wafer are singulated after the first wafer has been attached to the second wafer, such that a singulation process is performed on a stacked wafer structure. In some embodiments, the first wafer and the second wafer are singulated before the first wafer has been attached to the second wafer, such that the first wafer and the second wafer form individual devices, chips, etc.are items that are subsequently attached to each other and / or electrically connected.

[0081] An exemplary wafer-on-wafer stack comprises a first wafer attached to a second wafer. The first wafer has a first back-end-of-line (BEOL) structure arranged over a first fixture layer, the second wafer has a second BEOL structure arranged over a second fixture layer, a first fixture is formed from the first fixture layer and the first BEOL structure, and a second fixture is formed from the second fixture layer and the second BEOL structure. The wafer-on-wafer stack further comprises a trench insulation connector that joins the first fixture of the first wafer to the second wafer.The trench isolation connector is a section of the first device layer of the first wafer, the trench isolation connector has a conductive via arranged in an isolation structure, and the trench isolation connector is a backside interconnect connection of the first wafer.

[0082] In some embodiments, the insulation structure is a deep trench insulation structure located in a substrate of the first device layer. In some embodiments, the trench insulation connector links the first device of the first wafer to the second device of the second wafer. In some embodiments, the wafer-on-wafer stack includes a bonding wafer that attaches the first and second wafers, and the trench insulation connector is connected to the bonding wafer. In some embodiments, the first and second devices are high-voltage transistors.

[0083] In some embodiments, the trench isolation connector is a first trench isolation connector, the backside interconnect is a first backside interconnect, and the conductive via is a first conductive via. In such embodiments, the wafer-on-wafer stack may further include a third device formed from the first device layer and the first BEOL structure, and a second trench isolation connector that connects the third device of the first wafer to the second wafer. The second trench isolation connector is a section of the first device layer of the first wafer, the second trench isolation connector has a second conductive via arranged in the isolation structure, and the second trench isolation connector is a second backside interconnect of the first wafer.The first BEOL structure can connect a first gate of the first device to the first trench insulation connector and a first gate of the third device to the second trench insulation connector. The second BEOL structure can connect the first trench insulation connector and the second trench insulation connector. In some embodiments, the first BEOL structure can connect the first gate of the first device to a second gate of the first device, and the first BEOL structure can connect the first gate of the third device to a second gate of the third device.

Claims

[1] Stacked device arrangement comprising: a first device substrate (12) comprising a first device (10); a second device substrate (212) having a first surface (212A) opposite a second surface (212B), wherein the second device substrate (212) has a second device (200) on the first surface (212A) of the second device substrate (212), an insulation structure (220) arranged in the second device substrate (212) and surrounding the second device (200), the insulation structure (220) extending from the first surface (212A) of the second device substrate (212) through the second device substrate (212) to the second surface (212B) of the second device substrate (212); and a conductive connector (286) arranged in the insulation structure (220), wherein the conductive connector (286) is connected to the second device (200), the conductive connector (286) is connected to the first device (10), and the conductive connector (286) extends from the first surface (212A) of the second device substrate (212) to the second surface (212B) of the second device substrate (212). [2] Stacked device arrangement according to claim 1, wherein the first device (10) is a first high-voltage device and the second device (200) is a second high-voltage device. [3] Stacked device arrangement according to one of the preceding claims, further comprising: a first chip (10) comprising the first device substrate (12), wherein the first chip (10) further comprises a first multilayer interconnect connection arranged over the first device substrate (12), the first multilayer interconnect connection being connected to the first device (10); and a second chip (200) comprising the second device substrate (212), wherein the second chip (200) further comprises a second multilayer interconnect connection arranged over the second device substrate (212), the second multilayer interconnect connection being connected to the second device (200). [4] Stacked device arrangement according to claim 3, wherein: the first multilayer interconnect provides a front side of the first chip (10) and the first device substrate (12) provides a back side of the first chip (10); the second multilayer interconnect provides a front side of the second chip (200) and the second surface (212B) of the second device substrate (212) provides a back side of the second chip (200); and the back of the second chip (200) is attached to the front of the first chip (10) and the conductive connector (286) is connected to the first multilayer interconnect connection and the second multilayer interconnect connection. [5] Stacked device arrangement according to claim 3, wherein: the first multilayer interconnect provides a front side of the first chip (10) and the first device substrate (12) provides a back side of the first chip (10); the second multilayer interconnect provides a front side of the second chip (200) and the second surface (212B) of the second device substrate (212) provides a back side of the second chip (200); and the back of the second chip (200) is attached to the front of the first chip (10) via a bonding layer (410), an interconnect structure of the bonding layer (410) is connected to the conductive connector (286) and the first multilayer interconnect connection, and the conductive connector (286) is connected to the second multilayer interconnect connection. [6] Stacked device arrangement according to claim 3, 4 or 5, wherein the insulation structure (220) is a first insulation structure and the conductive connector (286) is a first conductive connector, wherein the stacked device arrangement further comprises: a second insulation structure (20) arranged in the first device substrate (12), wherein the second insulation structure (20) surrounds the first device (10) and the second insulation structure (20) extends from a first surface (12A) of the first device substrate (12) through the first device substrate (12) to a second surface (12B) of the first device substrate (12); and a second conductive connector (286) arranged in the second insulation structure (20), wherein the second conductive connector (286) is connected to the first device (10), the second conductive connector (286) is connected to the second device (200), and the second conductive connector (286) extends from the first surface (12A) of the first device substrate (12) to the second surface (12B) of the first device substrate (12). [7] Stacked device arrangement according to claim 6, wherein: the first multilayer interconnect provides a front side of the first chip (10) and the second surface (12B) of the first device substrate (12) provides a back side of the first chip (10); the second multilayer interconnect provides a front side of the second chip (200) and the second area (12B) of the second device substrate (212B) provides a back side of the second chip (200); and the back of the second chip (200) is attached to the back of the first chip (10) and the first conductive connector (286) is connected to the second conductive connector (86). [8] Stacked device arrangement according to claim 6, wherein: the first multilayer interconnect provides a front side of the first chip (10) and the second surface (12B) of the first device substrate (12) provides a back side of the first chip (10); the second multilayer interconnect provides a front side of the second chip (200) and the second surface (212B) of the second device substrate (212) provides a back side of the second chip (200); and the back of the second chip (200) is attached to the back of the first chip (10) via a bonding layer (410) and an interconnect structure of the bonding layer (410) is connected to the first conductive connector (286) and the second conductive connector (86). [9] Device stack comprising: a first device (10) above a second device (200), wherein the first device (10) is formed by a first back-end-of-line structure above a first device layer and the second device (200) is formed by a second back-end-of-line structure above a second device layer; and a trench insulation connector (85, 285) connecting the first device (10) to the second device (200), wherein the trench insulation connector (85, 285) is a section of the first device layer, the trench insulation connector (85, 285) comprises a conductive via (86, 286) arranged in an insulation structure (20, 220), and the trench insulation connector (85, 285) is a rear interconnect connection of the first device (10), wherein the insulation structure (20, 220) extends completely through a substrate of the first device layer and the conductive via (86, 286) extends completely through the insulation structure (20, 220). [10] Device stack according to claim 9, wherein the insulation structure (20, 220) is a trench insulation structure arranged in a substrate of the first device layer. [11] Stack of devices according to claim 9 or 10, wherein the trench insulation connector (85, 285) connects a front face of the first device (10) to a front face of the second device (200). [12] Device stack according to any one of claims 9 to 11, wherein the trench insulation connector (85, 285) is a first trench insulation connector, the rear interconnect connection is a first rear interconnect connection and the conductive via (86, 286) is a first conductive via, wherein the device stack further comprises: a third device (600) formed by the first device layer and the first back-end-of-line structure; a second trench insulation connector (685) connecting the third device (600) to the second device (200), wherein the second trench insulation connector (685) is a section of the first device layer, the second trench insulation connector (685) has a second conductive via (686) arranged in the insulation structure (20), and the second trench insulation connector (685) is a second rear interconnect connection of the third device (600); wherein the first back-end-of-line structure (BEOL) connects a gate of the first device (10) to the first trench insulation connector (85, 285) and a gate of the third device (600) to the second trench insulation connector (685); and wherein the second back-end-of-line structure connects the first trench insulation connector (85, 285) and the second trench insulation connector (685). [13] Device stack according to claim 12, wherein the gate of the first device (10) is a first gate of the first device (10) and the gate of the third device (600) is a first gate of the third device (600), the first back-end-of-line structure connects the first gate of the first device (10) to a second gate of the first device (10), and the first back-end-of-line structure connects the first gate of the third device (600) to a second gate of the third device (600). [14] Device stack according to any one of claims 9 to 13, further comprising a bonding layer (410) which attaches the first device layer and the second back-end-of-line structure, wherein the trench insulation connector (85, 285) is connected to the bonding layer (410). [15] Stack of devices according to any one of claims 9 to 14, wherein the first device (10) is a first high-voltage transistor and the second device (200) is a second high-voltage transistor. [16] Method for forming a wafer-on-wafer stack comprising: Performing a front-end-of-line processing on a first wafer (10) and a second wafer (200), wherein the first wafer (10) has a first trench insulation structure (85) arranged in a first substrate (12), the second wafer has a second trench insulation structure (285) arranged in a second substrate (212), the first trench insulation structure (85) surrounds a first device of the first wafer (10), and the second trench insulation structure (285) surrounds a second device of the second wafer (200); Forming a first trench insulation connector (86) in the first trench insulation structure (85) and a second trench insulation connector (286) in the second trench insulation structure (285), wherein the first trench insulation connector (86) is connected to the first device (10) and the second trench insulation connector (286) is connected to the second device (200); and Attaching the first wafer (10) to the second wafer (200), wherein the second trench insulation connector (286) is connected to the first device (10) and the second device (200). [17] Method for forming the wafer-on-wafer stack according to claim 15, wherein the first device (10) is a first high-voltage transistor and the second device (200) is a second high-voltage transistor. [18] Method for forming the wafer-on-wafer stack according to claim 16 or 17, further comprising carrying out a thinning process on the second wafer (200). [19] Method for forming the wafer-on-wafer stack according to any one of claims 16 to 18, further comprising the direct attachment of the first wafer (10) to the second wafer (200). [20] Method for forming the wafer-on-wafer stack according to any one of claims 16 to 18, further comprising forming a bonding layer (410) and attaching the first wafer (10) to the second wafer (200) via the bonding layer (410), wherein the second trench insulation connector (286) is connected to the bonding layer (410).

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