VOLUMELESS FLUORINE INSTALLATION METHOD

Abstract

Method comprising: Removing a dummy gate stack (30) to form a trench (58) between gate spacers (38); depositing a gate dielectric (62) extending into the trench (58); Performing a first treatment process (302) on the gate dielectric (62), wherein the first treatment process (302) is performed using a fluorine-containing gas; after performing the first treatment process (302), performing a first penetration process (304) to allow fluorine from the fluorine-containing gas to penetrate into the gate dielectric (62); after performing a first penetration process (304), performing a second treatment process (302) on the gate dielectric (62), wherein the second treatment process (302) is performed using the fluorine-containing gas; after performing the second treatment process (302), performing a second penetration process (304) to allow fluorine from the fluorine-containing gas to penetrate into the gate dielectric (62); after the second penetration process (304), forming conductive layers (78) to fill the trench (58); after the first penetration process (304), completely removing a first fluorine-containing layer (66) formed as a result of the first treatment process (302); and after the second penetration process (304), completely removing a second fluorine-containing layer (66) which is formed as a result of the second treatment process (302).

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given chip area. However, as the minimum feature sizes are reduced, additional challenges and requirements arise that must be addressed.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2021 / 0 287 905 A1 and US 2020 / 0 411 667 A1.

[0004] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with normal industry practice, various elements are not drawn to scale. Indeed, the dimensions of various elements may be arbitrarily exaggerated or reduced for the sake of clarity of illustration. Fig. 1 to 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 13A, 13B, 14 to 18, 19A, 19B, 20A, 20B, 21A, 21B, 21C, 21D and 21E illustrate the intermediate stages in the formation of a gate all-around (GAA) transistor according to some embodiments. Fig. 22 to 25 illustrate some fluorine incorporation processes according to some embodiments. Fig. 26 to 27 illustrate the distribution of atomic percent of fluorine according to some embodiments. Fig. 28 illustrates a process flow for forming a GAA transistor according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or reference symbols among the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, relative spatial terms such as "underlying," "beneath," "lower," "overlying," "higher," and the like may be used herein for convenience of description to describe a relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. These relative spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial descriptors used herein may be interpreted accordingly.

[0008] Methods for incorporating fluorine into a gate dielectric in a transistor are provided. According to some embodiments, nanostructures are formed. A plurality of gate dielectrics comprising a plurality of high-k dielectric layers are formed on the nanostructures. A fluorine incorporation process is performed to incorporate fluorine into the high-k dielectric layers so that the high-k dielectric layers can be passivated and defects therein can be repaired. The fluorine incorporation process may include removal processes so that the fluorine incorporation process does not result in additional layers being formed in the spaces between the nanostructures. The subsequent filling of the spaces with conductive layers can thus be performed without difficulty.

[0009] In the description of the present disclosure, gate all-around (GAA) transistors are discussed to explain the concept of the present disclosure. Embodiments of the present disclosure may also be applied to other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), and the like. Embodiments discussed herein serve to provide examples to enable making or using the subject matter of this disclosure, and those of ordinary skill in the art will readily understand modifications that may be made while remaining within the contemplated scope of various embodiments. Like reference numerals are used to refer to like elements throughout the various views and example embodiments.Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0010] Fig. 1 to 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 13A, 13B, 14 to 18, 19A, 19B, 20A, 20B, 21A, 21B, 21C, 21D, and 21E illustrate various views of intermediate stages in the formation of a GAA transistor according to some embodiments of the present disclosure. The corresponding processes are also schematically depicted in the process flow 200, as shown in Fig. 28 shown.

[0011] With reference to Fig. 1, a perspective view of a wafer 10 is shown. The wafer 10 includes a multilayer structure comprising a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, or the like, while other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium on insulator, or the like. The substrate 20 may be doped as a p-type semiconductor, although in other embodiments, it may be doped as an n-type semiconductor.

[0012] According to some embodiments, a multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The respective process is designated as a process 202 in the Fig. 28. According to some embodiments, the multilayer stack 22 includes first layers 22A formed from a first semiconductor material and second layers 22B formed from a second semiconductor material different from the first semiconductor material.

[0013] According to some embodiments, the first semiconductor material of a first layer 22A is formed from or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the deposition of first layers 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), partial vacuum CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed to a first thickness in the range between approximately 30 Å and approximately 300 Å. However, any suitable thickness may be used within the scope of the embodiments.

[0014] Once the first layer 22A has been deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layers 22B are formed from or include a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B may be formed from silicon, or vice versa. It is recognized that any suitable combination of materials may be employed for the first layers 22A and the second layers 22B.

[0015] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition process similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a thickness different from the first layer 22A. According to some embodiments, the second layer 22B may be formed to a second thickness ranging between, for example, approximately 10 Å and approximately 500 Å.

[0016] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until a desired topmost layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have thicknesses that are the same or similar to each other, and the second layers 22B have thicknesses that are the same or similar to each other. The first layers 22A may also have the same thicknesses or different thicknesses as those of the second layers 22B. According to some embodiments, the first layers 22A are removed in subsequent processes and are alternatively referred to throughout the description as sacrificial layers 22A. According to alternative embodiments, the second layers 22B are sacrificial layers and are removed in subsequent processes.

[0017] According to some embodiments, there are some oxide underlayer(s) and hard mask layer(s) (not shown) formed over the multilayer stack 22. These layers are patterned and are used for the subsequent patterning of the multilayer stack 22.

[0018] With reference to Fig. 2, the multilayer stack 22 and a portion of the underlying substrate 20 are structured in an etching process(es) so that trenches 23 are formed. The respective process is described as a process 204 in the Fig. 28. Trenches 23 extend into the substrate 20. The remaining portions of multilayer stacks are hereinafter referred to as the multilayer stacks 22'. Underlying multilayer stacks 22', some portions of the substrate 20 are left behind and are hereinafter referred to as substrate strips 20'. The multilayer stacks 22' include semiconductor layers 22A and 22B. The semiconductor layers 22A are hereinafter referred to as sacrificial layers, and the semiconductor layers 22B are hereinafter referred to as nanostructures. The portions of multilayer stacks 22' and the underlying substrate strips 20' are collectively referred to as semiconductor strips 24.

[0019] In the embodiments illustrated above, the GAA transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, which enable structures to be created having, for example, pitches smaller than what might otherwise be obtained using a single, immediate photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0020] Fig. Figure 3 illustrates the formation of isolation regions 26, which are also referred to throughout the description as shallow isolation trench regions (STI regions). The respective process is described as a process 206 in the Fig. 28. The STI regions 26 may include a cap oxide (not shown), which may be a thermal oxide formed by the thermal oxidation of a surface layer of the substrate 20. The cap oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like. The STI regions 26 may also include a dielectric material over the cap oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, HDPCVD, or the like.A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, may then be performed to flatten the top surface of the dielectric material, and the remaining portions of the dielectric material are STI regions 26.

[0021] The STI regions 26 are then recessed so that the upper portions of semiconductor stripes 24 protrude higher than the upper surfaces 26T of the remaining portions of STI regions 26 to form protruding fins 28. The protruding fins 28 comprise multilayer stacks 22' and the upper portions of substrate stripes 20'. The recessing of STI regions 26 may be performed by a dry etching process, using, for example, NF3 and NH3 as the etching gases. Plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of STI regions 26 is performed by a wet etching process. The etching chemical may include, for example, HF.

[0022] With reference to Fig. 4, dummy gate stacks 30 and gate spacers 38 are formed on the top surfaces and sidewalls of the (protruding) fins 28. The respective process is described as a process 208 in the Fig. 28. The dummy gate stacks 30 may include dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate dielectrics 32 may be formed by oxidizing the surface portions of protruding fins 28 to form oxide layers or by depositing a dielectric layer, such as a silicon oxide layer. The dummy gate electrodes 34 may be formed using, for example, polysilicon or amorphous silicon, and other materials, such as amorphous carbon, may also be used.

[0023] Each of the dummy gate stacks 30 may also include one or more hard mask layers 36 over the dummy gate electrode 34. The hard mask layers 36 may be formed from silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multilayers thereof. The dummy gate stacks 30 may traverse a single or multiple protruding fins 28 and the STI regions 26 between protruding fins 28. The dummy gate stacks 30 also have longitudinal directions perpendicular to the longitudinal directions of the protruding fins 28. The formation of the dummy gate stacks 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers by a patterning process(es).

[0024] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stacks 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed from a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure comprising multiple dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers and then performing an anisotropic etch process(es) on the dielectric layer(s). The remaining portions of the dielectric layer(s) are the gate spacers 38.

[0025] Fig. 5A and Fig. 5B illustrate the cross-sectional views of the Fig. 4 shown structure. Fig. Figure 5A illustrates the reference cross section A1-A1 in Fig. 4, whose cross-section cuts through the portions of the protruding fins 28 not covered by the gate stacks 30 and the gate spacers 38, and which is perpendicular to the gate longitudinal direction. Also illustrated are the gate spacers 38 located on the sidewalls of the protruding fins 28. Fig. Figure 5B illustrates the reference cross section BB in Fig. 4, wherein the reference cross-section is parallel to the longitudinal directions of the projecting fins 28.

[0026] With reference to Fig. 6A and Fig. 6B, the portions of the protruding fins 28 that are not directly below the dummy gate stacks 30 and the gate spacers 38 are recessed by an etching process to form the recesses 42. The respective process is described as a process 210 in the Fig. 28. For example, a dry etching process using the mixture of the mixture of or the like may be performed to etch the multilayer semiconductor stacks 22' and the underlying substrate strips 20'. The bottoms of the recesses 42 are at least level with, or possibly deeper than (as in Fig. 6B), the bottoms of the multilayer semiconductor stacks 22'. The etching may be anisotropic, so that the sidewalls of the multilayer semiconductor stacks 22', which face the recesses 42, are vertical and straight, as shown in Fig. 6B shown.

[0027] With reference to Fig. 7A and Fig. 7B, sacrificial semiconductor layers 22A are laterally recessed to form lateral recesses 41, which are recessed from the edges of the respective overlying and underlying nanostructures 22B. The respective process is described as a process 212 in the Fig. 28. The lateral deepening of sacrificial semiconductor layers 22A may be achieved by a wet etching process using an etchant that is more selective for the material (e.g., silicon germanium (SiGe)) of the sacrificial semiconductor layers 22A than for the material (e.g., silicon (Si)) of the nanostructures 22B and the substrate 20. For example, in an embodiment in which sacrificial semiconductor layers 22A are formed from silicon germanium and the nanostructures 22B are formed from silicon, the wet etching process may be performed using an etchant, such as hydrochloric acid (HCl).The wet etching process may be performed using a dipping process, a spraying process, or the like, and may be performed using any suitable process temperature (e.g., between approximately 400°C and approximately 600°C) and a suitable process duration (e.g., between approximately 100 seconds and approximately 1,000 seconds). According to alternative embodiments, the lateral deepening of the sacrificial semiconductor layers 22A is performed by an isotropic dry etching process or by a combination of a dry etching process and a wet etching process.

[0028] Fig. 8A and Fig. 8B illustrate the formation of inner spacers 44. The respective process is described as a process 214 in the Fig. 28. The formation process includes depositing a spacer layer extending into the recesses 41 and performing an etching process to remove the portions of an inner spacer layer outside the recesses 41, thus leaving inner spacers 44 in the recesses 41. The inner spacers 44 may be formed of or include SiOCN, SiON, SiOC, SiCN, or the like. The inner spacers 44 may also be porous, such that they have a lower k-value, which is lower than, for example, approximately 3.5. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process, in which the etching chemical may include H2SO4, dilute HF, ammonia solution (NH4OH, ammonia in water), or the like, or combinations thereof.

[0029] With reference to Fig. 9A and Fig. 9B, epitaxial source / drain regions 48 are formed in the recesses 42. The respective process is described as a process 216 in the Fig. 28. According to some embodiments, the source / drain regions 48 may exert stresses on the nanostructures 22B used as the channels of the corresponding GAA transistors, thereby improving performance. According to some embodiments, the corresponding transistor is n-type, and the epitaxial source / drain regions 48 are accordingly formed as n-type by doping an n-type dopant. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown to form the epitaxial source / drain regions 48. After the recesses 42 are filled with epitaxial regions 48, further epitaxial growth of the epitaxial regions 48 causes the epitaxial regions 48 to expand horizontally, and facets may be formed.The further growth of epitaxial regions 48 may also cause adjacent epitaxial regions 48 to merge with one another.

[0030] After the epitaxial process, the epitaxial regions 48 may be further implanted with an n-type impurity to form source and drain regions, which are also designated using reference numeral 48. According to alternative embodiments of the present disclosure, the implantation process is skipped if the epitaxial regions 48 are doped with the n-type impurity in-situ during epitaxy, and the epitaxial regions 48 are also source / drain regions.

[0031] Fig. 10A, Fig. 10B and Fig. 10C illustrate the cross-sectional views of the structure after the formation of a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. Fig. 10A, Fig. 10B and Fig. 10C are made of the same cross-section as the cross-sections A2-A2, BB, and A1-A1 in Fig. 4. The respective process is a process 218 in the Fig. 28. The CESL 50 may be formed from silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. The ILD 52 may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or any other suitable deposition method. The ILD 52 may be formed from an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0032] In subsequent processes, replacement gate stacks are formed to replace the dummy gate stacks 30. Referring to Fig. 11A and Fig. 11B, a planarization process, such as a CMP process or a mechanical grinding process, is performed to level the upper surface of the ILD 52. The respective process is designated as a process 220 in the Fig. 28. According to some embodiments, the planarization process may remove hard masks 36 to expose dummy gate electrodes 34, as shown in Fig. 11B. According to alternative embodiments, the planarization process may expose and stop hard masks 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrodes 34 (or hard masks 36), the gate spacer 38, and the ILD 52 are level with each other within the process variations.

[0033] Next, the dummy gate electrodes 34 (and the hard masks 36, if they remain) are removed in one or more etching processes so that the recesses 58 are formed, as shown in Fig. 12A and Fig. 12B. The respective process is shown as a process 222 in the Fig. 28. The portions of the dummy gate dielectrics 32 in the recesses 58 are also removed. According to some embodiments, the dummy gate electrodes 34 and the dummy gate dielectrics 32 are removed by dry etching processes. For example, the etching process may be performed using reactant gas(es) that selectively etches the dummy gate electrodes 34 at a faster rate than the ILD 52. Each recess 58 exposes and / or overlies portions of multilayer stacks 22' that comprise the future channel regions in subsequently completed nano-FETs. The corresponding portions of the multilayer stacks 22' are between adjacent pairs of the epitaxial source / drain regions 48.

[0034] Then, the sacrificial layers 22A are removed to widen the recesses 58 between the nanostructures 22B, and the resulting structure is in Fig. 13A and Fig. 13B. The respective process is shown as a process 224 in the Fig. 28. The sacrificial layers 22A may be removed by performing an isotropic etching process, such as a wet etching process using etchants that are selective for the materials of the sacrificial layers 22A. The nanostructures 22B, the substrate 20, the STI regions 26 remain relatively unetched compared to the sacrificial layers 22A. According to some embodiments, in which the sacrificial layers 22A contain, for example, SiGe, and the nanostructures 22B contain, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the sacrificial layers 22A. It is recognized that, although Fig. 13A and subsequent figures illustrate the cross-sections of nanostructures 22B as rectangular, the nanostructures 22B may have rounded corners, as indicated by dashed lines in Fig. 13A illustrated.

[0035] With reference to Fig. 14, gate dielectrics 62 are formed. The respective process is described as a process 226 in the Fig. 28. According to some embodiments, each of the gate dielectrics 62 includes an interface layer 62A and a high-k dielectric layer 62B on the interface layer 62A. The interface layer 62A may be formed from or include silicon oxide, which may be deposited by a conformal deposition process, such as ALD or CVD. According to alternative embodiments, the interface layer 62A is formed by thermal oxidation. When formed by thermal oxidation, the portions of the interface layer 62A are not formed on the top surfaces of STI regions 26. According to some embodiments, the high-k dielectric layers 62B include one or more dielectric layers.For example, the high-k dielectric layer(s) 62B may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0036] Fig. 15 illustrates the formation of the exit layer 64. The respective process is described as a process 228 in the Fig. 28. The exit layer 64 may be an n-type exit layer if the resulting transistor is an n-type transistor, or it may be a p-type exit layer if the resulting transistor is a p-type transistor. According to some embodiments, the exit layer 64 is an n-type exit layer and may be formed from or include TiAlC, TiAl, TiAlN, TaAl, TaAlN, TaAlC, or the like. Alternatively, the exit layer 64 is a p-type exit layer and may be formed from or include TiN, TaN, TiSiN, WCN, MOCN, or combinations thereof. According to some embodiments, a cap layer (not shown), such as a TiN layer or a TiSiN layer, is formed between (and in contact with both) the exit layer 64 and the gate dielectric 62.According to alternative embodiments, the exit layer 64 is in physical contact with the gate dielectric 62, without a cap layer therebetween. Formation of the exit layer 64 may comprise atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.

[0037] According to some embodiments, as in Fig. 15, the exit layer 64 is formed before the subsequent fluorine incorporation process 68, as shown in Fig. 16. The corresponding fluorine incorporation process 68 is also described in subsequent paragraphs with reference to Fig. 22 and Fig. 24. According to alternative embodiments, the exit layer 64 is formed after the subsequent fluorine incorporation process 68, as shown in Fig. 16. The corresponding fluorine incorporation process 68 is described in subsequent paragraphs with reference to Fig. 23 and Fig. 25. The exit layer 64 is in Fig. 15 is thus illustrated in a broken manner to indicate that it may or may not be formed at this time and at the time at which the fluorine incorporation process 68 is carried out.

[0038] With reference to Fig. 16, a fluorine incorporation process 68 is carried out. The respective process is known as a process 230 in the Fig. 28. The fluorine incorporation process 68 is used to incorporate fluorine into the high-k dielectric layer 62B so that the high-k dielectric layer 62B is passivated and the defects in the high-k dielectric layer 62B are repaired. The fluorine-containing layer 66 may be formed as a result of the fluorine incorporation process 68, according to some embodiments.

[0039] Fig. 22 through 24 illustrate the details of some exemplary fluorine incorporation processes 68 according to various embodiments. The portions of the Fig. 22 to 24 may correspond to the area 70 as shown in Fig. 16 shown.

[0040] Fig. 22 illustrates an exemplary fluorine incorporation process 68 performed after the formation of the exit layer 64. Accordingly, the exit layer 64 is a surface layer, with the gate dielectric 62 (including the high-k dielectric layer 62B and the interface layer 62A) and the nanostructure 22B underlying the exit layer 64. The fluorine incorporation process 68 may include the treatment process 302, which is performed using a fluorine-containing gas including tungsten fluoride (WF6).According to some embodiments, the treatment process 302 is performed in a vacuum chamber and is performed using a pure fluorine-containing gas, with no other added gas, or using a substantially pure fluorine-containing gas, where, for example, the atomic percent of the fluorine-containing gas among all gases is greater than approximately 90 percent, 95 percent, or 99 percent, in the vacuum chamber. According to alternative embodiments, a carrier gas is added to the fluorine-containing gas. The carrier gas may include N2, Ar, He, or the like, or combinations thereof. The treatment process 302 may also be performed in a furnace, which may or may not be evacuated.

[0041] According to some embodiments, the treatment process 302 includes a thermal treatment process performed at an elevated wafer temperature, which may be in the range between approximately 250°C and approximately 600°C. According to alternative embodiments, the treatment process 302 includes a plasma treatment performed in the vacuum chamber. The pressure in the vacuum chamber may be in the range between approximately 0.5 Torr and approximately 50 Torr. The treatment process 302 may last for a period of time in the range between approximately 1 second and approximately 600 seconds. According to further alternative embodiments, the treatment process 302 includes both the thermal treatment process and the plasma treatment process, as discussed above.

[0042] As a result of the treatment process 302, the fluorine-containing gas may be adsorbed onto the surfaces of the exit layer 64, which may (or may not) lead to the deposition of a fluorine-containing layer 66. The fluorine-containing layer 66 also contains tungsten when WF6 is used. Other gases, such as SiH4, B2H6, H2, or the like, or combinations thereof, may also be added to the process gas used in the treatment process 302 to assist in the deposition of the fluorine-containing layer 66. The resulting fluorine-containing layer 66 may be a continuous layer with 100 percent coverage of the underlying layer. Alternatively, the fluorine-containing layer 66 may have less than 100 percent coverage of the underlying layer, with some portions of the underlying layer exposed by the fluorine-containing layer 66, as shown in Fig. 22 is schematically illustrated.

[0043] Further with reference to Fig. 22, a fluorine penetration process 304 is performed. The fluorine penetration process 304 may be performed in-situ in the same environment (such as the vacuum chamber or furnace) in which the treatment process 302 is performed. Alternatively, the fluorine penetration process 304 may be performed ex-situ in an environment different from the environment in which the treatment process 302 is performed. For example, the fluorine penetration process 304 may be performed in a different vacuum chamber or furnace. The fluorine penetration process 304 may be performed at an elevated wafer temperature, which may be equal to or higher than the wafer temperature of the treatment process 302. For example, the wafer temperature in the fluorine penetration process 304 may be in the range between approximately 400°C and approximately 650°C.During the fluorine penetration process 304, gases such as N2, Ar, He, Ne, or the like may be introduced to prevent the exit layer 604 from being oxidized.

[0044] The fluorine-containing gas used in treatment process 302 may be stopped during fluorine penetration process 304. Alternatively, the fluorine-containing gas is also introduced, but at a lower flow rate than the flow rate of the fluorine-containing gas during treatment. In penetration process 304, the pressure of the vacuum chamber (if used) may be in the range between approximately 0.5 Torr and approximately 760 Torr (one atmosphere). The fluorine penetration process 304 may last for a period of time ranging between approximately 1 second and approximately 600 seconds.

[0045] According to alternative embodiments, no fluorine penetration process is performed. Because the treatment process 302 includes a thermal treatment process and / or a plasma treatment process, fluorine may still diffuse into the exit layer 64 and the gate dielectric layer 62 during the treatment process 302.

[0046] In the fluorine penetration process 304, fluorine and tungsten penetrate (diffused) into the exit layer 64, the gate dielectric 62, and possibly the nanostructures 22B. Tungsten is heavier and therefore has a lower diffusion rate than fluorine. Accordingly, the fluorine-containing layer 66 has some remaining undiffused portions after the fluorine penetration process 304. Consequently, a residue removal process 306 is performed to remove the residue of the fluorine-containing layer 66. During the residue removal process 306, the fluorine-containing process gases (such as WF6) used in the treatment process 302 are stopped. According to some embodiments, the residue removal process 306 may be performed using an etching gas containing nitrogen fluoride (NF3).According to some embodiments, the residue removal process 306 is performed in a vacuum chamber, and it is performed using a pure or substantially pure etching gas, without any other added gas. For example, the atomic percent of the etching gas (such as NF3) may be greater than approximately 90 percent, 95 percent, or 99 percent of all gases in the vacuum chamber. According to alternative embodiments, a carrier gas is added to the etching gas, such as NF3. The carrier gas may include N2, Ar, He, or the like.

[0047] According to some embodiments, the residue removal process 306 includes a thermal etching process performed at an elevated wafer temperature, which may be in the range between approximately 250°C and approximately 600°C. According to some embodiments, the residue removal process 306 includes a plasma etching process performed in the vacuum chamber. The pressure of the vacuum chamber may be in the range between approximately 0.5 Torr and approximately 50 Torr. As a result of the etching process, the remaining fluorine-containing layer 66 may be completely removed, or it may be partially removed, leaving a smaller residue portion.

[0048] The treatment process 302, the fluorine penetration process 304, and the residue removal process 306 are collectively referred to as a fluorine incorporation cycle 310. According to some embodiments, after the fluorine incorporation cycle 310, the process continues back to process 302, and one or more fluorine incorporation cycles 310 are performed. The total number of fluorine incorporation cycles 310 may be 2, 3, 4, 5, or more.

[0049] Incorporation of fluorine through the fluorine incorporation cycles 310, in which the fluorine-containing layer 66 is removed in each cycle, has several advantageous features. The spaces between adjacent nanostructures 22B have small distances S1 ( Fig. 15), especially after the formation of the gate dielectric layers 62 and the exit layers 64. To diffuse enough fluorine into the gate dielectric layer, the fluorine-containing layer 66 may be thick. However, the thick fluorine-containing layer 66 may block the gaps, and the fluorine-containing layer 66 deposited on an overlying nanostructure 22B may be merged with the fluorine-containing layer 66 deposited on an underlying nanostructure 22B. The merger may prevent subsequent layers from being deposited in the gaps, causing performance degradation and reliability degradation.

[0050] By performing a residue removal process 306 in each of the fluorine incorporation cycles 310, the interstices are cleared before merging occurs. Furthermore, the fluorine penetration process 304 can cause the fluorine concentration in the fluorine-containing residue layer 66 to be lower. By removing the fluorine-containing layer 66 and forming a new fluorine-containing layer 66, fluorine is replenished, and more fluorine can diffuse into the high-k dielectric layer 62, thus improving the efficiency of the defect repair process.

[0051] Further with reference to Fig. 22, after the fluorine incorporation cycles 310, a cleaning process 308 is performed. The cleaning process 308 may remove the tungsten on the exit layer 64 if the tungsten is not completely removed in the preceding residue removal processes 306. The cleaning process 308 may include a wet etching process or a dry etching process. According to some embodiments, the cleaning process 308 is performed using an etching chemistry including an oxidant-containing solution, which may include deionized water and an oxidant. For example, the etching chemistry may include H2O2, DiO3, the mixture of NH4OH, H2O2, and H2O, the mixture of NH4OH and O3, the mixture of HCl and H2O2, the mixture of HCl and O3, or the like. The concentration of the oxidant in the oxidant-containing solution may range between approximately 20 percent and approximately 50 percent.The cleaning process 308 may be performed at a temperature in the range between about 18°C ​​and about 80°C.

[0052] Fig. Figure 23 illustrates the fluorine incorporation process 68 according to alternative embodiments. Fig. 23 are essentially the same as those shown in Fig. 22 shown, except that in Fig. 23, the fluorine incorporation process 68 is performed on the gate dielectric layer 62 and is performed before the formation of the exit layer 64. The details of the fluorine incorporation process 68 are not repeated here.

[0053] Fig. Figure 24 illustrates the fluorine incorporation process 68 according to alternative embodiments. Fig. 24 processes are essentially the same as those in Fig. 22, except that instead of using WF6 to perform the treatment process 302, NF3 is used in the treatment process 302. Furthermore, the fluorine-containing residue layer 66 (which contains the adsorbed NF3) is thin. After the penetration process 304, the residue is even thinner. Therefore, no residue removal process is performed.

[0054] As in Fig. 24, the treatment process 302 is performed. The treatment process 302 is essentially the same as the treatment process 302 described with reference to Fig. 22, except that NF3 replaces WF6 as the fluorine-containing gas. After the treatment process 302, the flow of the fluorine-containing gas, such as NF3, is stopped, or the flow rate is reduced, and the penetration process 304 is performed. The details of the penetration process 304 can be found by referring to the penetration process 304 in Fig. 22. The penetration process 304 can also be performed at a higher (or the same) wafer temperature as the treatment process 302. The treatment process 302 and the penetration process 304 are collectively referred to as the fluorine incorporation cycle 310. The fluorine incorporation cycles 310 are repeated.

[0055] Fig. Figure 25 illustrates the fluorine incorporation process 68 according to further alternative embodiments. The processes as shown in Fig. 25 are essentially the same as those shown in Fig. 24, except that in the Fig. 25, the fluorine incorporation process 68 is performed on the gate dielectric layer 62 and is performed before the formation of the exit layer 64. The details of the fluorine incorporation process 68 can be reviewed by reference to the previous description and are not repeated here.

[0056] Fig. Figure 17 illustrates the structure after the fluorine incorporation process 68 as described with reference to Fig. 22 to 25. The exit layer 64 may already be formed in the previous processes, or it may not be formed. Once the exit layer 64 has been formed, the process continues with what is described in Fig. 18. Otherwise, if the exit layer 64 has not been formed, the exit layer 64 may be formed after the fluorine incorporation process 68 and before the Fig. 18. The respective process is defined as a process 232 in the Fig. 28 illustrates the process flow 200 shown.

[0057] With reference to Fig. 18, conductive layers 78 are formed over the exit layer 64. The respective process is described as a process 234 in the Fig. 28. The conductive layers 78 may or may not include a barrier layer, such as a TiN layer. The conductive layers 78 may further include a filler metal that fills the remaining recesses 58 if they are not yet completely filled. The conductive layers 78 may include a metal-containing material, such as cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof.

[0058] With reference to Fig. 19A and Fig. 19B, after filling the recesses 58, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove the excess portions of the gate dielectrics 62 and the material of the gate electrodes 80, the excess portions of which lie above the top surface of the ILD 52. The remaining portions of the conductive layers 78 form parts of the gate electrodes 80. The gate electrodes 80 and the gate dielectrics 62 are collectively referred to as the gate stacks 82.

[0059] Next, as in Fig. 20A and Fig. 20B, the gate stacks 82 are recessed so that recesses are formed immediately above the gate stacks 82 and between opposing portions of gate spacers 38. A gate mask 84 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into each of the recesses, followed by a planarization process to remove excess portions of the dielectric material extending over the ILD 52. The respective process is described as a process 236 in the Fig. 28 illustrates the process flow 200 shown.

[0060] How to continue through Fig. 20A and Fig. 20B, an ILD 86 is deposited over the ILD 52 and over the gate masks 84. The respective process is described as a process 238 in the Fig. 28. An etch stop layer (not shown) may or may not be deposited prior to the formation of the ILD 86. According to some embodiments, the ILD 86 is formed by FCVD, CVD, PECVD, or the like. The ILD 86 is formed from a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0061] In Fig. 21A and Fig. 21B, the ILD 86, the ILD 52, the CESL 50, and the gate masks 84 are etched to form recesses (populated by contact studs 88A and 88B) that expose surfaces of the epitaxial source / drain regions 48 and / or the gate stacks 82. The recesses may be formed by etching using an anisotropic etch process.

[0062] After the recesses are formed, silicide areas 90 ( Fig. 21B) over the epitaxial source / drain regions 48. The respective process is described as a process 240 in the Fig. 28. According to some embodiments, the silicide regions 90 are formed by first depositing a metal layer (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source / drain regions 48 (e.g., silicon, silicon-germanium, or germanium) to form silicide and / or germanide regions, then by performing a thermal annealing process to form the silicide regions 90. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, or the like. The unreacted portions of the deposited metal are then removed, for example, by an etching process.

[0063] Then, contact plugs 88B are formed over the silicide regions 90. Furthermore, contact plugs 88A (may also be referred to as gate plugs) are formed in the recesses and are above and contact the gate electrodes 80. The respective processes are described as a process 242 in the Fig. 28 illustrated process flow 200. Although Fig. While Figure 21B illustrates that contact studs 88A and 88B have the same cross-section, in various embodiments contact studs 88A and 88B can be formed with different cross-sections, thereby reducing the risk of short circuits between them. Consequently, a GAA transistor 92 is formed.

[0064] Fig. 21C illustrates a perspective view of the Fig. 14A and Fig. 24B, wherein the structure shown in Fig. 21A and Fig. 21B shown cross-sectional views from the cross sections 21A to 21A and 21B to 21B in Fig. 21C can be obtained. Fig. 24D and Fig. 24E illustrate the horizontal cross-sectional views of the Fig. 21A, Fig. 21B and Fig. 21C, wherein the horizontal cross-sectional views are taken from the horizontal planes 21D to 21D and 21E to 21E in Fig. 21B can be obtained.

[0065] Fig. Figure 26 illustrates the fluorine atomic percent in the gate stacks 82 according to some embodiments, where the x-axis represents the distance in the direction of the arrows 94 in Fig. 21B represents. Fig. 26 corresponds to the embodiments in which the exit layer 64 is formed before the fluorine incorporation process 68 is carried out. Since the fluorine-containing layer 66 ( Fig. 16, Fig. 22 and Fig. 24) is removed at a time before the conductive layers 78 are formed, the highest fluorine atomic percent may be at the outer surface of the exit layer 64. Due to the diffusion of fluorine into the conductive layers 78, in the final transistor 92, the highest fluorine atomic percent may be either in the exit layer 64, as shown by the dashed line 106, or at the boundary between the exit layer 64 and the conductive layers 78, as shown by the solid line 104. Furthermore, the fluorine atomic percent may be steeper in the conductive layers 78 than in the exit layer 64 and the gate dielectric 62.

[0066] Fig. Figure 27 illustrates the fluorine atomic percent in the gate stacks 82 according to some embodiments, wherein the x-axis also represents the distance in the direction of the arrows 94 in Fig. 21B represents. Fig. 27 corresponds to the embodiments in which the exit layer 64 is formed after the fluorine incorporation process 68. Since the fluorine-containing layer 66 ( Fig. 16, Fig. 22 and Fig. 24) is removed at a time before the conductive layers 78 are formed, the highest fluorine atomic percent may be at the outer surface of the gate dielectric 62. Due to diffusion, in the final transistor 92, the highest fluorine atomic percent may be in the gate dielectric 62, as shown by the dashed line 110, or it may be at the boundary between the gate dielectric 62 and the exit layer 64, as shown by the solid line 108. Furthermore, the fluorine atomic percent may be steeper in the exit layer 64 and the conductive layers 78 than in the gate dielectric 62.

[0067] As from Fig. 13B and Fig. 16, at the time the fluorine incorporation process 68 is performed, the ILD 52 and the gate spacers 38 have already been formed and therefore also have incorporated fluorine. The surfaces of the ILD 52 and the gate spacers 38 that receive fluorine have a higher fluorine concentration than the deeper sections. For example, in the direction of arrow 95 in Fig. 21B the fluorine concentration should be continuously reduced, similar to the profile of the left parts of the fluorine profile in Fig. 26 and Fig. 27.

[0068] The embodiments of the present disclosure have several advantageous features. By incorporating fluorine into gate dielectrics, the defects in the high-k dielectric layer are repaired. Cyclic fluorine incorporation processes, which involve the removal of fluorine-containing layers, repeatedly remove the fluorine-containing layers, and add new fluorine-containing layers with higher fluorine concentrations. Accordingly, fluorine incorporation into the gate dielectrics is more efficient.

[0069] According to some embodiments of the present disclosure, a method includes removing a dummy gate stack to form a trench between gate spacers; depositing a gate dielectric extending into the trench; performing a first treatment process on the gate dielectric, wherein the first treatment process is performed using a fluorine-containing gas; performing a first penetration process to penetrate fluorine from the fluorine-containing gas into the gate dielectric; performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas; performing a second penetration process to penetrate fluorine from the fluorine-containing gas into the gate dielectric; and after the second penetration process, forming conductive layers to fill the trench.

[0070] In one embodiment, the method further comprises, after the first penetration process, removing a first fluorine-containing layer formed due to the first treatment process; and after the second penetration process, removing a second fluorine-containing layer formed due to the second treatment process. In one embodiment, the method further comprises, after the second fluorine-containing layer is removed, performing a cleaning process to further remove residues of the first fluorine-containing layer and the second fluorine-containing layer. In one embodiment, the fluorine-containing gas contains tungsten fluoride, and the first fluorine-containing layer and the second fluorine-containing layer further contain tungsten therein.

[0071] In one embodiment, the fluorine-containing gas comprises nitrogen fluoride. In one embodiment, the method further comprises depositing an exit layer on the gate dielectric, wherein the first treatment process and the second treatment process are performed on the exit layer. In one embodiment, the method further comprises, after the first treatment process and the second treatment process, depositing an exit layer on the gate dielectric. In one embodiment, the first penetration process comprises an annealing process. In one embodiment, the method further comprises, after the second penetration process, performing a third treatment process on the gate dielectric, wherein the third treatment process is performed using the fluorine-containing gas; and performing a third penetration process to penetrate fluorine from the fluorine-containing gas into the gate dielectric.

[0072] According to some embodiments of the present disclosure, a method comprises forming a dummy gate stack on a top surface and on sidewalls of a multilayer stack, the multilayer stack comprising a plurality of sacrificial layers and a plurality of nanostructures arranged alternately; removing the dummy gate stack to form a recess in a dielectric layer; removing the plurality of sacrificial layers; depositing gate dielectrics encasing the plurality of nanostructures; depositing exit layers on the gate dielectrics; performing a plurality of cycles, each of the plurality of cycles comprising forming a plurality of fluorine-containing layers, each on one of the gate dielectrics; injecting fluorine into the plurality of fluorine-containing layers into the gate dielectrics; and removing the plurality of fluorine-containing layers;and after the plurality of cycles, forming a conductive layer, wherein the conductive layer includes portions in spaces between the plurality of nanostructures;

[0073] In one embodiment, forming the plurality of fluorine-containing layers comprises treating the gate dielectrics using WF6 as a process gas. In one embodiment, removing the plurality of fluorine-containing layers is performed using NF3 as an etch gas. In one embodiment, in each of the plurality of cycles, the plurality of fluorine-containing layers formed prior to penetration are completely removed.

[0074] In one embodiment, the penetration of fluorine comprises an annealing process. In one embodiment, the formation of the plurality of fluorine-containing layers is performed at a first wafer temperature and the penetration of fluorine is performed at a second wafer temperature that is higher than the first wafer temperature. In one embodiment, the removal of the plurality of fluorine-containing layers is performed by a dry etching process, and the method further comprises, after the plurality of cycles, performing a wet etching process to etch residues of the plurality of fluorine-containing layers. In one embodiment, the plurality of cycles are performed on the exit layers.

[0075] According to some embodiments of the present disclosure, a method comprises forming a nanostructure in a trench, wherein gate spacers are located on opposite sides of the trench; depositing a gate dielectric extending into the trench to enclose the nanostructure, wherein the gate dielectric comprises a high-k dielectric material; and, after the gate dielectric is deposited, performing a plurality of cycles, wherein each of the plurality of cycles comprises performing a treatment process on the gate dielectric using WF6 as a first process gas; and, after the treatment process, performing an etch process using NF3 as a second process gas. In one embodiment, the method further comprises a penetration process in each of the plurality of cycles, wherein the penetration process is performed after the treatment process and before the etch process.In one embodiment, the treatment process results in a tungsten and fluorine-containing layer remaining on the gate dielectric, and wherein the etching process results in the tungsten and fluorine-containing layer being etched.

Claims

[1] A method comprising: Removing a dummy gate stack (30) to form a trench (58) between gate spacers (38); depositing a gate dielectric (62) extending into the trench (58); Performing a first treatment process (302) on the gate dielectric (62), wherein the first treatment process (302) is performed using a fluorine-containing gas; after performing the first treatment process (302), performing a first penetration process (304) to allow fluorine from the fluorine-containing gas to penetrate into the gate dielectric (62); after performing a first penetration process (304), performing a second treatment process (302) on the gate dielectric (62), wherein the second treatment process (302) is performed using the fluorine-containing gas; after performing the second treatment process (302), performing a second penetration process (304) to allow fluorine from the fluorine-containing gas to penetrate into the gate dielectric (62); after the second penetration process (304), forming conductive layers (78) to fill the trench (58); after the first penetration process (304), completely removing a first fluorine-containing layer (66) formed as a result of the first treatment process (302); and after the second penetration process (304), completely removing a second fluorine-containing layer (66) which is formed as a result of the second treatment process (302). [2] The method of claim 1, further comprising, after the second fluorine-containing layer (66) is removed, performing a cleaning process to further remove residues of the first fluorine-containing layer (66) and the second fluorine-containing layer (66). [3] The method of claim 1 or 2, wherein the fluorine-containing gas contains tungsten fluoride and the first fluorine-containing layer (66) and the second fluorine-containing layer (66) further contain tungsten therein. [4] A process according to any one of the preceding claims, wherein the fluorine-containing gas contains nitrogen fluoride. [5] The method of any preceding claim, further comprising depositing a work function layer (64) on the gate dielectric (62), wherein the first treatment process (302) and the second treatment process (302) are performed on the work function layer (64). [6] The method of any preceding claim, further comprising, after the first treatment process (302) and the second treatment process (302), depositing a work function layer (64) on the gate dielectric (62). [7] The method of any preceding claim, wherein the first penetration process (304) comprises an annealing process. [8] A method according to any one of the preceding claims, further comprising: after the second penetration process (304), performing a third treatment process (302) on the gate dielectric (62), wherein the third treatment process (302) is performed using the fluorine-containing gas; and Performing a third penetration process (304) to allow fluorine from the fluorine-containing gas to penetrate into the gate dielectric (62). [9] A method comprising: Forming a dummy gate stack (30) on a top surface and on sidewalls of a multilayer stack (22'), the multilayer stack (22') comprising a plurality of sacrificial layers (22A) and a plurality of nanostructures (22B) arranged alternately; Removing the dummy gate stack (30) to form a recess (58) in a dielectric layer (38); removing the plurality of sacrificial layers (22A); depositing gate dielectrics (62) encasing the plurality of nanostructures (22B); Depositing work function layers (64) on the gate dielectrics (62); Performing a plurality of cycles (310), each of the plurality of cycles (310) comprising: forming (302) a plurality of fluorine-containing layers (66), each on one of the gate dielectrics (62); Penetration (304) of fluorine from the plurality of fluorine-containing layers (66) into the gate dielectrics (62); and Removing (306) the plurality of fluorine-containing layers (66); and after the plurality of cycles (310), forming a conductive layer (78), wherein the conductive layer (78) has sections in spaces between the plurality of nanostructures (22B), wherein in each of the plurality of cycles (310) the plurality of fluorine-containing layers (66) formed prior to the penetration (304) are completely removed. [10] The method of claim 9, wherein forming (302) the plurality of fluorine-containing layers (66) comprises treating the gate dielectrics (62) using WF6 as a process gas. [11] The method of claim 9 or 10, wherein the removal (306) of the plurality of fluorine-containing layers (66) is performed using NF3 as an etching gas. [12] The method of any one of the preceding claims 9 to 11, wherein the penetration (304) of fluorine comprises an annealing process. [13] The method of claim 12, wherein forming (302) the plurality of fluorine-containing layers (66) is performed at a first wafer temperature and penetrating (304) fluorine is performed at a second wafer temperature different from the first wafer temperature. [14] The method of any one of the preceding claims 9 to 13, wherein the removal (306) of the plurality of fluorine-containing layers (66) is performed by a dry etching process, and wherein the method further comprises, after the plurality of cycles (310), performing a wet etching process to etch residues of the plurality of fluorine-containing layers (66). [15] Method according to one of the preceding claims 9 to 14, wherein the plurality of cycles (310) are performed on the work function layers (64). [16] A method comprising: Forming a nanostructure (22B) in a trench (58), wherein gate spacers (38) are on opposite sides of the trench (58); Depositing a gate dielectric (62) extending into the trench (58) to enclose the nanostructure (22B), the gate dielectric (62) comprising a high-k dielectric material; and after the gate dielectric (62) is deposited, performing a plurality of cycles (310), each of the plurality of cycles (310) comprising the following steps A and B: A) performing a treatment process (302) on the gate dielectric (62) using WF6 as a first process gas; and B) after the treatment process (302), performing an etching process (306) using NF3 as a second process gas, wherein the treatment process (302) of step A results in a tungsten and fluorine-containing layer (66) remaining on the gate dielectric (62), and wherein the etching process (306) of step B results in the tungsten and fluorine-containing layer (66) being etched and completely removed. [17] The method of claim 16, further comprising a penetration process (304) in each of the plurality of cycles (310), wherein the penetration process (304) is performed after the treatment process (302) and before the etching process (306).

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