Semiconductor Modulation Arrangements

Abstract

Semiconductor module arrangement which features: a substrate (10) arranged in a housing (7) comprising a dielectric insulating layer (11) and a first metallization layer (111) arranged on a surface of the dielectric insulating layer (11), wherein the first metallization layer (111) comprises a first section (1111), a second section (1112) and a third section (1113), a fourth section (1114), a fifth section (1115), a sixth section (1116) and a seventh section (1117); a plurality of semiconductor bodies arranged on the first metallization layer (111) and a three-level neutral point clamped type 1, NPC1, -converter or a three-level active-neutral clamped, ANPC, -converter; and a first electrically conductive path (80 21 ), a second electrically conductive path (80 22), a third electrically conductive path (80 51 ), and a fourth electrically conductive path (80 52 ), where the substrate (10) has a first side, a second side opposite the first side, a third side and a fourth side opposite the third side, the first section (1111), the second section (1112) and the third section (1113) are arranged consecutively along the first page between the third page and the fourth page, the seventh section (1117), at least part of the sixth section (1116) and the fifth section (1115) are arranged consecutively along the second page between the third page and the fourth page, the fourth section (1114) is arranged along the fourth side and extends from the first side towards the second side, the first section (1111) is configured to be electrically coupled to a first electrical potential, and the seventh section (1117) is configured to be electrically coupled to a second electrical potential, wherein the first electrical potential is positive with respect to the second electrical potential during operation of the semiconductor module arrangement, the second section (1112) has a first end facing the first side of the substrate (10) and a second end facing the second side of the substrate (10), the first end being configured to extend via the first electrically conductive path (80) 21 ) to be electrically coupled with a third electrical potential (M1), and the second end is designed to be connected via the second electrically conductive path (80 22 ) to be electrically coupled with the third electrical potential (M1), and the fifth section (1115) has a first end facing the first side of the substrate (10) and a second end facing the second side of the substrate (10), the first end being configured to extend via the third electrically conductive path (80) 51 ) to be electrically coupled with the fourth electrical potential (M2), and the second end is designed to be connected via the fourth electrically conductive path (80 52 ) to be electrically coupled with the fourth electrical potential (M2).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor module assemblies. BACKGROUND

[0002] Document EP 3 772 750 A1 discloses a semiconductor module arrangement comprising a housing, a first semiconductor substrate arranged in the housing, a second semiconductor substrate arranged in the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses, and during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses.At least a first subgroup of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first subgroup of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

[0003] The document DE 10 2017 100 530 A1 discloses a three-level power module comprising at least one substrate on which one or more semiconductor switches are mounted, wherein the one or more semiconductor switches are wide bandgap semiconductors.

[0004] Power semiconductor module assemblies often include at least one semiconductor substrate arranged in a housing. A semiconductor assembly including a plurality of controllable semiconductor elements (e.g., IGBTs, MOSFETs, HEMTs, etc.) is contained on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer applied to a first side of the substrate layer, and optionally a second metallization layer applied to a second side of the substrate layer. The controllable semiconductor elements are mounted, for example, on the first metallization layer. The second metallization layer can optionally be attached to a base plate or a heat sink.The layout of the semiconductor device should be chosen to minimize the required size of at least one substrate while simultaneously ensuring symmetrical current flows. Furthermore, stray inductances should be as low as possible.

[0005] Therefore, there is a general need for a compact semiconductor module arrangement that has low stray inductances while providing symmetrical current flows. OVERVIEW

[0006] A semiconductor module arrangement includes a substrate arranged in a housing and including a dielectric insulation layer and a first metallization layer arranged on a surface of the dielectric insulation layer, wherein the first metallization layer includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion, and a seventh portion, a plurality of semiconductor bodies arranged on the first metallization layer and forming a three-level neutral point clamped (NPC1) type 1 converter or a three-level active neutral point clamped (ANPC) converter, and a first electrically conductive path, a second electrically conductive path, a third electrically conductive path, and a fourth electrically conductive path,wherein the substrate includes a first side, a second side opposite the first side, a third side, and a fourth side opposite the third side, the first section, the second section, and the third section are arranged sequentially along the first side between the third side and the fourth side, the seventh section, at least a portion of the sixth section, and the fifth section are arranged sequentially along the second side between the third side and the fourth side, the fourth section is arranged along the fourth side and extends from the first side toward the second side, the first section is configured to be electrically coupled to a first electrical potential, and the seventh section is configured to be electrically coupled to a second electrical potential,wherein, during operation of the semiconductor module arrangement, the first electrical potential is positive with respect to the second electrical potential, the second section includes a first end facing the first side of the substrate and a second end facing the second side of the substrate, the first end being configured to be electrically coupled to a third electrical potential via the first electrically conductive path, and the second end being configured to be electrically coupled to the third electrical potential via the second electrically conductive path, and the fifth section includes a first end facing the first side of the substrate and a second end facing the second side of the substrate, the first end being configured to be electrically coupled to the fourth electrical potential via the third electrically conductive path,and the second end is configured to be electrically coupled to the fourth electrical potential via the fourth electrically conductive path.

[0007] Another semiconductor module arrangement includes a substrate arranged in a housing and including a dielectric insulation layer and a first metallization layer arranged on a surface of the dielectric insulation layer, wherein the first metallization layer includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion, and a seventh portion, a plurality of semiconductor bodies arranged on the first metallization layer and forming a three-level neutral point clamped type 1, NPC1, converter or a three-level active neutral point clamped, ANPC, converter, and a first electrically conductive path, a second electrically conductive path, a third electrically conductive path, and a fourth electrically conductive path, wherein the substrate has a first side, a second side opposite the first side,a third side and a fourth side opposite the third side, the second section, the first section, and the third section are arranged sequentially along the first side between the third side and the fourth side, the fifth section, the seventh section, and the sixth section are arranged sequentially along the second side between the third side and the fourth side, the fourth section is arranged along the fourth side and extends from the first side toward the second side, the second section is configured to be electrically coupled to a third electrical potential, and the fifth section is configured to be electrically coupled to a fourth electrical potential, the first section includes a first end facing the first side of the substrate and a second end facing the second side of the substrate,wherein the first end is configured to be electrically coupled to a first electrical potential via the first electrically conductive path, and the second end is configured to be electrically coupled to the first electrical potential via the second electrically conductive path, and the seventh section includes a first end facing the first side of the substrate and a second end facing the second side of the substrate, wherein the first end is configured to be electrically coupled to a second electrical potential via the third electrically conductive path, and the second end is configured to be electrically coupled to the second electrical potential via the fourth electrically conductive path, wherein the first electrical potential is positive with respect to the second electrical potential during operation of the semiconductor module arrangement.

[0008] The invention will be better understood by reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the several views. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a semiconductor module assembly. Fig. 2 is a circuit diagram of a semiconductor device according to an example. Fig. 3 is a circuit diagram of a semiconductor device according to another example. Fig. 4 is a plan view of a semiconductor module assembly according to embodiments of the disclosure. Fig. 5, the Fig. 5A-5G schematically illustrates electrically conductive paths according to embodiments of the disclosure. Fig. 6 is a top view of a semiconductor module assembly according to further embodiments of the disclosure. DETAILED DESCRIPTION

[0009] In the following detailed description, reference is made to the accompanying drawings. The drawings illustrate specific examples of how the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with one another unless expressly stated otherwise. As in the claims, the designations of certain elements as "first element," "second element," "third element," etc., are not intended to be enumerative. Rather, such designations are merely intended to address various "elements." This means, for example, that the presence of a "third element" does not require the presence of both a "first element" and a "second element."An electrical line as described here may be a single electrically conductive element, or at least two single electrically conductive elements connected in series and / or parallel. Electrical lines may contain metal and / or semiconductor material and may be permanently (i.e., non-switchably) electrically conductive. An electrical line may have an electrical resistance that is independent of the direction of a current flowing through it. A semiconductor body as described here may be made of (doped) semiconductor material and may be a semiconductor chip or contained in a semiconductor chip. A semiconductor body has electrically connecting pads and contains at least one semiconductor element with electrodes. The pads are electrically connected to the electrodes, which implies that the pads are the electrodes, and vice versa.

[0010] Referring to Fig. 1 schematically shows a cross-sectional view of a power semiconductor module assembly 100. The power semiconductor module assembly 100 includes a housing 7 and a substrate 10. The substrate 10 includes a dielectric insulation layer 11, a patterned first metallization layer 111 attached to the dielectric insulation layer 11, and a (patterned) second metallization layer 112 attached to the dielectric insulation layer 11. The dielectric insulation layer 11 is arranged between the first and second metallization layers 111, 112.

[0011] Each of the first and second metallization layers 111, 112 may be made of or contain one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module assembly. The substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulation layer 11 is a ceramic, e.g., a thin ceramic layer. The ceramic may be made of or contain one of the following materials: aluminum oxide, aluminum nitride, zirconium oxide, silicon nitride, boron nitride, or any other dielectric ceramic. For example, the dielectric insulation layer 11 may be made of or contain one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 may, e.g.,a substrate with direct copper bonding (DCB), a substrate with direct aluminum bonding (DAB), or a substrate with active metal brazing (AMB). Furthermore, the substrate 10 can be an insulated metal substrate (IMS). An insulated metal substrate generally has a dielectric insulation layer 11 containing (filled) materials such as epoxy resin or polyimide. The material of the dielectric insulation layer 11 can be filled, for example, with ceramic particles. Such particles can be SiO2, Al2O3, AlN, or BN, for example, and can have a diameter between about 1 µm and about 50 µm. The substrate 10 can also be a conventional printed circuit board (PCB) with a non-ceramic dielectric insulation layer 11.For example, a non-ceramic dielectric insulation layer 11 may be made of or contain a cured resin.

[0012] The substrate 10 is arranged in a housing 7. In the Fig. In the example shown in Figure 1, the substrate 10 is arranged on a base plate 12, which has a bottom surface of the housing 7, while the housing 7 itself has only side walls and a cover. However, this is only an example. It is also possible for the housing 7 to further have a bottom surface and for the substrate 10 and the base plate 12 to be arranged within the housing 7. In some power semiconductor module arrangements 100, more than one substrate 10 is arranged on a single base plate 12 or on the bottom surface of a housing 7. It is also possible for the substrate 10 itself to form a bottom surface of the housing 7.

[0013] One or more semiconductor bodies 20 can be arranged on the at least one substrate 10. Each of the semiconductor bodies 20 arranged on the at least one substrate 10 can contain a diode, an IGBT (insulated-gate bipolar transistor), a MOSFET (metal-oxide-semiconductor field-effect transistor), a JFET (junction field-effect transistor), a HEMT (high-electron-mobility transistor), and / or any other suitable semiconductor element.

[0014] The one or more semiconductor bodies 20 may form a semiconductor device on the substrate 10. In Fig. 1, only two semiconductor bodies 20 are shown as examples. The second metallization layer 112 of the substrate 10 in Fig. 1 is a continuous layer. In the Fig. 1, the first metallization layer 111 is a structured layer. "Structured layer" means that the first metallization layer 111 is not a continuous layer, but contains gaps between different sections of the layer. Such gaps are Fig. 1 schematically. The first metallization layer 111 in the example contains three different sections. However, this is only an example. Any other number of sections is possible. Different semiconductor bodies 20 can be mounted on the same or different sections of the first metallization layer 111. Different sections of the first metallization layer 111 can have no electrical connection or can be electrically connected to one or more other sections using electrical connection elements 3 such as bond wires or bond ribbons. The electrical connections 3 can also include connection plates, conductor rails, or connection clips, to name just a few examples. The one or more semiconductor bodies 20 can be electrically and mechanically connected to the substrate 10 by an electrically conductive connection layer 30.Such an electrically conductive connecting layer 30 may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver powder. According to another example, it is also possible for the second metallization layer 112 to be a patterned layer. It is further possible to omit the second metallization layer 112 entirely. The substrate 10 may also be implemented as a multilayer substrate (not specifically shown) comprising more than one dielectric insulation layer 11 and at least one metallization layer arranged between two corresponding dielectric insulation layers, which may be referred to as a "buried metallization layer."For example, by providing an additional dielectric insulation layer between the second metallization layer 112 and the base plate 12, the second metallization layer 112 would become a buried metallization in this sense. The at least one buried metallization layer may also be patterned as described with respect to the first metallization layer 111. Electrical contact to the respective buried metallization layer (between different metallization layers of the multilayer substrate) may be established by one or more so-called "vias," which are electrically conductive connections extending through a dielectric insulation layer arranged adjacent to the respective buried metallization layer and to a further metallization layer, which may be the first, second, or another buried metallization layer.The respective buried metallization layer or at least a portion of the buried metallization layer can be used to transmit electrical currents or signals. For example, the respective buried metallization layer can be used in a manner similar to bond wires to connect various nodes and / or circuit elements arranged on the substrate. In other words, the connecting elements 3 can also be formed by or include a portion of a buried metallization layer (a portion of an additional metallization layer) of a multilayer substrate contacted by corresponding vias. Therefore, a multilayer substrate can be used to replace some or all surface connecting elements and / or it can be used to achieve a higher interconnect complexity between circuit nodes.

[0015] The Fig. The power semiconductor module arrangement 100 shown in Figure 1 further includes connection elements 40. The connection elements 40 are electrically connected to the first metallization layer 111 and establish an electrical connection between the inside and the outside of the housing 7. The connection elements 40 can be electrically connected to the first metallization layer 111 by a first end 41, while a second end 42 of each of the connection elements 40 protrudes from the housing 7. The connection elements 40 can be electrically contacted from the outside at their respective second ends 42. A first part of the connection elements 40 can extend in a vertical direction y through the interior of the housing 7. The vertical direction y is a direction that is perpendicular to an upper surface of the substrate 10, wherein the upper surface of the substrate 10 is a surface on which the at least one semiconductor body 20 is mounted. The Fig. However, the connecting elements 40 shown in Figure 1 are only examples.

[0016] The terminal elements 40 can be implemented in any other way and can be arranged anywhere within the housing 7. For example, one or more terminal elements 40 can be arranged close to or adjacent to the side walls of the housing 7. The terminal elements 40 can, for example, be attached or mounted to a side wall of the housing 7. According to one example, the side walls of the housing 7 have recesses, each recess accommodating one of a plurality of terminal elements 40. The terminal elements 40 could also protrude vertically or horizontally through the side walls of the housing 7 instead of through the lid. The first end 41 of a terminal element 40 can, for example, be electrically and mechanically connected to the substrate 10 by an electrically conductive connection layer (not explicitly shown in Fig. 1). Such an electrically conductive connecting layer may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver (Ag) powder. The first end 41 of a connecting element 40 may also be electrically coupled to the substrate 10, e.g., via one or more electrical connections 3.

[0017] Connection elements 40 can be implemented as simple pins having a comparatively small cross-sectional area, for example, as in Fig. 1 is shown by way of example. That is, a length of a connecting element 40 in the vertical direction y between its first end 41 and its second end 42 can be significantly greater than its greatest thickness (or width). Connecting elements 40 can, for example, have a round, oval, square, or rectangular cross-sectional area. However, any other regular or irregular shape is also possible. The greatest thickness of a connecting element 40 can be defined by its diameter, its width, or a greatest extent in a direction perpendicular to the length (e.g., perpendicular to the vertical direction y). For example, for a round connecting element 40, the greatest thickness is defined by the diameter of the connecting element 40, whereas for a connecting element 40 with a rectangular cross-section, the greatest thickness is defined by the length of the long sides, which are generally longer than the narrow sides.According to one example, each of the at least one connecting element 40 has a length between its first and second ends 41, 42 that is at least ten times, at least twenty times, or at least thirty times its greatest thickness. Due to their comparatively small cross-sectional area, such connecting elements are generally capable of delivering comparatively small voltages and currents.

[0018] Connection elements 40 can also have a comparatively large cross-sectional area in order to be able to supply higher supply voltages and conduct higher currents. Such connection elements 40 can also be referred to as conductor rails, for example. A conductor rail can, for example, comprise or be formed by a metal sheet. In order to be able to withstand large load currents, a connection element 40 or a conductor rail can have a length and a width that are greater (e.g., at least 10 times greater, at least 30 times greater, or even at least 50 times greater) than a thickness of the connection element or the conductor rail. For example, a length of a conductor rail can be greater than or substantially equal to the width of the conductor rail. However, it is also possible for the width to be even greater than the length of the conductor rail 6.For example, a length of a conductor rail may be less than ten times or less than five times the width of the conductor rail. The width represents the greatest extent of the conductor rail in a direction perpendicular to its length, similar to what was described above with respect to the connecting elements 40 with a smaller cross-sectional area. By significantly increasing the width, the cross-sectional area of ​​the conductor rails is large (at least five times, at least ten times, or at least thirty times) compared to the cross-sectional area of ​​the connecting elements 40 described above. According to one example, a thickness of a conductor rail may be between 0.5 and 1.5 mm (millimeters), e.g., 1 mm. Connecting elements 40 or conductor rails may be straight between their first end 41 and their second end 42. However, it is also possible for a connecting element 40 or a conductor rail to be bent at least once along its length.

[0019] The power semiconductor module arrangement 100 can further contain an encapsulation 5. The encapsulation 5 can, for example, consist of or contain a silicone gel or be a rigid molding compound. The encapsulation 5 can at least partially fill the interior of the housing 7 and thereby cover the components and electrical connections arranged on the substrate 10. The connection elements 40 or conductor rails can be partially embedded in the encapsulation 5. However, at least their second ends 42 are not covered by the encapsulation 5 and protrude from the encapsulation 5 through the housing 7 to the outside of the housing 7. The encapsulation 5 is designed to protect the components and electrical connections of the power semiconductor module 100, in particular the components arranged on the substrate 10 within the housing 7, from certain environmental conditions and mechanical damage.

[0020] The layout of a semiconductor module arrangement (e.g., various sections of the first metallization layer 111, semiconductor body 20, electrical connections 3, terminal elements 40, etc.) can generally be chosen to minimize the required size of the at least one substrate while avoiding uneven distribution of current densities, electrical losses, and thermal stress. Symmetry (with respect to current flow) is often essential with regard to gate drive and parasitic inductances. Furthermore, stray inductances should be as low as possible.

[0021] Now, with reference to Fig. 2 shows a schematic representation of a semiconductor device. The semiconductor device of Fig. 2 may contain and operate with a three-level neutral point clamped converter type 1 topology, NPC1. Fig. 2 is a circuit diagram of an exemplary three-level NPC1 topology. The semiconductor device in Fig. 2 contains a first supply node P, which is designed to be connected to a first electrical potential DC+ during operation. The semiconductor arrangement further contains a second supply node N, which is designed to be connected to a second electrical potential DC- during operation. The first potential DC+ is positive with respect to the second potential DC-. For example, the first potential DC+ can be a positive potential and the second potential DC- can be a negative potential. The arrangement further contains a first controllable semiconductor element T1, a second controllable semiconductor element T2, a third controllable semiconductor element T3 and a fourth controllable semiconductor element T4.The fourth controllable semiconductor element T4 each includes a control electrode G1, G2, G3, G4 and a controllable load path between a first load electrode (e.g., collector or drain electrode) and a second load electrode (e.g., emitter or source electrode). The load paths of the first controllable semiconductor element T1 and the second controllable semiconductor element T2 are coupled in series and between the first supply node P and an output node AC, and the load paths of the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 are coupled in series and between the output node AC and the second supply node N.

[0022] The first controllable semiconductor element T1 (i.e., the second load electrode of the first controllable semiconductor element T1) and the second controllable semiconductor element T2 (i.e., the first load electrode of the second controllable semiconductor element T2) are connected to each other via a first common node C1. The third controllable semiconductor element T3 (i.e., the second load electrode of the third controllable semiconductor element T3) and the fourth controllable semiconductor element T4 (i.e., the first load electrode of the fourth controllable semiconductor element T4) are connected to each other via a second common node C2. The first load electrode of the first controllable semiconductor element T1 is connected to the first supply node P, and the second load electrode of the fourth controllable semiconductor element T4 is connected to the second supply node N.

[0023] Each of the controllable semiconductor elements T1, T2, T3, T4 can be implemented by a single component (e.g., semiconductor body) or by a plurality of identical controllable semiconductor subcomponents (semiconductor bodies), each subcomponent having a control electrode and a controllable load path between a first load electrode and a second load electrode, the load paths being connected in parallel between the nodes between which the respective controllable semiconductor element is connected.

[0024] Each of the controllable semiconductor elements T1, T2, T3, T4 may comprise an intrinsic freewheeling element such as a body diode, which is electrically connected between the first load electrode and the second load electrode of the respective controllable semiconductor element T1, T2, T3, T4 (intrinsic freewheeling elements are in Fig. 2 not specifically shown). The semiconductor arrangement further includes first, second, third, and fourth freewheeling elements F1, F2, F3, F4. Each of the first, second, third, and fourth freewheeling elements F1, F2, F3, F4 includes a first electrode (e.g., an anode) and a second electrode (e.g., a cathode). Each of the first, second, third, and fourth freewheeling elements F1, F2, F3, F4 can be connected in parallel to one of the controllable semiconductor elements T1, T2, T3, T4. For example, the first freewheeling element F1 can have its second electrode connected to the first supply node P and its first electrode connected to the first common node C1, such that it is connected between the first supply node P and the first common node C1 and in parallel to the load path of the first controllable semiconductor element T1.The second freewheeling element F2 can be connected with its second electrode to the first common node C1 and with its first electrode to the output node AC, so that it is connected between the first common node C1 and the output node AC and parallel to the load path of the second controllable semiconductor element T2. The third freewheeling element F3 can be connected with its second electrode to the output node AC and with its first electrode to the second common node C2, so that it is connected between the output node AC and the second common node C2 and parallel to the load path of the third controllable semiconductor element T3.The fourth freewheeling element F4 can be connected with its second electrode to the second common node C2 and with its first electrode to the second supply node N, so that it is connected between the second common node C2 and the second supply node N and parallel to the load path of the fourth controllable semiconductor element T4.

[0025] Still referring to Fig. 2, the semiconductor device further includes a fifth freewheeling element F5 and a sixth freewheeling element F6, which can also be referred to as clamping diodes F5 and F6. Each of the fifth and sixth freewheeling elements F5, F6 includes a first electrode (e.g., an anode) and a second electrode (e.g., a cathode). The fifth freewheeling element F5 is connected by its second electrode to the first common node C1 and by its first electrode to a first midpoint node M1 (often referred to as the neutral node). The sixth freewheeling element F6 is connected by its first electrode to the second common node C2 and by its second electrode to a second midpoint node M2 ​​(neutral node).It is generally possible for the device to have only a single midpoint node, with the fifth freewheeling element F5 connected between the first common node C1 and the single midpoint node, and the sixth freewheeling element F6 connected between the second common node C2 and the single midpoint node. However, by providing a first midpoint node M1 and a second midpoint node M2 ​​separate and distinct from the first midpoint node M1, it is possible to implement the semiconductor device on a substrate in a more efficient and space-saving manner. This will be described further below with reference to FIG. Fig. 4 is explained in more detail.

[0026] Now, with reference to Fig. 3 shows a further semiconductor device schematically. The semiconductor device of Fig. 3 can incorporate and operate a three-level active-neutral-clamped, ANPC, converter topology. Fig. 3 is a schematic diagram of an exemplary three-level ANPC topology. The ANPC topology as shown in Fig. 3 is similar to the NPC1 topology described in relation to Fig. 2 above. In particular, the arrangement of the first, second, third and fourth controllable semiconductor elements T1, T2, T3, T4 and the first, second, third, fourth, fifth and sixth freewheeling elements F1, F2, F3, F4, F5, F6 corresponds to the arrangement of the respective components as described with reference to Fig. 2 above. The semiconductor device as shown in Fig. 3, but further comprises a fifth controllable semiconductor element T5 and a sixth controllable semiconductor element T6. The fifth controllable semiconductor element T5 and the sixth controllable semiconductor element T6 each include a control electrode G5, G6 and a controllable load path between a first load electrode (e.g., collector or drain electrode) and a second load electrode (e.g., emitter or source electrode). The load path of the fifth controllable semiconductor element T5 is coupled in parallel to the fifth freewheeling element F5 and between the first common node C1 and the first midpoint node M1. In particular, the first load electrode of the fifth controllable semiconductor element T5 is connected to the first common node C1, and the second load electrode of the fifth controllable semiconductor element T5 is connected to the first midpoint node M1.The load path of the sixth controllable semiconductor element T6 is coupled in parallel to the sixth freewheeling element F6 and between the second common node C2 and the second midpoint node M2. In particular, the first load electrode of the sixth controllable semiconductor element T6 is connected to the second midpoint node M2, and the second load electrode of the sixth controllable semiconductor element T6 is connected to the second common node C2.

[0027] Referring to the Fig. 2 and Fig. 3, each of the controllable semiconductor elements T1, T2, T3, T4, T5, T6 may further be connected to a respective auxiliary node, such as an auxiliary emitter node or Kelvin contact, which may be useful for measuring an operating parameter such as, for example, a voltage, a current, a resistance, and / or a temperature. In particular, the second load electrode of each controllable semiconductor element T1, T2, T3, T4, T5, T6 may be connected to a respective auxiliary node. However, such auxiliary nodes are optional and may be omitted. Each of the controllable semiconductor elements T1, T2, T3, T4, T5, T6 may include a semiconductor switch.The individual semiconductor switches can, for example, contain a transistor such as a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Field-Effect Transistor), HEMT (High Electron Mobility Transistor), BIP (Bipolar Transistor) or any other type of transistor.

[0028] If the semiconductor devices of the Fig. 2 and Fig. 3 are implemented in a semiconductor module arrangement, a large number of semiconductor devices (semiconductor bodies) are usually required. The semiconductor bodies can be arranged on a substrate of the semiconductor module arrangement, similar to what has been described with respect to Fig. 1 described above. The semiconductor bodies must be electrically coupled to the respective potentials by connecting elements and / or conductor rails. The specific arrangement of the semiconductor bodies and connecting elements or conductor tracks on the substrate leads to a defined current flow within the semiconductor module arrangement. A highly symmetrical current flow within the semiconductor module arrangement is generally desired. At the same time, however, the resulting stray inductances should be as low as possible. In order to minimize the costs of a semiconductor module arrangement, a very compact arrangement of the components is also generally desired in order to keep the size and weight of the semiconductor module arrangement as low as possible.

[0029] Now, with reference to Fig. 4 schematically illustrates a semiconductor module arrangement according to embodiments of the disclosure. The semiconductor module arrangement comprises a substrate 10 which is mounted in a housing 7 (the housing is shown in Fig. 4 not specifically shown) and comprises a dielectric insulation layer 11 and a first metallization layer 111 arranged on a surface of the dielectric insulation layer 11. The first metallization layer 111 comprises at least a first portion 1111, a second portion 1112, a third portion 1113, a fourth portion 1114, a fifth portion 1115, a sixth portion 1116, and a seventh portion 1117. The first metallization layer 111 may comprise further portions, e.g., for supplying control signals to the control electrodes of the controllable semiconductor elements. However, such additional portions are omitted for the sake of improved clarity.

[0030] The semiconductor module arrangement further comprises a plurality of semiconductor bodies arranged on the first metallization layer 111 and forming a three-level neutral point clamped type 1, NPC1, converter or a three-level active neutral point clamped, ANPC, converter. Fig. The example shown in Figure 4 illustrates the general principle using the NPC1 topology as it relates to Fig. 2 above. However, the same principles apply similarly to the ANPC topology of Fig. 3.

[0031] The substrate 10 has a first side, a second side opposite the first side, a third side, and a fourth side opposite the third side. In the figures, the substrate 10 is shown as a rectangular substrate, in which the third side and the fourth side are perpendicular to the first and second sides. In general, the substrate 10 can have any shape or geometry. That is, the third and fourth sides do not have to be perpendicular to the first and second sides. Those skilled in the art will understand that the described principle can be similarly applied to substrates with other geometries. Furthermore, the respective sides of the substrate 10 can also be curved, i.e., not form a perfectly straight line, and / or can contain sections that run at different angles. Those skilled in the art will understand that this does not have a negative impact on the operation of the arrangement, as long as the underlying principle, i.e.,the general arrangement and orientation of the various portions of the first metallization layer as described herein. The first portion 1111, the second portion 1112, and the third portion 1113 are sequentially disposed along the first side between the third side and the fourth side, the seventh portion 1117, at least a portion of the sixth portion 1116, and the fifth portion 1115 are sequentially disposed along the second side between the third side and the fourth side, and the fourth portion 1114 is disposed along the fourth side and extends from the first side toward the second side. Most portions of the first metallization layer 111 are shown in FIG. Fig. 4 with a square or rectangular cross-section. However, the various sections of the first metallization layer 111 may have any regular or irregular shape. According to one example, instead of a square shape, the sixth section 1116 may have a shape substantially corresponding to the shape of a rotated "H" (H rotated by 90°). That is, the sixth section 1116 may have two slightly larger segments connected to each other by a bridging segment of the sixth section 1116. The fifth section 1115 may, in this example, be arranged between the two larger segments of the sixth section 1116 in the second horizontal direction z. The fifth section 1115 may therefore have two separate segments separated from each other by the bridging segment of the sixth section 1116.In this case, it can be assumed that the seventh section 1117, one of the larger segments of the sixth section 1116 and the fifth section 1115 (followed by the second of the larger segments of the sixth section 1116 and the fourth section 1114) are arranged sequentially between the third side of the substrate 10 and the fourth side of the substrate 10.

[0032] The first section 1111 is configured to be electrically coupled to the first electrical potential DC+ during operation of the semiconductor module arrangement, and the seventh section 1117 is configured to be electrically coupled to the second electrical potential DC during operation of the semiconductor module arrangement, wherein the first electrical potential DC+ is positive with respect to the second electrical potential DC-.

[0033] The semiconductor module arrangement further comprises a first electrically conductive path 80 21, a second electrically conductive path 80 22 , a third electrically conductive path 80 51 and a fourth electrically conductive path 80 52 The second section 1112 has a first end facing the first side of the substrate 10 and a second end facing the second side of the substrate 10, wherein the first end is designed to be connected via the first electrically conductive path 80 during operation of the semiconductor module arrangement. 21 to be electrically coupled to a third electrical potential M1, and the second end is designed to be connected via the second electrically conductive path 80 during operation of the semiconductor module arrangement 22to be electrically coupled to the third electrical potential M1. Likewise, the fifth section 1115 has a first end facing the first side of the substrate 10 and a second end facing the second side of the substrate 10, wherein the first end is configured to be electrically coupled to the third electrically conductive path 80 during operation of the semiconductor module arrangement. 51 to be electrically coupled to the fourth electrical potential M2, and the second end is designed to be connected via the fourth electrically conductive path 80 52 to be electrically coupled to the fourth electrical potential M2. During operation of the semiconductor module arrangement, the third electrical potential M1 and the fourth electrical potential M2 are positive with respect to the second electrical potential DC- and negative with respect to the first electrical potential DC+.

[0034] As with the arrangement in Fig. 4, the plurality of semiconductor bodies of the semiconductor module arrangement to form a three-level neutral point clamped Type 1, NPC1, converter or a three-level active neutral point clamped, ANPC, converter may comprise a first plurality of semiconductor bodies T1, F1 arranged on the first section 1111, a second plurality of semiconductor bodies T2, F2 arranged on the third section 1113, a third plurality of semiconductor bodies T3, F3 arranged on the fourth section 1114, a fourth plurality of semiconductor bodies T4, F4 arranged on the sixth section 1116, a fifth plurality of semiconductor bodies T5, F5 arranged on the third section 1113, and a sixth plurality of semiconductor bodies T6, F6 arranged on the fifth section 1115. It should be noted that elements T5 and T6 in Fig. 4 are not shown, as these are only available in an ANPC topology (see Fig. 3) are present, but not in the NPC1 topology, which is Fig. 4 is shown as an example.

[0035] The first plurality of semiconductor bodies T1, F1 may include one or more controllable semiconductor elements and one or more freewheeling elements. Each of the first plurality of semiconductor bodies T1, F1 may be electrically coupled to the first section 1111 by an electrically conductive connecting layer and may be electrically coupled to the third section 1113 by one or more electrically conductive connecting elements (e.g., bonding wires, bonding strips, connecting rails, or sections of an additional metallization layer of the substrate contacted by corresponding vias). In this way, the first load electrodes of the first controllable semiconductor elements T1 and the second electrodes of the first freewheeling elements F1 may be coupled to the first potential DC+ via the first section 1111.The second load electrodes of the first controllable semiconductor elements T1 and the first electrodes of the first freewheeling elements F1 can be coupled by the one or more electrically conductive connecting elements 3 to the first common node C1 formed by the third section 1113.

[0036] The second plurality of semiconductor bodies T2, F2 may include one or more controllable semiconductor elements and one or more freewheeling elements. Each of the second plurality of semiconductor bodies T2, F2 may be electrically coupled to the third section 1113 by an electrically conductive connecting layer and may be electrically coupled to the fourth section 1114 by one or more electrically conductive connecting elements 3 (e.g., bonding wires, bonding strips, connecting rails, or sections of an additional metallization layer of the substrate contacted by corresponding vias). In this way, the first load electrodes of the second controllable semiconductor elements T2 and the second electrodes of the second freewheeling elements F2 may be coupled to the first common node C1.The second load electrodes of the second controllable semiconductor elements T2 and the first electrodes of the second freewheeling elements F2 can be coupled by the one or more electrically conductive connecting elements 3 to the output node AC formed by the fourth section 1114.

[0037] The fifth plurality of semiconductor bodies T5, F5 may comprise one or more freewheeling elements, as in Fig. 4 (in the case of an NPC1 topology). Alternatively, the fifth plurality of semiconductor bodies T5, F5 may comprise one or more controllable semiconductor elements and one or more freewheeling elements (in the case of an ANPC topology, not specifically shown). Each of the fifth plurality of semiconductor bodies T5, F5 may be electrically coupled to the third section 1113 by an electrically conductive connecting layer and may be electrically coupled to the second section 1112 by one or more electrically conductive connecting elements 3 (e.g., bonding wires, bonding strips, connecting rails, or sections of an additional metallization layer of the substrate contacted by corresponding vias). In this way, the second electrodes of the fifth freewheeling elements F5 and, if applicable, the first load electrodes of the fifth controllable semiconductor elements T5 may be coupled to the first common node C1.The first electrodes of the fifth freewheeling elements F5 and optionally the second load electrodes of the fifth controllable semiconductor elements T5 can be electrically coupled to the third electrical potential M1 (the first center node) by the one or more conductive connecting elements 3.

[0038] A current flow is therefore generally directed from the third side of the substrate 10 toward the fourth side when a current flows in a commutation loop comprising the first plurality of semiconductor bodies T1, F1, the second plurality of semiconductor bodies T2, F2, and the fifth plurality of semiconductor bodies T5, F5. The electrically conductive connecting elements 3, which electrically connect the semiconductor bodies of the fifth plurality of semiconductor bodies T5, F5 to the second section 1112, are connected to the second section 1112 at connection points arranged between the first end and the second end of the second section 1112. Since the third potential M1 is supplied to the second section 1112 from its first end and its second end, a (load) current can be divided and reaches each semiconductor body of the fifth plurality of semiconductor bodies T5, F5 to the same extent. Fig. 4, three fifth freewheeling elements F5 are schematically illustrated. The fifth freewheeling elements F5 are arranged along a line extending parallel to the third and fourth sides of the substrate 10. A current flow in the second section 1112 from its first end and its second end is Fig. 4 shown schematically by arrows.

[0039] The fourth plurality of semiconductor bodies T4, F4 may include one or more controllable semiconductor elements and one or more freewheeling elements. Each of the fourth plurality of semiconductor bodies T4, F4 may be electrically coupled to the sixth section 1116 by an electrically conductive connecting layer and may be electrically coupled to the seventh section 1117 by one or more electrically conductive connecting elements (e.g., bonding wires, bonding strips, connecting rails, or sections of an additional metallization layer of the substrate contacted by corresponding vias). In this way, the first load electrodes of the fourth controllable semiconductor elements T4 and the second electrodes of the fourth freewheeling elements F4 may be coupled to the second common node C2 formed by the sixth section 1116.The second load electrodes of the fourth controllable semiconductor elements T4 and the first electrodes of the fourth freewheeling elements F4 can be coupled to the seventh section 1117 and thus to the second potential DC- by the one or more electrically conductive connecting elements 3.

[0040] The third plurality of semiconductor bodies T3, F3 may include one or more controllable semiconductor elements and one or more freewheeling elements. Each of the third plurality of semiconductor bodies T3, F3 may be electrically coupled to the fourth section 1114 by an electrically conductive connecting layer and may be electrically coupled to the sixth section 1116 by one or more electrically conductive connecting elements (e.g., bonding wires, bonding strips, connecting rails, or sections of an additional metallization layer of the substrate contacted by corresponding vias). In this way, the first load electrodes of the third controllable semiconductor elements T3 and the second electrodes of the third freewheeling elements F3 may be coupled to the output node AC formed by the fourth section 1114.The second load electrodes of the third controllable semiconductor elements T3 and the first electrodes of the third freewheeling elements F3 can be coupled to the sixth section 1116 and thus to the second common node C2 by the one or more electrically conductive connecting elements 3.

[0041] The sixth plurality of semiconductor bodies T6, F6 may comprise one or more freewheeling elements F6, as in Fig. 4 (in the case of an NPC1 topology). Alternatively, the sixth plurality of semiconductor bodies T6, F6 may comprise one or more controllable semiconductor elements and one or more freewheeling elements (in the case of an ANPC topology, not specifically shown). Each of the sixth plurality of semiconductor bodies T6, F6 may be electrically coupled to the fifth section 1115 by an electrically conductive connecting layer and may be electrically coupled to the sixth section 1116 by one or more electrically conductive connecting elements 3 (e.g., bond wires, bond ribbons, connecting rails, or sections of an additional metallization layer of the substrate contacted by corresponding vias).In this way, the second electrodes of the sixth freewheeling elements F6 and, if applicable, the first load electrodes of the sixth controllable semiconductor elements T6 can be coupled to the fourth electrical potential M2 (the second center point node M2). The first electrodes of the sixth freewheeling elements F6 and, if applicable, the second load electrodes of the sixth controllable semiconductor elements T6 can be electrically coupled to the second common node C2, which is formed by the sixth section 1116, by the one or more electrically conductive connecting elements 3.

[0042] Similar to what was described above with respect to the first, second, and fifth pluralities of semiconductor bodies T1, F1, T2, F2, T5, F5, a current flow is therefore generally directed from the third side of the substrate 10 toward the fourth side when a current flows in a commutation loop comprising the third plurality of semiconductor bodies T3, F3, the fourth plurality of semiconductor bodies T4, F4, and the sixth plurality of semiconductor bodies T6, F6. The semiconductor bodies of the sixth plurality of semiconductor bodies T6, F6 are arranged on the fifth section 1115 between the first end and the second end of the fifth section 1115. Since the fourth potential M2 is supplied to the fifth section 1115 from its first end and its second end, a (load) current can be divided and reaches each semiconductor body of the sixth plurality of semiconductor bodies T6, F6 to the same extent. Fig. 4, three sixth freewheeling elements F6 are schematically illustrated. The sixth freewheeling elements F6 are arranged along a line extending parallel to the third and fourth sides of the substrate 10. A current flow in the fifth section 1115 from its first end and its second end is Fig. 4 shown schematically by arrows.

[0043] The number of semiconductor bodies of each plurality of semiconductor bodies as in Fig. 4 is merely an example. Each plurality of semiconductor bodies may have only one controllable semiconductor element and only one freewheeling element, or an even or odd number of controllable semiconductor elements or freewheeling elements. The number of controllable semiconductor elements of a plurality of semiconductor bodies may be equal to the number of freewheeling elements of the same plurality of semiconductor bodies. For example, if the first plurality of semiconductor bodies has two controllable semiconductor elements T1, it may also have two freewheeling elements F1, as shown in Fig. 4 is shown as an example.

[0044] Each of the first electrically conductive path 80 21 , the second electrically conductive path 80 22 , the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52may have one or more electrically conductive elements. The first electrically conductive path 80 21 , the second electrically conductive path 80 22 , the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52 However, they can be implemented in different ways. Various examples are provided in the Fig. 5A - 5G through the second section 1112, the first electrically conductive path 80 21 and the second electrically conductive path 80 22 shown schematically. All elements of the semiconductor module arrangement that are not necessary for understanding the various implementations of the electrically conductive paths and the general concept of the invention have been shown in the Fig. 5A - 5G omitted for clarity. The fifth section 1115, the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52 are in the Fig. 5A - 5G not specifically shown, but can be implemented similarly.

[0045] Fig. 5A schematically shows a first electrically conductive path 80 21 and a second electrically conductive path 80 22 according to embodiments of the disclosure. In this example, the first electrically conductive path 80 21 one or more connecting elements 4 21 up. In Fig. 5A is a connection element 4 21 indicated by a dashed circle. Each of the one or more connecting elements 4 21 extends from the first end of the second portion 1112 in a vertical direction y, which is perpendicular to an upper surface of the substrate 10 and through a top side of the housing 7, similar to what has been described with respect to the terminal elements 40 of Fig. 1 described above. The second electrically conductive path 80 22In this example, one or more connection elements 4 22 on (a connecting element 4 22 is in Fig. 5A indicated by a dashed circle). Each of the one or more connection elements 4 22 extends from the second end of the second portion 1112 in the vertical direction y and through the top of the housing 7. Similarly, the third electrically conductive path 80 51 one or more terminal elements, each of the one or more terminal elements extending from the first end of the fifth section 1115 in the vertical direction y and through the top of the housing 7, and the fourth electrically conductive path 80 52 may include one or more terminal elements, each of the one or more terminal elements extending from the second end of the fifth portion 1115 in the vertical direction y and through the top of the housing 7.

[0046] Fig. 5B schematically shows a first electrically conductive path 80 21 and a second electrically conductive path 80 22 according to further embodiments of the disclosure. In this example, the first electrically conductive path 80 21 an eighth section 111 81 the first metallization layer 111, which extends from the first end of the second section 1112 towards the third side of the substrate 10, wherein the eighth section 111 81 between the first side of the substrate 10 and the first section 1111. Similarly, the second electrically conductive path 80 22 a ninth section 111 82 the first metallization layer 111, which extends from the second end of the second section 1112 towards the third side of the substrate 10, wherein the ninth section 111 82between the first section 1111 and the sixth and seventh sections 1116, 1117. In a similar manner (not specifically shown), the third electrically conductive path 80 51 a tenth section of the first metallization layer 111 extending from the first end of the fifth section 1115 towards the third side of the substrate 10, wherein the tenth section is arranged between the sixth section 1116 and the first section 1111, and the fourth electrically conductive path 80 52 may include an eleventh portion of the first metallization layer 111 extending from the second end of the fifth portion 1115 toward the third side of the substrate 10, wherein the eleventh portion is disposed between the second side of the substrate 10 and the sixth portion 1116.

[0047] That is, the second section 1112 together with the eighth section 111 81and the ninth section 111 82 a generally U-shaped metallization surrounding the first section 1111 on three sides. Similarly, the fifth section 1115, together with a tenth section and an eleventh section, may form a generally U-shaped metallization surrounding the sixth section 1116 (or at least a segment of the sixth section 1116) on three sides. The eighth 111 81 , ninth 111 82 , tenth and eleventh sections can be electrically contacted from the outside of the housing 7 in different ways.

[0048] Still referring to Fig. 5B can be the eighth 111 81 , ninth 111 82 , tenth and eleventh sections are electrically contacted from the outside of the housing 7 by connecting elements 40 that protrude in a vertical direction from the housing 7. That is, the first electrically conductive path 80 21can also have one or more connecting elements 4 21 wherein each of the one or more connection elements 4 21 of the eighth section 111 81 in the vertical direction y and through the top of the housing 7. The second electrically conductive path 80 22 can also have one or more connecting elements 4 22 wherein each of the one or more connection elements 4 22 of the ninth section 111 82 in the vertical direction y and through the top of the housing 7. Similarly (not specifically shown), the third electrically conductive path 80 51 further comprising one or more terminal elements, each of the one or more terminal elements extending from the tenth section in the vertical direction y and through the top of the housing 7, and the fourth electrically conductive path 80 52may further comprise one or more terminal elements, each of the one or more terminal elements extending from the eleventh section in the vertical direction y and through the top of the housing 7.

[0049] As in Fig. 5B schematically illustrated by the dashed circles, the connection elements 40 can be arranged at one end of the respective section facing the third side of the substrate 10. That is, a current supplied by the connection elements flows through almost the entire length of the respective section before reaching the second section 1112. A connector element used to electrically contact the first section 1111 from outside the housing 7 can also be arranged on a side of the first section 1111 facing the third side of the substrate 10. The connector element used to electrically contact the first section 1111 from outside the housing 7 can, for example, comprise one or more connection elements or one or more conductor rails 61, similar to what was described above with respect to Fig. 1. Such connecting elements or conductor rails 61 may extend through a top or through a side wall of the housing 7. The connector element used to connect the first section 1111 in the embodiment shown in Fig. 5B shown arrangement from outside the housing 7, is between the one or more connection elements 4 21 , which differ from the eighth section 111 81 in the vertical direction y and through the top of the housing 7, and the one or more connection elements 4 22 , which differ from the ninth section 111 82in the vertical direction y and extending through the top side of the housing 7. This means that the electrical contacts used to electrically contact the respective sections of the first metallization layer 111 from the outside of the housing 7 are arranged comparatively close to one another along or near the third side of the substrate 10. In this way, the stray inductances within the semiconductor module arrangement are comparatively low. The electrical contacts are all arranged along the same side of the substrate 10. A distance between the connection elements 4 21 and 4 22 on the section formed by the second section 1112, the eighth section 111 81 and the ninth section 111 82 is formed, but is comparatively large, since the connecting elements 4 21 and 4 22 are arranged at opposite ends of the generally U-shaped section.

[0050] Now, with reference to Fig. 5C an embodiment corresponding to the arrangement of Fig. 5B is largely similar, shown schematically. The connecting elements in the arrangement of Fig. 5C, however, do not run through the top of the housing 7, but extend through a side wall of the housing 7. This means that the first electrically conductive path 80 21 In addition to the eighth section 111 81 furthermore one or more connecting elements 6 21 wherein each of the one or more connecting elements 6 21 of the eighth section 111 81 in a second horizontal direction z and extends through a side wall of the housing 7. The second electrically conductive path 80 22 In addition to the ninth section 111 82 furthermore one or more connecting elements 6 22 wherein each of the one or more connecting elements 622 of the ninth section 111 82 in the second horizontal direction z and extends through a side wall of the housing 7. Similarly, the third electrically conductive path 80 51 in addition to the tenth section, one or more connection elements, each of the one or more connection elements extending from the tenth section in the second horizontal direction z and through a side wall of the housing 7, and the fourth electrically conductive path 80 52 may further comprise, in addition to the eleventh section, one or more connection elements, each of the one or more connection elements extending from the eleventh section in the second horizontal direction z and through a side wall of the housing 7. The connection elements 6 21 , 6 22 can be implemented, for example, as conductor rails.

[0051] Now, with reference to Fig. 5D shows a further embodiment corresponding to the arrangements of Fig. 5B and Fig. 5C is largely similar. However, in this example, the eighth section 111 81 and the ninth section 111 82 , instead of using separate connecting elements as in the Fig. 5B and Fig. 5C, are electrically contacted by one and the same contact element. The contact element can be, for example, a conductor rail. This means that the first electrically conductive path 80 21 In addition to the eighth section 111 81 further comprises a first section of a first conductor rail 62, and the second electrically conductive path 80 22 In addition to the ninth section 111 82 further comprises a second section of the first conductor rail 62, wherein the first conductor rail 62 is connected with a first end to the eighth section 111 81and with a second end with the ninth section 111 82 is electrically coupled. The first section of the first conductor rail 62 may, for example, be a first half of the first conductor rail 62 (in the first horizontal direction x) and the second section of the first conductor rail 62 may be a second half of the first conductor rail 62 (in the first horizontal direction x). Fig. 5D is a schematic representation of a dotted line dividing the first conductor rail 62 into a first half and a second half. A current flow in the first electrically conductive rail 80 21 and the second electrically conductive rail 80 22 is indicated by arrows in Fig. 5D shown schematically.

[0052] Similarly, the third electrically conductive path 80 51 in addition to the tenth section, further comprise a first section of a second conductor rail, and the fourth electrically conductive path 8052 may further comprise, in addition to the eleventh section, a second section of the second conductor rail, wherein the second conductor rail is electrically coupled at a first end to the tenth section and at a second end to the eleventh section.

[0053] Now, with reference to Fig. 5E even shows a further embodiment which corresponds to the arrangements of Fig. 5B, Fig. 5C and Fig. 5D is largely similar, shown schematically. Instead of the eighth and ninth sections 111 81 , 111 82 and the connecting elements 4 21 , 4 22 from Fig. 5B, the connecting elements or conductor rails 6 21 , 6 22 from Fig. 5C or the conductor rail 62 of Fig. 5D shows the arrangement of Fig. 5E, however, has a twelfth section 1118 of the first metallization layer. This twelfth section 1118 may, for example, be generally U-shaped. The first electrically conductive path 80 21 has a first segment of the twelfth section 1118, and the second electrically conductive path 80 22 has a second segment of the twelfth section 1118. In Fig. 5E schematically illustrates a dotted line dividing the twelfth section 1118 into a first half and a second half. The twelfth section 1118 is electrically coupled at a first end to the first end of the second section 1112 and at a second end to the second end of the second section 1112, such that the second section 1112 and the twelfth section 1118 together form a closed loop horizontally surrounding the first section 1111.

[0054] Similarly, the third electrically conductive path 80 51a first segment of a thirteenth section of the first metallization layer 111, and the fourth electrically conductive path 80 52 may further comprise a second segment of the thirteenth section, the thirteenth section being electrically coupled at a first end to the first end of the fifth section 1115 and at a second end to the second end of the fifth section 1115, such that the fifth section 1115 and the thirteenth section together form a closed loop horizontally surrounding at least a portion of the sixth section 1116 and the seventh section 1117.

[0055] As in Fig. 5E, the semiconductor device may further comprise one or more terminal elements 63 extending from the twelfth section 1118 in the second horizontal direction z and through a side wall of the housing 7. Similarly, the semiconductor module device may comprise one or more terminal elements extending from the thirteenth section in the second horizontal direction z and through a side wall of the housing 7. Alternatively, the semiconductor module device may comprise one or more terminal elements 42 extending from the twelfth section 1118 in the vertical direction y and through the top of the housing 7 (see, e.g., Fig. 5F). Similarly, the semiconductor module assembly may include one or more terminal elements extending from the thirteenth portion in the vertical direction y and through the top of the housing 7.

[0056] An even further alternative embodiment is in Fig. 5G schematically shown. In this example, the semiconductor module arrangement has an eighth section 111 81 and a ninth section 111 82 similar to what happened with regard to the Fig. 5B, Fig. 5C and Fig. 5D described above. In the Fig. 5B, Fig. 5C and Fig. The examples shown in Figure 5D are the eighth section 111 81 and the ninth section 111 82 essentially symmetrical. However, this is not absolutely necessary. It is also possible that the eighth section 111 81 and the ninth section 111 82 have different lengths and / or shapes. The resulting current flows may not be completely symmetrical, but at least very similar. In any case, the potentials M1, M2 are supplied to the respective sections 1112, 1115 from both the first end and the second end. In the Fig. In the example shown in Figure 5G, the first electrically conductive path 80 21 further comprises one or more terminal elements 91, each of the one or more terminal elements 91 being mounted to a first side wall (e.g., the side wall arranged along the first side of the substrate 10) of the housing 7, and one or more electrically conductive connecting elements 31, each of the one or more electrically conductive connecting elements 31 comprising the eighth section 111 81 the first metallization layer 111 is electrically coupled to the one or more connection elements 91. The second electrically conductive path 80 22further comprises one or more terminal elements 92, each of the one or more terminal elements 92 being mounted to a second side wall (e.g., the side wall arranged along the third side of the substrate 10) of the housing 7, and one or more electrically conductive connecting elements 32, each of the one or more electrically conductive connecting elements 32 comprising the ninth portion 111 82 the first metallization layer 111 is electrically coupled to the one or more connection elements 92.

[0057] The terminals in this example are not arranged as close to each other as in the previous examples. However, the resulting leakage inductances and the symmetry of the current flow can still be satisfactory. If the terminals are arranged close to the side walls of the package, less mounting area can be required on the first metallization layer 111. This means that the arrangement of Fig. 5G can be implemented in a somewhat more space-saving manner. Instead of mounting the connection elements 91, 92 on different side walls of the housing 7, it is also possible to mount the connection elements 91, 92 on the same side wall (e.g., the second side wall), thereby achieving a higher symmetry compared to the example of Fig. 5G is achieved.

[0058] Similar to what was said above regarding the first electrically conductive path 80 21 and the second electrically conductive path 80 22described, the third electrically conductive path 80 51 in addition to a tenth section of the first metallization layer 111, one or more terminal elements, each of the one or more terminal elements being mounted to the second side wall of the housing 7, and one or more electrically conductive connecting elements, each of the one or more electrically conductive connecting elements electrically coupling the tenth section of the first metallization layer 111 to the one or more terminal elements. The fourth electrically conductive path 80 52In addition to an eleventh section of the first metallization layer 111, it may further comprise one or more terminal elements, each of the one or more terminal elements being mounted to the second sidewall or to a third sidewall of the housing 7, and one or more electrically conductive connecting elements, each of the one or more electrically conductive connecting elements electrically coupling the eleventh section of the first metallization layer 111 to the one or more terminal elements. Each electrically conductive connecting element 31, 32 may, for example, comprise a bonding wire, a bonding strip, a connecting bar, or a section of an additional metallization layer of the substrate that is contacted by corresponding vias.

[0059] For each of the Fig. 5A - 5G, the first electrically conductive path 80 21and the second electrically conductive path 80 22 implemented in a similar manner (ie the first electrically conductive path 80 21 and the second electrically conductive path 80 22 each have the same elements), resulting in a reduced stray inductance of a current flowing into or out of the first midpoint node M1 (or similarly the second midpoint node M2) and an improved symmetry of the current densities carried by the fifth plurality of semiconductor bodies D5. That is, the first electrically conductive path 80 21 and the second electrically conductive path 80 22 are essentially symmetrical to each other. In one and the same semiconductor module arrangement, the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52 be implemented in the same way as the first electrically conductive path 80 21and the second electrically conductive path 80 22 In general, the implementations shown in the various figures can also be combined in a single arrangement. This means, for example, that the first electrically conductive path 80 21 and the second electrically conductive path 80 22 can be implemented according to a figure, while for example the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52 implemented according to another figure. It is also generally possible to design the first electrically conductive path 80 21 and the second electrically conductive path 80 22 to implement in different ways and the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52in different ways. Such arrangements would not lead to completely symmetrical current flows, but can still be sufficiently symmetrical for at least some applications. The implementations, as they are described with respect to the Fig. 5A - 5G described above are only examples. It is generally possible to use the first electrically conductive path 80 21 , the second electrically conductive path 80 22 , the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52 in any other appropriate manner.

[0060] In the Fig. 4 and 5A-5G, the second section 1112 and the fifth section 1115 are each contiguous sections. That is, the second section 1112 and the fifth section 1115 each have only a single contiguous segment. However, this is only an example. As shown, for example, in Fig. 6, it is also possible for the second section 1112 to have two or more subsections, wherein two consecutive subsections are electrically coupled to one another by one or more electrically conductive connecting elements 3. Similarly, the fifth section 1115 may have two or more subsections, wherein two consecutive subsections are electrically coupled to one another by one or more electrically conductive connecting elements 3. Each electrically conductive connecting element 3 may, for example, comprise a bonding wire, a bonding strip, a connecting bar, or a section of an additional metallization layer of the substrate that is contacted by corresponding vias.Implementing the second section 1112 and / or the fifth section 1115 with two or more subsections may, for example, allow the entire semiconductor module arrangement to be realized in a more space-saving manner. The space available on the dielectric insulation layer 11 of the substrate 10 can be used more effectively. However, two or more subsections electrically coupled to each other by one or more electrically conductive connecting elements 3 will continue to be considered here as a second section 1112 or a fifth section 1115, since they are all coupled to the same potential.

[0061] As in Fig. 4, a distance 11112 between the first end and the second end of the second section 1112 in a first horizontal direction x may be greater than a length 11111 of the first section 1111 in the first horizontal direction x, which is perpendicular to the second horizontal direction z. Similarly, a distance 11115 between the first end and the second end of the fifth section 1115 in the first horizontal direction x may be greater than a length 11116 of the sixth section 1116 in the first horizontal direction x, which is perpendicular to the second horizontal direction z. In this way, even with the arrangement of Fig. 5A, in which the respective section 1112, 1115 is connected by connecting elements 4 21 , 4 22 is directly contacted, a distance between the first electrically conductive path 80 21 and the second electrically conductive path 80 22comparatively large, which reduces the resulting stray inductance.

[0062] The fourth section 1114, which forms the output node AC or is electrically coupled thereto, can also be electrically contacted from the outside of the housing 7, for example, by one or more terminal elements or conductor rails 44. In the embodiments described above, the elements used to provide the first, second, third, and fourth potentials DC+, DC-, M1, M2 are arranged on or near a first side of the substrate 10. The elements used to electrically contact the output node AC, in contrast, are located on an opposite side of the substrate 10. In this way, current flow within the semiconductor module arrangement is generally directed from the third side toward the fourth side. The stray inductances are comparatively low because the input terminals are arranged comparatively close to one another along the third side of the substrate 10.

[0063] The third potential M1 and the fourth potential may be separated from each other. However, it is also possible for the third potential M1 to be the same as the fourth potential M2. This means, for example, that the second section 1112 and the fifth section 1115 may be electrically coupled to each other either inside the housing 7 or outside the housing.

[0064] In the examples described above, the semiconductor device is implemented on a single substrate 10. However, it is generally possible to implement the semiconductor device on two or even more than two separate substrates instead. That is, the dielectric insulation layer 11 may have two or more subsections that are separate and distinct from each other.

[0065] Furthermore, in the examples described above, the second section 1112 is arranged in the second horizontal direction z between the first section 1111 and the third section 1113. Similarly, at least a segment of the sixth section 1116 is arranged between the seventh section 1117 and the fifth section 1115. The third potential M1 is supplied to the second section 1112 from two opposite sides of the second section 1112, and the fourth potential M2 is supplied to the fifth section 1115 from two opposite sides of the fifth section 1115. In the first horizontal direction x, the connection elements and / or conductor rails can be considered to be generally arranged in the order M1 - DC+ - M1 - M2 - DC- - M2. However, this is only an example. It is similarly possible to arrange the connection elements and / or conductor rails in the order DC+ - M1 - DC+ - DC- - M2 - DC-.That is, the positions of the first section 1111 and the second section 1112 in the second horizontal direction z can be interchanged. In this alternative example, the first potential DC+ would then be supplied to the first section 1111 from two opposite ends of the first section 1111. Similarly, the positions of the fifth section 1115 and the sixth section 1116 could be interchanged, and the second potential DC- could be supplied to the sixth section 1116 from two opposite ends of the sixth section 1116.

[0066] That is, a semiconductor module arrangement according to alternative embodiments of the disclosure may include a substrate 10 arranged in a housing 7 and comprising a dielectric insulation layer 11 and a first metallization layer 111 arranged on a surface of the dielectric insulation layer 11, wherein the first metallization layer 111 comprises a first portion 1111, a second portion 1112, a third portion 1113, a fourth portion 1114, a fifth portion 1115, a sixth portion 1116, and a seventh portion 1117. The semiconductor module arrangement further includes a plurality of semiconductor bodies arranged on the first metallization layer 111 and forming a three-level neutral-clamped type 1 (NPC1) converter or a three-level active neutral-clamping (ANPC) converter. The semiconductor module arrangement further includes a first electrically conductive path 80 21, a second electrically conductive path 80 22 , a third electrically conductive path 80 51 and a fourth electrically conductive path 80 52The substrate 10 has a first side, a second side opposite the first side, a third side, and a fourth side opposite the third side. The second section 1112, the first section 1111, and the third section 1113 are arranged sequentially along the first side between the third side and the fourth side. The fifth section 1115, the seventh section 1117, and the sixth section 1116 are arranged sequentially along the second side between the third side and the fourth side. The fourth section 1114 is arranged along the fourth side and extends from the first side toward the second side. The second section 1112 is configured to be electrically coupled to a third electrical potential M1, and the fifth section 1115 is configured to be electrically coupled to a fourth electrical potential M2.The first portion 1111 has a first end facing the first side of the substrate 10 and a second end facing the second side of the substrate 10, wherein the first end is configured to pass over the first electrically conductive path 80. 21 to be electrically coupled to a first electrical potential DC+, and the second end is designed to be connected via the second electrically conductive path 80 22 to be electrically coupled to the first electrical potential DC+. The seventh section 1117 has a first end facing the first side of the substrate 10 and a second end facing the second side of the substrate 10, wherein the first end is configured to be electrically coupled via the third electrically conductive path 80 51 to be electrically coupled to a second electrical potential DC-, and the second end is designed to be connected via the fourth electrically conductive path 80 52to be electrically coupled to the second electrical potential DC-. During operation of the semiconductor module arrangement, the first electrical potential DC+ is positive with respect to the second electrical potential DC-.

[0067] The first electrically conductive path 80 21 , the second electrically conductive path 80 22 , the third electrically conductive path 80 51 and the fourth electrically conductive path 80 52 can be similar to what is happening with regard to the Fig. 5A - 5G described above.

Claims

[1] Semiconductor module arrangement comprising: a substrate (10) arranged in a housing (7) and comprising a dielectric insulation layer (11) and a first metallization layer (111) arranged on a surface of the dielectric insulation layer (11), wherein the first metallization layer (111) has a first portion (1111), a second portion (1112), a third portion (1113), a fourth portion (1114), a fifth portion (1115), a sixth portion (1116), and a seventh portion (1117); a plurality of semiconductor bodies arranged on the first metallization layer (111) and comprising a three-level neutral point clamped type 1, NPC1, converter or a three-level active-neutral-point clamped, ANPC, converter; and a first electrically conductive path (80 21 ), a second electrically conductive path (80 22), a third electrically conductive path (80 51 ), and a fourth electrically conductive path (80 52 ), where the substrate (10) has a first side, a second side opposite the first side, a third side and a fourth side opposite the third side, the first section (1111), the second section (1112) and the third section (1113) are arranged successively along the first side between the third side and the fourth side, the seventh section (1117), at least a part of the sixth section (1116) and the fifth section (1115) are arranged successively along the second side between the third side and the fourth side, the fourth section (1114) is arranged along the fourth side and extends from the first side towards the second side, the first section (1111) is designed to be electrically coupled to a first electrical potential, and the seventh section (1117) is designed to be electrically coupled to a second electrical potential, wherein the first electrical potential is positive with respect to the second electrical potential during operation of the semiconductor module arrangement, the second section (1112) has a first end facing the first side of the substrate (10) and a second end facing the second side of the substrate (10), wherein the first end is designed to be connected via the first electrically conductive path (80 21 ) to be electrically coupled to a third electrical potential (M1), and the second end is designed to be connected via the second electrically conductive path (80 22 ) to be electrically coupled to the third electrical potential (M1), and the fifth section (1115) has a first end facing the first side of the substrate (10) and a second end facing the second side of the substrate (10), wherein the first end is designed to be connected via the third electrically conductive path (80 51 ) to be electrically coupled to the fourth electrical potential (M2), and the second end is designed to be connected via the fourth electrically conductive path (80 52 ) to be electrically coupled with the fourth electrical potential (M2). [2] Semiconductor module arrangement according to claim 1, wherein the third electrical potential (M1) and the fourth electrical potential (M2) are positive with respect to the second electrical potential and negative with respect to the first electrical potential during operation of the semiconductor module arrangement. [3] Semiconductor module arrangement according to claim 1 or 2, wherein from the first electrically conductive path (80 21), the second electrically conductive path (80 22 ), the third electrically conductive path (80 51 ) and the fourth electrically conductive path (80 52 ) each having one or more electrically conductive elements. [4] A semiconductor module assembly according to claim 3, wherein at least one of the following applies: the first electrically conductive path (80 21 ) has one or more connecting elements (4 21 ), wherein each of the one or more connecting elements (4 21 ) extends from the first end of the second portion (1112) in a vertical direction (y) perpendicular to an upper surface of the substrate (10) and through an upper side of the housing (7), the second electrically conductive path (80 22 ) has one or more connecting elements (4 22 ), wherein each of the one or more connecting elements (4 22) extends from the second end of the second portion (1112) in the vertical direction (y) and through the top of the housing (7), the third electrically conductive path (80 51 ) has one or more terminal elements, each of the one or more terminal elements extending from the first end of the fifth section (1115) in the vertical direction (y) and through the top of the housing (7), and the fourth electrically conductive path (80 52 ) has one or more terminal elements, each of the one or more terminal elements extending from the second end of the fifth section (1115) in the vertical direction (y) and through the top of the housing (7). [5] A semiconductor module assembly according to claim 3, wherein at least one of the following applies: the first electrically conductive path (80 21 ) has an eighth section (111 81) of the first metallization layer (111) extending from the first end of the second section (1112) towards the third side of the substrate (10), wherein the eighth section (111 81 ) is arranged between the first side of the substrate (10) and the first section (1111), the second electrically conductive path (80 22 ) has a ninth section (111 82 ) of the first metallization layer (111) extending from the second end of the second section (1112) towards the third side of the substrate (10), wherein the ninth section (111 82 ) is arranged between the first section (1111) and the sixth and seventh sections (1116, 1117), the third electrically conductive path (80 51) has a tenth section of the first metallization layer (111) extending from the first end of the fifth section (1115) towards the third side of the substrate (10), the tenth section being arranged between the sixth section (1116) and the first section (1111), and the fourth electrically conductive path (80 52 ) has an eleventh section of the first metallization layer (111) extending from the second end of the fifth section (1115) towards the third side of the substrate (10), the eleventh section being arranged between the second side of the substrate (10) and the sixth section (1116). [6] A semiconductor module assembly according to claim 5, wherein at least one of the following applies: the first electrically conductive path (80 21 ) further comprises one or more connecting elements (4 21), wherein each of the one or more connecting elements (4 21 ) from the eighth section (111 81 ) in the vertical direction (y) and through the top of the housing (7), the second electrically conductive path (80 22 ) further comprises one or more connecting elements (4 22 ), wherein each of the one or more connecting elements (4 22 ) from the ninth section (111 82 ) in the vertical direction (y) and through the top of the housing (7), the third electrically conductive path (80 51 ) further comprises one or more connection elements, each of the one or more connection elements extending from the tenth section in the vertical direction (y) and through the top of the housing (7), and the fourth electrically conductive path (80 52) further comprises one or more terminal elements, each of the one or more terminal elements extending from the eleventh section in the vertical direction (y) and through the top of the housing (7). [7] A semiconductor module assembly according to claim 5, wherein at least one of the following applies: the first electrically conductive path (80 21 ) further comprises one or more connecting elements (6 21 ), wherein each of the one or more connecting elements (6 21 ) from the eighth section (111 81 ) in a second horizontal direction (z) and through a side wall of the housing (7), the second electrically conductive path (80 22 ) further comprises one or more connecting elements (6 22 ), wherein each of the one or more connecting elements (6 22 ) from the ninth section (111 82) in the second horizontal direction (z) and through a side wall of the housing (7), the third electrically conductive path (80 51 ) further comprises one or more connection elements, each of the one or more connection elements extending from the tenth section in the second horizontal direction (z) and through a side wall of the housing (7), and the fourth electrically conductive path (80 52 ) further comprises one or more connection elements, each of the one or more connection elements extending from the eleventh section in the second horizontal direction (z) and through a side wall of the housing (7). [8] A semiconductor module assembly according to claim 5, wherein at least one of the following applies: the first electrically conductive path (80 21 ) further comprises a first portion of a first conductor rail (62), and the second electrically conductive path (8022 ) further comprises a second section of the first conductor rail (62), wherein the first conductor rail (62) has a first end connected to the eighth section (111 81 ) and with a second end with the ninth section (111 82 ) is electrically coupled, and the third electrically conductive path (80 51 ) further comprises a first portion of a second conductor rail, and the fourth electrically conductive path (80 52 ) further comprises a second section of the second conductor rail, wherein the second conductor rail is electrically coupled with a first end to the tenth section and with a second end to the eleventh section. [9] A semiconductor module assembly according to claim 3, wherein at least one of the following applies: the first electrically conductive path (80 21) has a first segment of a twelfth section (1118) of the first metallization layer (111), and the second electrically conductive path (80 22 ) further comprises a second segment of the twelfth section (1118), wherein the twelfth section (1118) is electrically coupled at a first end to the first end of the second section (1112) and at a second end to the second end of the second section (1112), such that the second section (1112) and the twelfth section (1118) together form a closed loop horizontally surrounding the first section (1111), and the third electrically conductive path (80 51 ) has a first segment of a thirteenth section of the first metallization layer (111), and the fourth electrically conductive path (80 52) further comprises a second segment of the thirteenth section, the thirteenth section being electrically coupled at a first end to the first end of the fifth section (1115) and at a second end to the second end of the fifth section (1115), such that the fifth section (1115) and the thirteenth section together form a closed loop horizontally surrounding at least a portion of the sixth section (1116) and the seventh section (1117). [10] A semiconductor module assembly according to claim 9, comprising at least one of the following: one or more connection elements (42) extending from the twelfth section (1118) in the vertical direction (y) and through the top of the housing (7), and one or more connection elements extending from the thirteenth section in the vertical direction (y) and through the top of the housing (7). [11] A semiconductor module assembly according to claim 9, comprising at least one of the following: one or more connection elements (63) extending from the twelfth section (1118) in the second horizontal direction (z) and through a side wall of the housing (7), and one or more connection elements extending from the thirteenth section in the second horizontal direction (z) and through a side wall of the housing (7). [12] A semiconductor module assembly according to claim 5, wherein at least one of the following applies: the first electrically conductive path (80 21 ) further comprises one or more terminal elements (91), each of the one or more terminal elements (91) being mounted on a first side wall of the housing (7), and one or more electrically conductive connecting elements (31), each of the one or more electrically conductive connecting elements (31) comprising the eighth section (111 81) of the first metallization layer (111) to the one or more connection elements (91), the second electrically conductive path (80 22 ) further comprises one or more terminal elements (92), each of the one or more terminal elements (92) being mounted on a second side wall of the housing (7), and one or more electrically conductive connecting elements (32), each of the one or more electrically conductive connecting elements (32) defining the ninth section (111 82 ) of the first metallization layer (111) to the one or more connection elements (92), the third electrically conductive path (80 51) further comprises one or more terminal elements, each of the one or more terminal elements being mounted to the second side wall of the housing (7), and one or more electrically conductive connecting elements, each of the one or more electrically conductive connecting elements electrically coupling the tenth portion of the first metallization layer (111) to the one or more terminal elements, and the fourth electrically conductive path (80 52 ) further comprises one or more terminal elements, each of the one or more terminal elements being mounted on a third side wall of the housing (7), and one or more electrically conductive connecting elements, each of the one or more electrically conductive connecting elements electrically coupling the eleventh section of the first metallization layer (111) to the one or more terminal elements wherein each electrically conductive connecting element (31, 32) comprises a bonding wire, a bonding band, a connecting rail or a section of an additional metallization layer of the substrate, which is contacted by corresponding vias. [13] Semiconductor module arrangement according to one of the preceding claims, wherein at least one of the following applies: the second section (1112) has two or more subsections, wherein two successive subsections are electrically coupled to one another by one or more electrically conductive connecting elements (3), and the fifth section (1115) has two or more subsections, wherein two successive subsections are electrically coupled to one another by one or more electrically conductive connecting elements (3), wherein each electrically conductive connecting element (3) comprises a bonding wire, a bonding band, a connecting rail or a section of an additional metallization layer of the substrate, which is contacted by corresponding vias. [14] Semiconductor module arrangement according to one of the preceding claims, wherein at least one of the following applies: a distance (11112) between the first end and the second end of the second section (1112) in a first horizontal direction (x) is greater than a length (11111) of the first section (1111) in the first horizontal direction (x) which is perpendicular to the second horizontal direction (z), and a distance (11115) between the first end and the second end of the fifth section (1115) in a first horizontal direction (x) is greater than a length (11116) of the sixth section (1116) in the first horizontal direction (x) which is perpendicular to the second horizontal direction (z). [15] Semiconductor module arrangement according to one of the preceding claims, wherein the plurality of semiconductor bodies comprises a first plurality of semiconductor bodies (T1, F1) arranged on the first section (1111), a second plurality of semiconductor bodies (T2, F2) arranged on the third section (1113), a third plurality of semiconductor bodies (T3, F3) arranged on the fourth section (1114), a fourth plurality of semiconductor bodies (T4, F4) arranged on the sixth section (1116), a fifth plurality of semiconductor bodies (T5, F5) arranged on the third section (1113), and a sixth plurality of semiconductor bodies (T6, F6) arranged on the fifth section (1115). [16] Semiconductor module arrangement according to claim 15, wherein the first plurality of semiconductor bodies (T1, F1) comprises a first plurality of controllable semiconductor elements and a first plurality of freewheeling elements, the second plurality of semiconductor bodies (T2, F2) comprises a second plurality of controllable semiconductor elements and a second plurality of freewheeling elements, the third plurality of semiconductor bodies (T3, F3) comprises a third plurality of controllable semiconductor elements and a third plurality of freewheeling elements, and the fourth plurality of semiconductor bodies (T4, F4) comprises a fourth plurality of controllable semiconductor elements and a fourth plurality of freewheeling elements. [17] Semiconductor module arrangement according to claim 16, wherein the fifth plurality of semiconductor bodies (F5) has a fifth plurality of freewheeling elements, and the sixth plurality of semiconductor bodies (F6) has a sixth plurality of freewheeling elements. [18] Semiconductor module arrangement according to claim 17, wherein the fifth plurality of semiconductor bodies (T5, F5) further comprises a fifth plurality of controllable semiconductor elements, and the sixth plurality of semiconductor bodies (T6, F6) further comprises a sixth plurality of controllable semiconductor elements. [19] Semiconductor module arrangement according to one of the preceding claims, wherein the fourth section (1114) is designed to be coupled to an output node (AC) or forms such an output node. [20] Semiconductor module arrangement comprising: a substrate (10) arranged in a housing (7) and comprising a dielectric insulation layer (11) and a first metallization layer (111) arranged on a surface of the dielectric insulation layer (11), wherein the first metallization layer (111) has a first portion (1111), a second portion (1112), a third portion (1113), a fourth portion (1114), a fifth portion (1115), a sixth portion (1116) and a seventh portion (1117); a plurality of semiconductor bodies arranged on the first metallization layer (111) and comprising a three-level neutral point clamped type 1, NPC1, converter or a three-level active-neutral-point clamped, ANPC, converter; and a first electrically conductive path (80 21 ), a second electrically conductive path (80 22 ), a third electrically conductive path (80 51), and a fourth electrically conductive path (80 52 ), where the substrate (10) has a first side, a second side opposite the first side, a third side and a fourth side opposite the third side, the second section (1112), the first section (1111) and the third section (1113) are arranged successively along the first side between the third side and the fourth side, the fifth section (1115), the seventh section (1117) and the sixth section (1116) are arranged successively along the second side between the third side and the fourth side, the fourth section (1114) is arranged along the fourth side and extends from the first side towards the second side, the second section (1112) is designed to be electrically coupled to a third electrical potential (M1), and the fifth section (1117) is designed to be electrically coupled to a fourth electrical potential (M2), the first section (1111) has a first end facing the first side of the substrate (10) and a second end facing the second side of the substrate (10), wherein the first end is designed to be connected via the first electrically conductive path (80 21 ) to be electrically coupled to a first electrical potential, and the second end is designed to be connected via the second electrically conductive path (80 22 ) to be electrically coupled to the first electrical potential, and the seventh section (1117) has a first end facing the first side of the substrate (10) and a second end facing the second side of the substrate (10), wherein the first end is designed to be connected via the third electrically conductive path (80 51 ) to be electrically coupled to a second electrical potential, and the second end is adapted to be connected via the fourth electrically conductive path (80 52 ) to be electrically coupled to the second electrical potential, wherein the first electrical potential is positive with respect to the second electrical potential during operation of the semiconductor module arrangement.

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