METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION PROCESSES

Abstract

A method for fabricating a semiconductor device is proposed. The method comprises forming a doped region (102) in a semiconductor body (104). Forming the doped region (102) includes introducing first dopants (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by means of a first ion implantation process (I2-1). Subsequently, forming the doped region (102) includes applying a first heat treatment (T1) to the semiconductor body (104). Subsequently, forming the doped region (102) includes introducing second dopants (1082) through the first surface (106) of the semiconductor body (104) at the first vertical reference level (L1) by means of a second ion implantation process (I2-2). An atomic number of the first dopants (1081) is equal to an atomic number of the second dopants (1082).The ion implantation energy (E2) of the second ion implantation process (I2-2) differs by less than 20% from the ion implantation energy (E1) of the first ion implantation process (I2-1). The ion implantation dose (D2) of the second ion implantation process (I2-2) differs by less than 20% from the ion implantation dose (D1) of the first ion implantation process (I2-1).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method of manufacturing a semiconductor device, in particular to a method comprising forming a doped region in a semiconductor body by means of ion implantation processes. BACKGROUND

[0002] The technological development of newer generations of power semiconductor devices, e.g., insulated-gate field-effect transistors (IGFETs) such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs), or freewheeling diodes, aims to improve the electrical device properties, e.g., the area-specific on-resistance or on-resistance. By adjusting or tailoring the properties of doped semiconductor regions, such as peaks, slopes, and extensions, electrical device properties can be adapted to the specific requirements of the semiconductor device.

[0003] There is a constant need to improve the flexibility in forming doped semiconductor regions. SUMMARY

[0004] One example of the present disclosure relates to a method for manufacturing a semiconductor device. The method comprises forming a doped region in a semiconductor body. Forming the doped region comprises introducing first dopants through a first surface of the semiconductor body at a first vertical reference level using an ion implantation process. Thereafter, a first heat treatment is applied to the semiconductor body. Thereafter, second dopants are introduced through the first surface of the semiconductor body at the first vertical reference level using a second ion implantation process. An atomic number of the first dopants is equal to an atomic number of the second dopants. An ion implantation energy of the second ion implantation process differs by less than 20% from an ion implantation energy of the first ion implantation process.An ion implantation dose of the second ion implantation process differs by less than 20% from an ion implantation dose of the first ion implantation process.

[0005] Another example of the present disclosure relates to another method for manufacturing a semiconductor device. The method comprises forming a doped region in a semiconductor body. Forming the doped region comprises introducing first dopants through a first surface of the semiconductor body at a first vertical reference level by means of a first ion implantation process. The first dopants are implanted along a beam axis that deviates by at most 1.5° from a main crystal axis of the semiconductor body along which channeling occurs. Thereafter, a first heat treatment is applied to the semiconductor body. Thereafter, second dopants are introduced through the first surface of the semiconductor body at the first vertical reference level by means of a second ion implantation process.The second dopants are implanted along a beam axis that deviates by a maximum of 1.5° from a main crystal axis of the semiconductor body along which channeling takes place.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of processing features of the semiconductor device and, together with the description, serve to explain principles of the examples. Further examples are described in the following detailed description and claims. Fig. 1A to 1C are schematic cross-sectional views to illustrate process features of a method of manufacturing a semiconductor device including forming a doped region. Fig. Figure 2 is a schematic cross-sectional view to illustrate a process feature of electrically activating dopants of the doped region. Fig. 3A to 3C are schematic cross-sectional views to illustrate further process features of a method of manufacturing a semiconductor device including forming a doped region. Fig. 4 and Fig. 5 are schematic cross-sectional views to illustrate configuration examples of a semiconductor device including a doped region formed by the structure described with reference to Fig. 1A to 1C described process characteristics. Fig. Figure 6 is a schematic illustration of simulated channeling profiles. DETAILED DESCRIPTION

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and show by way of illustration specific examples in which semiconductor substrates may be processed. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used on or in connection with other examples to arrive at yet another embodiment. It is intended that the present disclosure cover such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only.Corresponding elements are provided with the same reference numerals in the various drawings, unless otherwise stated.

[0009] The terms "have," "contain," "comprise," "have," and the like are open-ended terms. These terms indicate the presence of the identified structures, elements, or characteristics, but do not preclude the presence of additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0010] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" encompasses the possibility that one or more intermediate elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0011] If two elements A and B are combined with an "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B, unless explicitly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies mutatis mutandis to combinations of more than two elements.

[0012] Ranges specified for physical dimensions include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least."

[0013] The main components of a layer or structure made of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0014] The term "on" should not be construed to mean only "directly on." Rather, if an element is positioned "on" another element (e.g., a layer is "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0015] An example of a method for manufacturing a semiconductor device includes forming a doped region in a semiconductor body. Forming the doped region may include introducing first dopants through a first surface of the semiconductor body at a first vertical reference level using a first ion implantation process. A first heat treatment is then applied to the semiconductor body. Second dopants may then be introduced through the first surface of the semiconductor body at the first vertical reference level using a second ion implantation process. An atomic number of the first dopants may be equal to an atomic number of the second dopants. An ion implantation energy of the second ion implantation process may differ by less than 20%, less than 10%, or even less than 5% from an ion implantation energy of the first ion implantation process.An ion implantation dose of the second ion implantation process may differ by less than 20%, or by less than 10%, or even less than 5% from an ion implantation dose of the first ion implantation process.

[0016] The semiconductor body can have a crystal lattice suitable for channeling ions. Typically, in some crystal directions of single-crystalline materials, open spaces extend straight into the crystal. These open spaces form channels through which ions migrate with less interaction with the atoms of the crystal lattice than outside the channels. The channels control or determine the movement of the ions, with ions entering through such channels exhibiting a retardation pattern that differs from the retardation pattern for ions entering the semiconductor body outside the channels. In other words, in some crystal directions of single-crystalline materials, the atoms align in such a way that they form so-called channels, in which the incoming ion flow is restricted. The channel directions coincide with the main crystal directions.

[0017] The first and second dopants can be implanted into the semiconductor body, for example, via ions of the respective element or element compound. For example, no further ion implantations can be performed between the ion implantation of the first dopants and the ion implantation of the second dopants. In addition to the first and second ion implantation processes, further ion implantation processes can be performed to form the doped region. For example, each of the further ion implantation processes in addition to the first and second ion implantation processes can be performed either before the first ion implantation process or after the second ion implantation process. A further heat treatment can be performed after each or some of the additional ion implantation processes.A sequence of n ion implantations followed by annealing of crystal damage can be performed to form the doped region, where n is an integer equal to or greater than 2, e.g., 3, 4, 5, 6, 7, 8, 9, 10, or even greater. Between ion implantation processes, for example, a semiconductor layer can be formed on a surface of the semiconductor body, from which dopants enter or pass into the semiconductor body by means of the ion implantation processes. This can enable an increase in the lateral extent of the doped region. Parameters of the additional ion implantation processes, e.g., ion implantation energy and / or ion implantation dose and / or tilt angle of the ion implantation with respect to the vertical axis on the first surface, can be similar to the first and / or second ion implantation processes.

[0018] The first vertical reference level is measured with respect to a fixed vertical position within the semiconductor body and may define an outer surface of the semiconductor body. When a semiconductor layer is deposited on the first surface at the first reference level by means of a semiconductor layer deposition process, followed by a subsequent ion implantation process into the deposited semiconductor layer, the subsequent ion implantation process will introduce dopants through a surface of the deposited semiconductor layer located at a second vertical reference level that is different from the first vertical reference level. While the first vertical reference level may define the outer surface of the semiconductor layer prior to the layer deposition process, the second vertical reference level may define the outer surface of the semiconductor body plus the deposited semiconductor layer.

[0019] The first heat treatment can be performed to anneal the semiconductor body. The first heat treatment can be performed using a furnace process or rapid thermal processing (RTP). Additionally or alternatively, the annealing can be performed by laser thermal annealing (LTA), with or without melting. This can enable a reduction or minimization of crystal damage in the irradiated zone through a suitable heat balance for the annealing. This can reduce or minimize deterioration in the channeling performance or de-channeling of a subsequent ion implantation of dopants, e.g., the second ion implantation process, due to crystal damage caused by the first ion implantation process. This can, for example, enable an improvement in tuning a vertical dopant concentration profile.

[0020] The semiconductor device may, for example, be an integrated circuit or a discrete semiconductor device or a semiconductor module. The semiconductor device may be or include a power semiconductor device, e.g., a vertical power semiconductor device with a load current flow between a first surface and a second surface. The semiconductor device may be or include a power semiconductor IGFET, e.g., a power semiconductor MOSFET, or a power semiconductor IGBT. The power semiconductor device may be configured to conduct currents of more than 1 A, or more than 10 A, or even more than 30 A, and may further be configured to conduct voltages between load electrodes, e.g., between an emitter and a collector of an IGBT or between a drain and a source of a MOSFET, in the range of a few hundred to a few thousand volts, e.g.,400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device.

[0021] For example, the semiconductor body may be or contain a crystalline SiC semiconductor substrate. The crystalline SiC semiconductor substrate may, for example, have a hexagonal polytype, e.g., 4 H or 6 H. The semiconductor body may be homogeneously doped or may contain differently doped SiC layer regions, e.g., with a doping concentration of at least 2×10 17 cm -3 and a maximum of 1×10 19 cm -3, for example at least 5×10 17 cm -3 and a maximum of 1×10 19 cm -3, or can be nominally undoped (e.g. with a doping concentration of not more than 1×10 17 cm -3 or of a maximum of 1×10 15 cm -3; so-called "non-intentionally doped silicon carbide"). For example, the semiconductor body may comprise, e.g., differently doped SiC layer regions, a substantially homogeneously doped SiC semiconductor substrate and an epitaxial buffer layer on the SiC semiconductor substrate. The semiconductor body may, for example, contain one or more layers of another material with a melting point close to or higher than crystalline silicon carbide. For example, the layers of another material may be embedded in the crystalline SiC semiconductor substrate. The crystalline SiC semiconductor substrate may have two substantially parallel main surfaces of the same shape and size and a lateral surface region connecting the edges of the two main surfaces.For example, the silicon carbide semiconductor substrate may be a rectangular prism with or without rounded edges, or a right cylinder, or a slightly slanted cylinder (e.g., with the sides inclined at an angle of at most 8°, or at most 5°, or at most 3°) with or without one or more flats or notches along the outer circumference. As an alternative to SiC, a wide bandgap semiconductor wafer, e.g., a wide bandgap semiconductor material other than silicon carbide, may be processed. The wide bandgap semiconductor wafer may have a larger bandgap than the silicon bandgap (1.1 eV). For example, the wide bandgap semiconductor wafer may be a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer.As an alternative to SiC and wide bandgap materials, a silicon semiconductor body can also be used. For example, the semiconductor body can have a cubic diamond crystal lattice such as silicon (Si). In the case of a cubic diamond crystal lattice, a surface of the semiconductor body can coincide with a (100) crystal face, can be inclined by a maximum of ±2 degrees to the {100} crystal face, or can be any other surface suitable for channeling. Accordingly, a <100> -Crystal direction, which is one of several main crystal directions along which channeling takes place, or any other suitable direction perpendicular to the process surface.

[0022] By dividing an ion implantation dose from one ion implantation process into multiple ion implantations with a lower dose, interspersed with heat treatments to heal crystal damage caused by the previous implantation, the resulting ion implantation profile of the multiple ion implantations can allow for greater flexibility in shaping profiles compared to a single ion implantation process or fewer ion implantation processes with the same total dose as the multiple ion implantations. The interspersed heat treatments to heal crystal damage from the previous ion implantation process improve ion implantations via channeling of subsequent ion implantations by reducing de-channeling or the effects of channeling degradation.More specifically, the concentration of implanted ions in the channeling tail region can be increased as a consequence of reduced crystal damage by applying intermediate heat treatments.

[0023] For example, the first and / or second dopants can be implanted along a beam axis that deviates by at most 1.5°, by at most 1.0°, by at most 0.5°, by at most 0.3°, or by at most 0.1° from a main crystal axis of the semiconductor body along which channeling occurs. For example, a maximum inclination angle between a main beam direction and the main crystal direction along which channeling of ions occurs, as well as a variability of the angle of incidence of an implantation beam of at most ±0.5 degrees, can apply to at least 80% of the surface of the semiconductor body.

[0024] Details regarding the process features described above equally apply to another example of a method for manufacturing a semiconductor device. The method comprises forming a doped region in a semiconductor body. Forming the doped region may comprise introducing first dopants through a first surface of the semiconductor body at a first vertical reference level by means of a first ion implantation process. The first dopants may be implanted along a beam axis that deviates by at most 1.5° from a main crystal axis of the semiconductor body along which channeling occurs. Thereafter, a first heat treatment may be applied to the semiconductor body. Subsequently, second dopants may be introduced through the first surface of the semiconductor body at the first vertical reference level by means of a second ion implantation process.The second dopants can be implanted along a beam axis that deviates by at most 1.5° from a main crystal axis of the semiconductor body along which channeling occurs. For example, the semiconductor body can be a SiC semiconductor body and the main crystal axis can be the c-axis. An atomic number of the first dopants can, for example, differ from an atomic number of the second dopants. In addition or alternatively, an ion implantation energy of the second ion implantation process can differ by less than 20%, or by less than 10%, or even by less than 5% from an ion implantation energy of the first ion implantation process. In addition or alternatively, an ion implantation dose of the second ion implantation process can differ by less than 20% from an ion implantation dose of the first ion implantation process.

[0025] For example, the second ion implantation energy may be lower than the first ion implantation energy.

[0026] For example, the second ion implantation dose may be lower than the first ion implantation dose.

[0027] For example, an ion implantation mask of the first ion implantation process can be reused for the second ion implantation process.

[0028] The method may further comprise, for example, applying an activation heat treatment to the semiconductor body after the second ion implantation process. The activation heat treatment may be configured to electrically activate the first and second dopants. A maximum temperature of the activation heat treatment may be greater than a maximum temperature of the first heat treatment.

[0029] The maximum temperature of the activation heat treatment can be more than 400 K, more than 500 K, or even more than 600 K higher than the maximum temperature of the first heat treatment. For example, the temperature values ​​of the first heat treatment can range from 600°C to 1000°C, and the temperature values ​​of the activation heat treatment can range from 1600°C to 1900°C.

[0030] For example, the maximum temperature of the first heat treatment may be configured to heal crystal damage caused by the first ion implantation process.

[0031] The semiconductor body can be, for example, a SiC semiconductor body. The maximum temperature of the first heat treatment can, for example, be between 600°C and 1200°C, or between 600°C and 1000°C, or between 700°C and 900°C.

[0032] The method may, for example, further include ion implantation processes in addition to the first and second ion implantation processes. Each of the ion implantation processes in addition to the first and second ion implantation processes may be performed either before the first ion implantation process or after the second ion implantation process. Between subsequent ion implantation processes comprising at least one of the additional ion implantation processes, heat treatments for annealing crystal damage may be performed. An atomic number of the dopants used for the additional ion implantation processes to form the doped region may, for example, be the same as or different from the atomic number of the first / second dopants.

[0033] The doped region may, for example, be a p-doped region or an n-doped region of a superjunction structure with the p-doped region laterally adjacent to the n-doped region.

[0034] For example, forming the superjunction structure may further comprise forming a semiconductor layer on the first surface of the semiconductor body. Forming the superjunction structure may further comprise introducing third dopants through a surface of the semiconductor layer at a second vertical reference level using a third ion implantation process. A second heat treatment may then be applied to the semiconductor body and the semiconductor layer. Fourth dopants may then be introduced through the surface of the semiconductor layer at the second vertical reference level using a fourth ion implantation process. An atomic number of the third dopants may be equal to an atomic number of the fourth dopants.An ion implantation energy of the fourth ion implantation process may differ by less than 20%, less than 10%, or even less than 5% from an ion implantation energy of the third ion implantation process. An ion implantation dose of the fourth ion implantation process may differ by less than 20%, less than 10%, or even less than 5% from an ion implantation dose of the third ion implantation process.

[0035] For example, forming the superjunction structure may further comprise forming a semiconductor layer on the first surface of the semiconductor body. Forming the superjunction structure may further comprise introducing third dopants through a surface of the semiconductor layer at a second vertical reference level using a third ion implantation process and introducing fourth dopants through the surface of the semiconductor layer at the second vertical reference level using a fourth ion implantation process. The introduction of both the first dopants and the third dopants may be performed before the first heat treatment, and the introduction of both the second dopants and the fourth dopants may be performed after the first heat treatment.For example, an atomic number of the third dopants is equal to an atomic number of the fourth dopants and / or an ion implantation energy of the fourth ion implantation process differs by less than 20% from an ion implantation energy of the third ion implantation process and / or an ion implantation dose of the fourth ion implantation process differs by less than 20% from an ion implantation dose of the third ion implantation process.

[0036] For example, both the first dopants and the second dopants form the n-doped region or an n-doped column of the superjunction structure, and both the third dopants and the fourth dopants form the p-doped region or a p-doped column of the superjunction structure. In other words, the n-doped and the p-doped regions of the superjunction structure can be formed in at least two ion implantation steps along the channeling axis, respectively. Between the ion implantation steps, a respective heat treatment can be performed to anneal the crystal lattice to improve channeling in the subsequent ion implantation step.

[0037] The doped region may be an n-doped current spreading region of a power semiconductor device containing gate trenches. The current spreading region may border a bottom side of the gate trenches. Furthermore, the current spreading region may border a channel end opposite another channel end bordering the source region.

[0038] For example, both the ion implantation energy of the first ion implantation process and the ion implantation energy of the second ion implantation process may each be greater than 1000 keV.

[0039] The semiconductor device may, for example, include a doped region formed by the method of any of the examples disclosed herein. The semiconductor device may be a vertical power semiconductor device, which may, for example, be part of an integrated circuit, a discrete semiconductor device, or a semiconductor module, or at least one thereof. The semiconductor device may be used in applications related to power transmission and distribution, automotive and transportation, renewable energy, consumer electronics, and other industrial applications. The vertical power semiconductor device may, for example, be or include an insulated-gate field-effect transistor (IGFET) such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a junction field-effect transistor (JFET).For semiconductor devices based on substrate materials that allow only low diffusion of dopants, e.g., SiC, the examples described herein may, for example, allow for more flexibility in shaping doping concentration profiles. For example, higher concentrations at greater depths and box-shaped profiles may be achieved in such substrate materials. Doped regions that require greater depths to fulfill their intended purpose may, for example, benefit from the examples disclosed herein. The doped region may, for example, be an n-doped current spreading region of an n-channel MOSFET. The doped region may, for example, also be part, e.g., as an n-doped or p-doped part in the form of a pillar, a superjunction (SJ) structure of a superjunction MOSFET.

[0040] Further details and aspects are provided in connection with the examples described above or below. The processing of the semiconductor body may include one or more optional additional features according to one or more aspects provided in connection with the proposed concept or one or more of the examples described above or below.

[0041] The aspects and features cited and described together with one or more of the previously described examples and figures may also be combined with one or more of the other examples to replace an identical feature of the other example or to additionally incorporate the feature into the other example.

[0042] It is understood that while the method is described above and below as a series of steps or events, the described order of such steps or events is not to be interpreted in a limiting sense. Rather, some steps may occur in different orders and / or concurrently with other steps or events apart from those described above and below.

[0043] Functional and structural details described with respect to the examples above shall apply equally to the examples illustrated in the figures and further described below.

[0044] Referring to the schematic cross-sectional views of the Fig. 1A to 1C illustrate exemplary process features for manufacturing a semiconductor device.

[0045] The illustrated process features of the method illustrate exemplary process features for forming a doped region 102 in a semiconductor body 104.

[0046] Referring to Fig. 1A, first dopants 1081 are introduced through a first surface 106 of the semiconductor body 104 at a first vertical reference level L1 by means of a first ion implantation process I2-1. The first vertical reference level L1 refers to a predetermined vertical position within the semiconductor body 104. The first dopants 1081 are implanted along a beam axis 1101 at an angle α1 with respect to a vertical axis of the first surface 106. For example, the angle α1 may deviate by at most 1.5° from a main crystal axis of the semiconductor body along which channeling occurs, e.g., the c-axis in a SiC semiconductor body. The first ion implantation process I2-1 is based on an ion implantation energy E1 and an ion implantation dose D1.

[0047] Referring to Fig. 1B, a first heat treatment T1 is applied to the semiconductor body 104. For example, the first heat treatment G1 may comprise annealing the semiconductor body 104 using a furnace process or rapid thermal processing (RTP). Additionally or alternatively, the annealing may be performed by laser thermal annealing (LTA), with or without melting. This may enable a reduction or minimization of crystal damage in the irradiated zone through appropriate annealing.

[0048] Referring to Fig. 1C, after the first heat treatment T1, second dopants 1082 are introduced through the first surface 106 of the semiconductor body 104 at the first vertical reference level L1 by means of a second ion implantation process I2-2. The second dopants 1082 are implanted along a beam axis 1102 at an angle α2 with respect to the vertical axis on the first surface 106. For example, the angle α2 may deviate by at most 1.5° from a main crystal axis of the semiconductor body 104 along which channeling occurs, e.g., the c-axis in a SiC semiconductor body. The second ion implantation process I2-2 is based on an ion implantation energy E2 and an ion implantation dose D2. An atomic number of the first dopants 1081 is equal to an atomic number of the second dopants 1082. For example, the first and second dopants may be Al for a p-type doping, e.g.in a semiconductor body made of SiC or Si. The first and second dopants can be, for example, P for an n-type doping, e.g. in a semiconductor body made of SiC or Si. The ion implantation energy E2 of the second ion implantation process I2-2 differs by less than 20%, or less than 10%, or less than 5% from the ion implantation energy E1 of the first ion implantation process I2-1. The ion implantation dose D2 of the second ion implantation process I2-2 differs by less than 20%, or less than 10%, or less than 5% from the ion implantation dose D1 of the first ion implantation process I2-1.

[0049] Further process characteristics can be defined, for example, before, after or between the Fig. 1A, Fig. 1B, Fig. 1C. Examples of a further process feature include, but are not limited to, deposition processes for forming insulating layers or semiconductor layers or conductive layers, etching processes, e.g., via a lithographic etch mask(s), for patterning structures, and doping processes for forming further doped regions in the semiconductor body 104. Example doped regions include source and drain regions or emitter and collector regions, a body region(s), a body contact region(s), a current spreading region(s), a shielding region(s) configured to shield a gate dielectric against high electric fields, and a field stopping region(s). Example insulating layers include a gate dielectric(s), an interlayer insulating dielectric(s) in a wiring region above the semiconductor body 104.Example semiconducting layers include a gate electrode(s), a field electrode(s), and a floating electrode(s) formed by highly doped semiconductor materials. Example conductive layers include a patterned wiring layer(s), e.g., a patterned metal wiring layer(s), contact holes, contact plugs, and bond pad(s).

[0050] In the Fig. In the example illustrated in Figures 1A to 1C, the formation of the doped region 102 was illustrated based on two ion implantation processes I2-1, I2-2. The two ion implantation processes I2-1, I2-2 for forming the doped region 102 are merely exemplary and are not limiting in any way. Further ion implantation processes in addition to the first and second ion implantation processes I2-1, I2-2 may be performed to form the doped region 102. For example, each of the ion implantation processes in addition to the first and second ion implantation processes I2-1, I2-2 may be performed either before the first ion implantation process I2-1 or after the second ion implantation process I2-2. Parameters of the additional ion implantation processes, e.g.Ion implantation energy and / or ion implantation dose and / or tilt angle of the ion implantation with respect to the vertical axis on the first surface 106 may be similar to the first and / or second ion implantation process I2-1, I2-2.

[0051] Referring to the schematic cross-sectional view of Fig. 2, the method for forming the doped region 102 may further comprise an activation heat treatment Ta applied to the semiconductor body 104 after the second ion implantation process I2-2. The activation heat treatment is configured to electrically activate the first and second dopants 1081, 1082.

[0052] The method for forming the doped region 102 may be further described with reference to the schematic cross-sectional views of the Fig. 3A to 3C. The process characteristics can, for example, be defined according to the Fig. 1C and / or Fig. 2 illustrated process characteristics or according to the process characteristics of Fig. 1C and before the process characteristics of Fig. 2 are executed.

[0053] Referring to Fig. 3A, forming the doped region 102 further comprises forming a semiconductor layer 1041 on the first surface 106 of the semiconductor body 104. Third dopants 1083 are introduced through a surface 1061 of the semiconductor layer 1041 at a second vertical reference level L2 by means of a third ion implantation process I2-3. The third dopants 1083 are implanted along a beam axis 1103 at an angle α3 with respect to the vertical axis on the surface 1061. For example, the angle α3 may deviate by at most 1.5° from a main crystal axis of the semiconductor body 104 along which channeling occurs, e.g., the c-axis in a SiC semiconductor body. The third ion implantation process I2-3 is based on an ion implantation energy E3 and an ion implantation dose D3.

[0054] Referring to Fig. 3B, forming the doped region 102 further comprises applying a second heat treatment T2 to the semiconductor body 104 and the semiconductor layer 1041.

[0055] Referring to Fig. 3C, fourth dopants 1084 are introduced through the surface 1061 of the semiconductor layer 1041 at the second vertical reference level L2 by means of a fourth ion implantation process I2-4. The fourth dopants 1084 are implanted along the beam axis 1104 at an angle α4 with respect to the vertical axis on the surface 1061. For example, the angle α4 may deviate by at most 1.5° from a main crystal axis of the semiconductor body 104 along which channeling occurs, e.g., the c-axis in a SiC semiconductor body. The fourth ion implantation process I2-4 is based on an ion implantation energy E4 and an ion implantation dose D4. An atomic number of the third dopants 1083 may be equal to an atomic number of the fourth dopants 1084.An ion implantation energy E4 of the fourth ion implantation process I2-4 differs by less than 20%, or by less than 10%, or by less than 5% from an ion implantation energy E3 of the third ion implantation process I2-3. An ion implantation dose D4 of the fourth ion implantation process I2-4 differs by less than 20%, or by less than 10%, or by less than 5% from an ion implantation dose D3 of the third ion implantation process I2-3.

[0056] In the Fig. 1A to 1C in combination with Fig. In the example illustrated in FIGS. 3A to 3C, the formation of the doped region 102 was illustrated based on four ion implantation processes I2-1, I2-2, I2-3, I2-4. The four ion implantation processes for forming the doped region 102 are merely exemplary and not limiting in any way. Further ion implantation processes in addition to the first to fourth ion implantation processes I2-1, I2-2, I2-3, I2-4 may be performed to form the doped region 102. The ion implantation process(es) in addition to the ion implantation processes I2-1, I2-2, I2-3, I2-4 may be performed before the ion implantation processes I2-1, I2-2, I2-3, I2-4, between two of them, or after them.For example, one or more semiconductor layers may be formed on the surface 1061 of the semiconductor layer 1041, and two or more additional ion implantation processes may be performed to introduce dopants into each of the one or more semiconductor layers on the semiconductor layer 1041. This allows, for example, a flexible design of a vertical doping concentration profile with respect to profile depth and profile shape. Parameters of the additional ion implantation processes, e.g., ion implantation energy and / or ion implantation dose and / or tilt angle of an ion implantation with respect to the vertical axis, may, for example, be similar to the first to fourth ion implantation processes I2-1, I2-2, I2-3, I2-4.

[0057] The schematic cross-sectional view of Fig. 4 illustrates a configuration example of a semiconductor device 100 including a superjunction structure SJ with an n-doped region 1021 laterally adjacent to a p-doped region 1022. The n-doped region 1021 and / or the p-doped region 1022 may be formed by the process examples described herein for forming the doped region 102. The semiconductor device 100 is schematically illustrated as a vertical power semiconductor device including a first load contact LC1, e.g., a source or emitter electrode, electrically coupled to a transistor cell region 114 via a first side 1151 of the semiconductor device 100. The transistor cell region 114 is simplified by a dashed box, which may include any configuration of transistor cells, e.g., planar or trench gate configurations.The superjunction structure SJ is arranged between the transistor cell region 114 and a second side 1152 of the semiconductor device 100. A control electrode contact C, e.g., a gate pad, is electrically coupled to the transistor cell region via the first side 1151 of the semiconductor device 100. A second load contact LC2, e.g., a drain or collector electrode, is electrically coupled to the semiconductor body 104 via the second side 1152 of the semiconductor device 100.

[0058] The schematic cross-sectional view of Fig. 5 illustrates another example of a semiconductor device 100 configured as an n-channel trench-gate MOSFET including an n-doped current spreading region 116 adjacent to a trench-gate structure 118 comprising a gate dielectric 1181 and a gate electrode 1182. The gate electrode 1182 is electrically connected to the control contact C. The first load contact LC1, e.g., a source contact, is connected via the first side 1151 of the semiconductor device 100 to an n + -doped source region 120 and a p-doped body region 122. The second load contact LC2, e.g., a drain electrode, is electrically coupled to the semiconductor body 104 via a second side 1152 of the semiconductor device 100.

[0059] Fig.Figure 6 is a schematic illustration of simulated channeling profiles of aluminum at an ion implantation energy of 60 keV into the c-axis of a SiC semiconductor body. A concentration profile C1 results from a high-dose implantation (1E15 cm -2 ) and shows a pronounced de-channeling peak at a depth of about 90 nm. A concentration profile C3 is based on the same simulation parameters as the concentration profile C1, but at a 10-fold lower dose (e.g., 1E14 cm -2 ). Here, a more plateau-shaped profile is achieved. A concentration profile C2 is based on the concentration profile C3, but multiplied by a factor of 10. Here, it is assumed that the ion implantation is carried out with a dose of 1E14 cm -2The process is repeated 10 times, with the crystal annealing performed between each implantation process to maintain the crystal structure and enable consistent channeling performance. The hatched area shows how much more aluminum concentration is present at greater depths, and the checkerboard area shows how much the concentration is reduced at the random depth compared to the concentration profile C1. The illustrated separation into ten consecutive implantation and annealing steps is for illustrative purposes only. How often the channeling implantation should be divided into individual steps depends, for example, on the requirements of the technology itself.

[0060] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples provided herein are generally intended for illustrative purposes only to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to advance the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to include their equivalents.

[0061] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent designs may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Forming a doped region (102) in a semiconductor body (104), wherein the formation of the doped region (102) comprises: Introducing first dopants (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by means of a first ion implantation process (I2-1); thereafter Applying a first heat treatment (T1) to the semiconductor body (104); and thereafter Introducing second dopants (1082) through the first surface (106) of the semiconductor body (104) at the first vertical reference level (L1) by means of a second ion implantation process (I2-2), wherein an atomic number of the first dopants (1081) is equal to an atomic number of the second dopants (1082), an ion implantation energy (E2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation energy (E1) of the first ion implantation process (I2-1), and an ion implantation dose (D2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation dose (D1) of the first ion implantation process (I2-1). [2] Method according to the preceding claim, wherein the second dopants (1082) are implanted along a beam axis (1102) which deviates by at most 1.5° from a main crystal axis of the semiconductor body (104) along which channeling takes place. [3] Method according to one of the preceding claims, wherein the first dopants (1081) are implanted along a beam axis (1101) which deviates by at most 1.5° from a main crystal axis of the semiconductor body (104) along which channeling takes place. [4] A method of manufacturing a semiconductor device, the method comprising: Forming a doped region (102) in a semiconductor body (104), wherein the formation of the doped region (102) comprises: Introducing first dopants (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by means of a first ion implantation process (I2-1), wherein the first dopants (1081) are implanted along a beam axis (1101) that deviates by at most 1.5° from a main crystal axis of the semiconductor body (104) along which channeling takes place; thereafter Applying a first heat treatment (T1) to the semiconductor body (104); and thereafter Introducing second dopants (1082) through the first surface (106) of the semiconductor body (104) at the first vertical reference level (L1) by means of a second ion implantation process (I2-2), wherein the second dopants (1082) are implanted along a beam axis (1102) that deviates by at most 1.5° from a main crystal axis of the semiconductor body (104) along which channeling takes place. [5] Method according to one of the preceding claims 2 to 4, wherein the semiconductor body is a SiC semiconductor body and the main crystal axis is the c-axis. [6] A method according to claim 4 or claim 5 in relation to claim 4, wherein an atomic number of the first dopants (1081) differs from an atomic number of the second dopants (1082) and / or an ion implantation energy (E2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation energy (E1) of the first ion implantation process (I2-1) and / or an ion implantation dose (D2) of the second ion implantation process (I2-2) differs by less than 20% from an ion implantation dose (D1) of the first ion implantation process (I2-1). [7] Method according to one of the preceding claims, wherein the second ion implantation energy (E2) is lower than the first ion implantation energy (E1). [8] A method according to any one of the preceding claims, wherein the second ion implantation dose (D2) is less than the first ion implantation dose (D1). [9] A method according to any one of the preceding claims, wherein an ion implantation mask of the first ion implantation process (I2-1) is reused for the second ion implantation process (I2-2). [10] Method according to one of the preceding claims, further comprising: Applying an activation heat treatment to the semiconductor body (104) after the second ion implantation process (I2-2), wherein the activation heat treatment is configured to electrically activate the first and second dopants (1081, 1082), and wherein a maximum temperature of the activation heat treatment is higher than a maximum temperature of the first heat treatment (T1). [11] A method according to the preceding claim, wherein the maximum temperature of the activation heat treatment is more than 400 K higher than the maximum temperature of the first heat treatment. [12] The method of any preceding claim, wherein the maximum temperature of the first heat treatment is configured to heal crystal damage caused by the first ion implantation process (I2-1). [13] Method according to one of the preceding claims, wherein the semiconductor body (104) is a SiC semiconductor body and the maximum temperature of the first heat treatment (T1) has a value of 600°C to 1200°C. [14] A method according to any one of the preceding claims, further comprising ion implantation processes in addition to the first and second ion implantation processes (I2-1, I2-2), wherein each of the ion implantation processes in addition to the first and second ion implantation processes (I2-1, I2-2) is carried out either before the first ion implantation process (I2-1) or after the second ion implantation process (I2-2). [15] Method according to one of the preceding claims, wherein the doped region (102) is a p-doped region (1022) or an n-doped region (1021) of a superjunction structure (SJ) having the p-doped region (1022) laterally bordering the n-doped region (1021). [16] Method according to the preceding claim, wherein the formation of the superjunction structure (SJ) further comprises: Forming a semiconductor layer (1041) on the first surface (106) of the semiconductor body (104); and Introducing third dopants (1083) through a surface (1061) of the semiconductor layer (1041) at a second vertical reference level (L2) by means of a third ion implantation process (I2-3); thereafter Applying a second heat treatment (T2) to the semiconductor body (104) and the semiconductor layer (1041); and thereafter Introducing fourth dopants (1084) through the surface (1061) of the semiconductor layer (1041) at the second vertical reference level (L2) by means of a fourth ion implantation process (I2-4), wherein an atomic number of the third dopants (1083) is equal to an atomic number of the fourth dopants (1084), an ion implantation energy (E4) of the fourth ion implantation process (I2-4) differs by less than 20% from an ion implantation energy (E3) of the third ion implantation process (I2-3), and an ion implantation dose (D4) of the fourth ion implantation process (I2-4) differs by less than 20% from an ion implantation dose (D3) of the third ion implantation process (I2-3). [17] The method of claim 15, wherein forming the superjunction structure (SJ) further comprises: Forming a semiconductor layer (1041) on the first surface (106) of the semiconductor body (104); and introducing third dopants (1083) through a surface (1061) of the semiconductor layer (1041) at a second vertical reference level (L2) by means of a third ion implantation process (I2-3); and introducing fourth dopants (1084) through the surface (1061) of the semiconductor layer (1041) at the second vertical reference level (L2) by means of a fourth ion implantation process (I2-4), wherein the introduction of both the first dopants (1081) and the third dopants (1083) is carried out before the first heat treatment (T1), and wherein the introduction of both the second dopants (1082) and the fourth dopants (1084) is carried out after the first heat treatment (T1). [18] Method according to one of the preceding claims 16 or 17, wherein both the first dopants (1081) and the second dopants (1082) form the n-doped region (1021) of the superjunction structure (SJ); and both the third dopants (1083) and the fourth dopants (1084) form the p-doped region (1022) of the superjunction structure (SJ). [19] The method of any preceding claim, wherein the doped region (102) is an n-doped current spreading region (116) of a power semiconductor device including gate trenches, the current spreading region being adjacent to a bottom side of the gate trenches. [20] A method according to any one of the preceding claims, wherein each of the ion implantation energy (E1) of the first ion implantation process (I2-1) and the ion implantation energy (E2) of the second ion implantation process (I2-2) is greater than 1000 keV. [21] A semiconductor device (100), comprising: the doped region (102) formed by the method according to one of the preceding claims.

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