RESET SYSTEM SETTINGS MEMORY

Abstract

A system (100; 200), comprising: a controller (110; 210); Processing circuits (114; 214) with a processing resource (116; 216) and a system settings memory (118; 218); a battery (120; 220) for backing up the system settings memory (118; 218); and a standard closed relay-based hardware circuit (112; 212) coupled between the battery (120; 220) and system settings memory (118; 218); wherein the controller (110; 210) is coupled to the relay-based hardware circuit (112; 212), wherein the controller (110; 210) is configured to trigger the clearing of the system settings memory (118; 218) of the processing circuit (114; 214) by changing a state of the relay-based hardware circuit (112; 212), wherein the controller (110; 210) is configured to detect that a predetermined time interval has elapsed since the start of the erasure process of the system settings memory (118; 218) of the processing circuit (114; 214), and wherein the controller (110; 210) is configured to trigger a start sequence for the system (100; 200) based on the determination by the controller (110; 210) that the predetermined time interval has elapsed since the start of the deletion process of the system settings memory (118; 218) of the processing circuit (114; 214).

Description

BACKGROUND

[0001] Various CPU-based products (e.g., systems-on-a-chip (SoC)) have a small memory (e.g., a CMOS (Complementary Metal-Oxide-Semiconductor) area) that stores basic system settings (e.g., BIOS (Basic Input / Output System) settings, UEFI (Unified Extensible Firmware Interface) settings, and / or other basic system settings). This memory can be referred to as system settings memory. The system settings memory may be located on the motherboard of a computer device or integrated into the SoC / CPU. The basic system settings may be part of, or used by, software such as the BIOS, UEFI, or other low-level software or firmware that is configured to instruct a computer device / system to perform a set of basic functions, such as booting and keyboard control.The aforementioned basic system settings can also be used to identify and configure the hardware in the computer device / system.

[0002] US Patent 6,253,319 B1 discloses a computer system with a multi-function power switch. In addition to its normal function of turning the computer on and off, the power switch has the additional function of clearing the CMOS memory. Pressing the power switch while the computer is connected to a power source turns the computer on and off, and when the computer is disconnected from the power source, the CMOS memory can be cleared by pressing and holding the power switch for a predetermined time delay, e.g., 10 seconds. US Patent 2004 / 0064686 A1 relates to a method and device for marking the current memory configuration, wherein an enhanced Basic Input / Output System (BIOS) is introduced to initialize the system memory during a first boot process and to store the initialization settings in non-volatile memory for use during a subsequent boot process. OVERVIEW OF THE INVENTION

[0003] It is an object of the present invention to enable the simple and efficient resetting of a system settings memory in computer systems in order to correct a problem with the settings stored in the system settings memory. This object is achieved by a system according to claim 1, a method according to claim 7, and by a non-transitory, computer-readable storage medium according to claim 16. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Several examples are described below with reference to the following figures. Fig. Figure 1 is a block diagram of an exemplary computer device / system in accordance with some implementations of the present disclosure. Fig. 2 is a block diagram of an example configuration of the computer device / system of Fig. 1, in accordance with an implementation of the present disclosure. Fig. Figure 3 is a flowchart showing an illustrative procedure for resetting a system settings memory in accordance with an example implementation of the present disclosure. Fig. Figure 4 is a flowchart illustrating a procedure for resetting a system settings memory in accordance with an example implementation of the present disclosure. Fig. Figure 5 is a flowchart showing an illustrative procedure for resetting a system settings memory according to an example implementation of the present disclosure. Fig. Figure 6 is a block diagram showing an example of a computer device / system in accordance with some implementations of the present disclosure.

[0005] In the drawings, identical reference numerals denote similar, but not necessarily identical, elements. Furthermore, the drawings contain examples and / or embodiments that correspond to the description; however, the description is not limited to the examples and / or embodiments shown in the drawings. DETAILED DESCRIPTION

[0006] To power on a device or system efficiently and with minimal boot time, the device / system stores settings in system settings memory based on the hardware configurations from the last boot or, in the case of the device / system's first boot, based on the system's default settings. If a problem occurs with any of the stored settings, such as due to system settings memory corruption or user error, it can lead to performance degradation, loss of functionality, incomplete booting, complete boot failure, and / or other problems that prevent the device / system from functioning as intended. Causes of corruption can include, but are not limited to, electrostatic discharge (ESD), BIOS system updates, and replaced DRAM modules.

[0007] One way to resolve a problem with settings stored in the system settings memory is to reset the memory device to its default settings. In some cases, the system settings memory must also be reset as part of a manufacturing process (regardless of whether a problem is detected), for example, when the device / system is first powered on, or during or after validation, testing, or configuration of the device / system. Generally, resetting the system settings memory in this way requires removing and reinserting the battery that supports the system settings memory.More specifically, in some devices / systems, the battery can ensure that system settings remain stored in memory even when the device / system's main power supply is turned off. When this battery is removed (and the main power supply is off), the resulting loss of power to the system settings memory causes the data stored therein to be erased. The next time the device / system is turned on, the CPU detects that the system settings memory has been cleared and then starts with the default system values ​​that can be stored in the system settings memory instead of the previous values ​​erased by removing the battery (this is referred to here as "resetting" the system settings memory).

[0008] In some cases, it may even be necessary to send the computer device back to the ODM, where it can be at least partially disassembled, the battery removed and reinserted, and the computer reassembled. This is not only inconvenient for those using the computer devices on-site, but also involves significant financial and time expenditure. Even with devices where the battery is more easily accessible, the user still has to invest time and effort to replace it. If a reset is required during the manufacturing process, additional personnel or robots trained or configured to perform this process may be needed, increasing the complexity and cost of manufacturing and introducing the risk of additional damage, such as from electrostatic discharge.

[0009] To address the aforementioned issues, this disclosure provides a method for clearing / resetting a CPU's system settings memory without requiring the removal and reinstallation of the battery that backs up the system settings memory. A relay-based hardware circuit can be placed between the computer device's CPU system settings memory and the battery that backs up the system settings memory. The relay-based circuit can be configured to power the system settings memory in a default closed or connected position, or to cut off power from the battery to the system settings memory in an open or disconnected position. A control device configured to manage the power sequence of the computer device's motherboard can control the state of the relay-based circuit.The control unit can be the first component of the motherboard to receive power when it is applied. Before power is supplied to other components of the motherboard, the controller can be configured to determine whether a memory clear / reset is necessary or desired. The control unit can make such a determination based on receiving one or more corruption or other error messages, a user request to clear the system settings memory, or other criteria (such as it being the first time the system is booted).Based on the determination that clearing the system settings memory is necessary or desired, the controller can be configured to toggle a switch in the relay-based circuit from its default closed position to the open position for a predetermined period of time. This interrupts the power supply from the battery to the system settings memory area. In some embodiments, the predetermined period may be sufficient to ensure that any residual electrical charge temporarily stored in the system settings memory circuit dissipates, leaving the system settings memory completely de-energized (e.g., two seconds or less in some examples and / or more than 20 milliseconds in others). This results in the erasure of the data stored in the system settings memory.Once the predetermined time period has elapsed, the control unit can be configured to switch the relay-based circuit from the open position back to the closed position, thus restoring power from the battery to the system settings memory. From the CPU's perspective, this switching of power via the relay has the same effect as removing and replacing the battery, causing the CPU to reset the system settings memory to its default values ​​after the boot process resumes. This achieves the desired effect of resetting the system memory without the need to manually remove and reinsert the battery.

[0010] The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and in the following description to indicate identical or similar parts. However, it is expressly stated that the drawings are for illustration and description purposes only. Although several examples are described in this document, modifications, adaptations, and other embodiments are possible. Accordingly, the following detailed description does not limit the disclosed examples. Instead, the proper scope of the disclosed examples can be defined by the accompanying claims.

[0011] Fig. Figure 1 is a block diagram of a computer device 100 (e.g., a network device) according to some implementations of the present disclosure. The computer device 100 comprises a controller 110, a relay-based hardware circuit 112 coupled to the controller 110, and a processing circuit 114. The controller 110 can contain any dedicated hardware (e.g., an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), etc.) and can be configured to control the power sequencing of the mainboard (not shown) of the computer device 100.

[0012] The processing circuit 114 comprises a processing resource 116 (e.g., a processor, a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), etc.) and a system settings memory 118. The system settings memory 118 may be integrated internally into the processing resource 116 or, as shown, be located outside of the processing resource 116. The system settings memory 118 may be configured to store basic system settings for the computer device 100. The basic system settings may be part of software (e.g., BIOS, UEFI, etc.) that is configured to instruct, or used by, the computer device 100 on how to perform basic functions such as booting and keyboard control. The basic system settings may also be used to identify and configure the hardware in the computer device 100.

[0013] The computer device 100 further includes a battery 120, which backs up the system settings memory 118 and is arranged such that the relay-based hardware circuit 112 is inserted into the power supply path between the battery 120 and the system settings memory 118. The battery 120 can be configured to power the system settings memory (via the relay 112) to ensure that the basic system settings remain stored in the system settings memory 118 when the system settings memory 118 is not powered by the main computer.However, relay 112 may be able to selectively interrupt the current flow from the battery under certain conditions (which are described in more detail below), so that battery 120 cannot power system setting memory 118 when the main computer is not powered, and thus the basic system settings stored in system setting memory 118 are erased and reset to default settings.

[0014] The control unit 110 can be configured to initiate the clearing of the system settings memory 118 using the relay-based hardware circuit 112. In this respect, the control unit 110 can be configured to control the power supply sequencing of the mainboard (not shown) of the computer device 100 and, accordingly, control the state of the relay-based hardware circuit 112. When power is applied to the mainboard (not shown) of the computer device 100 and received by a power supply subsystem 122 of the computer device 100, initialization current (init_pwr) is supplied to the control unit 110 to initialize the computer device 100 before the processing circuit 114 is fully powered. The initialization current (init_pwr) can also be supplied to the relay-based hardware circuit 112, as described below.The term "power supply subsystem" used here generally refers to all devices that collectively supply power to the computer 100. This may include a power supply unit (PSU) and a number of power rails (which in turn may include current transformers or other power supply devices), with the power rails supplying different forms of power to different components of the computer as needed (e.g., there may be a 12V power rail, a 5V power rail, a 3V power rail, etc.). The connections of the power supply subsystem 122 to other components are shown in [reference missing]. Fig. 1 has been omitted to simplify the description.

[0015] Before the power supply subsystem 122 is allowed to supply power to other components of the computer device (e.g., the processing circuit 114, etc.), the control unit 110 can be configured to determine whether a memory clear / reset is required or desired. In some implementations, the control unit 110 can make such a determination based on receiving one or more corruption or other error messages, based on receiving a request from a user to clear the system settings memory, or based on the fact that the current power-on is the first power-on of the control unit 110 and / or the computer device 100.In the event that a clearing / resetting of the system settings memory 118 is required or desired because the current power-on is the first power-on of the control unit 110 and / or the computer device 100, the power-on history of the control unit 110 can be examined. In one implementation, it can be determined whether the current power-on is the first power-on for the control unit 110 and / or the computer device 100 by querying an internal non-volatile memory 124 of the control unit 110, where the internal non-volatile memory 124 is configured to store the power-on history of the control unit 110 / computer device 100.

[0016] Based on the determination that clearing the system settings memory is required or desired, the control unit 110 can be configured to send a memory clear signal (mem_clr) to the relay-based hardware circuit 112, requesting the circuit 112 to clear the system settings memory 118. Upon receiving the request, the relay-based hardware circuit 112 can be configured to switch a switch 126 within the circuit 112 from its default closed position to an open position for a predetermined time period, measured by a timer 128 of the control unit 110. As a result, the power supply (bat_pwr) from the battery 120 to the relay-based circuit 112, and consequently from the relay-based circuit 112 to the system settings memory 118, can be interrupted.In some embodiments, the predetermined time interval can be a period sufficient to ensure that any electrical charge temporarily stored in the system setting memory circuit 118 is dissipated, so that the system setting memory 118 is de-energized (e.g., two seconds or less in some examples; greater than or equal to 20 milliseconds in some examples; between 20 milliseconds and two seconds in some examples). Once the predetermined time interval has elapsed, the control unit 110 can be configured to switch the switch 126 of the relay-based circuit 112 from the open position back to the default closed position, thereby restoring power from the battery 120 to the system setting memory 118.The control unit 110 can, in turn, increment the counter for the card's power-on history in its non-volatile memory 124 for future use. Once the system settings memory 118 has been cleared, the power-on sequence for all other rails can be performed as usual.

[0017] Fig. Figure 2 is a block diagram of a computer device 200. The computer setup 200 is a sample configuration of the computer setup 100. Fig. 1 according to an implementation of the present disclosure. In particular, the computer device 200 comprises a power supply subsystem (not shown) which is an example configuration of the power supply subsystem 122. In this example, the power supply subsystem includes a power supply unit (PSU) 251 which receives input power from outside the computer device (e.g., from a main power supply) and converts it into a system power signal sys_power suitable for use by various components of the computer device. The power supply unit 251 can, for example, receive alternating current and convert it to direct current. In one example, the sys_power signal is a 12 V DC signal. The power supply subsystem also includes a number of power rails, including an early power rail 252 and a system settings memory power rail 253 (additional power rails not shown may also be present, such as...).a rail for powering the processing resource 216). The power supply 251 delivers the sys_power signal to each of the power rails, and each power rail may contain a DC-DC power conversion circuit to convert the received sys_power signal into a different power signal suitable for a particular component or subset of components of the computer device 200. For example, the early power rail 252 and the system settings memory power rail 253 can convert the sys_power signal at 12 V DC into init_pwr and mem_pwr signals, respectively. In some examples, these signals may be 3 V DC power signals. The power rails are generally able to selectively deliver their power output signals only when instructed to do so by the control unit 210, for example, by an enable signal (e.g., pwr_enable).The first power rail 252 is an exception, as it is always activated and therefore provides the init_pwr signal when the power supply 251 provides the sys_pwr signal.

[0018] Therefore, when power supply 251 is supplied with external power, it can supply all rails with sys_pwr, but initially, with the exception of the early power rail 252, the rails do not supply any power to the downstream components because they have not yet been enabled by the controller 210. The early power rail, however, immediately begins supplying init_pwr. When the controller 210 receives init_pwr, it begins its power-up sequence and, in this context, performs the operations described above with respect to the controller 110. That is, the controller 210 determines whether a reset of the system settings memory 218 is required, and if so, the controller 210 sends the mem_clr signal to the relay-based hardware circuit 212 to initiate the reset as described above.If, however, control unit 210 determines that no reset is required, it can output the power_enable signal to each of the rails to enable them to supply output power. For example, if the power supply rail for the system settings memory receives the pwr_enable signal, it will begin providing the mem_pwr output signal.

[0019] As in Fig. As shown in Figure 2, the current output bat_pwr from battery 220 is supplied to the relay-based hardware circuit 212, and the relay-based hardware circuit 212 outputs this bat_pwr signal when switch 226 is in the closed state. The relay-based hardware circuit 212 is controlled to change the state of switch 226 based on the mem_clr signal as described above.

[0020] As in Fig. As shown in Figure 2, the computing device can also include an OR circuit 260. The OR circuit 260 can receive the bat_pwr signal output by the relay-based hardware circuit 212 and the mem_pwr signal from the system settings memory power rail 253 and selectively supply either one or the other to the system settings memory 218 to power it. Thus, under normal operating conditions, when the system settings memory power rail 253 is enabled, the system settings memory 218 can be powered by the mem_pwr signal. However, if the power supply fails, mem_pwr is interrupted, and the OR circuit 260 can instead supply the bat_pwr signal from the battery to the system settings memory 218, ensuring that it retains its settings. Similarly, if bat_pwr fails while mem_pwr is still present, mem_pwr can be added.To clear the system settings memory 218, both bat_pwr and mem_pwr must be removed simultaneously. This is achieved in the examples disclosed here by toggling the switch 226 of the relay-based hardware circuit 212 while the computer device is in a state where the power rail 253 for the system settings memory is not enabled (e.g., during startup, but before the controller 210 sends the pwr_enable signal so that the full boot sequence can continue).

[0021] Fig. Figure 3 is a flowchart illustrating an example procedure 300 for resetting a system settings memory (e.g., system settings memory 118 and / or 218) of the processing circuit (e.g., processing circuit 114 and / or 214) of a computer device. Procedure 300 can be performed, for example, by the computer devices 100 and 200 described above. In step 310, it can be determined that a system settings memory reset is required or desired. For example, it can be determined that a system settings memory reset is required or desired based on receiving a system settings memory reset request, based on the finding that an error occurred during the execution of a boot sequence for the computer device, and / or based on the finding that a controller and / or the computer device was not previously booted (e.g.,by querying an internal non-volatile memory of the controller, which is configured to store the power-on history of the computer device).

[0022] In step 312, the system settings memory can be cleared at a control unit coupled to a relay-based hardware circuit (e.g., at control unit 110, 210 of relay-based hardware circuit 112, 212). In one implementation, the control unit can initiate the system settings memory clearing using the relay-based hardware circuit by switching a switch (e.g., switch 126 and / or 226) of the circuit from a closed or connected state to an open or disconnected state for a predetermined period of time (e.g., less than two seconds). When the switch of the relay-based hardware circuit is in the closed state, a battery coupled to it (e.g.,The battery (120 and / or 220) is able to power the system settings memory, and when the circuit's switch is in the open state, the battery is unable to power the system settings memory. Furthermore, the switch changes to the open state while a power rail supplying the system settings memory is not currently supplying power (e.g., before the controller activates such a supply). Therefore, when the switch opens, no current flows to the system settings memory.

[0023] In step 314, based on the detection that the predetermined time interval has elapsed since the system settings memory clearing process was initiated, procedure 300 can proceed with a boot sequence for the computer device. In some examples, the control unit causes the computer device to proceed with the boot sequence by releasing power from the power supply subsystem to the other components of the device, for example, by sending enable signals (such as `pwr_enable`) to the power rails that supply these components. Additionally, the controller can toggle the switch of the relay-based hardware circuit from the open or disconnected state to the closed or connected state when it detects that the predetermined time interval has elapsed. Furthermore, proceeding with the boot sequence can cause the computer device to reset the system settings memory to its default settings.This means that as soon as the processing resource begins to boot up and detects that the system settings memory has been cleared, the processing resource can automatically reset the settings to their default values ​​as part of its boot sequence.

[0024] Fig. Figure 4 is a flowchart illustrating another example procedure 400 for resetting a system settings memory (e.g., system settings memory 118 and / or 218) of the processing circuit (e.g., processing circuit 114 and / or 214) of a computer device. Procedure 400 can be performed, for example, by the computer devices 100 and 200 described above. In step 410, the power-on history of a controller (e.g., controller 110 and / or 210) of the computer device can be examined to determine whether the current power-on is the first power-on for the controller and / or the computer device. In one implementation, it can be determined whether the current power-on is the first power-on for the controller and / or the computer device by querying an internal non-volatile memory of the controller, where the internal non-volatile memory is configured to store the power-on history of the computer device.

[0025] If, in step 412, it is determined that the current power-on is not the first power-on of the control unit and / or computer device, procedure 400 can proceed with a boot sequence for the computer device, as shown in step 418. Alternatively, after the determination in step 412 that the current power-on is the first power-on for the control unit and / or computer device, a system settings memory clearing can be initiated in step 414. In one implementation, the control unit can initiate the system settings memory clearing using a relay-based hardware circuit (e.g., relay-based hardware circuit 112 and / or 212) by switching a switch (e.g., switch 126 and / or 226) of the circuit from a closed or connected state to an open or disconnected state for a predetermined period of time (e.g., less than two seconds).In particular, the operations described above in relation to step 312 of procedure 300 can be carried out.

[0026] In step 416, procedure 400 can wait for the predetermined time interval since the system settings memory clearing process to elapse, and in step 418, after determining that the predetermined time interval has elapsed, proceed with a boot sequence for the computer device. Additionally, the controller can also toggle the switch of the relay-based hardware circuit from the open or disconnected state to the closed or connected state when it determines that the predetermined time interval has elapsed. Furthermore, proceeding with the boot sequence can cause the computer device to reset the system settings memory to its default settings.This means that as soon as the processing resource begins to boot up and detects that the system settings memory has been cleared, the processing resource can automatically reset the settings to their default values ​​as part of its boot sequence.

[0027] Fig. Figure 5 is a flowchart illustrating another example procedure 500 for resetting a system settings memory (e.g., system settings memory 118 and / or 218) of the processing circuit (e.g., processing circuit 114 and / or 214) of a computer device. Procedure 500 can be performed, for example, by the computer devices 100 and 200 described above.

[0028] In step 510, a controller (e.g., controller 110 and / or 210) of the computer device can be powered. In step 512, the control unit can initiate a clearing of a system settings memory of the computer device using a relay-based hardware circuit (e.g., relay-based hardware circuit 112 and / or 212) located in a power supply path between the system settings memory and a battery (e.g., battery 120 and / or 220) that supports the system settings memory. In one implementation, the controller can initiate the clearing of the system settings memory using a relay-based hardware circuit (e.g., relay-based hardware circuit 112 and / or 212) by switching a switch (e.g., switch 126 and / or 226) of the circuit from a closed or connected state to an open or disconnected state for a predetermined period of time (e.g., 10 seconds).initiate (less than two seconds).

[0029] In step 514, procedure 500 can proceed with a boot sequence for the computer device based on the determination that a predetermined amount of time has elapsed since the system settings memory clearing process was initiated. In one implementation, the controller can be configured to cause the computer device to proceed with the boot sequence by switching the relay-based hardware circuit's switch from the open or disconnected state to the closed or connected state after determining that the predetermined amount of time has elapsed.

[0030] Fig. Figure 6 is a block diagram showing an example of a computer device / system 600 in accordance with some implementations of the present disclosure. In the Fig. In the example shown in Figure 6, the computer device / system 600 comprises a processing resource 610 coupled to a non-transitory, computer-readable medium 612 encoded with instructions for performing a system settings memory reset. The processing resource 610 may include a microcontroller, a microprocessor, core(s) of a central processing unit, core(s) of a graphics processing unit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), and / or other hardware device capable of retrieving and / or executing instructions from the computer-readable medium 612 to cause the execution of the functions relating to various examples described herein. Additionally or alternatively, the processing resource 610 may include an electronic circuit for performing the functionality of the instructions described herein.

[0031] The computer-readable medium 612 can be any medium suitable for storing executable instructions. Non-restrictive examples of computer-readable media 612 are RAM, ROM, EEPROM, flash memory, a hard disk drive, an optical disk, or the like. The computer-readable medium 612 can be located within the computer device 600, as shown in Fig. Figure 6 shows in which case the executable instructions can be considered "installed" or "embedded" in the computer device 600. Alternatively, the computer-readable medium 612 can be a portable (e.g., external) storage medium and part of an "installation package." The instructions stored on the computer-readable medium 612 can be useful for implementing at least the procedures described herein (e.g., those in the Fig. 3, Fig. 4 and Fig. 5 procedures shown).

[0032] In the context of the present example, the computer-readable medium 612 is encoded with a set of executable instructions 614-628. It is understood that some or all of the executable instructions and / or electronic circuits contained in one block may be contained in alternative implementations in another block shown in the figures or in another block not shown.

[0033] Instructions 614, when executed, can cause processing resource 610 to detect that power has been received at a controller of a computer device. In one implementation, instructions 614 can be used to execute block 510 of Fig. 5 can be useful.

[0034] Instructions 616, when executed, can cause processing resource 610 to determine that a system memory reset is necessary or desired. In one implementation, instructions 616 can be used to execute block 310 of Fig. 3. be useful.

[0035] Instructions 618, when executed, can cause processing resource 610 to determine that a system settings memory reset is necessary or desired by detecting that no power was previously supplied to the control unit. In implementations, instructions 618 can be used to execute block 310 of Fig. 3 and / or Block 412 of Fig. 4 can be useful.

[0036] Instruction 620, when executed, can cause processing resource 610 to determine that a system memory reset is necessary or desirable by detecting that an error occurred during the execution of a boot sequence for the computer device. In one implementation, instruction 620 can be used to execute block 310 of Fig. 3. be useful.

[0037] During execution, instructions 622 can cause processing resource 610 to determine whether a system settings memory reset is necessary or desired by receiving a system settings memory reset request. In one implementation, instructions 622 can be executed during block 310 of Fig. 3. be useful.

[0038] Instructions 624, when executed, can cause processing resource 610 to initiate the clearing of the computer device's system settings memory. In implementations, instructions 624 can occur when executing block 312 of Fig. 3, Block 414 of Fig. 4 and / or Block 512 of Fig. 5 can be useful.

[0039] Instructions 626, when executed, can cause processing resource 610 to determine that a predetermined amount of time has elapsed since the system settings memory clearing process was initiated. In one implementation, instructions 626 can, when executed, cause block 416 of Fig. 4 can be useful.

[0040] Instructions 628, upon execution, can cause processing resource 610 to proceed with a boot sequence for the computer device, based on the determination that the predetermined time interval has elapsed since the system settings memory clearing process was initiated. In implementations, instructions 628 can be executed during block 314 of Fig. 3, Block 418 of Fig. 4 and / or Block 514 of Fig. 5 can be useful.

[0041] The technology described here comprises various steps, examples of which were given above. As described earlier, these steps can be performed by hardware components or embodied in computer-executable instructions that can be used to instruct a processing resource (e.g., a processor) programmed with the instructions to execute the steps. Alternatively, at least some steps can be performed by a combination of hardware, software, and / or firmware.

[0042] The technology described here can be provided as a computer program product, which may include a tangible, computer-readable storage medium on which instructions are embodied that can be used to program a computer (or other electronic devices) to perform a process. The computer-readable medium may include, but is not limited to, hard disk drives, magnetic tapes, floppy disks, optical disks, compact disc read-only storage (CD-ROMs), magneto-optical disks, semiconductor memory such as ROMs, PROMs, random-access memory (RAMs), programmable read-only memory (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), flash memory, magnetic or optical cards, or other types of media / computer-readable media suitable for storing electronic instructions (i.e., computer programming code, such as software or firmware).

[0043] This technical description presents numerous specific details to enable a comprehensive understanding of the example implementations. However, it will be clear to a person skilled in the art that the implementations described here can also be carried out without some of these specific details. In other cases, known structures and devices are represented in the form of block diagrams.

[0044] The terminology used here serves only to describe examples and is not intended to be restrictive. The singular forms "ein," "ein," and "die" used here also include the plural forms, unless the context clearly indicates otherwise. The term "plural" used here is defined as two or more than two. The term "and / or," as used here, refers to and includes all possible combinations of one or more of the listed elements. The term "umfasst" used here means "includes but is not limited to," and the term "klusiv" means "including but not limited to." The term "basierend auf" means at least partially based on.If the specification states that a component or feature "may be included," "may," "could," or "might" be included, this does not mean that particular component or feature is included or possesses the feature. As used in this description, the meaning of "in" includes both "in" and "at" unless the context clearly indicates otherwise.

[0045] Various methods described herein can be performed by combining one or more computer-readable storage media containing the code according to the exemplary embodiments described herein with suitable standard computer hardware for executing the code contained therein. An apparatus for performing various embodiments described herein may comprise one or more computing elements or computers (or one or more processors within a single computer) and storage systems containing or network-accessible computer programs coded according to various methods described herein, and the method steps of various embodiments described herein may be performed by modules, routines, subroutines, or subparts of a computer program product.

Claims

[1] A system (100; 200), comprising: a controller (110; 210); Processing circuits (114; 214) with a processing resource (116; 216) and a system settings memory (118; 218); a battery (120; 220) for backing up the system settings memory (118; 218); and a standard closed relay-based hardware circuit (112; 212) coupled between the battery (120; 220) and system settings memory (118; 218); wherein the controller (110; 210) is coupled to the relay-based hardware circuit (112; 212), wherein the controller (110; 210) is configured to trigger the clearing of the system settings memory (118; 218) of the processing circuit (114; 214) by changing a state of the relay-based hardware circuit (112; 212), wherein the controller (110; 210) is configured to detect that a predetermined time interval has elapsed since the start of the erasure process of the system settings memory (118; 218) of the processing circuit (114; 214), and wherein the controller (110; 210) is configured to trigger a start sequence for the system (100; 200) based on the determination by the controller (110; 210) that the predetermined time interval has elapsed since the start of the deletion process of the system settings memory (118; 218) of the processing circuit (114; 214). [2] System (100; 200) according to claim 1, wherein the controller (110; 210) is configured to initiate the clearing of the system settings memory (118; 218) of the processing circuit (114; 214) by controlling the state of the relay-based hardware circuit (112; 212) by switching a switch (126; 226) of the relay-based hardware circuit (112; 212) from a closed state to an open state for a predetermined period of time, wherein the battery (120; 220) is configured in the closed state to power the system settings memory (118; 218) and in the open state the battery (120; 220) is configured not to power the system settings memory (118; 218). [3] System (100; 200) according to claim 2, wherein the controller (110; 210) is configured to cause a boot sequence for the system (100; 200) to proceed by switching the switch (126; 226) of the relay-based hardware circuit (112; 212) from the open state to the closed state when it detects that the predetermined time interval has elapsed. [4] System (100; 200) according to claim 2, wherein the specified time interval is greater than or equal to 20 ms. [5] System (100; 200) according to claim 1, wherein the controller (110; 210) is configured to initiate the clearing of the system settings memory (118; 218) of the processing circuit (114; 214) by controlling the state of the relay-based hardware circuit (112; 212) in a state in which no current is supplied from a power supply subsystem (122; 251) to the system settings memory (118; 218) of the processing circuit (114; 214). [6] System (100; 200) according to claim 1, wherein the system settings memory (118; 218) comprises a complementary metal oxide semiconductor, CMOS. [7] A method (300) for resetting a system settings memory (118; 218) of a processing circuit (114; 214) of a computer device (100; 200), the method comprising: Determine (310), by means of a controller (110; 210), to reset the system settings memory (118; 218); Triggering (312), by the controller (110; 210), which is coupled to a normally closed relay-based hardware circuit (112, 212) coupled between the system settings memory (118; 218) and a battery (120; 220) that supports the system settings memory (118; 218), of clearing the system settings memory (118; 218) of the processing circuit (114; 214) of the computer device (100; 200) by changing a state of the relay-based hardware circuit (112; 212); Determine, by the controller (110; 210), that a predetermined time interval has elapsed since the initiation of the deletion of the system settings memory (118; 218) of the processing circuit (114; 214) of the computer device (100; 200), and Cause (314), by the controller (110; 210), based on the determination by the controller (110; 210) that the predetermined time interval has elapsed since the initiation of the deletion of the system settings memory (118; 218) of the processing circuit (114; 214) of the computer device (100; 200), that a boot sequence for the computer device (100; 200) is to proceed. [8] Method (300) according to claim 7, wherein the determination to reset the system settings memory (118; 218) comprises receiving a request to reset the system settings memory (118; 218) of the processing circuit (114; 214) of the computer device (100; 200) at the controller (110; 210). [9] Method (300) according to claim 7, wherein the determination to reset the system settings memory (118; 218) includes the determination that an error has occurred during the execution of the startup sequence for the computer device (100; 200). [10] Method (300) according to claim 7, wherein the provision to reset the system settings memory (118; 218) includes the provision that the computer device (100; 200) has never been booted before. [11] Method (300) according to claim 7, wherein initiating the erasure of the system settings memory (118; 218) of the processing circuit (114; 214) of the computer device (100; 200) comprises switching a switch (126; 226) of the relay-based hardware circuit (112; 212) from a closed state to an open state for the predetermined period of time, wherein the battery (120; 220) is configured in the closed state to power the system settings memory (118; 218) and the battery (120; 220) is configured in the open state not to power the system settings memory (118; 218). [12] Method (300) according to claim 11, wherein the method (300) further comprises switching the switch (126; 226) of the relay-based hardware circuit (112; 212) from the open state to the closed state based on the finding that the predetermined time interval has elapsed. [13] Method (300) according to claim 7, wherein the erasure of the system settings memory (118; 218) of the processing circuit (114; 214) of the computer device (100; 200) is initiated by controlling the state of the relay-based hardware circuit (112; 212) in a state in which a power supply subsystem (122; 251) does not supply power to the system settings memory (118; 218) of the processing circuit (114; 214). [14] Method (300) according to claim 7, wherein the system settings memory (118; 218) comprises a CMOS. [15] Method (300) according to claim 7, wherein the specified time interval is greater than or equal to 20 ms. [16] A non-transitory, computer-readable storage medium on which a set of computer-executable instructions (500) is stored to cause one or more processing resources of a controller (110; 210) of a computer system (100; 200): are powered at the controller (110; 210) (510); initiating the deletion of a system settings memory (118; 218) of the computer system (100; 200) by the controller (110; 210) (512) by controlling a state of a relay-based hardware circuit (112; 212) located in a power supply path between the system settings memory (118; 218) and a battery (120; 220) that supports the system settings memory (118; 218); by the controller (110; 210) determine that a predetermined time period has elapsed since the start of the deletion of the system settings memory (118; 218) of the computer system (100; 200); and based on the finding that a predetermined period of time has elapsed, proceed with a boot sequence for the computer system (100; 200) (514). [17] Computer-readable storage medium according to claim 16, wherein the set of computer-executable instructions (500) causes one or more processing resources to initiate the erasure of the system settings memory (118; 218) of the computer system (100; 200) using the relay-based hardware circuit (112, 212) by switching a switch (126; 226) of the relay-based hardware circuit (112; 212) from a closed state to an open state for the predetermined period of time, wherein the battery (120; 220) can supply power to the system settings memory (118; 218) in the closed state and the battery (120; 220) cannot supply power to the system settings memory (118; 218) in the open state. [18] Computer-readable storage medium according to claim 17, wherein the set of computer-executable instructions (500) causes the one or more processing resources to switch the switch (126; 226) of the relay-based hardware circuit (112; 212) from the open state to the closed state based on the finding that the predetermined time period has elapsed. [19] Computer-readable storage medium according to claim 16, wherein triggering the deletion of the system settings memory (118; 218) of the computer system (100; 200) causes one or more system settings to be reset to a default system setting. [20] Computer-readable storage medium according to claim 16, wherein the set of computer-executable instructions (500) causes the one or more processing resources to initiate the deletion of the system settings memory (118; 218) of the computer system (100; 200) based on the determination from an internal non-volatile memory of the controller (110; 210) that the controller (110; 210) has not previously received any power.

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