Resistive random access memory and memory mini-array with improved reliability

Abstract

A memory element comprises a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first resistive memory element, and a second resistive memory element. The first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor each have a drain terminal, a source terminal, and a gate terminal. The drain terminal of the third switching transistor is coupled to the source terminal of the first switching transistor. The drain terminal of the fourth switching transistor is coupled to the source terminal of the second switching transistor. The first resistive memory element is coupled to the source terminal of the fourth switching transistor and the source terminal of the first switching transistor. The second resistive memory element is coupled to the source terminal of the third switching transistor and the source terminal of the second switching transistor.

Description

Background of the invention 1. Field of the invention

[0001] The disclosure relates to a resistive random access memory and a memory mini-array, and more particularly to a resistive random access memory and a memory mini-array with improved reliability. 2. Description of the state of the art

[0002] Thanks to advances in memory technology, resistive random access memories (RRAMs) are now available. A resistive memory can contain a resistive storage element. By applying a voltage, the resistance of the resistive storage element can be changed, allowing data to be written and erased using the resistive storage element.

[0003] However, current resistive memory elements have many shortcomings. For example, the resistance of a conventional resistive memory is difficult to distinguish after many write and read operations (e.g., 100,000 times). Therefore, the data stored in the memory is difficult to read correctly after multiple accesses, resulting in insufficient reliability. In addition, current resistive memory devices form the same electrodes of different resistive memory elements at opposite ends, requiring numerous complicated circuits and making it difficult to reduce the memory area.

[0004] US 2023 / 0164970 A1, US 2019 / 0341109 A1, US 2021 / 0398618 A1, DE 10 2018 123 822 A1, DE 10 2018 124 716 A1 and DE 11 2022 003 362 T5 relate to memory devices including transistors.

[0005] The task is to improve the reliability of the memory and the memory mini-array.

[0006] The object is achieved by a memory according to patent claim 1 and a memory mini-array according to patent claim 16. Further embodiments emerge from the dependent patent claims. Summary of the invention

[0007] One embodiment provides a memory comprising a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first resistive storage element, and a second resistive storage element. The first switching transistor may have a drain terminal, a source terminal, and a gate terminal. The second switching transistor may have a drain terminal, a source terminal, and a gate terminal. The third switching transistor may have a drain terminal directly connected to the source terminal of the first switching transistor, a source terminal, and a gate terminal. The fourth switching transistor may have a drain terminal directly connected to the source terminal of the second switching transistor, a source terminal, and a gate terminal.The first resistive storage element may have a first terminal directly connected to the source terminal of the fourth switching transistor and a second terminal directly connected to the source terminal of the first switching transistor. The second resistive storage element may have a first terminal directly connected to the source terminal of the third switching transistor and a second terminal directly connected to the source terminal of the second switching transistor.

[0008] Another example of the first embodiment further provides a memory comprising a first diffusion layer, a second diffusion layer, a first polysilicon layer, a second polysilicon layer, a first resistive memory element, and a second resistive memory element. The first diffusion layer may be formed along a first direction. The second diffusion layer may be formed along the first direction. The first polysilicon layer may be formed along a second direction and at least partially overlap with the first diffusion layer and the second diffusion layer, wherein the first direction is substantially perpendicular to the second direction. The second polysilicon layer may be formed along the second direction and at least partially overlap with the first diffusion layer and the second diffusion layer.The first resistive storage element can be formed at least partially overlapping the first diffusion layer and between the first polysilicon layer and the second polysilicon layer. The second resistive storage element can be formed at least partially overlapping the second diffusion layer and between the first polysilicon layer and the second polysilicon layer.

[0009] Another example of the first embodiment further provides a memory mini-array comprising a first diffusion layer, a second diffusion layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, a fourth polysilicon layer, a first resistive memory element, a second resistive memory element, a third resistive memory element, and a fourth resistive memory element. The first diffusion layer may be formed along a first direction. The second diffusion layer may be formed along the first direction. The first polysilicon layer may be formed along a second direction and at least partially overlap with the first diffusion layer and the second diffusion layer, wherein the first direction is substantially perpendicular to the second direction.The second polysilicon layer may be formed along the second direction and at least partially overlap the first diffusion layer and the second diffusion layer. The third polysilicon layer may be formed along the second direction and at least partially overlap the first diffusion layer and the second diffusion layer. The fourth polysilicon layer may be formed along the second direction and at least partially overlap the first diffusion layer and the second diffusion layer, wherein the third polysilicon layer is formed between the second polysilicon layer and the fourth polysilicon layer. The first resistive memory element may be formed at least partially overlapping the first diffusion layer and between the first polysilicon layer and the second polysilicon layer.The second resistive memory element may be formed at least partially overlapping the second diffusion layer and between the first polysilicon layer and the second polysilicon layer. The third resistive memory element may be formed at least partially overlapping the first diffusion layer and between the third polysilicon layer and the fourth polysilicon layer. The fourth resistive memory element may be at least partially overlapped by the second diffusion layer and formed between the third polysilicon layer and the fourth polysilicon layer. The first polysilicon layer, the second polysilicon layer, the first resistive memory element, and the second resistive memory element may correspond to a first memory.The third polysilicon layer, the fourth polysilicon layer, the third resistive memory element, and the fourth resistive memory element may correspond to a second memory. The memory mini-array may include the first memory and the second memory.

[0010] Another example of the first embodiment further provides a memory including a first diffusion layer, a second diffusion layer, a first conductive layer, a second conductive layer, a first resistive storage element, and a second resistive storage element. The first conductive layer may be formed over the first diffusion layer. The second conductive layer may be formed over the second diffusion layer. The first resistive storage element may be formed over the first conductive layer. The second resistive storage element may be formed over the second conductive layer. The first conductive layer and the second conductive layer may be formed from the same conductive layer. Short description of the characters Fig. 1 illustrates a memory write operation according to one embodiment. Fig.2 illustrates a reading operation of the memory shown in Fig. 1. Fig. 3 illustrates a circuit with two memories according to one embodiment. The Fig. 4 to Fig. 8 illustrate layout diagrams of a manufacturing process for the memory shown in Fig. 1 according to one embodiment. Fig. Figure 9 illustrates a cross-sectional view of the memory shown in Fig. 8 along cross-section line 9-9'. Fig. 10 illustrates the read window when reading data from a plurality of memories according to one embodiment. Detailed description

[0011] To increase the permissible number of accesses to a memory and reduce the memory area, a memory and a memory mini-array are provided according to the embodiments. When an object A is formed at least partially overlapping with an object B, this means in the text that at least a part of the object A may overlap with at least a part of the object B, or that the object A may completely overlap with the object B in a plan view. In the text, a via (also called a VIA) may be a conductive connection path formed by drilling holes and coating the holes with conductive material. Each of the memories 100 and 200 mentioned here may be a bit cell of a resistive random access memory (RRAM).

[0012] The Fig. 1 and Fig. 2 illustrate a memory 100 according to one embodiment. Fig.1 illustrates a write operation of the memory 100. Fig. 2 shows a read operation of the memory 100

[0013] As in the Fig. 1 and Fig.2, the memory 100 may include a first switching transistor 110, a second switching transistor 120, a third switching transistor 130, a fourth switching transistor 140, a first resistive storage element 151, and a second resistive storage element 152. The first switching transistor 110 may have a drain terminal, a source terminal, and a gate terminal. The second switching transistor 120 may have a drain terminal, a source terminal, and a gate terminal. The third switching transistor 130 may have a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal of the third switching transistor 130 may be coupled to the source terminal of the first switching transistor 110.The fourth switching transistor 140 may have a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal of the fourth switching transistor 140 may be coupled to the source terminal of the second switching transistor 120.

[0014] The first resistive storage element 151 may include a first terminal and a second terminal. The first terminal of the first resistive storage element 151 may be coupled to the source terminal of the fourth switching transistor 140. The second terminal of the first resistive storage element 151 may be coupled to the source terminal of the first switching transistor 110. The second resistive storage element 152 may have a first terminal and a second terminal. The first terminal of the second resistive storage element 152 may be coupled to the source terminal of the third switching transistor 130. The second terminal of the second resistive storage element 152 may be coupled to the source terminal of the second switching transistor 120.

[0015] As in the Fig. 1 and Fig.2, the first resistive memory element 151 and the second resistive memory element 152 may each have an upper electrode TE, a lower electrode BE, and a transition metal oxide layer TMO. The upper electrode TE of the first resistive memory element 151 may be coupled to the first terminal of the first resistive memory element 151. The lower electrode BE of the first resistive memory element 151 may be coupled to the second terminal of the first resistive memory element 151. The transition metal oxide layer TMO of the first resistive memory element 151 may be formed between the upper electrode TE and the lower electrode BE of the first resistive memory element 151. Likewise, the upper electrode TE of the second resistive memory element 152 may be coupled to the first terminal of the second resistive memory element 152.The lower electrode BE of the second resistive storage element 152 can be coupled to the second terminal of the second resistive storage element 152. The transition metal oxide layer TMO of the second resistive storage element 152 can be formed between the upper electrode TE and the lower electrode BE of the second resistive storage element 152.

[0016] As in the Fig. 1 and Fig.2, the drain terminal of the first switching transistor 110 may be coupled to a first bit line BL1. The gate terminal of the first switching transistor 110 may be coupled to a read word line RWL. The drain terminal of the second switching transistor 120 may be coupled to a second bit line BL2. The gate terminal of the second switching transistor 120 may be coupled to the read word line RWL. The gate terminal of the third switching transistor 130 may be coupled to a write word line WWL. The source terminal of the third switching transistor 130 may be coupled to a second source line SL2. The gate terminal of the fourth switching transistor 140 may be coupled to the write word line WWL. The source terminal of the fourth switching transistor 140 may be coupled to a first source line SL1.

[0017] As in Fig.1, data can be written into the memory 100 via the first source line SL1 and the second source line SL2 when the first switching transistor 110 and the second switching transistor 120 are turned off and the third switching transistor 130 and the fourth switching transistor 140 are turned on. As shown in Fig. 1, data can be written into the first resistive storage element 151 and the second resistive storage element 152 via a path P11 and a path P12.

[0018] In Fig.1, when writing a logic 0 to the memory 100, the first source line SL1 may have a high voltage level (expressed as VH in the text), the second source line SL2 may have a low voltage level (expressed as VL in the text) lower than the high voltage level VH, the first resistive storage element 151 may have a high resistance (expressed as RH in the text), and the second resistive storage element 152 may have a low resistance (expressed as RL in the text) lower than the high resistance RH.

[0019] In Fig. 1, when writing a logic 1 to the memory 100, the first source line SL1 may have the low voltage level VL, the second source line SL2 may have the high voltage level VH, the first resistive storage element 151 may have the low resistance RL, and the second resistive storage element 152 may have the high resistance RH.

[0020] As in Fig. 2, data can be read from the memory 100 when the first switching transistor 110 and the second switching transistor 120 are turned on and the third switching transistor 130 and the fourth switching transistor 140 are turned off. As shown in Fig. 2, data can be read from the first resistive storage element 151 and the second resistive storage element 152 via a path P21 and a path P22.

[0021] In Fig. 2, when reading a logic 0 from the memory 100, the first source line SL1 may have the high voltage level VH and the second source line SL2 may have the high voltage level VH. In Fig. 2, when reading a logic 1 from the memory 100, the first source line SL1 may have the high voltage level VH and the second source line SL2 may have the high voltage level VH.

[0022] The above-mentioned write and read operations of the memory 100 can be described in Table 1. (Table 1) When writing a logical 0 The first source line SL1: high voltage level VH In Fig. 1, the first switching transistor 110 and the second switching transistor 120 are turned off, and the third switching transistor 130 and the fourth switching transistor 140 are turned on. The second source line SL2: low voltage level VL The first resistance storage element 151: high resistance RH The second resistance storage element 152: low resistance RL When writing a logical 1 The first source line SL1: low voltage level VL The second source line SL2: high voltage level VH The first resistance storage element 151: low resistance RL The second resistance storage element 152: high resistance RH When reading a logical 0 The first source line SL1: high voltage level VH In Fig. 2, the first switching transistor 110 and the second switching transistor 120 are switched on, and the third switching transistor 130 and the fourth The second source line SL2: high voltage level VH When reading a logical 1 Switching transistor 140 is switched off.

[0023] Fig. 3 illustrates a circuit including memory 100 and a memory 200 according to one embodiment. As shown in Fig. As illustrated in Figure 3, memory 100 may be coupled to memory 200, and memory 200 may be coupled to the first bit line BL1, the second bit line BL2, the first source line SL1, and the second source line SL2. Coupling memory 100 to memory 200 reduces the area of ​​the circuit. Fig.2, the memory 100 may include the first switching transistor 110 through the fourth switching transistor 140, the first resistive storage element 151, and the second resistive storage element 152, as mentioned above, and will therefore not be described repeatedly. Like the first switching transistor 110 through the fourth switching transistor 140, the first resistive storage element 151, and the second resistive storage element 152 in the memory 100, the memory 200 may include a fifth switching transistor 210, a sixth switching transistor 220, a seventh switching transistor 230, an eighth switching transistor 240, a third resistive storage element 251, and a fourth resistive storage element 252. The component couplings and operations of the memory 200 may be similar to those of the memory 100 and will not be described repeatedly.

[0024] As in the Fig. 1 to Fig.As illustrated in Figure 3, the same electrodes of the first resistive storage element 151 and the second resistive storage element 152 are formed at the same ends, i.e., the lower electrodes BE of the first resistive storage element 151 and the second resistive storage element 152 are coupled to the sources of the first switching transistor 110 and the second switching transistor 120, respectively. This simplifies the associated connections of the components of the memory 100.

[0025] As in Fig. 3, the memory 100 and the memory 200 may share the first bit line BL1, the second bit line BL2, the first source line SL1, and the second source line SL2. Regarding the semiconductor layout, the memory 100 and the memory 200 may be incorporated into a memory mini-array 800 having the structure shown in Fig. 8 shown layout can be integrated.

[0026] The Fig. 4 to Fig.8 illustrate layout diagrams of a manufacturing method for the memory 100 according to an embodiment. In the manufacturing method of the memory 100, the layout diagrams may be sequentially produced according to a time sequence as shown in FIGS. Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 are shown.

[0027] As in Fig.As illustrated in Figure 4, the memory 100 may include a diffusion layer DF1, a diffusion layer DF2, a polysilicon layer PLY1, a polysilicon layer PLY2, a polysilicon layer PLY3, and a polysilicon layer PLY4. The polysilicon layer PLY1, the polysilicon layer PLY2, the polysilicon layer PLY3, and the polysilicon layer PLY4 may correspond to gate terminals of transistors, e.g., gate terminals of field-effect transistors (FETs). The diffusion layers DF1 and DF2 may be formed along a first direction D1. The polysilicon layer PLY1 through the polysilicon layer PLY4 may be formed along a second direction D2 substantially perpendicular to the first direction D1. Each of the polysilicon layers PLY1 to PLY4 may be formed at least partially overlapping with the diffusion layer DF1 and the diffusion layer DF2. Fig.4, the diffusion layer DF1 and the diffusion layer DF2 can be formed from a single diffusion layer. For example, a trench can be formed to separate the diffusion layer DF1 from the diffusion layer DF2. As shown in Fig. As illustrated in Figure 4, a plurality of contact elements CT can be formed on the diffusion layers DF1, DF2. In plan view, each of the contact elements CT can be arranged between two polysilicon layers.

[0028] When the polysilicon layer PLY1 in Fig. 4 the gate terminals of the first switching transistor 110 and the second switching transistor 120 in Fig. 1, and the polysilicon layer PLY2 in Fig. 4 the gate terminals of the third switching transistor 130 and the fourth switching transistor 140 in Fig. 1, the polysilicon layer PLY1 can be connected to the read word line RWL in Fig. 1, and the polysilicon layer PLY2 in Fig. 4 can be connected to the write word line WWL in Fig. 1 can be coupled.

[0029] In Fig. 5, a conductive layer M1, a plurality of vias VA, and a plurality of resistive storage elements RSE1, RSE2, RSE3, and RSE4 may be formed over the diffusion layers DF1 and DF2. One of the resistive storage elements RSE1, RSE2, RSE3, and RSE4 may correspond to one of the Fig. 1 to Fig. 3 mentioned first resistance storage elements 151, second resistance storage elements 152, third resistance storage elements 251 and fourth resistance storage elements 252. As in Fig.As shown in Figure 5, in plan view, the resistive storage element RSE1 can be formed at least partially overlapping the diffusion layer DF1 and between the polysilicon layer PLY1 and the polysilicon layer PLY2. The resistive storage element RSE2 can be formed at least partially overlapping the diffusion layer DF2 and between the polysilicon layer PLY1 and the polysilicon layer PLY2.

[0030] In Fig. 6, a conductive layer M2 may further be formed over the diffusion layer DF1 and the diffusion layer DF2. In plan view, the conductive layer M2 may not overlap with the resistive storage elements RSE1, RSE2, RSE3, and RSE4.

[0031] As in Fig. As illustrated in Figure 7, a conductive layer M3 and a plurality of conductive vias V2 can be formed over the conductive layer M2 and the resistive storage elements RSE1 to RSE4.

[0032] As in Fig. As illustrated in Figure 8, a conductive layer M4 and a plurality of conductive vias V3 can be formed over the conductive layer M3.

[0033] In Fig.8, the first switching transistor 110, the second switching transistor 120, the third switching transistor 130, the fourth switching transistor 140, the resistive storage element RSE1, and the resistive storage element RSE2 can be used to form a memory with four switching transistors and two resistive storage elements, and the memory can be referred to as a 4T2R memory (e.g., the memory 100 mentioned above). The fifth switching transistor (210), the sixth switching transistor (220), the seventh switching transistor (230), the eighth switching transistor (240), the resistive storage element RSE3, and the resistive storage element RSE4 can be used to form another memory with four switching transistors and two resistive storage elements, and the memory can be referred to as a 4T2R memory (e.g., the memory 200 mentioned above).In the layout, the memory 100 and the memory 200 may be used to form the memory mini-array 800, and the memory 100 and the memory 200 may share the bit lines and source lines, as shown in FIG. Fig. 3 illustrates.

[0034] Fig. 9 is a cross-sectional view of the memory 100 in Fig. 8 along the cross-section line 9-9'. As in Fig. 8, the memory 100 may include the diffusion layer DF1, the diffusion layer DF2, a conductive layer M11, a conductive layer M12, a contact element CT1, a contact element CT2, a conductive via VA1, a conductive via VA2, a resistive storage element RSE1, a resistive storage element RSE2, a conductive layer M21, a conductive via V21, a conductive via V22, a conductive via V23, a conductive layer M31, a conductive layer M32, a conductive layer M41, a conductive layer M42, a conductive layer M43, a conductive layer M44, and a conductive via V31.

[0035] In Fig. 9, a trench T1 may be used to separate the diffusion layer DF1 from the diffusion layer DF2. The conductive layer M11 may be formed at least partially overlapping with the diffusion layer DF1. In the plan view, the conductive layer M11 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The conductive layer M12 may be formed at least partially overlapping with the diffusion layer DF2. In the plan view, the conductive layer M12 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The conductive layer M11 and the conductive layer M12 in Fig. 9 can be formed from the same conductive layer as the conductive layer M1 in Fig. 5. As in Fig. As shown in Figure 9, the conductive layer M11 can be formed over the diffusion layer DF1. The conductive layer M12 can be formed over the diffusion layer DF2. The resistive storage element RSE1 can be formed over the conductive layer M11. The resistive storage element RSE2 can be formed over the conductive layer M12.

[0036] The contact element CT1 can be formed between the diffusion layer DF1 and the conductive layer M11, coupled to the diffusion layer DF1 and the conductive layer M11, and at least partially overlap with the diffusion layer DF1. In plan view, the contact element CT1 can be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The contact element CT2 can be formed between the diffusion layer DF2 and the conductive layer M12, coupled to the diffusion layer DF2 and the conductive layer M12, and at least partially overlap with the diffusion layer DF2. In plan view, the contact element CT2 can be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The contact element CT1 and the contact element CT2 can be Fig. 4 correspond.

[0037] The via VA1 can be formed between the conductive layer M11 and the resistive storage element RSE1, coupled to the conductive layer M11 and the resistive storage element RSE1 and at least partially overlapped with the resistive storage element RSE1.

[0038] The via VA2 can be formed between the conductive layer M12 and the resistive storage element RSE2, coupled to the conductive layer M12 and the resistive storage element RSE2, and at least partially overlapped with the resistive storage element RSE2. The conductive via VA1 and the conductive via VA2 can be connected to the conductive vias VA in Fig. 5 correspond.

[0039] The resistance storage element RSE1 and the resistance storage element RSE2 can be assigned to the first resistance storage element 151 and the second resistance storage element 152 in the Fig. 1 to 3 correspond.

[0040] As in Fig. As illustrated in Figure 9, in plan view, the conductive layer M21 can be formed between the resistive storage element RSE1 and the resistive storage element RSE2. The conductive layer M31 can be formed over the resistive storage element RSE1 and at least partially overlap the resistive storage element RSE1.

[0041] The conductive layer M32 can be formed over the resistive storage element RSE2 and the conductive layer M21. The conductive layer M32 can be formed at least partially overlapping with the resistive storage element RSE2 and the conductive layer M21. The conductive layer M21 can be formed from the conductive layer M2 in Fig. 6. The conductive layer M31 and the conductive layer M32 may be formed from the same conductive layer, such as the conductive layer M3 in Fig. 7.

[0042] In Fig. 9, the conductive via V21 can be formed between the resistive storage element RSE1 and the conductive layer M31, coupled to the resistive storage element RSE1 and the conductive layer M31, and at least partially overlapped with the resistive storage element RSE1.

[0043] The via V22 can be formed between the conductive layer M21 and the conductive layer M32, coupled to the conductive layer M21 and the conductive layer M32, and at least partially overlapped with the conductive layer M21.

[0044] The conductive via V23 can be formed between the resistive storage element RSE2 and the conductive layer M32, coupled to the resistive storage element RSE2 and the conductive layer M32, and at least partially overlapped with the resistive storage element RSE2. The conductive via V21, the conductive via V22, and the conductive via V23 in Fig. 9 can be connected to the conductive vias V2 in Fig. 7 correspond.

[0045] As in Fig. As illustrated in Figure 9, the conductive layer M41, the conductive layer M42, the conductive layer M43, and the conductive layer M44 may be formed over the conductive layer M31 and the conductive layer M32. The conductive layer M41 may be formed at least partially overlapping the conductive layer M32.

[0046] The via V31 can be formed between the conductive layer M32 and the conductive layer M41, coupled to the conductive layer M32 and the conductive layer M41, and at least partially overlapped with the conductive layer M32. The conductive via V31 in Fig. 9 can be connected to the conductive vias V3 in Fig. 8. The conductive layer M41, the conductive layer M42, the conductive layer M43 and the conductive layer M44 in Fig. 9 can be formed from the same conductive layer as, for example, the conductive layer M4 in Fig. 8.

[0047] When the resistance storage element RSE1 and the resistance storage element RSE2 correspond to the first resistance storage element 151 and the second resistance storage element 152 in Fig. 1 and Fig. 2, the conductive layer M31 can be Fig. 9 with the first source line SL1 in Fig. 1, the conductive layer M41 in Fig. 9 with the second source line SL2 in Fig. 1, the conductive layer M11 in Fig. 9 with the source terminal of the first switching transistor 110 in Fig. 1 and the conductive layer M12 in Fig. 9 with the source terminal of the second switching transistor 120 in Fig. 1 can be coupled.

[0048] Fig. 10 illustrates the read window when reading data from a plurality of memories according to one embodiment. In Fig. 10, the horizontal axis represents the flows in the memories and the vertical axis the statistical number of memories generated after normalization. On the horizontal axis of Fig. 10, the HR level may be the current level at which the resistive storage element of the memory has a high resistance value and a logic 0 is written to the memory. The LR level may be the current level at which the resistive storage element of the memory has a low resistance value and a logic 1 is written to the memory. The NR level may be a reference current level when a machine is used to measure the memory.

[0049] When the memory 100 provided in the embodiment is not used, a memory can be read according to the current of a single resistance memory element, and the reading operation corresponds to a single-mode operation. Therefore, the window corresponding to the high resistance can be Fig. 10 WH, and the window corresponding to the low resistance can be in Fig. 10 WL. It can be expressed as WH=|NR-HR| and WL=|LR-NR|.

[0050] When the memory 100 provided by the embodiment is in use, the memory can be read according to a difference in the currents of two resistive storage elements, and the read operation corresponds to a differential mode operation. Thus, the window corresponding to the high and low resistances can be expressed as W = |LR-HR|. Since |LR-HR| is larger than |NR-HR| and |LR-HR| is larger than |LR-NR|, it can be expressed as W > WH and W > WL. Therefore, when the memory 100 is in use, the read window is larger. With the larger read window, the data stored in the memory 100 can still be effectively determined as 0 or 1 even if the memory 100 is written and read many times (for example, but not limited to, 100,000 times), thereby improving the accuracy of reading the memory and the reliability of the memory.

[0051] Since the two resistive memory elements are arranged in the same direction, the connections between the components are simplified using the memory 100 of the present embodiment. The differential mode is used to increase the read window, thus improving the accuracy of reading the memory and the reliability of the memory after many accesses to the memory. Furthermore, two memory cells (e.g., memory 100 and memory 200 in Fig. 3) Coupling them together through appropriate circuitry, layout design, and semiconductor structure to further reduce the circuit area. This allows the memory and memory mini-array of the embodiments to be used in this area.

Claims

[1] Storage, including: a first switching transistor (110) having a drain terminal, a source terminal and a gate terminal; a second switching transistor (120) having a drain terminal, a source terminal and a gate terminal; a third switching transistor (130) having a drain terminal directly connected to the source terminal of the first switching transistor (110), a source terminal, and a gate terminal; a fourth switching transistor (140) having a drain terminal directly connected to the source terminal of the second switching transistor (120), a source terminal, and a gate terminal; a first resistive storage element (151) having a first terminal directly connected to the source terminal of the fourth switching transistor (140) and a second terminal directly connected to the source terminal of the first switching transistor (110); and a second resistive storage element (152) having a first terminal directly connected to the source terminal of the third switching transistor (130) and a second terminal directly connected to the source terminal of the second switching transistor (120). [2] The memory of claim 1, wherein when writing data to the memory, the first switching transistor (110) and the second switching transistor (120) are turned off and the third switching transistor (130) and the fourth switching transistor (140) are turned on. [3] The memory of claim 1, wherein when reading data from the memory, the first switching transistor (110) and the second switching transistor (120) are turned on and the third switching transistor (130) and the fourth switching transistor (140) are turned off. [4] Memory according to claim 1, wherein: the drain terminal of the first switching transistor (110) is coupled to a first bit line, and the gate terminal of the first switching transistor (110) is coupled to a read word line; the drain terminal of the second switching transistor (120) is coupled to a second bit line, and the gate terminal of the second switching transistor (120) is coupled to the read word line; the gate terminal of the third switching transistor (130) is coupled to a write word line, and the source terminal of the third switching transistor (130) is coupled to a second source line; and the gate terminal of the fourth switching transistor (140) is coupled to the write word line, and the source terminal of the fourth switching transistor (140) is coupled to a first source line. [5] The memory of claim 4, wherein when writing a logic 0 to the memory, the first switching transistor (110) and the second switching transistor (120) are turned off, the third switching transistor (130) and the fourth switching transistor (140) are turned on, the first source line has a high voltage level, and the second source line has a lower voltage level than the high voltage level. [6] The memory of claim 5, wherein when writing the logic 0 to the memory, the first resistive memory (151) is set to have a high resistance and the second resistive memory element (152) is set to have a low resistance which is lower than the high resistance. [7] The memory of claim 4, wherein when reading a logic 0 from the memory, the first switching transistor (110) and the second switching transistor (120) are turned on, the third switching transistor (130) and the fourth switching transistor (140) are turned off, the first source line has a high voltage level, and the second source line has the high voltage level. [8] The memory of claim 4, wherein when writing a logic 1 to the memory, the first switching transistor (110) and the second switching transistor (120) are turned off, the third switching transistor (130) and the fourth switching transistor (140) are turned on, the first source line has a low voltage level, and the second source line has a high voltage level that is higher than the low voltage level. [9] The memory of claim 8, wherein when writing the logic 1 to the memory, the first resistive storage element (151) is set to have a low resistance and the second resistive storage element (152) is set to have a high resistance higher than the low resistance. [10] The memory of claim 4, wherein when reading a logic 1 from the memory, the first switching transistor (110) and the second switching transistor (120) are turned on, the third switching transistor (130) and the fourth switching transistor (140) are turned off, the first source line has a high voltage level, and the second source line has the high voltage level. [11] Memory according to claim 4, wherein: the first resistive storage element (151) has an upper electrode coupled to the first terminal of the first resistive storage element (151), a lower electrode coupled to the second terminal of the first resistive storage element (151), and a transition metal oxide layer formed between the upper electrode of the first resistive storage element (151) and the lower electrode of the first resistive storage element (151); and the second resistive storage element (152) has an upper electrode coupled to the first terminal of the second resistive storage element (152), a lower electrode coupled to the second terminal of the second resistive storage element (152), and a transition metal oxide layer formed between the upper electrode of the second resistive storage element (152) and the lower electrode of the second resistive storage element (152). [12] Memory according to claim 1, comprising: a first diffusion layer formed along a first direction; a second diffusion layer formed along the first direction; a first polysilicon layer formed along a second direction and formed to at least partially overlap the first diffusion layer and the second diffusion layer, the first direction being substantially perpendicular to the second direction; and a second polysilicon layer formed along the second direction and formed to at least partially overlap the first diffusion layer and the second diffusion layer; wherein the first resistive storage element (151) is formed at least partially overlapping with the first diffusion layer and between the first polysilicon layer and the second polysilicon layer; and the second resistive storage element (152) is formed at least partially overlapping with the second diffusion layer and between the first polysilicon layer and the second polysilicon layer. [13] The memory according to claim 12, wherein the first diffusion layer and the second diffusion layer are formed using the same diffusion layer. [14] The memory of claim 12, further comprising: a first conductive layer formed at least partially overlapping the first diffusion layer and between the first polysilicon layer and the second polysilicon layer; a second conductive layer formed at least partially overlapping the second diffusion layer and between the first polysilicon layer and the second polysilicon layer, wherein the first conductive layer and the second conductive layer are formed from a same conductive layer; a first contact element coupled to the first diffusion layer and the first conductive layer and formed at least partially overlapping the first diffusion layer and between the first polysilicon layer and the second polysilicon layer; a second contact element coupled to the second diffusion layer and the second conductive layer and formed at least partially overlapping the second diffusion layer and between the first polysilicon layer and the second polysilicon layer; a first conductive via coupled to the first conductive layer and the first resistive storage element (151) and formed at least partially overlapping with the first resistive storage element (151); and a second conductive via coupled to the second conductive layer and the second resistive storage element (152) and formed to at least partially overlap the second resistive storage element (152). [15] The memory of claim 14, further comprising: a third conductive layer formed between the first resistance storage element (151) and the second resistance storage element (152); a fourth conductive layer formed at least partially overlapping with the first resistive storage element (151); a fifth conductive layer formed at least partially overlapping the second resistive storage element (152) and the third conductive layer, wherein the fourth conductive layer and the fifth conductive layer are formed from a same conductive layer; a third conductive via coupled to the first resistive storage element (151) and the fourth conductive layer and formed at least partially overlapping with the first resistive storage element (151); a fourth conductive via coupled to the third conductive layer and the fifth conductive layer and formed at least partially overlapping with the third conductive layer; and a fifth conductive via coupled to the second resistive storage element (152) and the fifth conductive layer and formed to at least partially overlap the second resistive storage element (152). [16] Storage mini-array comprising: a first diffusion layer formed along a first direction; a second diffusion layer formed along the first direction; a first polysilicon layer formed along a second direction and at least partially overlapped by the first diffusion layer and the second diffusion layer, the first direction being substantially perpendicular to the second direction; a second polysilicon layer formed along the second direction and at least partially overlapped by the first diffusion layer and the second diffusion layer; a third polysilicon layer formed along the second direction and at least partially overlapped by the first diffusion layer and the second diffusion layer; a fourth polysilicon layer formed along the second direction and at least partially overlapped by the first diffusion layer and the second diffusion layer, wherein the third polysilicon layer is formed between the second polysilicon layer and the fourth polysilicon layer; a first resistive storage element (151) formed at least partially overlapping with the first diffusion layer and between the first polysilicon layer and the second polysilicon layer; a second resistive storage element (152) formed at least partially overlapping the second diffusion layer and between the first polysilicon layer and the second polysilicon layer; a third resistive storage element (251) formed at least partially overlapping with the first diffusion layer and between the third polysilicon layer and the fourth polysilicon layer; and a fourth resistive storage element (252) formed at least partially overlapping the second diffusion layer and between the third polysilicon layer and the fourth polysilicon layer; wherein the first polysilicon layer, the second polysilicon layer, the first resistive storage element (151) and the second resistive storage element (152) correspond to a first memory; the third polysilicon layer, the fourth polysilicon layer, the third resistive storage element (251) and the fourth resistive storage element correspond to a second memory; and the memory mini-array comprises the first memory and the second memory; wherein the first memory is formed according to claim 1. [17] Memory according to claim 1, comprising: a first diffusion layer; a second diffusion layer; a first conductive layer formed over the first diffusion layer; and a second conductive layer formed over the second diffusion layer; wherein the first resistive storage element (151) is formed over the first conductive layer; and the second resistive storage element (152) is formed over the second conductive layer; the first conductive layer and the second first conductive layer are formed from the same conductive layer. [18] The memory of claim 17, further comprising: a first contact element coupled to the first diffusion layer and the first conductive layer and formed between the first diffusion layer and the first conductive layer; a second contact element coupled to the second diffusion layer and the second conductive layer and formed between the second diffusion layer and the second conductive layer; a first conductive via coupled to the first conductive layer and the first resistive storage element (151) and formed between the first conductive layer and the first resistive storage element (151); and a second conductive via coupled to the second conductive layer and the second resistive storage element (152) and formed between the second conductive layer and the second resistive storage element (152). [19] The memory of claim 18, further comprising: a third conductive layer; a fourth conductive layer formed over the first resistive storage element (151); a fifth conductive layer formed over the second resistive storage element (152) and the third conductive layer; a third conductive via coupled to the first resistive storage element (151) and the fourth conductive layer and formed between the first resistive storage element (151) and the fourth conductive layer; a fourth conductive via coupled to the third conductive layer and the fifth conductive layer and formed between the third conductive layer and the fifth conductive layer; and a fifth conductive via coupled to the second resistive storage element (152) and the fifth conductive layer and formed between the second resistive storage element (152) and the fifth conductive layer; wherein the fourth conductive layer and the fifth conductive layer are formed from the same conductive layer. [20] The memory of claim 19, further comprising: a sixth conductive layer formed over the fifth conductive layer; and a sixth conductive via coupled to the fifth conductive layer and the sixth conductive layer and formed between the fifth conductive layer and the sixth conductive layer.

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