INTERCONNECT STRUCTURES FOR THE INTEGRATION OF STORAGE CELLS AND LOGIC CELLS

Abstract

semiconductor structure comprising: a memory cell (302) connected to a bit line (BL), a complementary bit line (BLB), a first voltage line (VDD) for receiving a supply voltage and a second voltage line (VSS) for receiving a ground voltage; one or more logic cells configured to provide logical function to the memory cell (302);and an interconnect structure placed above the memory cell (302) and the one or more logic cells, wherein: the interconnect structure comprises the bit line (BL), the complementary bit line (BLB), the first voltage line (VDD), and the second voltage line (VSS) located in the same metal conductor layer (M0) of the interconnect structure; at least one of the bit line (BL) and the complementary bit line (BLB) extends from the inside of a boundary of the one or more logic cells and into a boundary of the memory cell (302); and at least one of the first (VDD) and second voltage lines (VSS) extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell (302), wherein the bit line (BL) extends completely through the memory cell (302).

Description

PRIORITY DATA

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 489,217, filed March 9, 2023, which is incorporated by reference into the present application. BACKGROUND

[0002] The semiconductor IC industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, with each generation featuring progressively smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected components per chip area) has generally increased, while geometric size (i.e., the smallest component (or circuit) that can be created using a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling-down has also increased the complexity of IC processing and manufacturing.

[0003] Memories are commonly used in integrated circuits (ICs). For example, static random-access memory (SRAM) is a volatile memory used in electronic applications where high speed, low power consumption, and simple operation are required. Embedded SRAM is particularly popular in high-speed communications, image processing, and system-on-chip (SOC) applications. SRAM has the advantage of being able to retain data without requiring refresh. An SRAM structure comprises memory cells and logic cells. During IC design, designers retrieve the required cells from cell libraries and position them at desired locations. Routing is then performed to establish connections between the memory cells and logic cells, creating the desired IC.For example, an SRAM structure generally includes multilayer interconnect structures that provide metal traces (metal lines) to connect power lines and signal lines between the memory cells and logic cells. However, interconnect structures may consist of one set of metal traces in the memory region and another set of metal traces in the logic region. The two sets of metal traces are generally not aligned and therefore not directly connected. Consequently, metal junctions to higher metal layers are necessary to electrically connect the metal traces in the memory region and the logic region. Such junctions increase resistance and capacitance in the interconnect structures, posing performance, yield, and cost challenges.It has been observed that these higher resistances and / or higher capacitances exhibited by interconnects in advanced IC technology nodes can significantly delay (and in some situations prevent) efficient routing of signals to and from IC components, such as transistors, thereby negating any improvements in the performance of such IC components in the advanced technology nodes. Such junctions can be implemented in edge cells inserted between the memory region and the logic region, which also consumes valuable on-chip area and increases manufacturing costs. Therefore, although existing interconnect structures for memory-based ICs were generally adequate for their intended purpose, they were not entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] This disclosure is best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry practice, various features are not drawn to scale and are for illustrative purposes only. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for the sake of clarity of explanation. Fig. 1 illustrates a block diagram of a semiconductor device having a memory macro in accordance with some embodiments of the present disclosure. Fig. 2 illustrates a circuit diagram for a single-port static random access memory (SRAM) cell in accordance with some embodiments of the present disclosure. Fig. 3 illustrates a cross-sectional view of various layers of a memory device in accordance with some embodiments of the present disclosure. Fig. 4 and Fig. 5 illustrate a layout including a device layer and metal layer of the single-terminal SRAM cell as shown in Fig. 2, in accordance with some embodiments of the present disclosure. Fig. 6 illustrates a layout including a metal layer of a logic cell in accordance with some embodiments of the present disclosure. Fig. 7, Fig. 8, Fig. 9 and Fig. 10 illustrate layouts of a section of the memory macro as in Fig. 1 in accordance with some embodiments of the present disclosure. Fig. 11 illustrates a circuit diagram for a dual-port SRAM cell in accordance with some embodiments of the present disclosure. Fig. 12 and Fig. 13 illustrate a layout including a device layer and metal layer of the dual terminal SRAM cell as shown in Fig. 11, in accordance with some embodiments of the present disclosure. Fig. 14 illustrates a layout of a metal layer of a portion of the memory macro as in Fig. 1 in accordance with some embodiments of the present disclosure. Fig. 15 and Fig. 16 illustrate an alternative layout comprising a device layer and metal layer of the dual terminal SRAM cell as in Fig. 11, in accordance with some embodiments of the present disclosure. Fig. 17 illustrates an alternative layout of a metal layer of a portion of the memory macro as in Fig. 1 in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact.

[0006] Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, imply a relationship between the various embodiments and / or configurations discussed. Moreover, the formation of one structural element upon, connected to, and / or coupled to another structural element in the following present disclosure may include embodiments in which the structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the structural elements such that the structural elements may not be in direct contact. Further, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "upward," "downward," "top," "bottom," etc.as well as derivatives thereof (e.g., "horizontal," "downward," "upward," etc.) are used herein to facilitate the present disclosure of the relationship of one structural element to another structural element. The spatially relative terms are intended to encompass various orientations of the device incorporating the structural elements. Further, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to encompass numbers that are within + / - 10% of the described number, unless otherwise specified. For example, the term "about 5 nm" encompasses the dimensional range of 4.5 nm to 5.5 nm.

[0007] The present disclosure generally relates to static random access memory (SRAM) structures that include memory cells and logic cells. The memory cells are also referred to as bit cells and are configured to store memory bits. The memory cells may be arranged in rows and columns of an array. The logic cells may be standard cells (STD cells), such as inverter (INV), AND, OR, NAND, NOR, flip-flip, SCAN, and so on. The logic cells are mounted around the memory cells and are configured to implement various logic functions. Multilayer interconnect structures provide metal traces (metal lines) to connect power lines and signal lines between the memory cells and logic cells.

[0008] It will now Fig. 1 referred to. Fig. 1 is a simplified block diagram of a semiconductor device (or IC) 10 in accordance with some embodiments of the present disclosure. The semiconductor device 10 can be, for example, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a portion thereof, which includes various passive and active microelectronic components such as resistive elements, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, gate-all-around transistors (GAA transistors) (such as nanosheet FETs or nanowire FETs), other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors (BJTs),Bipolar Junction Transistors (BJTs), Lateral Diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. The exact functionality of the semiconductor device 10 is not a limitation on the provided article.

[0009] Semiconductor device 10 includes a circuit macro (hereinafter, macro) 20. In some embodiments, macro 20 is a static random access memory (SRAM) macro, such as a single-port SRAM macro, a dual-port SRAM macro, or other types of SRAM macro. However, the present disclosure contemplates embodiments where macro 20 is a different type of memory, such as dynamic random access memory (DRAM), non-volatile random access memory (NVRAM), flash memory, or other suitable memory. Fig. 1 has been simplified for a better understanding of the inventive concepts of the present disclosure. Additional structural elements may be added to macro 20, and some of the structural elements described below may be replaced, modified, or eliminated in other embodiments of macro 20.

[0010] In some embodiments, the macro 20 includes memory cells and peripheral circuitry. The memory cells may also be referred to as bit cells and are configured to store memory bits. The peripheral cells are also referred to as logic cells, which are mounted around the bit cells and are configured to implement various logical functions. The logical functions of the logic cells include, for example, write and / or read decoding, word line selection, bit line selection, data driving, and memory self-testing. The logical functions of the logic cells described above are for explanation purposes. Various logical functions of the logic cells are within the intended scope of the present disclosure. In the illustrated embodiment, the macro 20 includes a circuit area 22 in which at least one memory cell block 30 and at least one logic cell block 40 are positioned in close proximity to one another.The memory cell block 30 includes at least one memory cell. In general, the memory cell block 30 may include many memory cells arranged in rows and columns of an array. The logic cell block 40 includes at least one logic cell. In general, the logic cell block 40 may include many logic cells to provide read operations and / or write operations to the memory cells in the memory cell block 40. Transistors in the one or more memory cell blocks 30 and the one or more logic cell blocks 40 may be implemented with various PFETs and NFETs, such as planar transistors or non-planar transistors, including various FinFET transistors, GAA transistors, or a combination thereof. GAA transistors refer to transistors with gate electrodes surrounding transistor channels, such as vertically stacked gate-all-around, horizontal nanowire, or nanosheet MOSFET devices.The following disclosure continues with one or more GAA examples to illustrate various embodiments of the present disclosure. However, it is understood that the application is not intended to be limited to any particular type of device except as specifically claimed. For example, aspects of the present disclosure may also apply to an implementation based on FinFETs or planar FETs.

[0011] Fig. 2 is a circuit diagram of an exemplary SRAM cell 50 that may be implemented as a memory cell of an SRAM array, according to various aspects of the present disclosure. In some implementations, SRAM cell 50 is included in one or more memory cell blocks 30 of macro 20 ( Fig. 1). In the illustrated embodiment, SRAM cell 50 is a single-terminal, six-transistor SRAM cell (SP 6T SRAM cell). In various embodiments, SRAM cell 50 may be another type of memory cell, such as a dual-terminal memory cell or a memory cell with more than six transistors. Fig. Figure 2 has been simplified for a better understanding of the inventive concepts of the present disclosure. Additional structural elements may be added to the single-port SRAM cell 50, and some of the structural elements described below may be replaced, modified, or eliminated in other embodiments of a single-port SRAM cell 50.

[0012] The exemplary SRAM cell 50 is a single-port SRAM cell that includes six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the pass-gate transistor PG-1 and the pass-gate transistor PG-2 provide access to a data storage portion of the SRAM cell 50 that includes a cross-coupled pair of inverters, an inverter 52 and an inverter 54. The inverter 52 includes the pull-up transistor PU-1 and the pull-down transistor PD-1, and the inverter 54 includes the pull-up transistor PU-2 and the pull-down transistor PD-2. In some implementations, the pull-up transistors PU-1, PU-2 are configured as p-FinFET transistors or p-GAA transistors and the pull-down transistors PD-1, PD-2 are configured as n-FinFET transistors or n-GAA transistors.

[0013] A gate of pull-up transistor PU-1 connects a source (electrically coupled to a supply voltage (VDD)) and a first common drain (CD1), and a gate of pull-down transistor PD-1 connects a source (electrically coupled to a supply voltage (VSS), which may be ground) and the first common drain. A gate of pull-up transistor PU-2 connects a source (electrically coupled to the supply voltage (VDD)) and a second common drain (CD2), and a gate of pull-down transistor PD-2 connects a source (electrically coupled to the supply voltage (VSS)) and the second common drain. In some implementations, the first common drain (CD1) is a data storage node (SN) that stores data in true form, and the second common drain (CD2) is a data storage node (SNB) that stores data in complementary form.The gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1 are coupled to the second common drain (CD2), and the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2 are coupled to the first common drain (CD1). A gate of pass-gate transistor PG-1 connects a source (electrically coupled to a bit line BL) and a drain electrically coupled to the first common drain (CD1). A gate of pass-gate transistor PG-2 connects a source (electrically coupled to a complementary bit line BLB) and a drain electrically coupled to the second common drain (CD2). In this context, the bit line BL and the complementary bit line BLB may also be collectively referred to as bit lines if not specified separately. The gates of the pass-gate transistors PG-1, PG-2 are electrically coupled to a word line WL.In some implementations, pass-gate transistors PG-1, PG-2 provide access to data storage nodes SN, SNB during read operations and / or write operations. For example, pass-gate transistors PG-1, PG-2 couple data storage nodes SN and SNB, respectively, to bit lines BL and BLB, respectively, in response to a voltage applied to the gates of pass-gate transistors PG-1, PG-2 by word line WL.

[0014] Fig. Figure 3 is a fragmentary schematic cross-sectional view of various layers (levels) that may be fabricated over a semiconductor substrate (or wafer) 60 to form a portion of a memory, such as IC device 10 of Fig. 1, and / or a portion of an SRAM cell, such as SRAM cell 50 of Fig. 2, according to various aspects of the present disclosure. In Fig. 4, the various layers comprise a device layer DL and a multilayer interconnect MLI disposed over the device layer DL. Device layer DL comprises devices (e.g., transistors, resistive elements, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain features). In some embodiments, device layer DL comprises substrate 60, doped regions 62 disposed in substrate 60 (e.g., n-wells and / or p-wells), isolation features 64, and transistors T. In the embodiment shown, transistors T comprise pending channel layers 70 and gate structures 68 disposed between source / drains 72, where gate structures 68 wrap and / or surround pending channel layers 70.Each gate structure 68 includes a metal gate stack formed from a gate electrode 74 disposed over a gate dielectric 76 and gate spacers 78 disposed along sidewalls of the metal gate stack. The multilayer interconnect MLI electrically couples various devices and / or components of device layer DL so that the various devices and / or components can operate as specified by the memory design requirements.

[0015] In the illustrated embodiment, the multilayer interconnect MLI includes a contact layer (CO level), a via zero layer (Vo level), a metal zero level (Mo level), a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), and a metal three layer (M3 level). The present disclosure contemplates a multilayer interconnect MLI with more or fewer layers and / or levels, for example, a total of N metal layers (levels) of the multilayer interconnect MLI, with N being an integer in the range of 2 to 10. Each level of multilayer interconnect MLI includes conductive structural elements (e.g., metal lines, metal vias, and / or metal contacts).which are disposed in one or more dielectric layers (e.g., an interlayer dielectric layer (ILD layer) and a contact etch stop layer (CESL layer)). In some embodiments, conductive features on a same level of multilayer interconnect MLI, such as the Mo level, are formed simultaneously. In some embodiments, conductive features on a same level of multilayer interconnect MLI have top surfaces that are substantially planar with each other and / or bottom surfaces that are substantially planar with each other. The C0 level has source / drain contacts (MD) disposed in a dielectric layer 66; the V0 level has gate vias VG, source / drain contact vias VD, and butt contacts disposed in the dielectric layer 66; the Mo level has Mo metal lines disposed in the dielectric layer 66.where gate vias VG connect gate structures to Mo metal lines, source / drain vias Vo connect source / drains to Mo metal lines, and butt contacts connect gate structures and source / drains to each other and to Mo metal lines; V1 level has V1 vias disposed in dielectric layer 66, where V1 vias connect Mo metal lines to M1 metal lines; M1 level has M1 metal lines disposed in dielectric layer 66; V2 level has V2 vias disposed in dielectric layer 66, where V2 vias connect M1 lines to M2 lines; M2 level has M2 metal lines disposed in dielectric layer 66; V3 level has V3 vias disposed in the dielectric layer 66, where V3 vias connect M2 lines to M3 lines. , Fig. Figure 3 has been simplified for a better understanding of the inventive concepts of the present disclosure. Additional structural elements may be added in the various layers of the memory, and some of the described structural elements may be replaced, modified, or eliminated in other embodiments of the memory. Fig. 3 is only an example and may not depict an actual cross-sectional view of the IC device 10 and / or the SRAM cells 50, which are discussed in more detail below.

[0016] Fig. 4 and Fig. 5 illustrate an exemplary layout 200 of the SRAM cell 50 as in Fig. 2, where Fig. 4 illustrates the DL level, CO level and Vo level of the layout 200 and Fig. 5 Vo-level and Mo-level of the layout 200. The SRAM cell 50 has a cell boundary 202, which is indicated by dotted lines in Fig. 4 and Fig. 5. The cell boundary 202 is a rectangular box that is longer in the Y direction than in the X direction, for example, about 3.5 times to about 6 times longer. The first dimension of the cell boundary 202 along the X direction is referred to as a cell width W, and the second dimension of the cell boundary 202 along the Y direction is referred to as a cell height H. When the SRAM cell 50 is repeated in a memory array, the cell width W may represent and be referred to as a memory cell pitch in the memory array along the X direction, and the cell height H may represent and be referred to as a memory cell pitch in the memory array along the Y direction. In the illustrated embodiment, the cell width W is twice a poly pitch.A poly pitch refers to a minimum center-to-center distance between two adjacent gate structures along the X direction.

[0017] SRAM cell 50 includes active regions 205 (including 205A, 205B, 205C, and 205D) oriented longitudinally along the X direction, and gate structures 240 (including 240A, 240B, 240C, and 240D) oriented longitudinally along the Y direction perpendicular to the X direction. Active regions 205B and 205C are disposed over an n-well (or n-type well) 204N. Active regions 205A and 205D are disposed over p-wells (or p-type wells) 204P located on either side of n-well 204N along the Y direction. The gate structures 240 engage the channel regions of the respective active regions 205 to form transistors.In this regard, the gate structure 240A intervenes in the channel region of the active region 205A to form an n-type transistor as the pass-gate transistor PG-1; the gate structure 240B intervenes in the channel region of the active region 205A to form an n-type transistor as the pull-down transistor PD-1, and intervenes in the channel region of the active region 205B to form a p-type transistor as the pull-up transistor PU-1; the gate structure 240C intervenes in the channel region of the active region 205D to form an n-type transistor as the pull-down transistor PD-2, and intervenes in the channel region of the active region 205C to form a p-type transistor as the pull-up transistor PU-2; and the gate structure 240D engages the channel region of the active region 205D to form an n-type transistor as the pass-gate transistor PG-2.In the present embodiment, each of the channel regions is in the form of vertically stacked nanostructures, and each of the transistors PU-1, PU-2, PD-1, PD-2, PG-1, and PG-2 is a GAA transistor. Alternatively, each of the channel regions 215A-F is in the form of a fin, and each of the transistors PU-1, PU-2, PD-1, PD-2, PG-1, and PG-2 is a FinFET transistor.

[0018] Different active areas in different transistors of SRAM cell 50 may have different widths (e.g., dimensions measured in the Y direction) to optimize device performance. Specifically, the active area 205A of pull-down transistor PD-1 and pass-gate transistor PG-1 has a width W1, the active area 205B of pull-up transistor PU-1 has a width W2, the active area 205C of pull-up transistor PU-2 has a width W3, and the active area 205D of pass-gate PG-2 and pull-down transistor PD-2 has a width W4. Widths W1-W4 may also be measured in portions of the active areas corresponding to the channel regions. In other words, these sections of the active areas (from which the widths W1-W4 are measured) are the channel regions (e.g., the vertically stacked nanostructures of GAA devices) of the transistors.To optimize SRAM performance, in some embodiments, one of the widths W1 and W4 is configured to be larger than one of the widths W2 and W3 in an effort to balance the speed among the n-type transistors and the p-type transistors. For example, a ratio of W1 / W2 (or W4 / W3) may range from about 1.2 to about 3. In accordance with some embodiments, the widths W2 and W3 may be the same, and the widths W1 and W4 may be the same.

[0019] The SRAM cell 50 further includes conductive features in the C0 level, V0 level, M0 level, and even higher metal levels (e.g., M1 level, M2 level, etc.). A gate contact 260A electrically connects a gate of the pass-gate transistor PG-1 (formed by gate structure 240A) to a landing pad 280A of the first word line WL. The first WL landing pad 280A is electrically coupled to a word line WL located at a higher metal level. A gate contact 260L electrically connects a gate of the pass-gate transistor PG-2 (formed by gate structure 240D) to a landing pad 280L of the second word line WL. The second WL landing pad 280L is electrically coupled to a word line WL located at a higher metal level.An S / D contact 260K electrically connects a drain region of the pull-down transistor PD-1 (formed on the active region 205A (which may include n-epitaxial source / drain structure elements)) and a drain region of the pull-up transistor PU-1 (formed on the active region 205B (which may include p-epitaxial source / drain structure elements)), such that a common drain of the pull-down transistor PD-1 and the pull-up transistor PU-1 forms a data storage node SN. A gate contact 260B electrically connects a gate of the pull-up transistor PU-2 (formed by gate structure 240C) and a gate of the pull-down transistor PD-2 (also formed by gate structure 240C) to the data storage node SN. The gate contact 260B can be a push contact that is in contact with the S / D contact 260K.An S / D contact 260C electrically connects a drain region of the pull-down transistor PD-2 (formed on the active region 205D (which may include n-epitaxial source / drain structure elements)) and a drain region of the pull-up transistor PU-2 (formed on the active region 205C (which may include p-epitaxial source / drain structure elements)) such that a common drain of the pull-down transistor PD-2 and the pull-up transistor PU-2 forms a complementary data storage node SNB. A gate contact 260D electrically connects a gate of the pull-up transistor PU-1 (formed by the gate structure 222) and a gate of the pull-down transistor PD-1 (also formed by the gate structure 240B) to the complementary data storage node SNB. The gate contact 260D may be a push contact that contacts the S / D contact 260C.

[0020] An S / D contact 260E and an S / D contact via 270E landing thereon electrically connect a source region of pull-up transistor PU-1 (formed on active region 205B (which may include p-epitaxial source / drain features)) to a VDD line 280E. VDD line 280E is electrically coupled to a supply voltage VDD. An S / D contact 260F and an S / D contact via 270F landing thereon electrically connect a source region of pull-up transistor PU-2 (formed on active region 205C (which may include p-epitaxial source / drain features)) to the VDD line 280E. An S / D contact 260G and an S / D contact via 270G landing thereon electrically connect a source region of the pull-down transistor PD-1 (formed on the active region 205A (which may include n-epitaxial source / drain structures)) to a first VSS landing pad 280G.The first VSS landing pad 280G is electrically coupled to a ground VSS. An S / D contact 260H and an S / D contact via 270H landing thereon electrically connect a source region of the pull-down transistor PD-2 (formed on the active region 205D (which may include n-epitaxial source / drain structures)) to a second VSS landing pad 280H. The second VSS landing pad 280H is electrically coupled to a ground VSS. The S / D contact 260G and the S / D contact 260H may be device-level contacts shared by adjacent SRAM cells 100 (e.g., four SRAM cells 100 adjacent to a same corner may share one S / D contact 260H). An S / D contact 260I and an S / D contact via 2701 landing thereon electrically connect a source region of the pass-gate transistor PG-1 (formed on the active region 205A (which may include n-epitaxial source / drain structures)) to a bit line BL 280I.An S / D contact 260J and an S / D contact via 270J landing thereon electrically connect a source region of the pass-gate transistor PG-2 (formed on the active region 205D (which may include n-epitaxial source / drain structures)) to a complementary bitline (bitline rail) BLB 280J.

[0021] Conductive features in the CO level, Mo level, and higher metal levels (e.g., M1 level, M2 layer, etc.) are routed along a first routing direction or a second routing direction that differs from the first routing direction. For example, the first routing direction is the X direction (and substantially parallel to the longitudinal direction of active areas 205A-205D), and the second routing direction is the Y direction (and substantially parallel to the longitudinal direction of gate structures 240A-240D). In the embodiment shown, source / drain contacts (260C, 260E, 260F, 260G, 260H, 260I, 260J) have longitudinal directions (longitudinal) substantially along the Y-direction (i.e., second routing direction), and butt contacts (260B, 260D) have longitudinal directions substantially along the X-direction (i.e., first routing direction). Metal lines of even-numbered metal layers (i.e., Mo-level and M2-level) are routed along the X-direction (i.e.,The metal lines of odd-numbered metal layers (i.e., M1 layer and M3 layer) are routed along the Y direction (i.e., the second routing direction). For example, in the Mo layer, as shown in . Fig. 5, the bit line 280I, bit line rail 280J, VDD line 280E, the VSS landing pad 280G, VSS landing pad 280H, word line landing pad 280A, and word line landing pad 280L have longitudinal directions substantially along the X-direction. Furthermore, since the metal lines in the same metal plane (e.g., the Mo plane) have the same longitudinal directions, the metal lines can be positioned in metal traces that are arranged in parallel. A metal trace may include one or more metal lines. For example, a metal trace may include a single metal line that extends through the entire SRAM cell, or a metal trace may include one or more local metal lines that do not extend through the entire SRAM cell. The illustrated metal lines are substantially rectangular in shape (i.e.,each having a length greater than its width), but the present disclosure contemplates metal lines having various shapes and / or combinations of shapes to optimize and / or improve performance (e.g., reducing resistance) and / or layout footprint (e.g., reducing density).

[0022] “Landing pad” generally refers to metal lines in metal layers that provide an intermediate local interconnect for the SRAM cell, such as (1) an intermediate local interconnect between a device-level feature (e.g., gate or source / drain) and a bitline, a bitline rail, a wordline, a voltage line, or (2) an intermediate local interconnect between bitlines, wordlines, or voltage lines.For example, the VSS landing pad 280G is connected to source / drain contact 260G of transistor PD-1 and further connected to a VSS line located in a higher metal level, the VSS landing pad 280H is connected to source / drain contact 260H of transistor PD-2 and further connected to a VSS line located in a higher metal level, the WL landing pad 280A is connected to a gate of transistor PG-1 and further connected to a word line WL located in a higher metal level, and the WL landing pad 280L is connected to a gate of transistor PG-2 and further connected to a word line WL located in a higher metal level. Landing pads have longitudinal dimensions large enough to provide sufficient landing area for their overlying vias (thus minimizing overlay problems and providing greater patterning flexibility).In the illustrated embodiment, landing pads have longitudinal dimensions that are smaller than dimensions of the SRAM cell 50, such as dimensions along the X direction that are smaller than the cell width W and dimensions along the Y direction that are smaller than the cell height H. Compared to the landing pads, the bit line 280I, the bit line rail 280J, and the VDD line 280E have longitudinal dimensions along the X direction that are larger than the cell width W of the SRAM cell 50. Running through the entire SRAM cell 50 along the X direction, the bit line 280I, the bit line rail 280J, and the VDD line 280E are also referred to as global metal lines at the Mo level, while others are referred to as local metal lines (including landing pads).In some embodiments, a length of each of the bit line 280I, the bit line rail 280J, and the VDD line 280E is sufficient to enable electrical connection of multiple SRAM cells in a column (or a row) to the corresponding global metal line.

[0023] The metal lines (global metal lines and local metal lines) in the SRAM cell 50 at the Mo level can have different widths. For example, the VDD line 280E has a width Wa, the bit line 280I and bit line rail 280J each have a width Wb, and the landing pads each have a width Wc, where the widths Wa and Wc are each wider than the width Wb. The widths Wa and Wc can be substantially equal, or alternatively, the width Wa can be greater than the width Wc. If the largest width Wa is reserved for the VDD line 280E, the VDD line can generally benefit from reduced resistance and thus reduced voltage drop. If the smallest width Wb is reserved for the bit line 280I and bit line rail 280J, the signal lines can generally benefit from reduced parasitic capacitance and thus improved response time.In some embodiments, a ratio of width Wa to width Wb (i.e., Wa:Wb) is about 1.1 to about 2. The spacing between the metal lines may not be the same. For example, bit line 280I and bit line rail 280J are each spaced from the VDD line by a distance S1, and the landing pads are each spaced from the nearest signal line by a distance S2. In the illustrated embodiment, distance S2 is greater than distance S1. That is, bit line 280I and bit line rail 280J are each closer to VDD line 280E in the Y direction than to the landing pads. In some embodiments, a ratio of width S2 to width S1 (i.e., S2:S1) is about 1.1 to about 2. Alternatively, depending on the layout, distance S2 may be less than distance S1.Thus, in the alternative embodiments, bit line 280I and bit line rail 280J may each be closer to the landing pads in the Y direction than to VDD line 280E.

[0024] In some embodiments, the SRAM cell 50 is stored in the same memory macro (as the macro 20 in Fig. 1) with a logic cell (often referred to as a standard cell). In such embodiments, metal lines in the Mo level of the SRAM cell 50 and metal lines in the Mo level of the logic cell may be configured to optimize both SRAM performance and logic density (co-optimization). For example, Fig. 6 illustrates a layout 290 of metal lines in the Mo-plane of two logic cells arranged in the Y-direction, according to various aspects of the present disclosure. Each of the logic cells has a cell boundary 292, represented by dotted lines. The cell boundary 292 has a first dimension, such as a cell width CW, along a first direction (e.g., X-direction) and a second dimension, such as a cell height CH, along a second direction (e.g., Y-direction). In some embodiments, as shown, cell height CH is half of the SRAM cell height H, such that two logic cells that abut each other have a total height 2*CH that is the same as the SRAM cell height H (i.e., H = 2*CH).

[0025] The Mo level of the logic cells has metal lines electrically connected to a device layer. The device layer of the logic cell includes transistors, such as NFETs and PFETs, each of which has a gate disposed between a source and a drain, where the Mo level of the logic cells is electrically connected to at least one gate, at least one source, and / or at least one drain of the transistors. In some embodiments, gates of the transistors of the logic cells extend longitudinally along the same direction as gates in SRAM cell 50, and metal lines of the Mo layer of the logic cell have a routing direction substantially perpendicular to the gate longitudinal direction. In some embodiments, the two adjacent logic cells have a total of 2*N+1 (an odd number) metal lines arranged in the Y direction, where N is an integer.In the illustrated embodiment, N is equal to 5, and the two adjacent logic cells have eleven metal lines, namely metal lines 294-1 through 294-11. In various other embodiments, N may be integers other than 5, such as 4 or 6. In some embodiments, the two adjacent logic cells may be functionally considered as one logic cell, with a cell height H and a cell width CW, and with 2*N+1 metal lines.

[0026] As shown, the metal lines on the Mo level are evenly distributed along the Y-direction with a pitch So. The metal lines can each be arranged in a corresponding metal trace. On the Mo level, the SRAM structure can have multiple metal traces arranged in parallel (e.g., from trace 1 to trace 2*N+1). In the illustrated embodiment of the layout 290, the logic cells have eleven metal traces arranged in the order from the first (Mo trace 1) to the eleventh (Mo trace 11) along the Y-direction. The middle lines of the metal traces are indicated by the dashed lines in Fig. 6 shown.

[0027] In the illustrated embodiment, the middle metal track (the (N+1)-th metal track or the Mo track 6 in Fig. 6) a metal line (e.g. metal line 294-6 in Fig. 6) which is designated as a VDD line. The metal track which is designated as the second away from the middle metal track (the (N-1)-th metal track or the (N+3)-th metal track or the Mo track 4 or the Mo track 8 in Fig. 6) has a metal line (e.g. the metal line 294-4 or the metal line 294-8 in Fig. 6), which is designated as a signal line coupled to the SRAM cell 50, which is either a bit line BL or a bit line rail BLB. The metal traces designated as the first and last metal traces (1st and (2*N+1)-th metal traces or the Mo trace 1 and the Mo trace 11 in Fig. 6) are positioned, each have a metal line (e.g. the metal line 294-1 and the metal line 294-11 in Fig. 6), which is designated as the VSS line.

[0028] With reference to Fig. 5 and Fig. 6, one solution to electrically connect bit line 2801 in SRAM cell 50 and bit line 294-4 in the first logic cell, and to electrically connect bit line rail 280J in SRAM cell 50 and bit line rail 294-8 in the second logic cell, is to implement one or more edge cells positioned between SRAM cell 50 and the logic cells. Metal junctions are provided inside the edge cells to electrically couple metal lines at the Mo level to other metal lines in higher metal layers (e.g., M1 level and / or M2 level) to implement a bridge for connecting the signal lines in SRAM cell 50 and the logic cells.However, such metal junctions increase routing resistance and parasitic capacitance on the already resistance- and capacitance-sensitive signal lines, thereby undesirably increasing RC delay and reducing SRAM speed, such as read / write speed. As discussed in more detail below, another solution is to align the metal traces (metal lines) in the SRAM cell 50 and the logic cells, allowing the signal lines to extend directly from the logic cells into the SRAM cell 50 without requiring additional metal junctions.

[0029] Fig. Fig. 7 illustrates the DL level and Vo level of a layout 300 of a circuit area 45 in the macro 20 ( Fig. 1) comprising a portion of the SRAM cell block 30 and a portion of the logic cell block 40 and extending across an interface between the SRAM cell block 30 and the logic cell block 40. Fig. Figure 7 has been simplified for a better understanding of the inventive concepts of the present disclosure. For example, active areas, gate structures, gate cut isolation features, and vias on the Vo level in the SRAM cells are shown, while numerous other features are shown in Fig. 7 are omitted.

[0030] The circuit region 45 includes a first type of active regions 305A in the SRAM cell block 30 and a second type of active regions 305B in the logic cell block 40 (collectively referred to as active regions 305). The active regions 305A are arranged along the Y-direction and longitudinally aligned in the X-direction. As discussed above, the active regions 305A may have different widths (e.g., W1-W4 in Fig. 4). The active areas 305B are arranged along the Y-direction and longitudinally aligned in the X-direction. In the illustrated embodiment, the active areas 305B are evenly distributed along the Y-direction and each have a uniform width. The circuit portion 45 further includes gate structures 340 arranged along the X-direction and extending longitudinally in the Y-direction. In the illustrated embodiment, the gate structures 340 are evenly distributed along the X-direction with a uniform distance between two adjacent gate structures 340. The uniform distance is referred to as a gate pitch or a poly pitch ("PP"). The gate structures 340 intersect the active areas 305A, 305B when forming transistors.Transistors formed at the intersections of active areas 305A and gate structures 340 are located within SRAM cell block 30 and are intended to form SRAM cells. Transistors formed at the intersections of active areas 305B and gate structures 340 are located within logic cell block 40 and are intended to form logic cells.

[0031] In the illustrated embodiment, the transistors in the SRAM cell block 30 form a plurality of SRAM cells 302a, 302b, 302c, and 302d (collectively, SRAM cells 302). The SRAM cells 302 are arranged in the X-direction and the Y-direction, thereby forming a 2x2 array of SRAM cells. Each SRAM cell 302 in the array may use the layout 200 of the SRAM cell 50, as shown in Fig. 4. In some embodiments, two adjacent SRAM cells in the X direction are line-symmetric with respect to a common boundary therebetween, and two adjacent SRAM cells in the Y direction are line-symmetric with respect to a common boundary therebetween. That is, SRAM cell 302b is a duplicate cell for SRAM cell 302a, but flipped across the Y axis; SRAM cell 302c is a duplicate cell for SRAM cell 302a, but flipped across the X axis; and SRAM cell 302d is a duplicate cell for SRAM cell 302b, but flipped across the X axis.

[0032] Some active areas 305 extend through multiple SRAM cells in a row. For example, the active area for transistors PD-1, PG-1 in SRAM cell 302b extends through SRAM cell 304a as the active area for its transistors PG-1, PD-1; the active area for transistors PG-2, PD-2 in SRAM cell 302b extends through SRAM cell 302a as the active area for its transistors PD-2, PG-2; and the active area for transistors PU-2 in SRAM cell 302b extends into SRAM cell 302a as the active area for its transistors PU-2. The active areas in SRAM cells 302c, 302d are arranged similarly. The vias on the Vo level in the SRAM cells are also in Fig. 7 illustrates.

[0033] In the illustrated embodiment, the transistors in logic cell block 40 form multiple logic cells. The logic cells can be standard cells, such as inverters (INV), AND, OR, NAND, NOR, flip-flip, SCAN, and so on. The logic cells implement various logic functions on SRAM cells 302. The logic functions of the logic cells include, for example, write and / or read decoding, word line selection, bit line selection, data drive, and memory self-test. As shown, each logic cell has a logic cell height CH that is half the SRAM cell height H. Therefore, two logic cells have a boundary with opposite edges aligned with opposite edges of the boundary of an SRAM cell, where the edges are spaced apart in the Y direction and each edge extends in the X direction.

[0034] In the illustrated embodiment, SRAM cell block 30 directly abuts logic cell block 40, with no intervening edge cells. Between the opposing boundary lines of the SRAM cells in SRAM cell block 30 and the logic cells in logic cell block 40 is a transition region 370 of the active region, or simply the transition region. Inside the transition region 370, the active regions 305A, which extend from the edge column of the SRAM cells, meet the active regions 305B, which extend from the edge column of the logic cells. Because a pair of meeting active regions 305A, 305B have different widths, a kink is created where the active regions 305A, 305B meet. A kink refers to a transition where two segments of different widths meet.For example, in region 372A, represented by a dotted circle, a relatively wide active region 305A meets a relatively narrow active region 305B, creating a kink. The upper edges of the active regions 305A, 305B are aligned, while the lower edges of the active regions 305A, 305B create a step profile. Similarly, in region 372B, represented by another dotted circle, a relatively narrow active region 305A meets a relatively wide active region 305B, creating another kink. The lower edges of the active regions 305A, 305B are aligned, while the upper edges of the active regions 305A, 305B create a step profile.

[0035] As shown in layout 300, transition region 370 has a span of one poly pitch between the opposing boundary lines of the SRAM cells and the logic cells along the X direction. In transition region 370, a dielectric feature (or isolation feature) 374 is longitudinally aligned in the Y direction and provides isolation between active areas 305A and 305B. Dielectric feature 374 overlaps the kinks. In the exemplary layout 300, dielectric feature 374 extends continuously along the boundary lines of the SRAM cells and the logic cells in the Y direction. In other words, dielectric feature 374 is taller than the SRAM cell height H.

[0036] The dielectric feature 374 may be formed in a continuous poly on diffusion edge (CPODE) process. In a CPODE process, a polysilicon gate is replaced by a dielectric feature. For the purposes of this disclosure, a "diffusion edge" may equally be referred to as an active edge, where, for example, an active edge abuts adjacent active regions. Prior to the CPODE process, the active edge may comprise a dummy GAA structure with a dummy gate structure (e.g., a polysilicon gate) and a plurality of vertically stacked nanostructures as channel layers. Additionally, internal spacers may be attached between adjacent nanostructures at lateral ends of the nanostructures.In various examples, epitaxial source / drain features are attached to one side of the dummy GAA structure such that the adjacent epitaxial source / drain features are in contact with the internal spacers and nanostructures of the dummy GAA structure. The subsequent CPODE etch process removes the dummy gate structure and channel layers from the dummy GAA structure to form a CPODE trench. The dielectric material that fills a CPODE trench for isolation is referred to as a CPODE feature. In some embodiments, after the CPODE features are formed, the remaining dummy gate structures are replaced with metal gate structures in a gate-last process.In other words, in some embodiments, the CPODE structure element replaces a portion or all of the otherwise continuous gate structure and is confined between the opposing gate spacers of the replaced portion of the gate structure. The dielectric structure element 374 is also referred to as a gate-cut structure element or a CPODE structure element. Because the CPODE structure element 374 is formed by replacing the previously formed polysilicon gate structures, the CPODE structure element 374 inherits the arrangement of the gate structures 340. That is, the CPODE structure element 374 may have the same width as the gate structures 340 and the same pitch as the gate structures 340.

[0037] Fig. Figure 8 illustrates the Vo-level and Mo-level of the layout 300 of the circuit area 45 in the macro 20 ( Fig. 1), which includes a portion of the SRAM cell block 30 and a portion of the logic cell block 40 and extends across an interface between the SRAM cell block 30 and the logic cell block 40. On the Mo level, the logic cell block 40 has a plurality of metal traces arranged in parallel. In particular, in the illustrated embodiment of the layout 300, two adjacent logic cells have eleven metal traces arranged sequentially from the first (Mo trace 1) to the eleventh (Mo trace 11) along the Y direction. The center lines of the metal traces are indicated by the dashed lines in Fig. 8 shown.

[0038] The metal lines in the SRAM cells are aligned with the metal traces in logic cell block 40, allowing the metal lines in the logic cells to extend into the SRAM cells. Therefore, there is no need for edge cells between SRAM cell block 30 and logic cell block 40 to provide metal junctions for the metal lines at the Mo level. In Mo trace 1, a VSS line extends into SRAM cell 302a and converges with the otherwise standalone VSS landing pad. In Mo trace 2, the metal line remains as a signal line in the logic cell in the boundary of logic cell block 40. In Mo trace 3, the metal line remains as a signal line in the logic cell in the boundary of logic cell block 40. In Mo trace 4, the metal line extends as the bit line in the logic cell and also into and through the SRAM cells as a bit line for multiple SRAM cells in a row.In Mo lane 5, the metal line remains as a signal line in the logic cell within the boundary of logic cell block 40. In Mo lane 6, the metal line extends as a VDD line in the logic cell and also into and through the SRAM cells as a VDD line for multiple SRAM cells in a row. In Mo lane 7, the metal line remains as a signal line in the logic cell within the boundary of logic cell block 40. In Mo lane 8, the metal line extends as the bit line rail in the logic cell and also into and through the SRAM cells as a bit line rail for multiple SRAM cells in a row. In Mo lane 9, the metal line remains as a signal line in the logic cell within the boundary of logic cell block 40. In Mo lane 10, the metal line remains as a signal line in the logic cell within the boundary of logic cell block 40.In Mo lane 7, the metal line may extend as a VSS line in the logic cell through the boundary of the logic cell block 40, but does not contact the word line WL landing pad.

[0039] In the illustrated embodiment, the metal lines in metal traces 4 and 8 extend from the logic cells and through the SRAM cells as a bit line and a bit line rail, respectively. Alternatively, depending on the layout, the metal lines in metal traces 2 and 10, or metal traces 3 and 9, or metal traces 5 and 7 may extend from the logic cells and through the SRAM cells as a bit line and a bit line rail, respectively.

[0040] In general, the boundary of an SRAM cell can directly adjoin the boundary of one or two logic cells. The one or two logic cells provide 2*N+1 metal traces, where N is an integer. The metal line in the middle metal trace (the (N+1)th metal trace) extends into the SRAM cell as a common VDD line for both the SRAM cell and the one or two logic cells. The two metal lines in the two metal traces equidistant from the middle metal trace extend into the SRAM cell as a common bit line and a common bit line rail, respectively, for both the SRAM cell and the one or two logic cells. The two metal lines in the first and (2*N+1)th metal traces extend through the boundary of the one or two logic cells and are connected to one of the VSS landing pads in the SRAM cell.

[0041] Fig. Figure 9 illustrates an alternative embodiment of the layout 300 of the circuit portion 45. For clarity and ease of explanation, similar structural elements in the illustrated embodiments, as in Fig. 8 and Fig. 9, are provided with the same reference numerals and such similar aspects are not repeated. A difference between the layouts 300 in Fig. 8 and Fig. 9 is that the VDD line in Fig. 9 kinks have been added. The kinked portion of the VDD line has a greater width than any other portion of the VDD line. The kink can add approximately 1% to approximately 50% additional width to the VDD line. The kinks are added to the interconnect regions (interconnect pads) of the VDD line to increase the cross-sectional areas of the interconnect regions, thereby reducing the resistance of the VDD line. Increasing the cross-sectional areas of the VDD line's interconnect regions allows for an increase in the cross-sectional areas of the source / drain vias in the V0 plane, which connect the VDD line to source / drain contacts (and thus to underlying source / drain regions).

[0042] Fig. Figure 10 illustrates an alternative embodiment of the layout 300 of the circuit portion 45. For clarity and ease of explanation, similar structural elements in the illustrated embodiments, as in Fig. 8 and Fig. 10 are provided with the same reference numerals and such similar aspects are not repeated. A difference between the layouts 300 in Fig. 8 and Fig. 10 is that in Fig. 9, the metal lines in Mo trace 2 and Mo trace 10 also extend from the logic cells and through the SRAM cells. However, the metal lines in Mo trace 2 and Mo trace 10 are not functional metal lines for the SRAM cells, even though they are functional metal lines for the logic cells. The metal lines in Mo trace 2 and Mo trace 10 improve the uniformity of the metal line density in the SRAM cell block 30. Furthermore, the metal lines in Mo traces 2, 4, 8, and 10 can be formed simultaneously in a double patterning process, and the separate removal of the metal lines in Mo trace 2 and Mo trace 10 may require an additional photolithography process and etching process, which increases manufacturing costs.

[0043] Although the exemplary SRAM cell 50 is a single-port SRAM cell, the alignment of signal lines and power lines in the SRAM cells and logic cells can also be applied to multi-port SRAM cells. Furthermore, the exemplary single-port SRAM cell and / or multi-port SRAM cell can have a different number of transistors to meet performance requirements, such as six transistors (6T), seven transistors (7T), eight transistors (8T), ten transistors (10T), or even more. Fig. Figure 11 illustrates an example of a circuit diagram for a dual-port SRAM cell 100 having seven transistors (7T). Dual-port SRAM cell 100 has a write port 100W and a read port 100R. Write port 100W includes pull-up transistors PU-1, PU-2, pull-down transistors PD-1, PD-2, and pass-gate transistors PG-1, PG-2. In the illustrated embodiment, transistors PU-1 and PU-2 are p-type transistors, and transistors PG-1, PG-2, PD-1, and PD-2 are n-type transistors.

[0044] The drains of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled together, and the drains of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a data latch. The gates of transistors PU-1 and PD-1 are coupled together and to the common drains of transistors PU-2 and PD-2 to form a data storage node SN, and the gates of transistors PU-2 and PD-2 are coupled together and to the common drains of transistors PU-1 and PD-1 to form a complementary data storage node SNB. Sources of the pull-up transistors PU-1 and PU-2 are coupled to a supply voltage VDD and the sources of the pull-down transistors PD-1 and PD-2 are coupled to a voltage VSS, which in some embodiments may be a ground.

[0045] The data latch's data storage node SN is coupled to a bit line W_BL of the write port 100W through the pass-gate transistor PG-2, and the complementary data storage node SNB is coupled to a complementary bit line W_BLB of the write port 100W through the pass-gate transistor PG-1. The data storage node SN and the complementary data storage node SNB are complementary nodes that are often at opposite logic levels (logic high or logic low). The gates of the pass-gate transistors PG-1 and PG-2 are coupled to a word line W_WL of the write port 100W.

[0046] The read port 100R of the SRAM cell 100 includes a read port pass-gate transistor (R-PG) coupled between the bit line R_BL and the data storage node SN (or to the gates of the transistors PU-1 and PD-1). The gate of the read port pass-gate transistor R-PG is coupled to a word line R_WL of the read port 100R. In the illustrated embodiment, the transistor R-PG is a p-type transistor. That is, in the dual-port SRAM cell 100, the pass-gate transistors in a write port are n-type transistors, and the pass-gate transistor in a read port is a p-type transistor.

[0047] Fig. 12 and Fig. 13 illustrate an exemplary layout 400 of the SRAM cell 100 as shown in Fig. 11, where Fig. 12 illustrates the DL level, CO level and Vo level of the layout 400 and Fig. 13 illustrates the Vo-plane and Mo-plane of the layout 400. The dual-port SRAM cell 100 has active regions 102 and 104. The active regions 102, 104 each extend longitudinally in the X-direction in Fig. 12. The active region 102 is a component of the write port 100W, and the active region 104 has a side portion as a component of the read port 100R and a remaining portion as a component of the write port 100W. In other words, the read port 100R and the write port 100W share the active region 104. In the illustrated embodiment, the active region 104 belongs to the transistors PU-1, PU-2, R-PG, which are PMOS devices. As such, the active region 104 is formed over an n-well. Incidentally, the active region 102 belongs to the transistors PG-1, PD-1, PD-2, PG-2, which are NMOS devices. As such, the active region 102 is formed over a p-well (or a p-substrate).

[0048] The dual-port SRAM cell 100 further includes gate structures 112, 114, 116, 118, and 120. Gate structures 112-120 each extend longitudinally in the Y direction. Gate structures 112, 114, 116, and 120 are components of the write port 100W. Gate structure 118 is a component of the read port 100R. Gate structures 114, 116 each extend through the two active regions 102, 104. As such, transistors PD-1 and PU-1 share gate structure 114, and transistors PD-2 and PU-2 share gate structure 116.

[0049] A boundary 140 of the dual-port SRAM cell 100 is illustrated in dashed lines. Note that some of the active areas and gate structures may extend beyond the illustrated boundary 140, as these active areas and gate structures may also form components of other, adjacent SRAM cells. The boundary 140 is longer in the X direction than in the Y direction. In other words, the boundary 140 may be rectangular. The first dimension of the boundary 140 along the X direction is referred to as a cell width W, and the second dimension of the boundary 140 along the Y direction is referred to as a cell height H.Where the dual-port SRAM cell 100 is repeated in a memory array, the cell width W may represent and be referred to as a memory cell pitch in the memory array along the X direction, and the cell height H may represent and be referred to as a memory cell pitch in the memory array along the Y direction.

[0050] The cell size of the dual-port SRAM cell 100 is W x H, where the cell width W is approximately four times a poly pitch (e.g., a center-to-center distance between two adjacent gate structures along the X direction) and the cell height H is approximately twice an isolation pitch (e.g., a center-to-center distance between two adjacent STI structure elements along the Y direction). Where an area of ​​poly pitch times isolation pitch is referred to as a unit area, each unit area has an intersection of a gate structure and an active area, and the dual-port SRAM cell 100 uses a cell size of approximately eight times a unit area when accommodating the seven transistors, namely transistors PG-1, PG-2, PU-1, PU-2, PD-1, PD-2, and R-PG.The area utilization in the device layer of the SRAM cell 100 is considered efficient because only one unit of area is not used to form a functional transistor, but instead accommodates an intersection of a CPODE structure element and an active area.

[0051] A gate contact 150A electrically connects a gate of the read-port pass-gate transistor R-PG (formed by gate structure 118) to the read-port wordline node (R_WL). A gate contact 150C electrically connects a gate of the write-port pass-gate transistor PG-1 (formed by gate structure 112) to the write-port wordline node (W_WL). A gate contact 150D electrically connects a gate of the write-port pass-gate transistor PG-2 (formed by gate structure 120) to the write-port wordline node (W_WL). A gate contact 150E electrically connects a gate of the write terminal pull-down transistor PD-1 (formed by the gate structure 114) and a gate of the write terminal pull-up transistor PU-1 (also formed by the gate structure 114) to the data storage node (SN).A gate contact 150F electrically connects a gate of the write terminal pull-down transistor PD-2 (formed by the gate structure 116) and a gate of the write terminal pull-up transistor PU-2 (also formed by the gate structure 116) to the complementary data storage node (SNB).

[0052] A source / drain contact 160A and a source / drain contact via 170A landing thereon electrically connect a source region of the read-port pass-gate transistor R-PG to the read-port bitline node (R_BL). A source / drain contact 160B lands on a source / drain region and remains floating because there is no corresponding source / drain contact via landing thereon. A source / drain contact 160C and a source / drain contact via 170C landing thereon electrically connect a source region of the write-port pass-gate transistor PG-1 to the complementary write-port bitline node (W_BLB). A source / drain contact 160D and a source / drain contact via 170D landing thereon electrically connect a source region of the write terminal pass-gate transistor PG-2 to the write terminal bitline node (W_BL).A source / drain contact 160E and a source / drain contact via 170E landing thereon electrically connect a common drain region of the write-port pass-gate transistor PG-1 and the write-port pull-down transistor PD-1, together with a drain region of the write-port pull-up transistor PU-1, to the complementary data storage node (SNB). A source / drain contact 160F and a source / drain contact via 170F landing thereon electrically connect a common drain region of the write-port pass-gate transistor PG-2 and the write-port pull-down transistor PD-2, together with a common drain region of the write-port pull-up transistor PU-2 and the read-port pass-gate transistor R-PG, to the data storage node (SN).A source / drain contact 160G and a source / drain contact via 170G landing thereon electrically connect a common source region of the write-port pull-down transistor PD-1 and the write-port pull-down transistor PD-2 to the ground node VSS. A source / drain contact 160H and a source / drain contact via 170H landing thereon electrically connect a common source region of the write-port pull-up transistor PU-1 and the write-port pull-up transistor PU-2 to the supply voltage node VDD. In the illustrated embodiment, the source / drain contacts 160A-160H are each elongated and have a longitudinal direction in the Y direction that is parallel to the extension direction of gate structures.

[0053] The data storage node SN includes the gate contact 150E and the source / drain contact via 170F positioned on two opposite sides of the gate structure 116. As discussed in more detail below, a metal line on the Mo level extends in the X direction up above the gate structure 116 and connects the gate contact 150E and the source / drain contact via 170F. In other words, a Mo metal line overhangs the gate structure 116 and provides a cross-coupling function between the gate contact 150E and the source / drain contact via 170F. Therefore, in the layout 100C, the gate contact 150E and the source / drain contact via 170F are positioned to be co-planar in the Y direction so that a metal line extending in the X direction can connect both.Similarly, the complementary data storage node (data storage node rail) SNB includes the gate contact 150F and the source / drain contact via 170E positioned on two opposite sides of the gate structure 114. As discussed in more detail below, another metal line on the Mo level extends in the X direction above the gate structure 114 and connects the gate contact 150F and the source / drain contact via 170E. In other words, another Mo metal line overhangs the gate structure 114 and provides a cross-coupling function between the gate contact 150F and the source / drain contact via 170E. Therefore, in the layout 400, the gate contact 150F and the source / drain contact via 170E are positioned to be co-planar in the Y direction so that a metal line extending in the X direction can connect both.

[0054] Fig. Figure 13 illustrates the Vo-level and Mo-level of the layout 400 of the metal interconnect structures of the dual-terminal SRAM cell 100. At the Mo-level, the SRAM cell 100 has multiple metal traces arranged in parallel. Specifically, in the illustrated embodiment of the layout 100C, the SRAM cell 100 has six metal traces arranged sequentially from the first (Mo-track 1) to the sixth (Mo-track 6) along the Y-direction. The centerlines of the metal traces are shown in Fig. 13 represented by the dotted lines.

[0055] In layout 400, the first metal trace, "Mo-Trace 1," includes a global metal line 480A, which is a VSS line electrically coupled to source / drain contact via 170G. VSS line 480A is attached to a top edge of SRAM cell 100 and may be shared with an adjacent SRAM cell. The second metal trace, "Mo-Trace 2," includes a local metal line 480B as a landing pad for the write port word line (W_WL). Local metal line 480B lies entirely within SRAM cell 100 and is electrically connected to gate contact 150C and gate contact 150D. The third metal trace, "Mo-Trace 3," includes three local metal lines, 480C, 480D, and 480E. Local metal line 480C provides a landing pad for the complementary write port bit line (W_BLB). Local metal line 480C extends beyond a left edge of SRAM cell 100 and may be shared with an adjacent SRAM cell.The local metal line 480D lies entirely within the SRAM cell 100 associated with the data storage node (SN) and provides cross-coupling between the gate contact 150E and the source / drain contact via 170F. As discussed above, the local metal line 480D traverses over the gate structure 116. The local metal line 480E provides a landing pad for the write port bit line (W_BL). The local metal line 480E extends beyond a right edge of the SRAM cell 100 and may be shared with an adjacent SRAM cell. The fourth metal trace, "Mo-Trace 4," includes two local metal lines 480F and 480G. The local metal line 480F lies entirely within the SRAM cell 100 and is floating. Therefore, the local metal line 480F is a non-functional metal line that primarily serves to improve uniform metal density in the layout.Local metal line 480G lies entirely within SRAM cell 100 and provides a landing pad for the read port word line (R_WL). The fifth metal trace, "Mo-Trace 5," includes three local metal lines, 480H, 480I, and 480J. Local metal line 480H extends across a left edge of SRAM cell 100 and may be shared with an adjacent SRAM cell. Local metal line 480H is floating. Therefore, local metal line 480H is a non-functional metal line primarily used to improve uniform metal density in the layout. Local metal line 480I lies entirely within SRAM cell 100, associated with the complementary data storage node (SNB), and provides cross-coupling between gate contact 15oF and source / drain contact via 170E. As discussed above, the local metal line 4801 crosses over the gate structure 116.The local metal line 480J extends beyond a right edge of the SRAM cell 100 and may be shared with an adjacent SRAM cell. The local metal line 480J provides a landing pad for the read port bit line (R_BL). The sixth metal trace, "Mo Trace 6," includes a global metal line 480K, which is a VDD line electrically coupled to the source / drain contact via 170H. The VDD line 480K is attached to a bottom edge of the SRAM cell 100 and may be shared with an adjacent SRAM cell.

[0056] A width of the VSS line 480A is denoted by Wa, with one half of Wa in one SRAM cell and another half of Wa in the adjacent SRAM cell. A width of the VDD line 480K may be substantially the same as that of the VSS line 480A, with one half of Wa in one SRAM cell and another half of Wa in the adjacent SRAM cell. The other Mo metal lines 480B-480J may each have the same width, denoted by Wb. The distance between two adjacent Mo metal lines may be uniform and is denoted by S1. Therefore, the SRAM cell height H is equal to Wa+4*Wb+5*S1. Compared to the layout 200 of the single-terminal SRAM cell 50, which has a cell height H corresponding to eleven Mo metal traces, the layout 400 of the dual-terminal SRAM cell 100 has a cell height H corresponding to six metal traces. Therefore, the dual-terminal SRAM cell 100 and the logic cell, as shown in Fig. 6, have the same cell height (H=CH), allowing each dual-port SRAM cell 100 to directly adjoin a single logic cell.

[0057] Fig. 14 illustrates the Mo level of a layout 500 of the circuit area 45 in the macro 20 ( Fig. 1) comprising a portion of the SRAM cell block 30 and a portion of the logic cell block 40 and extending across an interface between the SRAM cell block 30 and the logic cell block 40. As discussed above, the dual-port SRAM cell 100 and the logic cell may have the same cell height (H=CH). Fig. 14 shows a column of two SRAM cells in which a first SRAM cell 100a is connected to a first logic cell and a second SRAM cell 100b is connected to a second logic cell.

[0058] The metal traces in the SRAM cells are aligned with the metal traces in logic cell block 40, allowing the metal lines in the logic cells to extend into the SRAM cells. Thus, there is no need for edge cells between SRAM cell block 30 and logic cell block 40 to provide metal junctions for the metal lines at the Mo level. Mo trace 1 includes a VSS line extending through the first SRAM cell and the first logic cell. Mo trace 2 includes a landing pad for W-WL inside the first SRAM cell and a signal line inside the first logic cell. Mo trace 3 includes a landing pad for W-BLB, a local metal line for SN, and a metal line as the W-BL in the first logic cell that extends into the first SRAM cell and merges with the landing pad for W-BL. Mo lane 4 has a landing pad for R-WL inside the first SRAM cell and a signal line inside the first logic cell.Mo trace 5 includes the local metal line for SNB in ​​the first SRAM cell and a metal line as the R-BL in the first logic cell, which extends into the first SRAM cell and converges with the landing pad for R-BL. Mo trace 6 includes a VDD line extending through the first / second SRAM cells and first / second logic cells. Mo trace 7 includes the local metal line for SNB in ​​the second SRAM cell and a metal line as the R-BL in the second logic cell, which extends into the second SRAM cell and converges with the landing pad for R-BL. Mo trace 8 includes a landing pad for R-WL inside the second SRAM cell and a signal line inside the second logic cell. The Mo track 9 has a local metal line for SN in the second SRAM cell and a metal line as the W-BL in the second logic cell, which extends into the second SRAM cell and merges with the landing port for W-BL.Mo trace 10 includes a landing pad for W-WL inside the second SRAM cell and a signal line inside the second logic cell. Mo trace 11 includes a VSS line extending through the second SRAM cell and the second logic cell.

[0059] Fig. 15 and Fig. 16 illustrate an alternative layout 600 of the SRAM cell 100 as in Fig. 11, where Fig. 15 illustrates the DL level, CO level and Vo level of the layout 600 and Fig. 16 illustrates the Vo-plane and Mo-plane of the layout 600. The dual-port SRAM cell 100 has active regions 102 and 104. The active regions 102, 104 each extend longitudinally in the X-direction in Fig. 15. Active region 102 is a component of write port 100W, and active region 104 has a side portion as a component of read port 100R and a remaining portion as a component of write port 100W. In other words, read port 100R and write port 100W share active region 104. In the illustrated embodiment, active region 104 belongs to transistors PU-1, PU-2, R-PG, which are PMOS devices. As such, active region 104 is formed over an n-well. Meanwhile, active region 102 belongs to transistors PG-1, PD-1, PD-2, PG-2, which are NMOS devices. As such, active region 102 is formed over a p-well (or p-substrate).

[0060] The dual-port SRAM cell 100 further includes gate structures 112, 114, 116, 118, and 120. Gate structures 112-120 each extend longitudinally in the Y direction. Gate structures 112, 114, 116, and 120 are components of the write port 100W. Gate structure 118 is a component of the read port 100R. Gate structures 114, 116 each extend through the two active regions 102, 104. As such, transistors PD-1 and PU-1 share gate structure 114, and transistors PD-2 and PU-2 share gate structure 116.

[0061] A boundary 140 of the dual-port SRAM cell 100 is illustrated in dashed lines. It should be noted that some of the active areas and gate structures may extend beyond the illustrated boundary 140, as these active areas and gate structures may also form components of other adjacently positioned SRAM cells. For example, the gate structure 118 extends beyond the boundary 140, as shown in Fig. 15. The boundary 140 is longer in the X direction than in the Y direction. In other words, the boundary 140 may be rectangular. The first dimension of the boundary 140 along the X direction is referred to as a cell width W, and the second dimension of the boundary 140 along the Y direction is referred to as a cell height H. Where the dual-port SRAM cell 100 is repeated in a memory array, the cell width W may represent and be referred to as a memory cell pitch in the memory array along the X direction, and the cell height H may represent and be referred to as a memory cell pitch in the memory array along the Y direction.

[0062] A gate contact 150A electrically connects a gate of the read-port pass-gate transistor R-PG (formed by gate structure 118) to the read-port wordline node (R_WL). A gate contact 150C electrically connects a gate of the write-port pass-gate transistor PG-1 (formed by gate structure 112) to the write-port wordline node (W_WL). A gate contact 150D electrically connects a gate of the write-port pass-gate transistor PG-2 (formed by gate structure 120) to the write-port wordline node (W_WL). A gate contact 150E electrically connects a gate of the write terminal pull-down transistor PD-1 (formed by the gate structure 114) and a gate of the write terminal pull-up transistor PU-1 (also formed by the gate structure 114) to the data storage node (SN).A gate contact 150F electrically connects a gate of the write terminal pull-down transistor PD-2 (formed by the gate structure 116) and a gate of the write terminal pull-up transistor PU-2 (also formed by the gate structure 116) to the complementary data storage node (SNB).

[0063] A source / drain contact 160A and a source / drain contact via 170A landing thereon electrically connect a source region of the read terminal pass-gate transistor R-PG to the read terminal bitline node (R_BL). A source / drain contact 160B lands on a source / drain region adjacent to the CPODE structure element 132 and remains floating because there is no corresponding source / drain contact via landing thereon. A source / drain contact 160C and a source / drain contact via 170C landing thereon electrically connect a source region of the write terminal pass-gate transistor PG-1 to the complementary write terminal bitline node (W_BLB). A source / drain contact 160D and a source / drain contact via 170D landing thereon electrically connect a source region of the write terminal pass-gate transistor PG-2 to the write terminal bitline node (W_BL).A source / drain contact 160E and a source / drain contact via 170E landing thereon electrically connect a common drain region of the write-port pass-gate transistor PG-1 and the write-port pull-down transistor PD-1, together with a drain region of the write-port pull-up transistor PU-1, to the complementary data storage node (SNB). A source / drain contact 160F and a source / drain contact via 170F landing thereon electrically connect a common drain region of the write-port pass-gate transistor PG-2 and the write-port pull-down transistor PD-2, together with a common drain region of the write-port pull-up transistor PU-2 and the read-port pass-gate transistor R-PG, to the data storage node (SN).A source / drain contact 160G and a source / drain contact via 170G landing thereon electrically connect a common source region of the write-port pull-down transistor PD-1 and the write-port pull-down transistor PD-2 to the ground node Vss. A source / drain contact 160H and a source / drain contact via 170H landing thereon electrically connect a common source region of the write-port pull-up transistor PU-1 and the write-port pull-up transistor PU-2 to the supply voltage node VDD. In the illustrated embodiment, the source / drain contacts 160A-160H are each elongated and have a longitudinal direction in the Y direction that is parallel to the extension directions of gate structures.

[0064] The data storage node SN includes the gate contact 150E and the source / drain contact via 170F positioned on two opposite sides of the gate structure 116. As discussed in more detail below, a metal line on the Mo level extends in the X direction up to above the gate structure 116 and connects the gate contact 150E and the source / drain contact via 170F. In other words, a Mo metal line hangs over the gate structure 116 and provides a cross-coupling function between the gate contact 150E and the source / drain contact via 170F. Therefore, in the layout 100E, the gate contact 150E and the source / drain contact via 170F are positioned in a plane in the Y direction so that a metal line extending in the X direction can connect both.Similarly, the complementary data storage node (data storage node rail) SNB includes the gate contact 150F and the source / drain contact via 170E positioned on two opposite sides of the gate structure 114. As discussed in more detail below, another metal line on the Mo level extends in the X direction up to above the gate structure 114 and connects the gate contact 150F and the source / drain contact via 170E. In other words, another Mo metal line hangs above the gate structure 114 and provides a cross-coupling function between the gate contact 150F and the source / drain contact via 170E. Therefore, in the layout 100E, the gate contact 150F and the source / drain contact via 170E are positioned in a plane in the Y direction so that a metal line extending in the X direction can connect both.

[0065] A difference between the layout 600, as in Fig. 15, and the layout 400, as shown in Fig. 12, in layout 600, the gate structure 118 for transistor R-PG extends along the Y direction across the boundary between SRAM cell 100 and an adjacent SRAM cell, allowing gate contact 150A to be mounted at the bottom edge of SRAM cell 100.

[0066] Fig. Figure 16 illustrates the Vo-level and Mo-level of the layout 600 of the metal interconnect structures of the dual-terminal SRAM cell 100. At the Mo-level, the SRAM cell 100 has multiple metal traces arranged in parallel. Specifically, in the illustrated embodiment of the layout 600, the SRAM cell 100 has six metal traces arranged sequentially from the first (Mo-track 1) to the sixth (Mo-track 6) along the Y-direction. The centerlines of the metal traces are indicated by the dotted lines in Fig. 16 shown.

[0067] In layout 600, the first metal trace "Mo-Trace 1" includes a global metal line 680A, which is a VSS line electrically coupled to source / drain contact via 170G. VSS line 680A is attached to a top edge of SRAM cell 100 and may be shared with an adjacent SRAM cell. The second metal trace "Mo-Trace 2" includes a local metal line 680B as a landing pad for the write port word line (W_WL). Local metal line 680B lies entirely within SRAM cell 100 and is electrically connected to gate contact 150C and gate contact 150D. The third metal trace "Mo-Trace 3" includes three local metal lines 680C, 680D, and 680E. Local metal line 680C provides a landing pad for the complementary write port bit line (W_BLB). Local metal line 680C extends across a left edge of SRAM cell 100 and may be shared with an adjacent SRAM cell.Local metal line 680D lies entirely within SRAM cell 100 associated with the data storage node (SN) and provides cross-coupling between gate contact 150E and source / drain contact via 170F. As discussed above, local metal line 680D traverses over gate structure 116. Local metal line 680E provides a landing pad for the write port bit line (W_BL). Local metal line 680E extends across a right edge of SRAM cell 100 and may be shared with an adjacent SRAM cell. The fourth metal trace, "Mo Trace 4," includes local metal line 680F. Local metal line 680F lies entirely within SRAM cell 100 associated with the complementary data storage node (SNB) and provides cross-coupling between gate contact 150F and source / drain contact via 170E. As discussed above, local metal line 480F crosses over gate structure 116.The fifth metal trace, "Mo-Trace 5," includes a global metal line 680G, which may be a read port bit line (R_BL), and is electrically coupled to the source / drain contact via 170A. The sixth metal trace, "Mo-Trace 6," includes local metal lines 680H and 680I. The local metal line 680H provides a landing pad for the VDD line, which is electrically coupled to the source / drain contact via 170H. The local metal line 680H is attached to a bottom edge of the SRAM cell 100 and may be shared with an adjacent SRAM cell. The local metal line 680I provides a landing pad for the read port word line (R_WL), which is electrically coupled to the gate contact 150A. The local metal line 680I is attached to a lower edge of the SRAM cell 100 and may be shared with an adjacent SRAM cell.

[0068] A width of the VSS line 680A is denoted by Wa, with half of Wa in one SRAM cell and another half of Wa in the adjacent SRAM cell. A width of the landing pad for the VDD line 680H and a width of the landing pad for the read terminal word line 680I may be substantially the same as those of the VSS line 680A, with half of Wa in one SRAM cell and another half of Wa in the adjacent SRAM cell. The other Mo metal lines 680B-680G may each have the same width, denoted by Wb. The distance between two adjacent Mo metal lines may be uniform and is denoted by s1. Therefore, the SRAM cell height H is equal to Wa+4*Wb+5*S1. Compared to the layout 200 of the single-terminal SRAM cell 50, which has a cell height H corresponding to eleven Mo metal traces, the layout 400 of the dual-terminal SRAM cell 100 has a cell height H corresponding to six metal traces.Therefore, the dual-port SRAM cell 100 and the logic cell as shown in . Fig. 6, have the same cell height (H=CH), so that each individual dual-port SRAM cell 100 can be directly connected to a corresponding logic cell.

[0069] Fig. 17 illustrates the Mo level of a layout 700 of the circuit area 45 in the macro 20 ( Fig. 1) comprising a portion of the SRAM cell block 30 and a portion of the logic cell block 40 and extending across an interface between the SRAM cell block 30 and the logic cell block 40. As discussed above, the dual-port SRAM cell 100 and the logic cell may have the same cell height (H=CH). Fig. 17 shows a column of two SRAM cells, with a first SRAM cell 100a connected to a first logic cell and a second SRAM cell 100b connected to a second logic cell.

[0070] The metal traces in the SRAM cells are aligned with the metal traces in logic cell block 40, allowing the metal lines in the logic cells to extend into the SRAM cells. Therefore, there is no need for edge cells between SRAM cell block 30 and logic cell block 40 to provide metal junctions for the metal lines at the Mo level. Mo trace 1 includes a VSS line extending through the first SRAM cell and the first logic cell. Mo trace 2 includes a landing pad for W-WL inside the first SRAM cell and a metal line as a signal line inside the first logic cell. Mo trace 3 includes a landing pad for W-BLB, a local metal line for SN, and a metal line as the W-BL in the first logic cell that extends into the first SRAM cell and converges with the landing pad for W-BL.Mo trace 4 includes the local metal line for SNB in ​​the first SRAM cell and a metal line as a signal line inside the first logic cell. Mo trace 5 includes a metal line as R-BL that extends through the first SRAM cell and the first logic cell. Mo trace 6 includes a landing pad for VDD, a landing pad for R-WL, and a metal line as the VDD line inside the logic cells. Mo trace 7 includes a metal line as R-BL that extends through the second SRAM cell and the second logic cell. Mo trace 8 includes the local metal line for SNB in ​​the second SRAM cell and a metal line as a signal line inside the second logic cell. The Mo lane 9 has a landing pad for W-BLB, a local metal line for SN, and a metal line as the W-BL in the second logic cell, which extends into the second SRAM cell and merges with the landing pad for W-BL.Mo trace 10 includes a landing pad for W-WL inside the second SRAM cell and a metal line as a signal line inside the second logic cell. Mo trace 11 includes a VSS line extending through the second SRAM cell and the second logic cell.

[0071] Based on the foregoing discussion, it can be seen that the present disclosure offers advantages over conventional semiconductor structures. However, it is understood that other embodiments may offer additional advantages, not all advantages are necessarily disclosed here, and no particular advantage is required for all embodiments. For example, the present disclosure provides a memory macro that allows the memory cell block and the logic cell to be adjacent to each other and have aligned metal traces (and metal lines). Edge cells, which are typically inserted between the memory cell block and the logic cell block, may no longer be necessary. Memory macro area can be reduced by more than 40% in some embodiments.Furthermore, metal line alignment allows signal lines (such as bit line and / or bit line rail) as well as voltage lines (such as VDD line and / or VSS line) to extend continuously through the memory cells and logic cells, thereby reducing resistance and parasitic capacitance and improving circuit performance.

[0072] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a memory cell connected to a bit line, a bit line rail, a first voltage line for receiving a supply voltage and a second voltage line for receiving a ground voltage, one or more logic cells configured to provide logic functionality to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells.The interconnect structure includes the bit line, the bit line rail, the first voltage line, and the second voltage line located in a same metal line layer of the interconnect structure, wherein at least one of the bit line and the bit line rail extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell, and at least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell. In some embodiments, the memory cell is a static random access memory (SRAM) cell. In some embodiments, the boundary of the memory cell directly adjoins the boundary of the one or more logic cells. In some embodiments, the bit line extends completely through the memory cell.In some embodiments, the bitline rail extends completely through the memory cell. In some embodiments, the first voltage line extends completely through the memory cell. In some embodiments, the second voltage line extends completely through the memory cell. In some embodiments, the first voltage line has a uniform width within the boundary of the one or more logic cells and a varying width within the boundary of the memory cell. In some embodiments, the interconnect structure includes a metal line located in the metal line layer, the metal line extending from within the boundary of the one or more logic cells and into the boundary of the memory cell, the metal line being a functional line for the one or more logic cells and a non-functional line for the memory cell.In some embodiments, the metal line layer includes a plurality of metal traces within the boundary of the one or more logic cells, wherein the first voltage line is located at a center of one of the plurality of metal traces, and the bit line and the bit line rail are evenly spaced from the first voltage line. In some embodiments, a number of the plurality of metal traces within the boundary of the one or more logic cells is an odd number.

[0073] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a memory cell, a logic cell adjacent to the memory cell, and an interconnect structure disposed over the memory cell and the logic cell. The interconnect structure includes a bottom metal line layer having a first signal line, a second signal line, a power line, and a ground line, wherein the first signal line extends from the logic cell and into the memory cell, the second signal line remains within the logic cell, and the ground line extends from the logic cell and into the memory cell. In some embodiments, the first signal line is a bit line. In some embodiments, the first signal line extends completely through the memory cell.In some embodiments, the first signal line converges with a landing pad for the bit line in the memory cell. In some embodiments, the ground line extends completely through the memory cell. In some embodiments, the power supply line extends from the logic cell and completely through the memory cell.

[0074] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a memory cell having a plurality of first parallel metal traces and one or more logic cells having a plurality of second parallel metal traces. Each of the first metal traces is aligned with one of the second metal traces, a number of the second metal traces is an odd number, and a middle one of the second metal traces is a power supply line extending through the memory cell. In some embodiments, the second metal traces include a first signal line and a second signal line, each extending through the memory cell. In some embodiments, the power supply line is positioned between the first and second signal lines, and the first and second signal lines are evenly spaced from the power supply line.

[0075] Structural elements of several embodiments have been set forth above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 489217

[0001]

Claims

[1] Semiconductor structure, comprising: a memory cell connected to a bit line, a bit line rail, a first voltage line for receiving a supply voltage, and a second voltage line for receiving a ground voltage; one or more logic cells configured to provide logic function to the memory cell; and an interconnect structure disposed over the memory cell and the one or more logic cells, where: the interconnect structure comprises the bit line, the bit line rail, the first voltage line and the second voltage line located in a same metal line layer of the interconnect structure, at least one of the bit line and the bit line rail extends from the interior of a boundary of the one or more logic cells and into a boundary of the memory cell and at least one of the first and second voltage lines extends from within the boundary of the one or more logic cells and into the boundary of the memory cell. [2] The semiconductor structure of claim 1, wherein the memory cell is a static random-access memory (SRAM) cell. [3] Semiconductor structure according to claim 1 or 2, wherein the boundary of the memory cell is directly adjacent to the boundary of the one or more logic cells. [4] Semiconductor structure according to one of claims 1 to 3, wherein the bit line extends completely through the memory cell. [5] The semiconductor structure of claim 4, wherein the bit line rail extends completely through the memory cell. [6] Semiconductor structure according to one of claims 1 to 5, wherein the first voltage line extends completely through the memory cell. [7] The semiconductor structure of claim 6, wherein the second voltage line extends completely through the memory cell. [8] The semiconductor structure of claim 6, wherein the first voltage line has a uniform width within the boundary of the one or more logic cells and a different width within the boundary of the memory cell. [9] The semiconductor structure of any one of claims 1 to 8, wherein the interconnect structure comprises a metal line located in the metal line layer, the metal line extending from within the boundary of the one or more logic cells and into the boundary of the memory cell, and the metal line is a functional line for the one or more logic cells and a non-functional line for the memory cell. [10] The semiconductor structure of any one of claims 1 to 9, wherein the metal line layer comprises a plurality of metal traces within the boundary of the one or more logic cells, the first voltage line being located at a center of one of the plurality of metal traces, and the bit line and the bit line rail being equally spaced from the first voltage line. [11] The semiconductor structure of claim 10, wherein a number of the plurality of metal traces within the boundary of the one or more logic cells is an odd number. [12] Semiconductor structure, comprising: a memory cell; a logic cell connected to the memory cell; and an interconnect structure mounted above the memory cell and the logic cell, where: the interconnect structure has a bottom metal line layer having a first signal line, a second signal line, a power supply line and a ground line, the first signal line extends from the logic cell and into the memory cell, the second signal line remains within the logic cell and the ground line extends from the logic cell and into the memory cell. [13] The semiconductor structure of claim 12, wherein the first signal line is a bit line. [14] The semiconductor structure of claim 13, wherein the first signal line extends completely through the memory cell. [15] The semiconductor structure of claim 13, wherein the first signal line converges with a landing pad for the bit line in the memory cell. [16] Semiconductor structure according to one of claims 12 to 15, wherein the ground line extends completely through the memory cell. [17] A semiconductor structure according to any one of claims 12 to 16, wherein the power supply line extends from the logic cell and completely through the memory cell. [18] Semiconductor structure, comprising: a memory cell having a plurality of parallel first metal tracks; and one or more logic cells with several parallel second metal tracks, where: each of the first metal tracks is aligned with one of the second metal tracks, a number of the second metal tracks is an odd number and a middle one of the second metal traces is a power supply line extending through the memory cell. [19] The semiconductor structure of claim 18, wherein the second metal traces comprise a first signal line and a second signal line each extending through the memory cell. [20] The semiconductor structure of claim 19, wherein the power supply line is positioned between the first and second signal lines and the first and second signal lines are equally spaced from the power supply line.