Semiconductor device

Abstract

Semiconductor device, comprising: a heat sink (9, 21, 31); a die pad (8) located above and away from the heat sink (9, 21, 31); a power chip (1) arranged on a surface of the die pad (8) opposite a surface of the die pad (8) facing the heat sink (9, 21, 31); and a casting resin (10) that seals a portion of the heat sink (9, 21, 31), the die pad (8) and the power chip (1), wherein a surface of the heat sink (9, 21, 31) facing the die pad (8) has a flow support part (12) which is designed to separate from a plane having the die pad (8) in an area overlapping the die pad (8) and not overlapping the power chip (1).

Description

BACKGROUND OF THE INVENTION AREA

[0001] The present invention relates to an encapsulated semiconductor device. background

[0002] In a conventional technique, a semiconductor device was disclosed which includes a semiconductor device, a conductor frame and a dissipating or conducting metal plate and in which the semiconductor device, the conductor frame and the conducting metal plate are cast (e.g. patent literature 1).

[0003] Patent Document 1: JP H08-148 515 A

[0004] The publication JP H07 - 245 324 A relates to a semiconductor device that features an external heat sink. The IC chip's housing is entirely cast in resin, enabling highly efficient heat dissipation to the outside by allowing the ends of the external leads and the heat sink to protrude from the resin housing. After the IC chip is electrically connected to a substrate, a heat sink made of a material with high thermal conductivity is mounted on the back of the chip. The chip is then sealed by casting an epoxy resin around it in a predefined mold. The end of the heat sink protrudes from the resin housing. After the chip is sealed with the resin, the heat sink is shaped to either act as a heat pipe with cooling fins or, during the molding of the external leads, to be connected to the chip on a mounting substrate.The heat sink is then soldered to a predefined area of ​​a thermal conductivity pattern present on the substrate. This allows the heat generated by the chip to be dissipated with high efficiency.

[0005] German patent application DE 10 2021 205 995 A1 discloses a power module that can prevent the formation of voids caused by bubbles generated during resin potting in a power module that uses a plate-shaped conductor frame for interconnection wiring within the module. The known power module comprises a base plate, a substrate arranged on the base plate, at least one power semiconductor chip arranged on the substrate, a plate-shaped conductor frame serving as interconnection wiring, a housing connected to the base plate and containing the substrate, the power semiconductor chip, and the conductor frame, and a potting resin filling the housing and sealing the substrate, the power semiconductor chip, and the conductor frame. At least a portion of the conductor frame has an upwardly convex shape, and the upper surface of the upwardly convex shape is provided with an opening that vertically penetrates the conductor frame. Summary

[0006] However, in conventional technology, the problem was that when a semiconductor device is sealed with resin, a narrow gap between the conductor frame and the dissipating metal plate cannot be filled with the resin.

[0007] The present invention was created to solve the problem described above, and its objective is to provide a semiconductor device in which resin is sufficiently filled between a conductor frame and a dissipating metal plate. Solution to the problem

[0008] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0009] A semiconductor device according to the present invention comprises: a heat sink; a die pad arranged above and away from the heat sink; a power chip arranged on a surface of the die pad opposite a surface of the die pad facing the heat sink; and a casting resin sealing a portion of the heat sink, the die pad, and the power chip, wherein a surface of the heat sink facing the die pad has a flow-supporting portion configured to separate from a plane containing the die pad in a region overlapping the die pad and not overlapping the power chip. Advantageous effects of the invention

[0010] In the semiconductor device according to the present invention, even if the space between the conductor frame and the heat sink is narrow, resin is sufficiently filled between the conductor frame and the dissipating metal plate. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic top view of the semiconductor device according to the first embodiment. Fig. Figure 2 is a side view of the semiconductor device according to the first embodiment. Fig. Figure 3 is a side view of the semiconductor device according to the first embodiment. Fig. Figure 4 is an enlarged view of the heat sink in the semiconductor device according to the first embodiment. Fig. Figure 5 is a side view of the semiconductor device according to the second embodiment. Fig. Figure 6 is a top view of the semiconductor device according to the third embodiment. Fig. Figure 7 is a side view of the semiconductor device according to the third embodiment. Fig. Figure 8 is a side view of the semiconductor device according to the third embodiment. Fig. Figure 9 is a top view of the semiconductor device according to the fourth embodiment. DESCRIPTION OF THE EXECUTION FORMS

[0011] With reference to the accompanying drawings, embodiments of the present invention are described below. The drawings are schematic, and the interrelationships between sizes and positions illustrated in different drawings are not necessarily described in detail but can be modified as appropriate. In the following description, similar components are designated with the same reference numerals, and the respective designations and functions of the components are identical or similar. Accordingly, their detailed description can be omitted. First embodiment

[0012] A semiconductor device 101 according to a first embodiment is described with reference to Fig. 1 to 4 described. Fig. Figure 1 is a schematic top view of the semiconductor device 101 according to the first embodiment.

[0013] As in Fig. As illustrated in Figure 1, the semiconductor device 101 according to the present embodiment comprises a plurality of power chips (switching devices) 1, a plurality of freewheeling diodes (diode devices) 3, each electrically connected to the plurality of power chips 1, a high-voltage IC 4 electrically connected to the high-voltage side of the power chips 1, a low-voltage IC 5 electrically connected to the low-voltage side of the power chips 1, a diode (bootstrap diode) 2 forming a bootstrap circuit, at least part of which is electrically connected to the high-voltage IC 4, a conductor frame 6 in which elements such as the power chips 1, the diode 2, the freewheeling diodes 3, the high-voltage IC 4 and the low-voltage IC 5 are installed, and a plurality of wires 7 electrically connecting the elements to each other.

[0014] The ladder frame 6 is marked by a dashed line in Fig. 1. A multitude of components are integrated into the circuit board 6. That is, the circuit board 6 has a die pad 8, on which the power chips 1 are placed, and other sub-areas. The power chips 1 are arranged on an upper surface of the die pad 8. Examples of the sub-areas in the circuit board 6, separate from the die pad 8, include sub-areas each equipped with the diode 2, the high-voltage IC 4, and the low-voltage IC 5, as well as sub-areas that each serve as a terminal.

[0015] The power chips 1, the bootstrap diode 2, the freewheeling diodes 3, the high-voltage IC 4, and the low-voltage IC 5 are each arranged on an upper surface of the conductor frame 6. As shown in Fig. As illustrated in Figure 1, the six power chips 1 in the drawing are arranged in a direction from top to bottom, for example on an upper surface of the conductor frame 6.

[0016] For example, a large number of die pads are arranged in 8. In Fig. In the drawing, four die pads 8 are arranged from top to bottom. Only the top die pad 8 has the three power chips 1, and the other die pads 8 each have one power chip 1. The six freewheeling diodes 3 are arranged in the drawing from top to bottom, for example, on the upper surface of the conductor frame 6.

[0017] The freewheeling diodes 3 are each arranged to correspond to the positions where the power chips 1 are installed, and are arranged in each of the plurality of die pads 8 in the same number as the power chips 1. Three bootstrap diodes 2, for example, are arranged on a top surface of a sub-area in the conductor frame 6 that is different from the die pad 8.

[0018] As in Fig. As illustrated in Figure 1, the semiconductor device 101 according to the present embodiment comprises an RC-IGBT, which is obtained by integrating the power chip 1 and the freewheeling diode 3, for example, as a semiconductor device. The semiconductor device need not necessarily be an RC-IGBT.

[0019] For example, one high-voltage IC 4 is arranged on the upper surface of the sub-area in the conductor frame 6 that differs from the die pad 8. Similarly, one low-voltage IC 5 is also arranged on the upper surface of the sub-area in the conductor frame 6 that differs from the die pad 8. In the present embodiment, the high-voltage IC 4 and the low-voltage IC 5 are arranged on the same conductor frame 6. Fig. For the sake of the obvious simplicity of the drawing, only some of the elements are shown, such as the power chips 1, the diode 2, the freewheeling diodes 3, the high-voltage IC 4 and the low-voltage IC 5, each labelled with reference numerals.

[0020] Each of the multiple wires 7 electrically connects the bootstrap diode 2 and the conductor frame 6. Wire 7 electrically connects the high-voltage IC 4 and the conductor frame 6. Wire 7 electrically connects the high-voltage IC 4 and the power chip 1. Wire 7 electrically connects the low-voltage IC 5 and the conductor frame 6. Wire 7 electrically connects the low-voltage IC 5 and the power chip 1. Wire 7 electrically connects the power chip 1 and the freewheeling diode 3. Wire 7 electrically connects the freewheeling diode 3 and the conductor frame 6. In Fig. 1 represent all linear components that connect the elements such as the power chips 1, the diode 2, the freewheeling diodes 3, the high-voltage IC 4 and the low-voltage IC 5, each represented by the wires 7, and only some of the wires 7 are labelled with reference numerals for the sake of obvious simplicity of the drawing.

[0021] As in Fig. As illustrated in Figure 1, the elements such as the power chips 1, the diode 2, the freewheeling diodes 3, the high-voltage IC 4 and the low-voltage IC 5 and a section of the conductor frame 6 are sealed with a casting resin 10.

[0022] Fig. Figure 2 is a side view of the semiconductor device 101 according to the first embodiment. Fig. 2 is a diagram that shows one from the perspective of Fig. 1 from the bottom (direction A in Fig. 1) corresponds to the considered lateral surface of the semiconductor device 101. As in Fig. As illustrated in Figure 2, the semiconductor device 101 has a heat sink 9 on the side that differs from the side of the circuit board 6 on which each of the elements is located. That is, the heat sink 9 is located on the side of the lower surface of the circuit board 6. The heat sink 9 is positioned on the circuit board 6 at a location that corresponds to a lower surface, in particular of the die pad 8. The heat sink 9 absorbs heat generated by the power chip 1 and dissipates the heat from the semiconductor device 101.

[0023] The power chip 1 is located on the upper surface of the die pad 8 contained in the conductor frame 6. That is, the power chip 1 is located on a surface on the side opposite a surface of the die pad 8 facing the heat sink 9.

[0024] The power chip 1, the bootstrap diode 2, the freewheeling diode 3, the high-voltage IC 4, the low-voltage IC 5, a section of the conductor frame 6, the wires 7 and a section of the heat sink 9 are sealed with the casting resin 10.

[0025] This means that the entire assembly of the power chip 1, the bootstrap diode 2, the freewheeling diode 3, the high-voltage IC 4, the low-voltage IC 5, and the wires 7 is sealed with the casting resin 10. On the other side, the respective sections of the conductor frame 6 and the heat sink 9 are exposed within the casting resin 10.

[0026] A fin (not illustrated) is arranged on a lower surface of the semiconductor device 101. The fin cools the semiconductor device 101. As shown in Fig. As illustrated in Figure 2, a lower surface is exposed from the casting resin 10 as the rib mounting surface 11 of the heat sink 9, to which the rib is attached.

[0027] The rib is arranged in contact with the heat sink 9 and the casting resin 10 on the lower surface of the semiconductor device 101. The conductor frame 6 and the rib are electrically insulated from each other by the casting resin 10.

[0028] An insulating layer 14 is arranged between the conductor frame 6 and the heat sink 9. The insulating layer 14 insulates the conductor frame 6 and the heat sink 9 from each other. The insulating layer 14 is formed in one piece with the casting resin 10 when the casting resin 10 is applied.

[0029] The circuit board 6 and the heat sink 9 are spaced apart from each other at a predetermined distance. That is, the circuit board 6 is positioned above and away from the heat sink 9. Accordingly, the die pad 8 located within the circuit board 6 is positioned above and away from the heat sink 9. The resin 10 is poured between the die pad 8 and the heat sink 9. A surface of the die pad 8 and a surface of the heat sink 9 are desirablely parallel to each other. When the surfaces of the circuit board 6 and the heat sink 9 are parallel, a uniform heat dissipation effect is achieved for the heat dissipation of the power chip 1 and the freewheeling diode 3.

[0030] The casting resin 10 is, for example, viewed from the perspective of Fig. 2 filled from the near side.

[0031] As in Fig. As illustrated in Figure 1, the conductor frame 6 includes a connection part 20 exposed from the casting resin 10. The conductor frame 6 is, for example, oriented in a left-right direction between two surfaces of the casting resin 10. Fig. 1 out of free. The connection part 20 exposed from the casting resin 10 in the conductor frame 6 functions as a supply line or conductor connection.

[0032] A conductor terminal located near a surface close to the conductor frame 6 equipped with the bootstrap diode 2, i.e., a surface on the left side of Fig. 1, which is exposed, is a control-side connection. The connection part 20, which is located on a surface on which the conductor frame 6 equipped with the power chip 1 is positioned, i.e., a surface on the right side of Fig. 1, which is exposed, is a power-side connection as a conductor connection.

[0033] The control-side connection and the power-side connection are arranged so that they are accessible from different surfaces, for example as in Fig. 1 illustrates, from being exposed.

[0034] The ladder frame 6 can consist of a surface that is defined by the in Fig. The surfaces shown in the illustration are different and exposed. The entire conductor frame 6 can be sealed with the casting resin 10.

[0035] The casting resin 10 is used, for example, in the Fig. The resin is poured in direction A as illustrated. When the semiconductor device is manufactured, the elements, such as the power chips 1, the diode 2, the freewheeling diodes 3, the high-voltage IC 4, the low-voltage IC 5, and a portion of the conductor frame 6, are installed in a mold (not illustrated), and the heated, fluid resin 10 is injected into the mold. The injection opening of the resin 10 in the mold can be located in a direction A, regardless of its shape and position. Fig. 1. The side surface considered in direction A is illustrated, i.e., one in Fig. 2 illustrated side surface and the side in the in Fig. 3 illustrated direction A, are located.

[0036] Fig. Figure 3 is a side view of the semiconductor device 101 according to the first embodiment. As in Fig. As illustrated in Figure 3, the heat sink 9 is arranged above the conductor frame 6 below the power chip 1. Fig. 3 is a sub-area of ​​the conductor frame 6 where the power chip 1 is installed, in particular the die pad 8.

[0037] Fig. Figure 4 is an enlarged side view of the heat sink 9 in the semiconductor device 101 according to the first embodiment. Fig. Figure 4 illustrates an enlarged section on the right-hand side enclosed by a dashed line, from the perspective of Fig. 3.

[0038] As in Fig. As illustrated in Figure 4, the heat sink 9 has a flow promotion part 12, which is configured to gradually separate from a plane containing the power chip 1 from a central sub-region to an end-region of an upper surface of the heat sink 9. That is, the upper surface of the heat sink 9, which faces the die pad 8, has the flow promotion part 12 configured to separate from the plane containing the die pad 8 in a region that, in plan view, overlaps the die pad 8 but does not overlap the power chip 1. The flow promotion part 12 can have a curved shape or an R-shape. The flow promotion part 12 can also have a linear shape.

[0039] As in Fig. As illustrated in Figure 4, the flow support element 12 is not located at a position corresponding to a lower surface of the power chip 1. Fig. The four illustrated dashed lines each represent the ends of an area in which the power chip 1 is located. The flow support part 12 is positioned as shown from the perspective of Fig. 4 is located closer to an end of the heat sink 9 than the dashed line, i.e., on the right side of the dashed line. That is, a surface of the heat sink 9 facing the conductor frame 6 has the flow support part 12, which is configured to separate from the plane containing the power chip 1 at a position of the heat sink 9 that lies outside an area corresponding to the power chip 1 and opposite an end part area of ​​the conductor frame 6. The area of ​​the heat sink 9 corresponding to the power chip 1 is an area of ​​the heat sink 9 on the upper side of Fig. 4, i.e., which is obscured by the power chip 1 when the semiconductor device is viewed, for example, from the side on which the power chip 1 is installed.

[0040] The heat sink 9 is flat at the position corresponding to the lower surface of the power chip 1, that is, in an area located between the Fig. The 4 illustrated dashed lines indicate that the upper surface of the heat sink 9 is parallel to the plane containing the power chip 1.

[0041] The flow support element 12 is not located at the position corresponding to the lower surface of the power chip 1, i.e., a position immediately below the area where the power chip is located. In other words, the position of the heat sink 9 corresponding to the lower surface of the power chip 1 is parallel to the plane containing the power chip 1, thus preventing the power chip 1 and the heat sink 9 from separating or drifting apart, thereby preventing a deterioration in heat dissipation performance.

[0042] On the other hand, for a positional relationship between the flow support part 12 and the ladder frame 6, the flow support part 12 has a position of the heat sink 9 that faces the flow support part 12, i.e., an area on the upper side of Fig. 4, i.e. immediately below the end section of the conductor frame 6, when the semiconductor device is viewed from the side on which the power chip 1 is installed.

[0043] The entire flow support element 12 can be contained within the area immediately below the end section of the conductor frame 6, or a portion of the flow support element 12 can be located outside the area immediately below the end section of the conductor frame 6. That is, the end section of the conductor frame 6 can be contained in a direction towards an upper surface of a region of the heat sink 9 where the flow support element 12 is formed.

[0044] The end section of the conductor frame 6 is contained in the direction towards the upper surface of the area of ​​the heat sink 9 where the flow support part 12 is formed, thus making it possible to avoid an increase in the size of the heat sink 9 and to maximize the heat dissipation efficiency of the power chip 1.

[0045] As described above, in the present embodiment the casting resin 10 is in the Fig. 3 illustrated direction A filled in, that is, from the perspective of Fig. 3 from the left side. That is, the filling opening of the casting resin 10 is, from the perspective of Fig. 3 arranged on the left side.

[0046] A section of the outer mold of the casting resin 10 is provided with a gate mark that differs in gloss from other sections of the casting resin 10. Alternatively, the section of the outer mold of the casting resin 10 is provided with a gate mark that differs in height from the surface of a section of the outer mold of the casting resin due to a pit or a protrusion.

[0047] The partial area of ​​the outer shape of the casting resin 10 refers to the surface of the casting resin 10, that is, to a surface to which the casting resin 10 is exposed from the semiconductor device 101. The gate mark is a mark that remains in the injection opening into which the casting resin 10 is injected.

[0048] The flow support element 12 is located in an end region near a surface on the side opposite the surface into which the casting resin 10 is poured. That is, the flow support element 12 is located in an end region of a surface of the heat sink 9 that the casting resin 10 reaches last. In other words, the flow support element 12 in the heat sink 9 is located in a position on the side opposite the side on which the gate mark is located.

[0049] When the casting resin 10 is poured in, the pressure of the casting resin 10 at a point further away from the filling opening is lower than at a point closer to the filling opening. Since the flow support element 12 is located in the end region of the surface of the heat sink 9 that the casting resin last reaches, an outlet used when the excess casting resin 10 is extruded from the semiconductor device 101 can be enlarged, thereby increasing the fluidity or flowability of the casting resin 10.

[0050] If the flowability of the casting resin 10 can be increased, a resin cavity that forms when the casting resin 10 is poured can be extruded from the semiconductor device 101. If the resin cavity can be extruded, the casting resin 10 can be sufficiently filled between the conductor frame 6 and the heat sink 9, even if the gap between the conductor frame 6 and the heat sink 9 is narrow, i.e., if the insulating layer 14 is thin, thus enabling an improvement in the heat dissipation and insulating properties.

[0051] The casting resin 10 is not necessarily viewed from the perspective of Fig. 3. The resin is poured from the left side. The flow support element 12 is not necessarily located in the final part of the surface that the casting resin 10 last reaches.

[0052] Even if the flow support part 12 is located on a surface that is, for example, closer to the surface into which the casting resin 10 is poured, the flowability of the casting resin 10 can be increased.

[0053] The semiconductor device 101 is formed or cast using a transfer molding process. The semiconductor device 101 is used for high-power applications.

[0054] The bootstrap diode 2 is not strictly necessary. A portion of the conductor frame 6 may or may not be bent. Second embodiment

[0055] A semiconductor device 102 according to a second embodiment is described with reference to Fig. 5 described. The description of components similar to those in the first embodiment is omitted. In Fig. 5 denotes the same reference numbers as those in Fig. Figures 1 to 4 each illustrate identical or corresponding sub-areas.

[0056] Fig. Figure 5 is a side view of the semiconductor device 102 according to the second embodiment. Fig. 5 is a diagram showing a side surface from the perspective of Fig. 1 from the right. A heat sink 21 in the semiconductor device 102 according to the present embodiment differs from that in the first embodiment in that the heat sink 21 has a plurality of recesses 22, as shown in Fig. Figure 5 illustrates the differences between the heat sink 9 in the first embodiment and the heat sink 9 in the first embodiment. The following describes the main differences.

[0057] As in Fig. As illustrated in Figure 5, a surface on the side of a plurality of die pads 8 of the heat sink 21, i.e., an upper surface of the heat sink 21, has recesses 22 which are designed to gradually separate from a plane containing power chips 1 at the positions corresponding to the spaces between the die pads 8. Fig. In section 5, each of the multiple recesses 22 is indicated by a square dashed line. For example, the three recesses 22 are each arranged such that they correspond to the number of spaces between the die pads 8. That is, the number of recesses 22 to be arranged is one less than the number of die pads 8. The number of recesses 22 to be arranged in the heat sink 21 need not be limited to the number of die pads 8. The number of recesses 22 could, for example, be one.

[0058] In the present embodiment, when the semiconductor device is manufactured, the casting resin 10 is poured in the direction in which the power chips 1 are arranged, i.e., in the direction in which the die pads 8 are arranged. In other words, the casting resin 10 is poured in the direction in which the plurality of recesses 22 are arranged. That is, the casting resin 10 is poured from the perspective of Fig. 5. The resin is poured in from either the left or right side. The direction in which the resin is poured is direction A or direction B, which is indicated in Fig. 5 are illustrated.

[0059] If the recesses 22 are arranged at the corresponding positions between the multiple die pads 8, the flowability of the casting resin 10 is also improved at positions corresponding to the lower surfaces of the die pads 8 between the conductor frames 6 and the heat sink 21. Since the flowability of the casting resin 10 is improved, any resin cavity that forms when the casting resin 10 is poured can be easily extruded from the semiconductor device 102.

[0060] Since the resin cavity can be easily extruded from the semiconductor device 102, the casting resin 10 can be sufficiently filled between the conductor frames 6 and the heat sink 21. This means that an insulating layer 14 sufficiently filled with the casting resin 10 can be formed.

[0061] The recesses 22 are each arranged between the plurality of die pads 8 and are not each arranged at positions corresponding to the lower surfaces of the power chips 1, i.e., positions of the heat sink 21 corresponding to the lower surfaces of the power chips 1 are parallel to the plane containing the power chips 1.

[0062] Since the recesses 22 are not arranged at the positions corresponding to the lower surfaces of the power chips 1, it is possible to prevent the power chips 1 and the heat sink 21 from separating or drifting apart, thus preventing a deterioration of the heat dissipation performance. Third embodiment

[0063] A semiconductor device 103 according to a third embodiment is described with reference to Fig. Sections 6 to 8 are described. A description of components similar to those in the first embodiment is omitted. Fig. 6 to 8 denote the same reference numbers as those that are in Fig. Figures 1 to 5 illustrate identical or corresponding sub-areas.

[0064] The semiconductor device 103 according to the present embodiment differs from that in the first embodiment in that the heat sink 31 has an inclined part 32 and a conductor frame 33 has a curved part 34. The following primarily describes the differences from the first embodiment.

[0065] Fig. Figure 6 is a top view of the semiconductor device 103 according to the third embodiment. A conductor frame 33 in the semiconductor device 103 according to the present embodiment has the curved part 34, as shown in Fig. Figure 6 illustrates this. The curved part 34 is positioned between a terminal part 20 exposed in the casting resin 10 and a die pad 8 in the conductor frame 33. That is, the curved part 34 connects the terminal part 20 and the die pad 8.

[0066] In the present embodiment, the casting resin 10 is, for example, in the Fig. The resin 10 is poured in direction C as illustrated in diagram 6. That is, from the perspective of... Fig. 6 filled from the right side.

[0067] Fig. Figure 7 is a side view of the semiconductor device 103 according to the third embodiment. Fig. 7 is a diagram that shows one from the perspective of Fig. 6 corresponds to the lateral surface viewed from below.

[0068] As in Fig. As illustrated in Figure 7, the conductor frame 33 has a curved section 34 which is inclined such that it approaches a lower surface of the heat sink 31 from the terminal section 20 in the direction of the die pad 8. The curved section 34 is, for example, located in a partial area between the conductor terminal 15 and the die pad 8 in the conductor frame 33. A surface having the terminal section 20 is located at a position farther from the heat sink 31 than a surface having the die pad 8.

[0069] The heat sink 31 has the inclined part 32 extending along the curved part 34 in the conductor frame 33. In other words, the curved part 34 in the conductor frame 33 is formed along the inclined part 32 in the heat sink 31. The inclined part 32 is arranged in a region in the heat sink 31 that overlaps the curved part 34 when viewed from above.

[0070] The casting resin 10 is used in the Fig. 7 illustrated direction C. That is, the casting resin 10 is poured from the perspective of Fig. 7 filled from the right side.

[0071] The inclined part 32 in the heat sink 31 and the curved part 34 in the conductor frame 33 are inclined such that they gradually approach a rib mounting surface 11 in the direction in which the casting resin 10 is poured. Accordingly, the casting resin 10 flows easily into an insulating layer 14.

[0072] In the insulating layer 14, the flow rate of the casting resin 10 increases, improving its flowability and thus its fillability. If the insulating layer 14 is thin, the casting resin 10 can therefore be sufficiently filled between the conductor frame 33 and the heat sink 31, thereby improving the heat dissipation and insulation properties.

[0073] Fig. Figure 8 is a side view of the semiconductor device 103 according to the third embodiment. Fig. 8 is a diagram that shows one from the perspective of Fig. 6 in one direction from the right, i.e. in the Fig. The direction C shown in section 6 corresponds to the lateral surface under consideration.

[0074] One in Fig. The dashed line in Figure 8 indicates the conductor frame 33. The conductor frame 33 includes the curved section 34, which is inclined to approach the die pad 8 from the conductor terminal 15 on the lower surface of the heat sink 31. Accordingly, for example, the die pad 8 containing a power chip 1 is closer to the fin mounting surface 11 than a portion of the heat sink 31 that is furthest from the fin mounting surface 31.

[0075] The die pad 8 can be positioned at a location farther from the fin mounting surface 11 than the portion of the heat sink 31 that is furthest from the fin mounting surface 11.

[0076] The casting resin 10 is viewed from the perspective of Fig. 8 filled from the near side. Fourth embodiment

[0077] A semiconductor device 104 according to a fourth embodiment is described with reference to Fig. 9 described. The description of components similar to those in the first embodiment is omitted. Fig. 9 denotes the same reference numbers as those in Fig. Figures 1 to 8 each illustrate identical or corresponding sub-areas.

[0078] The semiconductor device 104 according to the present embodiment differs from that in the third embodiment in that a curved part 42 in a conductor frame 41 is provided with a slot 43. The following primarily describes the differences from the third embodiment.

[0079] Fig. Figure 9 is a top view of the semiconductor device 104 according to the fourth embodiment. The conductor frame 41 in the semiconductor device 104 according to the present embodiment has a plurality of slots 43, each in a plurality of curved parts 42, as shown in Fig. Figure 9 illustrates this.

[0080] The casting resin 10 is in a Fig. 9 illustrated direction C is poured. That is, the casting resin 10 is poured from the perspective of Fig. 9 filled from the right side.

[0081] Since each of the curved parts 42 in the conductor frame 41 is provided with the slot 43, the casting resin 10 also flows from an upper surface of the curved part 42 into an insulating layer 14. If the casting resin 10 also flows from the slot 43 into the insulating layer 14, the flow rate of the casting resin 10 in the insulating layer 14 increases. Even if the insulating layer 14 is thin, the casting resin 10 can be sufficiently filled between the conductor frame 41 and a heat sink 9, thus improving the heat dissipation properties. Although all the curved parts 42 in Fig. 9 each have slots 43, but not all curved parts 42 need each have slots 43, only some of the curved parts 42 may each have slots 43. Fifth embodiment

[0082] A semiconductor device 105 according to a fifth embodiment is described. A description of components similar to those in the first embodiment is omitted.

[0083] In the semiconductor device 105 according to the present embodiment, a switching device and a diode device are each formed from a semiconductor with a wide band gap.

[0084] The switching device and the diode device, each formed from a wide-bandgap semiconductor, exhibit high dielectric strength and a high permissible current density. Accordingly, the switching device and the diode device can be miniaturized. By using the miniaturized switching device and diode device, the semiconductor device can also be miniaturized.

[0085] The switching device and the diode device, each formed from the wide-bandgap semiconductor, also exhibit high thermal resistance. Consequently, the heat sink and fins can be miniaturized. Furthermore, the wide-bandgap semiconductor exhibits low power loss. Therefore, the switching device and the diode device can be made highly efficient, and the semiconductor device can be designed with high efficiency in mind.

[0086] Although both the switching device and the diode device are preferably formed from a wide bandgap semiconductor, one of the elements may be formed from a wide bandgap semiconductor.

[0087] Aspects of the present invention are described together as complements. (Supplementary Note 1)

[0088] A semiconductor device comprising: a heat sink; a die pad that is positioned above and away from the heatsink; a power chip located on a surface of the die pad that is opposite a surface of the die pad facing the heat sink; and a casting resin that seals a portion of the heatsink, the die pad and the power chip, wherein a surface of the heat sink facing the die pad has a flow support part which is designed to separate from a plane having the die pad in an area overlapping the die pad and not overlapping the power chip. (Supplementary Note 2)

[0089] The semiconductor device according to supplementary note 1, wherein a portion of the outer shape of the casting resin is provided with a gate mark which differs in gloss from other portions of the casting resin or differs in height from a surface of a portion of the outer shape of the casting resin due to a cavity or a projection and the flow support part of the heat sink is located in a position on the side opposite the side on which the gate mark is located. (Supplementary Note 3)

[0090] The semiconductor device according to supplementary note 1 or 2, comprising a plurality of power chips, wherein a surface of the heat sink on the side of the die pad has recesses designed to separate from a plane comprising the die pad at intervals between the positions corresponding to the plurality of die pads. (Supplementary Note 4)

[0091] The semiconductor device according to one of supplementary remarks 1 to 3, wherein a conductor frame arranged above and away from the heat sink and comprising the die pad, has a terminal part exposed from the casting resin and a curved part connecting the terminal part and the die pad, a surface that has the connector part, is located in a position further away from the heatsink than a surface that has the die pad, and The heat sink has an inclined part that is arranged along the curved part of the conductor frame in an area that overlaps the curved part in plan view. (Supplementary Note 5)

[0092] The semiconductor device according to supplementary note 4, wherein the curved part in the conductor frame is provided with a slot. (Supplementary Note 6)

[0093] The semiconductor device according to one of supplementary remarks 1 to 5, wherein the power chip includes an RC-IGBT. (Supplementary Note 7)

[0094] The semiconductor device according to one of supplementary remarks 1 to 6, wherein the power chip and a diode device are formed from a wide bandgap semiconductor. Reference symbol list

[0095] 1 Power chip; 2 Bootstrap diode; 3 Freewheeling diode; 6, 33, 41 Conductor frame; 7 Wire; 8 Die pad; 9, 21, 31 Heat sink; 10 Cast resin; 12 Flow support part; 14 Insulating layer; 15 Conductor connection; 22 Recess; 32 Inclined part; 34, 42 Bent part; 43 Slot; 101, 102, 103, 104 Semiconductor device

Claims

[1] Semiconductor device comprising: a heat sink (9, 21, 31); a die pad (8) located above and away from the heat sink (9, 21, 31); a power chip (1) arranged on a surface of the die pad (8) opposite a surface of the die pad (8) facing the heat sink (9, 21, 31); and a casting resin (10) that seals a portion of the heat sink (9, 21, 31), the die pad (8) and the power chip (1), wherein a surface of the heat sink (9, 21, 31) facing the die pad (8) has a flow support part (12) which is designed to separate from a plane having the die pad (8) in an area overlapping the die pad (8) and not overlapping the power chip (1). [2] Semiconductor device according to claim 1, wherein a portion of the outer shape of the casting resin (10) is provided with a gate mark which differs in gloss from other portions of the casting resin (10) or differs in height from a surface of a portion of the outer shape of the casting resin (10) due to a cavity or projection, and the flow support part (12) of the heat sink (9, 21, 31) is arranged at a position on the side opposite a side on which the gate mark is arranged. [3] Semiconductor device according to claim 1, comprising a plurality of power chips (1), wherein a surface of the heat sink (21) on the side of the die pad (8) has recesses (22) which are designed to separate from a plane comprising the die pad (8) at intervals between the positions corresponding to the plurality of die pads (8). [4] Semiconductor device according to claim 1, wherein a conductor frame (33) arranged above and away from the heat sink (31) and comprising the die pad (8), has a terminal part (20) exposed from the casting resin (10) and a curved part (34, 42) connecting the terminal part (20) and the die pad (8), a surface having the connector part (20) is located at a position further away from the heat sink (31) than a surface having the die pad (8), and the heat sink (31) has an inclined part (32) which is arranged along the curved part (34, 42) of the conductor frame (33) in an area overlapping the curved part (34, 42) in plan view. [5] Semiconductor device according to claim 4, wherein the curved part (42) in the conductor frame (33) is provided with a slot (43). [6] Semiconductor device according to claim 1, wherein the power chip (1) includes an RC-IGBT. [7] Semiconductor device according to any one of claims 1 to 6, wherein the power chip (1) and a diode device (3) are formed from a wide bandgap semiconductor.

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