Semiconductor device and method of manufacture thereof

Abstract

A semiconductor device comprises a resistive random-access memory (RRAM) device (100), a dual damascus structure (102), and a spacer (104). The dual damascus structure (102) is located near the RRAM device (100), and the spacer (104) is located in a side wall of the RRAM device. The RRAM device (100) comprises a lower electrode (112), a metal oxide layer (114), and an upper electrode (116). The metal oxide layer (114) is located on the lower electrode (112), and the upper electrode (116) is located on the metal oxide layer (114). The dual damascene structure (102) includes a via (118) and a wire (120) arranged on the via (118), wherein an upper part (120a) of the wire (120) is coplanar with an upper part (116a) of the upper electrode (116) in the RRAM device (100).

Description

BACKGROUNDTechnical field

[0001] The disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof that simultaneously form a resistive random access memory (RRAM) device and internal connections. Description of the state of the art

[0002] An RRAM device is a non-volatile memory characterized by a small memory cell size, extremely fast operation, low power consumption, and a long endurance. Therefore, this device has become a type of non-volatile memory that has been intensively studied in recent years. However, the manufacturing process of an RRAM device requires at least three mask processes. Furthermore, there is currently no research on integrating the manufacturing process of an RRAM device and the manufacturing process of a dual damascene structure. US 2018 / 0 040 817 A1 discloses an improved integrated circuit having an embedded memory disposed between two discontinuous metal layers and adjacent to two interconnected metal vias, and related manufacturing methods.Furthermore, US 2019 / 0 131 524 A1 describes a memory device comprising a substrate, an etch stop layer, a protective layer and a resistive switching element, wherein the substrate has a memory region and a logic region, and has a metallization pattern therein.US 8 000 128 B2 describes an RRAM cell including a first electrode having a lower portion, a continuous side portion, and wherein the continuous side portion includes an outer and an inner surface; a resistive layer including a lower portion, a continuous side portion, and an upper portion, wherein the lower portion and the continuous side portion include an outer and an inner surface; and a second electrode having a lower portion, an upper portion, and an outer surface; wherein the outer surface of the resistive layer contacts the inner surface of the first electrode. US 2022 / 0 393 105 A1 discloses non-volatile memories (NVM) and in particular RRAM cells, for example cation-based resistive RAM, CBRAM cells, and oxide-based resistive RAM, OxR-RAM cells, and methods for their fabrication.US 2010 / 0 081 268 A1 relates to integrated circuits containing non-volatile memory arrays, and in particular, these arrays comprise passive element memory cells. Furthermore, a method for fabricating a memory cell comprising a metal insulator diode and a carbon memory element in a single damascene process is disclosed.

[0003] The object is therefore to create an improved RRAM device with an internal connection.

[0004] The object is achieved by the semiconductor device according to patent claim 1 and the method for producing a semiconductor device according to patent claim 8. Further embodiments emerge from the dependent patent claims. SUMMARY

[0005] The disclosure provides a semiconductor device that can fabricate a resistive random access memory (RRAM) device and a dual damascene structure with few mask processes.

[0006] The disclosure also provides a manufacturing method for a semiconductor device that can integrate the manufacturing process of the RRAM device and the manufacturing process of the dual damascene structure.

[0007] The semiconductor device according to the disclosure includes a resistive random access memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed adjacent to the RRAM device, and the spacer is disposed on the sidewall of the RRAM device. The RRAM device includes a bottom electrode, a metal oxide layer, and a top electrode. The metal oxide layer is disposed on the bottom electrode, and the top electrode is disposed on the metal oxide layer.The dual damascene structure comprises a via and a wire disposed on the via, wherein an upper portion of the wire is coplanar with an upper portion of the upper electrode in the RRAM device, wherein in a cross-sectional view, the thickness of the spacer (104) disposed on a right side of the RRAM device (100) is different from the thickness of the spacer (104) disposed on a left side of the RRAM device (100).

[0008] In one embodiment of the disclosure, the upper part of the spacer may also be coplanar with the upper part of the top electrode of the RRAM device.

[0009] In one embodiment of the disclosure, the upper portion of the spacer may be coplanar with the upper portion of the wire.

[0010] In one embodiment of the disclosure, the shape of the spacer is formed as a rectangle in a cross-sectional view.

[0011] In one embodiment of the disclosure, the metal oxide layer is U-shaped.

[0012] In one embodiment of the disclosure, the lower surface of the lower electrode is coplanar with the lower part of the dual damascene structure.

[0013] In one embodiment of the disclosure, the material of the lower electrode may be titanium, the material of the metal oxide layer may be hafnium oxide, and the material of the upper electrode may be titanium nitride.

[0014] The manufacturing method of the semiconductor device according to the disclosure includes forming a dielectric layer on a base having a metal layer, forming an opening in the dielectric layer to expose the metal layer, forming a spacer on the sidewall of the opening, forming a lower electrode on the lower part of the opening, conformally forming a metal oxide layer on the lower electrode, forming an upper electrode on the metal oxide layer, wherein the upper electrode (116) fills the opening (01), forming a dual damascene hole having a cavity and a trench in the dielectric layer near the opening, filling the dual damascene hole with a conductive material, and then performing a planarization process to simultaneously remove a part of the conductive material and a part of the upper electrode.

[0015] In another embodiment of the disclosure, the method of manufacturing the spacer includes first filling the opening with a nitride layer, forming a patterned mask on the dielectric layer and exposing a portion of the nitride layer, and then, using the patterned mask as an etch mask, etching the exposed portion of the nitride layer until the metal layer is exposed.

[0016] In another embodiment of the disclosure, the method of fabricating the spacer includes conformally depositing a nitride layer on the inner surface of the opening and then etching back the nitride layer until the metal layer is exposed.

[0017] In another embodiment of the disclosure, the step of forming the top electrode includes forming a redundant portion on the dielectric layer that is not the opening. The method of forming the dual damascene hole includes patterning the redundant portion on the dielectric layer to form a first patterned mask, etching the dielectric layer to form the trench in the dielectric layer using the first patterned mask as an etch mask, forming a second patterned mask in the trench to expose a portion of the dielectric layer, and then etching the dielectric layer to form the cavity in the dielectric layer below the trench using the second patterned mask as an etch mask.

[0018] In another embodiment of the disclosure, the method of forming the lower electrode includes filling the opening with a conductive layer, planarizing the conductive layer, and then etching back the conductive layer.

[0019] In order to make the above-mentioned features of the disclosure more understandable, the embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the disclosure. Fig. 2A to Fig. 2N are schematic cross-sectional views of a manufacturing method for a semiconductor device according to the second embodiment of the disclosure. DESCRIPTION OF THE EMBODIMENTS

[0020] The disclosure is applied to a semiconductor device including a resistive random access memory (RRAM) device and internal interconnections, and through device and process design, the position and height of the RRAM device can be the same as or similar to the dual damascene structure in the internal interconnections, in particular, with respect to the manufacturing process, at least one mask process can be reduced, thereby reducing the manufacturing cost, and the process can be integrated with the manufacturing process of the internal interconnections.

[0021] To illustrate the disclosure, some embodiments are listed below; however, the disclosure is not limited to the listed embodiments. It is also possible to combine the various embodiments.

[0022] Fig. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the disclosure.

[0023] See Fig. 1. The semiconductor device according to the first embodiment essentially includes an RRAM device 100, a dual damascene structure 102, and a spacer 104. The dual damascene structure 102 is disposed adjacent to the RRAM device 100, and the spacer 104 is disposed on a sidewall 100a of the RRAM device 100. In one embodiment, the RRAM device 100 and the dual damascene structure 102 may be disposed on a base 106. Generally, the base 106 includes a semiconductor base (not shown), a dielectric layer IMD1 thereon, and a metal layer 108a and a metal layer 108b formed in the dielectric layer IMD1.The material of the dielectric layer IMD1 is, for example, but not exclusively, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide (SiO2), SiOC-based material, or other suitable extremely low dielectric constant (ELC) or ultra-low dielectric constant (ULC) materials. The material of the metal layer 108a and the metal layer 108b is, for example, copper (Cu) or other suitable metal materials such as cobalt (Co), aluminum (Al), tungsten (W), nickel (Ni), platinum (Pt), tantalum (Ta), or titanium (Ti). A barrier layer 110 may be disposed between the metal layer 108a and the dielectric layer IMD1, and similarly, another barrier layer 110 may be disposed between the metal layer 108b and the dielectric layer IMD1.The material of the barrier layer 110 is, for example, but not exclusively, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a stack layer comprising the above-mentioned materials. Although in . Fig. 1, it should be noted that there may be other internal connections, such as metal layers or contacts formed beneath the dielectric layer IMD1, etc. The material of the dual damascene structure 102 is, for example, but not exclusively, a group including, but not limited to, Cu, Co, Al, W, Ni, Pt, Ta, Ti, titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), etc.

[0024] In Fig. 1, the RRAM device 100 includes a bottom electrode 112, a metal oxide layer 114, and a top electrode 116. The metal oxide layer 114 is disposed on the bottom electrode 112, and the top electrode 116 is disposed on the metal oxide layer 114. The bottom electrode 112 is connected to the metal layer 108a to establish electrical connection. The material of the bottom electrode 112 is, for example, titanium (Ti) or other suitable conductive materials, such as tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), iridium (Ir), ruthenium (Ru), aluminum (Al), copper (Cu), gold (Au), and tungsten (W). The material of the top electrode 116 is, for example, titanium nitride or other suitable conductive materials, such as titanium, tantalum, tantalum nitride, platinum, iridium, ruthenium, aluminum, copper, gold, and tungsten. The material of the metal oxide layer 114 is e.g.Hafnium oxide (HfO2) or other suitable metal oxides such as, but not limited to, nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), tantalum oxide (TaO), or other transition metal oxides (TMO). Furthermore, due to the manufacturing process, the metal oxide layer 114 may extend on two sides of the top electrode 116 and directly contact the spacer 104, such that the metal oxide layer 114 is U-shaped. The dual damascene structure 102 generally includes a via 118 and a wire 120 disposed on the via 118, with the via 118 connected to the metal layer 108b to establish electrical connection.In the first embodiment, an upper portion 120a of the wire 120 is coplanar with an upper portion 116a of the upper electrode 116 in the RRAM device 100, so that the wire 120 and the upper electrode 116 can be obtained through the same planarization process, thereby integrating the manufacturing process of the RRAM device 100 and the dual damascene structure 102. In one embodiment, a lower surface 112a of the lower electrode 112 is coplanar with a lower portion 102a of the dual damascene structure 102. The RRAM device 100 and the dual damascene structure 102 are generally formed in a dielectric layer IMD2. The material of the dielectric layer IMD2 is, for example, but not exclusively, USG, PSG, BSG, BPSG, FSG, SiO2, SiOC-based materials or other suitable ELK or ULK materials.Furthermore, a barrier layer 122 may be disposed between the dual damascene structure 102 and the dielectric layer IMD2, a cap layer 124 may be formed on the dielectric layer IMD1, and a cap layer 126 may also be formed on the dielectric layer IMD2. The material of the barrier layer 122 is, for example, but not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a stacked layer of the above-mentioned materials. The materials of the cap layer 124 and the cap layer 126 may independently include, but are not limited to, silicon nitride (SiN), silicon oxynitride (SiON), silicon nitride carbide (SiCN), or nitrogen-doped carbon (NDC).

[0025] Since the key to the operation of the RRAM device 100 lies in the thickness of the metal oxide layer 114, the sizes (such as the thicknesses) of the upper electrode 116 and the lower electrode 112 can be adjusted as long as the thickness of the metal oxide layer 114 is controlled within a required range. Therefore, in addition to the upper electrode 116 and the lower electrode 112 shown in Fig. 1 have almost the same thickness, a thick bottom electrode 112 with a thin top electrode 116 may also be used. Alternatively, a thin bottom electrode 112 with a thick top electrode 116 may also be used. In one embodiment, an upper portion 104a of the spacer 104 may also be coplanar with the upper portion 116a of the top electrode 116 of the RRAM device 100. In one embodiment, the upper portion 104a of the spacer 104 may be coplanar with the upper portion 120a of the wire 120.

[0026] See also Fig. 1. In cross-sectional view, the shape of the spacer 104 may be rectangular. This means that the thickness difference between the upper and lower ends of the spacer 104 is small, so that the upper half of the spacer 104 may have a sufficient thickness to achieve a significant effect in preventing the diffusion of oxygen atoms. In one embodiment, the material of the spacer 104 is, for example, silicon nitride or another suitable dielectric material, such as silicon oxynitride or silicon nitride carbide.

[0027] Fig. 2A to Fig. 2N are schematic cross-sectional views of a manufacturing method for a semiconductor device according to the second embodiment of the disclosure.

[0028] See first Fig. 2A. A dielectric layer 206 is formed on a base 200 with a metal layer 202. The base 200 may include a semiconductor base (not shown), a dielectric layer IMD thereon, and the metal layer 202, etc. The materials of the dielectric layer 206 and the dielectric layer IMD each independently include, but are not limited to, USG, PSG, BSG, BPSG, FSG, SiO2, SiOC-based materials, or other suitable ELK or ULK materials. The material of the metal layer 202 is, for example, copper or other suitable metal materials such as Co, Al, W, Ni, Pt, Ta, or Ti. A barrier layer 201 may be formed between the metal layer 202 and the dielectric layer IMD. The material of the barrier layer 201 is, for example, but not exclusively, Ti, TiN, Ta, TaN, or a stacked layer of the above-mentioned materials. Although Fig. 2A, it should be noted that there may be other internal connections, such as metal layers or contacts formed beneath the dielectric layer IMD1, etc. In one embodiment, a cap layer 204 may be formed on the base 200 prior to the formation of the dielectric layer IMD, where the material of the cap layer 204 may include, but is not limited to, SiN, SiON, SiCN, or NDC.

[0029] Next, Fig. 2B. Using a photolithographic process, an opening O1 is formed in the dielectric layer 206 to expose the metal layer 202. The method for forming the opening O1 is, for example, a photolithographic etching process. During the etching process, a portion of the dielectric layer 206 is removed, and then the cap layer 204 is further etched until a portion of the metal layer 202 is exposed.

[0030] See after Fig. 2C. To form a spacer on the sidewall of opening O1, a nitride layer 208 may first be used to fill opening O1, wherein the material of nitride layer 208 may be, for example, silicon nitride or other suitable dielectric materials such as silicon oxynitride or silicon nitride carbide. After opening O1 is filled with nitride layer 208, a planarization process may be required to remove nitrides other than opening O1. Next, a patterned mask 210 may be formed on dielectric layer 206 using another photolithographic process, and a portion of nitride layer 208 may be exposed. Patterned mask 210 may be a photoresist layer or other material layers having an etch selectivity relationship to nitride layer 208.

[0031] See also Fig. 2D. Using the structured mask 210 in Fig. 2C as an etching mask, the exposed part of the nitride layer 208 is Fig. 2C, the patterned mask 210 is etched until the metal layer 202 is exposed, and a narrow opening O2 is formed in the original opening O1. Then, the patterned mask 210 is removed. In the cross-sectional view, the shape of a spacer 208' formed according to the above step is approximately rectangular. This means that the difference in thickness between the upper end and the lower end of the spacer 208' is small. Also in the cross-sectional view, the thickness of the spacer 208' obtained on the left side after the above two photolithographic processes differs from the thickness of the spacer 208' obtained on the right side, but the spacer 208' serving as a protective layer is not affected. In another embodiment, the spacer 208' may also be manufactured using a general spacer process.For example, a nitride layer is conformally deposited on the inner surface of the opening O1, and then an etch-back is performed until the metal layer 202 is exposed.

[0032] See now Fig. 2E. To form a lower electrode on the lower part of the opening O2, the opening may be filled with a conductive layer 212. The fabrication method for the conductive layer 212 is, for example, evaporation or other suitable deposition methods, and the material of the conductive layer 212 is, for example, Ti or other suitable conductive materials such as Ta, TiN, TaN, Pt, Ir, Ru, Al, Cu, Au, or W.

[0033] See also Fig. 2F. After the conductive layer 212 in Fig. 2E, a bottom electrode 212' may be obtained, in which the etchant used for the above etching is, for example, sulfuric acid. Since the key to the operation of the RRAM device lies in the thickness of the metal oxide layer, the thickness of the bottom electrode 212' may, for example, be adjusted to be thicker or thinner than in Fig. 2F.

[0034] Then, with reference to Fig. 2G, a metal oxide layer 214 is conformally formed on the lower electrode 212', wherein the material of the metal oxide layer 214 is, for example, HfO2 or other suitable metal oxides such as, but not limited to, nickel oxide, titanium oxide, zinc oxide, zirconium oxide, tantalum oxide, or other transition metal oxides (TMO). Thereafter, an upper electrode 216 is formed on the metal oxide layer 214 and the opening O2 is filled, wherein the material of the upper electrode 216 is, for example, titanium nitride or other suitable conductive materials such as titanium, tantalum, tantalum nitride, platinum, iridium, ruthenium, aluminum, copper, gold, tungsten. During the formation of the upper electrode 216, a redundant portion 218, which is not the opening O2, is formed on the dielectric layer 206. The redundant section 218 may also include the metal oxide layer 214, wherein the thickness of the redundant section 218 may be 100 Å to 200 Å.

[0035] Next, see Fig. 2H, the redundant section 218 can be Fig. 2G may first be patterned to form a first patterned mask 218' on the dielectric layer 206, and a predetermined dual damascene hole formation portion is exposed to form a dual damascene hole in the dielectric layer 206 near the opening O2.

[0036] Then, as in Fig. 2I, using the first patterned mask 218' as an etch mask, the dielectric layer 206 is etched to form a trench 220 in the dielectric layer 206, and the trench 220 may extend into the side. Then, a second patterned mask 222 is formed in the trench 220 to expose a portion of the dielectric layer 206, and using the second patterned mask 222 as an etch mask, the dielectric layer 206 is etched to form a cavity 224 in the dielectric layer 206 below the trench 220. The second patterned mask 222 also covers the remaining portions so that the surrounding structures are not affected during the etching of the cavity 224.

[0037] After removing the second structured mask 222 in Fig. 2I can next, as in Fig. 2J, a barrier layer 228 may be formed on the inner surface of a dual damascene hole 226 formed by the trench 220 and the cavity 224, wherein the material of the barrier layer 228 is, for example, but not limited to, Ti, TiN, Ta, TaN, or a stacked layer of the above-mentioned materials.

[0038] Then, the dual damascene hole 226 is filled with a conductive material 230, wherein the conductive material 230 is selected from a group including, but not limited to, Cu, Co, Al, W, Ni, Pt, Ta, Ti, TiAl, CoWP, etc.

[0039] Next, a planarization process (such as a CMP process) is performed to simultaneously remove a portion of the conductive material and a portion of the top electrode 216 to form a dual damascene structure 230' and an RRAM device 232 positioned adjacent to the dual damascene structure 230', where the RRAM device 232 includes the bottom electrode 212', the metal oxide layer 214, and the top electrode 216. Because the removed portions include different materials, the planarization process may require segmented grinding using different grinding materials.

[0040] Next, see Fig. 2M, the interconnect structure may be further formed on the finished semiconductor device, e.g., a cap layer 234 is first formed to cover the dielectric layer 206, the dual damascene structure 230', the top electrode 216, and the spacer 208', etc. Regarding the material of the cap layer 234, reference may be made to the cap layer 204, so details will not be repeated here.

[0041] See also Fig. 2N. After a dielectric layer 236 has been formed, a dual damascene structure 238a and a dual damascene structure 238b can be formed therein, a barrier layer 240 can be formed between the dual damascene structure 238a and the dielectric layer 236, and similarly, the barrier layer 240 can be formed between the dual damascene structure 238b and the dielectric layer 236. Regarding the manufacturing process of the dielectric layer 236, the dual damascene structure 238a and the dual damascene structure 238b, reference can be made to the manufacturing process of the dual damascene structure 230' in Fig. 2H to Fig. 2L, so details are not repeated here. The dual damascene structure 238a is connected to the upper electrode 216, and the dual damascene structure 238b is connected to the dual damascene structure 230'.

[0042] In this embodiment, opening O1 is formed first, then spacer 208' is formed on the sidewall of opening O1, and RRAM device 232 is deposited and formed in opening O2, followed by a series of planarization processes. Therefore, at least one photomask process can be omitted. Furthermore, before the planarization process of RRAM device 232, dual damascene structure 230' is formed, then the upper part of dual damascene structure 230' can be planarized while RRAM device 232 is planarized, thereby achieving the integration of the manufacturing process of RRAM device 232 and dual damascene structure 230'.

[0045] List of reference symbols RRAM Resistive Random Access Memory 100, 232 RRAM device 102, 230', 238a, 238b dual Damascus structure 104, 208' spacers 100a side wall 106 Base IMD1 dielectric layer 108a metal layer 112.212' lower electrode 114 Metal oxide layer 116, 216 upper electrode 118 vias 120 wire 108b metal layer 120a top layer 112a lower surface 102a lower part IMD2 dielectric layer 122, 201, 228, 240 barrier layer 124, 204, 234 top layer 126 Top layer 206, 236 dielectric layer 200 base 202, 108a metal layer IMD dielectric layer 01 Opening 208 Nitride layer 210, 218' structured mask 222 second structured mask O2 narrow opening 212 conductive layer 218 redundant section 220 ditch 224 Cavity 226 Damascus Hole 228 barrier layer 230 conductive material 116a, 120a, 104a upper part IMD dielectric layer

Claims

[1] Semiconductor device comprising: a resistive random access memory, RRAM device (100); a dual damascene structure (102) disposed adjacent to the RRAM device (100); and a spacer (104) arranged on a side wall of the RRAM device (100), wherein the RRAM device (100) comprises: a lower electrode (112); a metal oxide layer (114) disposed on the lower electrode (112); and an upper electrode (116) disposed on the metal oxide layer (114); wherein the dual Damascus structure (102) comprises: a via (118); and a wire (120) disposed on the via (118), wherein an upper portion (120a) of the wire (120) is coplanar with an upper portion (116a) of the upper electrode (116) of the RRAM device (100), wherein, in a cross-sectional view, the thickness of the spacer (104) on a right side of the RRAM device (100) is different from the thickness of the spacer (104) on a left side of the RRAM device (100). [2] The semiconductor device according to claim 1, wherein an upper part (104a) of the spacer (104) is coplanar with the upper part (116a) of the upper electrode (116) of the RRAM device (100). [3] The semiconductor device according to claim 1, wherein an upper part (104a) of the spacer (104) is coplanar with the upper part (120a) of the wire (120). [4] The semiconductor device according to claim 1, wherein in a cross-sectional view, a shape of the spacer (104) is formed as a rectangle. [5] A semiconductor device according to claim 1, wherein the metal oxide layer (114) is U-shaped. [6] The semiconductor device according to claim 1, wherein a bottom surface (112a) of the lower electrode (112) is coplanar with a bottom surface (102a) of the dual damascene structure (102). [7] The semiconductor device according to claim 1, wherein a material of the lower electrode (112) comprises titanium, a material of the metal oxide layer (114) comprises hafnium oxide, and a material of the upper electrode (116) comprises titanium nitride. [8] A method of manufacturing a semiconductor device, comprising: Forming a dielectric layer (IMD) on a base with a metal layer (108a); Forming an opening (Ol) in the dielectric layer (IMD) to expose the metal layer (108a); Forming a spacer (104) on a side wall (100a) of the opening (O1); Forming a lower electrode (112) on a lower part (102a) of the opening (O1); conformally forming a metal oxide layer (114) on the lower electrode (112); Forming an upper electrode (116) on the metal oxide layer (114), the upper electrode (116) filling the opening (Ol); Forming a dual damascene hole (226) having a cavity (224) and a trench (220) in the dielectric layer (IMD) adjacent to the opening (O1); Filling the dual Damascus hole (226) with a conductive material (230); and Performing a planarization process to simultaneously remove a portion of the conductive material (230) and a portion of the top electrode (116). [9] A method of manufacturing the semiconductor device according to claim 8, wherein a method of forming the spacer (104) comprises: Filling the opening (Ol) with a nitride layer (208); Forming a patterned mask (210) on the dielectric layer (IMD) and exposing a portion of the nitride layer (208); and Etching the exposed portion of the nitride layer (208) using the patterned mask (210) as an etching mask until the metal layer (108a) is exposed. [10] A method of manufacturing the semiconductor device according to claim 8, wherein a method of forming the spacer (104) comprises: conformally depositing a nitride layer (208) on an inner surface of the opening (O1); and Etching back the nitride layer (208) until the metal layer (108a) is exposed. [11] A manufacturing method for the semiconductor device according to claim 8, wherein a step of forming the upper electrode (116) comprises forming a redundant portion (218) on the dielectric layer (IMD) other than the opening (Ol), and a method of forming the dual damascene hole (226) comprises: Patterning the redundant portion (218) on the dielectric layer (IMD) to form a first patterned mask (218'); Etching the dielectric layer (IMD) using the first patterned mask (218') as an etch mask to form the trench (220) in the dielectric layer (IMD); Forming a second patterned mask (222) in the trench (220) to expose a portion of the dielectric layer (IMD); and Etching the dielectric layer (IMD) using the second patterned mask (222) as an etch mask to form a cavity (224) in the dielectric layer (IMD) below the trench (220). [12] A method of manufacturing the semiconductor device according to claim 8, wherein a method of forming the lower electrode (112) comprises: Filling the opening (Ol) with a conductive layer (212); Planarizing the conductive layer (212); and Etching back the conductive layer (212).

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