VERIFICATION SYSTEM FOR AN I2S BUS PROTOCOL

Abstract

An I2S bus protocol verification system comprises a receiver and converter unit, a configuration unit, a clock control unit, and a data conversion unit. The receiver and converter unit receives a control command sent by the UVM verification platform and converts it into an execution command. The configuration unit configures the system parameters. The clock control unit opens or closes and generates a clock signal with a corresponding timing sequence according to the system parameters. The data conversion unit receives data information from the UVM verification platform and converts it into a data type that matches the device under test (DUT), or it receives data information from the device under test and converts it into a data type that matches the UVM verification platform.The present system can cover all device types used for the I2S protocol standard, thus enabling rapid verification and monitoring of data on the interface to realize verification for I2S bus devices.

Description

FIELD OF THE INVENTIONThe invention relates to the technical field of protocol verification for communication buses, in particular to a verification system for an I2S bus protocol (inter-IC sound).BACKGROUND OF THE INVENTIONAn I2S bus (Inter-IC sound) as a standard for audio data transmission is widely used in audio apparatuses. The existing technology for verifying the I2S bus protocol involves the use of FPGA (field-programmable gate array) or other fixed circuitry for simulating I2S devices and for communication with the device under test (DUT) to ultimately validate the communication results. However, the content of communication is generally limited by the circuit.Current verification of the I2S bus protocol uses FPGA or fixed I2S circuits to communicate with the DUT. Such verification is not suitable for the multiple supply of audio devices with I2S circuits in the consumer market, however. It is difficult to cover the various scenarios that may result from the different device types using the I2S bus. In addition, this method lacks randomness in the validation process and requires high cost and limited versatility to build a large number of I2S circuits. On the other hand, the use of FPGA to simulate the I2S devices for verification would be awkward and error prone, as the code must be replaced in different scenarios. Moreover, using the fixed I2S circuits or the FPGA simulation, only the normal communication between the device under test (DUT) and the I2S package can be validated, which does not allow a check for randomness, so that validation engineers can easily overlook abnormal bus communication. These overseeed abnormal situations are likely not found in normal tests, but may have fatal consequences when occurring in the actual chip product.For this reason, it is difficult for the existing technical solutions to locate and identify specific failures when a defective device under test (DUT) is connected via the I2S bus, and the ability to recover from failures is limited.Therefore, it is necessary to develop an improved verification system for the I2S bus to address the above deficiencies.SUMMARY OF THE INVENTIONThe object of the present invention is to provide a verification system for an I2S bus protocol. By configuring various system parameters, the verification system of the present invention can cover all types of devices that are applied to the I2S protocol standard, thereby quickly achieving verification and monitoring all data on the interface to realize the verification of the I2S bus devices.In order to achieve the above purpose, a verification system for an I2S bus protocol based on a Universal Verification Methodology (UVM) verification platform comprises a receiving and converting unit, a configuration unit, a clock control unit and a data converting unit. The receiving and converting unit is configured to receive a control command sent from the UVM verification platform and convert the control command into another execution command that can be recognized and executed by other units. The configuration unit is configured to configure the system parameters based on the execution instruction sent from the receiving and converting unit such that the system parameters conform to the requirements of the UVM verification platform. The clock control unit is configured to open or close based on the execution command sent from the receiving and converting unit and to generate a clock signal having a corresponding time sequence according to the system parameters, through which the verification system communicates with the device under test. The data conversion unit is configured to receive data information from the UVM verification platform via the receiving and converting unit, convert the data information into a data type matching the DUT, and transmit the data information to the device under test for verification; or the data conversion unit is configured to receive data information from the device under test, convert the data information into a data type matching the UVM verification platform, and transmit the data information to the UVM verification platform for verification.In a preferred embodiment, a pre-storage unit is further included and is configured to pre-store the data information sent from the UVM verification platform via the receiving and converting unit and the data information sent from the device under test via the data converting unit.In a preferred embodiment, a communication role, a communication clock, a communication mode, a data transmission direction and a valid data length of the verification system are configured in the configuration unit based on specifications of an I2S communication protocol and the UVM verification platform.In a preferred embodiment, the communication role of the system comprises a master and a slave, the communication mode comprises a half-duplex communication mode and a full-duplex communication mode, and the data transmission direction comprises data input and data output.In a preferred embodiment, a frequency and a time sequence of the communication clock are configured in the configuration unit.Preferably, the data conversion unit is configured to convert the data received from the receiving and converting unit into serial data and to convert the data received from the device under test into parallel data.In a preferred embodiment, the data conversion unit is configured to compare a received data length with the valid data length set in the configuration unit; if the received data length is less than the valid data length, binary zero padding is performed on the lower bits of the received data; if the received data length is greater than the valid data length, the lower bits of the received data are ignored.In a preferred embodiment, the verification system further includes an interface unit provided with a bit clock signal line, a frame clock signal line and two serial data lines, each line being in point-to-point communication with the device under test.Preferably, in half-duplex communication mode, one of the two serial data lines is not connected; in full-duplex communication mode, the two serial data lines have an opposite direction of transmission.Compared to the prior art, the verification system for an I2S bus protocol in the present invention is a dedicated verification system for the I2S bus and is based on the UVM verification platform. In the verification system for an I2S bus protocol of the present invention, various system parameters are configured in the configuration unit, communication between various I2S devices and the device under test (DUT) is simulated over the bus interface, and all data on the interface is monitored, thereby checking completeness and correctness of the design function. Moreover, with this verification system, the verification engineers can flexibly change the attributes of the verification platform according to the specific design specifications, thus ensuring the integrity and efficiency of the verification process.BRIEF DESCRIPTION OF THE DRAWINGSThe figures facilitate understanding of the various embodiments of the present invention: FIG. 1 is a schematic diagram of the verification system for an I2S bus protocol according to an embodiment of the present invention; andReferring now to FIG. 2, there is shown a schematic illustration of the connection between the interface unit of the I2S bus protocol verification system and the device under test (DUT) in accordance with an embodiment of the present invention.DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTSReferring to the accompanying drawings, the embodiments of the present invention will be described. Like reference numerals in the drawings represent like elements. As described above, the present invention provides an I2S bus protocol verification system that can cover all device types specified in the I2S protocol standard by configuring various system parameters, thereby enabling rapid verification and monitoring of all data on the interface and achieving verification of I2S bus devices.The verification system for an I2S bus protocol of the present invention is based on a UVM verification platform and comprises a receiving and converting unit, a configuration unit, a clock control unit and a data converting unit. The receiving and converting unit is configured to receive control commands from the UVM verification platform and convert the control commands into various execution commands that can be recognized and executed by other units. The configuration unit is adapted to configure the system parameters on the basis of the execution instructions sent from the receiving and converting unit, so that the system parameters correspond to the requirements of the UVM verification platform, whereby different test specimens (DUTs) can be adapted to the UVM verification platform after the parameter configuration and the UVM verification platform can accordingly perform verification operations on them. The clock control unit is configured to open or close based on the execution commands sent from the receiving and converting unit and to generate a clock signal having a corresponding time sequence according to the system parameters configured by the configuration unit, through which the verification system for an I2S bus protocol communicates with the DUT. The data conversion unit is configured to receive data information from the UVM verification platform via the receiving and converting unit, convert the data information into a data type corresponding to that of the device under test (DUT), and transmit the data information to the device under test for verification. Alternatively, the data conversion unit is configured to receive data information from the device under test (DUT), convert the data information into a data type corresponding to that of the UVM verification platform, and transmit the data information to the UVM verification platform for verification.In a preferred embodiment of the present invention, the verification system for an I2S bus protocol as shown in Figure 1 further comprises a pre-storage unit. The pre-storing unit is configured to pre-store the data information sent from the UVM verification platform via the receiving and converting unit and the data information sent from the device under test (DUT) via the data converting unit. In this way, the data transmitted from the UVM verification platform to the test object (DUT) or the data transmitted from the test object to the UVM verification platform are temporarily stored in the pre-storage unit until a transmission command is received or the clock control unit generates a clock for transmitting data. It is thus ensured that the data transmission between the verification system and the test object (DUT) takes place according to a defined command and a temporal sequence, whereby the accuracy and upduality of the communication is ensured. In the present invention, various system parameters are configured in the configuration unit, and the data between the UVM verification platform and the device under test (DUT) is converted by the data conversion unit so that the normal communication between the device under test (DUT) and the UVM verification platform is achieved, which allows the UVM verification platform to perform normal verifications on various devices under test and achieve the verifications for the I2S bus devices.The verification system for an I2S bus protocol of the present invention (see FIG. 2 ) further comprises an interface unit. The interface unit is provided with a bit clock signal line (BCLK), a frame clock signal line (LRCK), and two serial data lines (SDATA1, SDATA0), each line being in point-to-point communication with the device under test (DUT). The two serial data lines are mainly used for different transmission modes having different connection methods.In the pre-storage unit, the pre-storage process of the data specifically includes the pre-transmission and the pre-reception. When the receiving and converting unit outputs the execution command "start transmission", the data in the pre-storing unit is read and converted by the data converting unit. Thereafter, the pre-storage unit is deleted. Then, at the first falling edge of the bit clock signal line (BCLK), the most significant bit of the data is sent to the serial data line (SDATA0 / 1), and the remaining bits are sent according to the clock order. When the receiving and converting unit determines that the current data communication is completed, the prestored data is read by the receiving and converting unit, and the prestored unit is deleted.In particular, in the configuration unit, the communication role, the communication clock, the communication mode, the data transmission direction and the data validity length of the verification system are configured on the basis of the specifications of the I2S communication protocol and the UVM verification platform, such that the parameters conform to the specifications of the I2S communication protocol and the UVM verification platform, thereby enabling the normal communication between the DUT and the UVM verification platform. The communication role of the verification system comprises in particular a master and a slave. When the master is configured as a communication role, the clock control unit transmits bit clock signals and frame clock signals at the specified clock frequency. When the slave is configured as a communication role, the clock control unit monitors the bit clock signals and the frame clock signals. The communication mode includes a half-duplex communication mode and a full-duplex communication mode, wherein the connection between the interface unit of the present invention and the device under test (DUT) is different depending on the communication mode. In the half duplex communication mode, the serial data line (SDATA1) is not connected, and only the serial data line (SDATA0) is connected to the device under test (DUT). In the full duplex communication mode, the transmission directions of the two serial data lines (SDATA1, SDATA0) are opposite. The data transmission direction can comprise data input and data output. For the data output direction, the data conversion unit receives the data from the receiving and conversion unit (from the UVM verification platform) and outputs it to the device under test (DUT). For the direction of data input, the data conversion unit receives data from the device under test (DUT) and outputs it to the UVM verification platform via the pre-storage unit. Moreover, in the configuration unit, the frequency and the timing of the communication clock are configured such that the frequency and the timing of the communication clock of the verification system coincide with the DUT (DUT), thereby enabling communication between the verification system and the DUT (DUT) at the same clock frequency.In the present invention, the data conversion unit is configured to convert the data from the receiving and converting unit into serial data and the data from the device under test (DUT) into parallel data. In the context of the present invention, the data output by the UVM verification platform are parallel data, while the data output by the test object (DUT) is serial data. To enable normal communication between the two parties, the data output by each party must be converted to a form that can be recognized and transmitted by the other party. Specifically, the data conversion unit compares the received data length with the valid data length configured in the configuration unit. If the length of the received data is less than the valid data length, the lower bits of the received data are filled with binary zeros. For example, if the data length received from the data conversion unit is 1 and the valid data length configured in the configuration unit is n, binary zero padding is performed on the n-l lower bits of the received data (starting with the least significant bit). If the data length received by the data conversion unit is greater than the valid data length configured in the configuration unit, the lower bits of the received data are ignored. For example, if the data length received by the data conversion unit is i and the valid data length configured in the configuration unit is j, the lower j-i bits of the received data are ignored (starting with the least significant bit). In this way, it is ensured that the length of the received data matches the pre-configured valid data length, thereby ensuring effective data transmission based on the configured parameters.The working process of the verification system for an I2S bus protocol is described in conjunction with Figures 1 and 2 as follows.First, the UVM verification platform sends a "parameter configuration" command to the verification system based on the attributes of the device under test (DUT) (e.g., the device under test acts as a slave, has a data bit width of 16 bits and a tone sampling frequency of 44.1 kHz, and supports only half-duplex communication). Upon receiving the command, the receiving and converting unit instructs the configuring unit to configure the communication role as master, the valid data length as 16, the clock frequency as 1411200 (44100*16*2), the data transmission direction as data output, and the communication mode as half-duplex communication. The UVM verification platform sends the command "Send data 0x1AB" to the verification system. Upon receipt of the command, the receiving and converting unit inputs the data 0x1AB to the pre-storing unit, and sends the command "start transmission" to the clock control unit and the data converting unit. Upon receiving the start-of-transfer command, the clock control unit reads the parameters from the configuration unit, then pulls down the bit clock signal line (BCLK) and the frame clock signal line (LRCK), and generates a clock of the bit clock signal line (BCLK) based on the clock frequency in the configuration parameters.At the same time, the data conversion unit receives the command "start transmission", reads the prestored data 0x1AB from the prestored unit, erases the prestored data, and then converts the data into the binary form (000110101111100). Starting from the first falling edge of the bit clock signal line (BCLK), the data conversion unit outputs the most significant bit of the binary data to the serial data line (SDATA0) at each falling edge of the bit clock signal line (BCLK). When the clock control unit determines that the data output has reached the valid length of 16, the level of the frame clock signal line (LRCK) is switched, the clock on the bit clock signal line (BCLK) is stopped, and the data conversion unit is configured to wait for a next transmission start command from the receiving and converting unit. When the communication is to be continued, the receiving and converting unit inputs new data into the pre-storing unit and sends the command "start transmission" to repeat the above-described operation. When the communication is not needed, a stop transmission command is sent, and upon receiving the stop transmission command, the clock control unit and the data conversion unit are reset to the initial state.Second, the UVM verification platform sends a "parameter configuration" command to the verification system based on the attributes of the device under test (DUT) (e.g., the device under test acts as a slave, has a data bit width of 8 bits and a tone sampling frequency of 48 kHz, and supports only half-duplex communication). Upon receiving the command, the receiving and converting unit instructs the configuring unit to configure the communication role as master, the valid data length as 16, the clock frequency as 768000 (48000*8*2), the data transmission direction as data input, and the communication mode as half-duplex communication. The UVM verification platform sends a "data received" command to the verification system. Upon receiving the command, the receiving and converting unit sends the command "start transmission" to the clock control unit and the data converting unit. Upon receiving the start-of-transfer command, the clock control unit reads the parameters from the configuration unit, then pulls down the bit clock signal line (BCLK) and the frame clock signal line (LRCK), and generates a clock of the bit clock signal line (BCLK) based on the clock frequency in the configuration parameters. At the same time, the data conversion unit receives the command "start transmission", starts detecting the level of the serial data line (SDATA0) at the second rising edge of the bit clock signal line (BCLK), and then converts the detected data (binary number 01011010) output from the device under test (DUT) into hexadecimal code (0x5A). Since the received data length of 8 is less than the valid data length of 16, the data conversion unit continues to insert zeros in the 8 lower bits of the data at the following rising edges of the bit clock signal line (BCLK). The final hexadecimal data is 0x5A00 which is stored in the pre-store unit as the already received data. When the clock control unit determines that the received data has reached the valid data length of 16, the level of the frame clock signal line (LRCK) is switched, the clock is stopped on the bit clock signal line (BCLK), and the data conversion unit is configured to wait for a next transmission start command from the receiving and conversion unit. The receiving and converting unit reads the previously received data 0x5A00 from the pre-storage unit, deletes the pre-storage unit, and returns the data to the UVM verification platform for data validation and correctness. When the communication is to be continued, the receiving and converting unit sends the command "start transmission" to repeat the above-described process. When the communication is not needed, the command "stop transmission" is sent, and after receiving the command "stop transmission", the clock control unit and the data conversion unit are reset to the initial stateIn summary, the verification system for an I2S bus protocol of the present invention is a dedicated verification system for the I2S bus and is based on the UVM verification platform. In the verification system for an I2S bus protocol of the present invention, various system parameters are configured in the configuration unit, communication between various I2S devices and the device under test (DUT) is simulated over the bus interface, and all data on the interface is monitored, thereby checking completeness and correctness of the design function. Moreover, with this verification system, the verification engineers can flexibly alter the attributes of the verification platform according to the specific design specifications, thus ensuring the integrity and efficiency of the verification process.The above embodiments are only some embodiments of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the patented invention. It should be noted that various changes and improvements can be made to those skilled in the art without departing from the concept of the present invention, all of which fall within the scope of the present invention. The scope of the patent of the present invention is therefore defined by the appended claims

Claims

A verification system for an I2S bus protocol based on a UVM verification platform, comprising a receiving and converting unit, a configuration unit, a clock control unit and a data converting unit; wherein the receiving and converting unit is configured to receive a control command sent from the UVM verification platform and convert the control command into another execution command that can be recognized and executed by other units; the configuration unit is adapted to configure system parameters based on the execution command sent from the receiving and converting unit such that the system parameters meet the requirements of the UVM verification platform; the clock control unit is configured to open or close based on the execution command sent from the receiving and converting unit and generate a clock signal having a corresponding time sequence according to the system parameters by which the verification system communicates with the device under test; the data converting unit is configured to receive data information from the UVM verification platform via the receiving and converting unit, convert the data information into a data type that matches the DUT, and send the data information to the device under test for verification; or the data converting unit is configured to receive data information from the device under test, convert the data information into a data type that matches the UVM verification platform, and send the data information to the UVM verification platform.The I2S bus protocol verification system according to claim 1, further comprising a pre-storage unit configured to pre-store the data information sent from the UVM verification platform via the receiving and converting unit and the data information sent from the device under test via the data converting unit.The verification system for I2S bus protocol according to claim 1, wherein in the configuration unit, a communication role, a communication clock, a communication mode, a data transmission direction, and a valid data length of the verification system are configured based on specifications of an I2S communication protocol and the UVM verification platform.The verification system for an I2S bus protocol according to claim 3, wherein the communication role of the system comprises a master and a slave, the communication mode comprises a half-duplex communication mode and a full-duplex communication mode, and the data transmission direction comprises data input and data output.The verification system for an I2S bus protocol according to claim 3, wherein a frequency and a time sequence of the communication clock are configured in the configuration unit.The verification system for an I2S bus protocol according to claim 1, wherein the data conversion unit is configured to convert the data received from the receiving and converting unit into serial data and the data received from the device under test into parallel data.The verification system for an I2S bus protocol according to claim 6, wherein the data conversion unit is configured to compare a received data length with the valid data length set in the configuration unit; if the received data length is less than the valid data length, binary zero padding is performed on the lower bits of the received data; if the received data length is greater than the valid data length, the lower bits of the received data are ignored.The verification system for an I2S bus protocol according to claim 4, further comprising an interface unit provided with a bit clock signal line, a frame clock signal line and two serial data lines, each line being in point-to-point communication with the device under test.The verification system for an I2S bus protocol of claim 8, wherein in half-duplex communication mode, one of the two serial data lines is unconnected; in full-duplex communication mode, the two serial data lines have an opposite direction of transmission.

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